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- ;EIGHT BIT SUCCESSIVE
- ;APPROXIMATION REGISTER
- ;WITH CONVERSION COMPLETE
- ;AND END OF CONVERSION.
- TITLE SAR 8
- PATTERN 01
- REVISION 01
- AUTHOR CHRIS JAY
- COMPANY MMI SANTA CLARA
- DATE 29 JANUARY 1985
-
- CHIP SAR_8 PAL20RS10
-
- ;PIN 1 2 3 4 5 6
- CLK /RST CMP POL NC NC
- ;PIN 7 8 9 10 11 12
- NC NC NC NC EN GND
- ;PIN 13 14 15 16 17 18
- /OE EOC CC Q3 Q2 Q4
- ;PIN 19 20 21 22 23 24
- Q1 Q5 Q0 Q6 Q7 VCC
-
- EQUATIONS
-
- /Q7 := /RST*Q7*CMP*/Q6*/Q5*/Q4*/Q3 ;ACTIVE LOW RESET WILL
- */Q2*/Q1*/Q0*/CC*/EOC*POL ;SET Q7 HIGH. THE CMP
- + /RST*Q7*/CMP*/Q6*/Q5*/Q4 ;OR /CMP INPUT IS REG-
- */Q3*/Q2*/Q1*/Q0*/CC*/EOC*/POL ;ISTERED DEPENDING ON
- + /RST*/Q7*/EOC ;POL INPUT. Q7 IS HELD
- ;UNTIL THE END OF CON-
- ;VERSION.
- Q6 := /RST*Q7*/Q6*/Q5*/Q4 ;ACTIVE LOW RESET WILL
- */Q3*/Q2*/Q1*/Q0*/CC*/EOC ;RESET Q6 LOW. Q6 GOES
- + /RST*Q6*/CMP*/Q5*/Q4 ;HIGH AFTER Q7 AND THE
- */Q3*/Q2*/Q1*/Q0*/CC*/EOC*POL ;CMP OR /CMP INPUT IS
- + /RST*Q6*CMP*/Q5*/Q4*/Q3 ;REGISTERED.POL SELECTS
- */Q2*/Q1*/Q0*/CC*/EOC*/POL ;CMP POLARITY. THE DATA
- + /RST*Q6*Q5*/EOC ;REGISTERED IN Q6 IS
- + /RST*Q6*Q4*/EOC ;HELD THROUGH THE WHOLE
- + /RST*Q6*Q3*/EOC ;APPROXIMATION CYCLE Q5
- + /RST*Q6*Q2*/EOC ;DOWN TO CONVERSION
- + /RST*Q6*Q1*/EOC ;COMPLETE. THE EOC LOW
- + /RST*Q6*Q0*/EOC ;SIGNAL, END OF CONVER-
- + /RST*Q6*CC*/EOC ;-SION CLEARS THE
- ;REGISTERS.
- Q0 := /RST*Q1*/Q0*/CC*/EOC ;SET REGISTER Q0
- + /RST*Q0*/CMP*/CC*/EOC*POL ;REGISTER CMP
- + /RST*Q0*CMP*/CC*/EOC*/POL ;OR /CMP INPUT
- + /RST*Q0*CC*/EOC ;HOLD Q0 DATA
- ;
- Q5 := /RST*Q6*/Q5*/Q4*/Q3 ;SET REGISTER Q5
- */Q2*/Q1*/Q0*/CC*/EOC ;AFTER Q6. DURING
- + /RST*Q5*/CMP*/Q4*/Q3 ;COMPARE CYCLE.
- */Q2*/Q1*/Q0*/CC*/EOC*POL ;REGISTER CMP
- + /RST*Q5*CMP*/Q4*/Q3 ;OR /CMP INPUT
- */Q2*/Q1*/Q0*/CC*/EOC*/POL ;
- + /RST*Q5*Q4*/EOC ;HOLD Q5 DATA
- + /RST*Q5*Q3*/EOC ;DURING THE
- + /RST*Q5*Q2*/EOC ;APPROXIMATION
- + /RST*Q5*Q1*/EOC ;CYCLE FROM Q4
- + /RST*Q5*Q0*/EOC ;TO CONVERSION
- + /RST*Q5*CC*/EOC ;COMPLETE.
- ;
- Q1 := /RST*Q2*/Q1*/Q0*/CC*/EOC ;SET REGISTER Q1
- + /RST*Q1*/CMP*/Q0*/CC ;HIGH AFTER Q2
- */EOC*POL ;REGISTER CMP
- + /RST*Q1*CMP*/Q0*/CC ;OR /CMP INPUT
- */EOC*/POL ;SELECTED BY POL
- + /RST*Q1*Q0*/EOC ;HOLD Q1 DATA FOR
- + /RST*Q1*CC*/EOC ;REST OF CONVERSION
- ;
- Q4 := /RST*Q5*/Q4*/Q3*/Q2 ;SET REGISTER Q4
- */Q1*/Q0*/CC*/EOC ;AFTER Q5 THEN
- + /RST*Q4*/CMP*/Q3*/Q2 ;COMPARE CYCLE
- */Q1*/Q0*/CC*/EOC*POL ;REGISTER CMP OR
- + /RST*Q4*CMP*/Q3*/Q2 ;/CMP INPUT.
- */Q1*/Q0*/CC*/EOC*/POL ;
- + /RST*Q4*Q3*/EOC ;HOLD Q4 DATA
- + /RST*Q4*Q2*/EOC ;DURING THE
- + /RST*Q4*Q1*/EOC ;APPROXIMATION
- + /RST*Q4*Q0*/EOC ;CYCLE OF Q3
- + /RST*Q4*CC*/EOC ;DOWN TO CC
- ;RESET REGISTER Q3
- Q2 := /RST*Q3*/Q2*/Q1*/Q0*/CC*/EOC ;SET REGISTER Q2
- + /RST*Q2*/CMP*/Q1*/Q0*/CC ;HIGH AFTER Q3
- */EOC*POL ;REGISTER CMP OR
- + /RST*Q2*CMP*/Q1*/Q0*/CC ;/CMP INPUT SELECT
- */EOC*/POL ;WITH POL
- + /RST*Q2*Q1*/EOC ;HOLD Q2 DATA
- + /RST*Q2*Q0*/EOC ;FOR APPROXIMATION
- + /RST*Q2*CC*/EOC ;CYCLE TO CC.
- ;RESET REGISTER Q3
- Q3 := /RST*Q4*/Q3*/Q2*/Q1*/Q0 ;THEN SET Q3.
- */CC*/EOC ;REGISTER THE CMP
- + /RST*Q3*/CMP*/Q2*/Q1*/Q0 ;OR /CMP INPUTS
- */CC*/EOC*POL ;AND HOLD CONTENTS
- + /RST*Q3*CMP*/Q2*/Q1*/Q0 ;OF Q3 DURING THE
- */CC*/EOC*/POL ;REST OF THE APP-
- + /RST*Q3*Q2*/EOC ;-ROXIMATION CYCLE
- + /RST*Q3*Q1*/EOC ;DOWN TO CC
- + /RST*Q3*Q0*/EOC ;
- + /RST*Q3*CC*/EOC ;
- ;RESET CC. CC GOES
- CC := /RST*Q0*/CC*/EOC ;HIGH AFTER Q0 TO
- + /RST*CC*/CMP*/EOC*/EN*POL ;INDICATE THAT
- + /RST*CC*CMP*/EOC*/EN*/POL ;CONVERSION IS NOW
- ;COMPLETE. IF EN
- ;IS LOW THEN CC
- ;CAN PROVIDE ONE
- ;ADDITIONAL BIT OF
- ;RESOLUTION.
- ;
- EOC := /RST*CC*/EOC ;END OF COUNT
- ;GOES HIGH TO
- ;RESET THE SAR.
- SIMULATION
- TRACE_ON CLK /RST EN CMP POL
- Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CC EOC
- SETF OE /CLK RST EN CMP /POL ;SET INITIAL CONDITIONS
- CLOCKF ;AND RESET Q6 - Q0, CC
- SETF /RST ;AND EOC, SET Q7
- CLOCKF ;FOR NINE CLOCK CYCLES
- FOR I := 1 TO 9 DO ;PERFORM ONE PASS OF
- BEGIN CLOCKF ;SUCCESSIVE APPROXIMATION
- END ;WITH CMP HIGH AND POL
- SETF /CMP ;LOW. PERFORM SECOND
- FOR J := 1 TO 9 DO ;PASS WITH CMP LOW
- BEGIN CLOCKF CLK ;
- END ;SET POLARITY PIN ACTIVE
- SETF POL ;TEST SUCCESSIVE CYCLE OF
- FOR K := 1 TO 9 DO ;APPROXIMATION WITH THE
- BEGIN CLOCKF CLK ;INVERSION INPUT ACTIVE
- SETF CMP ;FOR CMP HIGH AND CMP
- FOR L := 1 TO 9 DO ;LOW
- BEGIN CLOCKF CLK ;
- END ;
- CLOCKF ;
- END ;
- TRACE_OFF ;
-
-