Global Amiga Experience

home *** CD-ROM | disk | FTP | other *** search

/ Global Amiga Experience / globalamigaexperience.iso / graphic / cad / board_design / proboard_demo / manual < prev next >

Wrap

Text File | 1995-07-10 | 152.8 KB | 3,697 lines

zq(Bpwv"z v"zP r o - B o a r d D e m ov"z User's Manual for the demonstration version of a fully automatic PCB routing package. v"z© 1993 Prolific, Inc.v"z v"zAll Rights Reservedv"z P r o l i f i c , I n c . 6905 Oslo Circle, Suite B3 Buena Park, CA 90621 Phone: (714) 522-5655 FAX: (714) 994-6435 Internet: Prolific@cup.portal.com Table of Contents 1. Introduction............................................4 2. Operational Overview....................................4 3. Terms and Conventions...................................7 4. Installing and starting Pro-Board......................15 Extracting the files...................................15 Using ASSIGN...........................................15 Starting the program...................................15 CLI Startup...........................................15 From hard disk.......................................15 From floppy..........................................16 Workbench Startup......................................16 Opening screen.........................................16 5. Top-Down Approach......................................17 5.1 Required files and preparation.........................17 Generating the Net List................................17 Generating the Part List...............................17 5.2 Simple autoplace and autoroute.........................18 Specifying your PCB....................................19 Main menu..............................................20 Adjusting the screen view..............................20 Preparing to autoroute.................................22 Autorouting the PCB....................................23 Evaluating the results.................................23 5.3 Typical autoplacement..................................23 Outlining your PCB.....................................24 Manually placing parts.................................24 Guiding autoplacement..................................25 Placement Grids........................................25 Grouping to control autoplacement......................25 Optimizing intergroup connections......................26 5.4 Routing a single layer board...........................26 5.5 Library Part Design....................................26 Custom Header..........................................27 Goldfinger edge connector..............................27 PGA Device.............................................28 PLCC Devices...........................................29 5.6 Tips and Tricks........................................29 Two layer boards.......................................29 Ground plane on a 2 layer board........................30 Multiple Power Planes..................................30 Pseudo Ground Plane....................................31 Autorouting Power & Ground traces......................31 Single-ended Ground Traces.............................31 Multiple PGrids for autoplacement......................32 6. Pro-Lib................................................33 Pro-Board Demo manual P. 2 Table of Contents 7. Tutorials..............................................34 7.1 Simple autoplacement...................................35 Improving autoplacement................................36 Swap to improve routing................................38 Adjust PGrid for improved autoplacement................38 7.2 Define a PLCC..........................................39 Preparation............................................40 Creating the PLCC......................................40 7.3 Memory card layout.....................................42 Creating Library Parts.................................42 Routing the Traces.....................................47 Alternate Solution.....................................50 A.1 Net List format........................................51 A.2 Part List format.......................................53 A.3 Pro-Drill..............................................54 A.4 Contacting Prolific....................................55 Pro-Board Demo manual P. 3 Section 1: Introduction v"z1.v"z v"zIntroductionv"z This package is a demonstration version of our fully automatic placement and routing Printed Circuit Board package, with the exception that you will not be able to save your data files. We at Prolific, Inc. are certain you will find this demonstration version of our layout software to be an excellent tool for Printed Circuit Board design on the Amiga, combining power and ease of use to increase your productivity, and making the process of PCB production faster and more enjoyable. Like any productivity software, Pro-Board will take some getting used to. The first item to note is that Pull Down menus are NOT used. The right mouse button is still used, but in a different manner. When you are in the mode to add an object (part, trace, text, drawing, etc.), the Left Mouse Button is used to Add the object and the Right Mouse Button is used to Delete it. The Operational Overview in the next section, as well as the section on Terms and Conventions, should be read before trying any serious work. When a word that is not at the beginning of a sentence is capitalized, it either has a specific meaning explained in this section or is an IFK. The material in Section 5 provides a sequence of steps to be used in the creation of any PCB. Specific design examples, with step-by-step instructions, are included in Section 7. There are several PCB data files included in this package which serve to familiarize you with many of the features provided in this powerful program. At most screens and menus, the <Alt><Help> hot key will display context sensitive help describing the various functions available. We hope this demonstration version of our software is useful to you. Jeff Lindstrom Prolific, Inc. February 15, 1993 v"z2.v"z v"zOperational Overviewv"z We use intelligent (context sensitive) function keys (referred to as IFKs) to display the functions available in any mode. IFKs are displayed at the bottom of the screen and correspond to the Function Keys. The <Help> key will display additional functions which are available at most screens, and the <Alt><Help> hot key will display context sensitive Help information. The basic device types supported by Pro-Board are Dual In-line Packages (DIPs), Single In-line Packages (SIPs), and 2-Pin devices (resistors, capacitors, diodes, etc.). However, there are many devices which do not use these basic shapes, such as Plastic Leaded Chip Carriers (PLCCs), Pin Grid Arrays (PGAs), power transistors (TO-3, etc.), potentiometers, goldfinger edge connectors, board mounted connectors, etc. Custom Library Parts can be created in a separate utility, Pro-Lib. A fully functional version of Pro-Lib is included, so you can experiment with the power and ease of use when creating custom Library Parts. You may also place these Pro-Board Demo manual P. 4 Section 2: Operational Overview also place these parts on your PCB designs. Several data files have been included which demonstrate the range of functions available for designing PCBs. They start with a simple tutorial on automatic placement and routing and progress to a design for a memory board which will be best created using a combination of sutomatic and manual procedures. Pro-Board uses information provided in a Net List to determine the interconnections to be made. A corresponding Part List cross references the Device Labels in the Net List with a physical description of the part. This is required by Pro-Board's automatic placement function. The Net List is most easily generated by Pro-Net, Prolific's schematic editor. The Part List can be generated within Pro-Board, under an external ARexx script, or even with a text editor (although this approach can easily cause errors). Pro-Board V2.1 is a large program. Minimum recommended memory configuration is 1.5 Megs, although small boards can be done in 1 Meg. Pro-Board accepts Net Lists generated by Pro-Net, along with the Part List generated by the Foot-P (FootPrint) function, and performs component placement, trace routing, Rat's Nesting, Guide Line routing, automatic XY Coordinate marking, Surface Mount Device support, automatic Surface Trace handling, and Net List comparison. Pro-Board and Pro-Net are tailored to work with and for each other. They can therefore accomplish many tasks that are not addressed by stand-alone schematic capture or pcb layout programs. Most of these tasks are tedious and repetitive, and should be done by computer rather than with paper and pencil. Some examples of these tasks are: · Rat's Nesting aids the component placement process which is of vital importance for good PCB layout. · Automatically assign and mark XY coordinates on the PCB. Coordinate marking is non-linear, assuring easy identification of components regardless of layout or density. · Automatically rename IC by coordinates, such that U17, for example, now becomes 3D on the PCB. · Automatically rename IC by coordinates on schematic to match that of the PCB (done by Pro-Net's Back Annotation function). · Compare the Net List produced by Pro-Net with results from Pro-Board and report any discrepancies. Tags missing components and Traces, verifies that Nets are completely connected, identifies Pins and Traces which are connected but were not called out in the Net List. Pro-Board can run concurrently with other programs, if they observe the guide lines for multitasking and you have enough memory. The following files will be generated either for or by Pro-Board. The Pro-Board Demo manual P. 5 Section 2: Operational Overview files that are associated with a PCB called <PCBname> and a Net List called <NETname> are as follows: <NETname>.NET ASCII file: the Net List created by Pro-Net and used to lay out the PCB. <NETname> may or may not be the same as <PCBname>. <NETname>.PAT ASCII file: the Part List created by the Foot-P function in Pro-Board and some user input. It is used to cross-reference the Net List Device Labels with the Device footprints. Without this file, the Net List is ignored by Pro-Board. <PCBname>.APCB The PCB data file of a PCB called <PCBname>. When specifying the PCB file, do not include the .APCB suffix. There is a twelve character limit on file name length. If you were to list the directory containing the data files, you would see that PCB data file names are padded with <space> characters for a total of twelve to the left of the `.APCB' suffix. When listing the files inside Pro-Board, do not use the spaces. Pro-Board Demo manual P. 6 Section 3: Terms and Conventions v"z3.v"z v"zTerms and Conventionsv"z The Terms and Conventions listed in this section refer to specific meanings or actions. Words and phrases which have a special meaning will be capitalized when referenced in the text. Add Button The Left Mouse Button (LMB) is the Add Button. To Add a Part, Trace, or Object (Circle, Box, Line, Text String, Forbidden Area, etc.), enter the mode to create the item. Click at the location (sometimes a Drag operation will be needed before Clicking) with the Left Mouse Button. Click Press and release the mouse button. By default, Clicking refers to the Left Mouse Button (LMB). If the Right Mouse Button (RMB) is required, it will be stated in the Command Description. Component layer The Component layer is the Signal layer on the side of the PCB on which Devices are (usually) placed. It is also referred to as Signal layer #1. As Pro-Board now supports 16 Signal layers, the letter <C> has been replaced in the DISPLAY and WORK gadgets with odd numbers (depending on the current Signal Pair in use). It is still used in Pro-Lib, however. With the advent of PCBs with SMD components on both sides, this term may soon become archaic but is still in use. It is marked on the screen by the color Green. Only the Component and Solder layers may have SMT Devices Placed on them. See also Even, Odd, ad Master, and Solder layer descriptions. Delete Button The Right Mouse Button. Prolific, Inc.'s Pro-series programs use the mouse slightly differently than other Amiga programs. As the IFKs replace the need for Pull-Down menus, the Menu (Right Mouse) Button has been reconfigured as a Delete Button. This speeds the process for developing a PCB by making it very easy to Add and Delete without having to make any extra movements. To Delete a Device, Trace, or Object (Circle, Box, Line, Text String, Forbidden Area, etc.), you must be in the mode to Add (Create) that item and on the proper Work layer. Move the mouse over the desired item and Click with the Right Mouse Button (RMB). DIPs, SIPs, and 2-Pins require that the cursor be over Pin#1 (identified with a square pad instead of the normal round pad) in order to be Deleted. Pads have only one Pin, so Deletion is obvious. Library Parts require only that the cursor be within the Bound (See description for Bound in Pro-Lib). Circles, Boxes, Lines, and Forbidden Areas can be Deleted simply by placing the cursor over the item and Clicking the RMB. Text Strings require the cursor to be at the upper left corner of the first character. See also RMB. Pro-Board Demo manual P. 7 Section 3: Terms and Conventions Drag Drag is an operation performed with the mouse. To drag an object, press and hold the LMB (Left Mouse Button, also called the Add Button because it is used for Adding parts) and move the mouse to the desired position before releasing the LMB. Drag is used for Moving Devices or Text Strings, or defining an operation. See also RMB, Add, Click, and Move. <Enter> key At the right of the keyboard is the numeric keypad (except for the A600). The <Enter> key on the keypad has been reserved as a Screen Refresh command (on the A600, use the <Tab> key). Pro-series programs do not refresh the screen at every opportunity as this would slow the design process. When items are removed from the screen, however, they leave an impression that can be distracting. Tapping the <Enter> key redraws the main display area (but not the IFKs or the Entry Bar). To enter text or answer prompts, you must press the <Carriage Return> key on the main keypad. Note: The A600 does not have a numeric keypad, so the <Tab> key has been reconfigured to perform screen refresh as well. Entry Bar The Entry Bar is the Cyan-colored display area immediately above the IFKs at the bottom of the screen. The left section is used for messages and function prompts. The center has a collection of DISPLAY gadgets which determine which layers are shown, while the right side has the WORK gadgets which determine which layer will be affected by the operation. At the far right is a PAIR gadget which cycles through the available Signal layers (as determined in the Design Rule). Some functions will cause the DISPLAY and WORK gadgets to disappear to make room for prompts. Even layer With 8 Pairs of Signal layers supported in the latest version of Pro-Board, the phrase `Solder layer' is of marginal value and is used only to specify one of the two layers that allows SMD mounting. Therefore, each Signal layer pair is differentiated by its modulo 2 result and the Even numbered layers are displayed in Red. The display of Traces, Devices, and other markings on this layer is determined by the even number (2, 4, 6, 8, 10, 12, 14, or 16) to the left of the PAIR gadget on the Entry Bar. See also Odd, Solder, and ad Master layers. Pro-Board Demo manual P. 8 Section 3: Terms and Conventions Exit An operation or menu can be Exited by entering the Escape key (at the upper left of the keyboard) or by placing the mouse cursor over the IFK region and Clicking the RMB (see below). Some operations cannot be Exited until they have been completed or completely undone, such as manually routing a Trace or specifying the diagonals of a Box. See RMB for undoing part or all of an operation. Function In the description of the IFKs, a Function refers to an IFK (see Intelligent Function Key description) which performs an operation. There are three classes of operations by which Functions operate: some Functions work directly (Go, NetOpt, Next, etc.), invoking the Function has an immediate effect; another class requires additional mouse controls to specify the operation (Line, Box, Trace, etc.), and the third class brings up prompts which must be answered in order to complete the operation (placing a DIP or 2-Pin, for instance). <G>round layer If a Power Plane is specified in the Net List and Power/Ground was turned On in the Design Rule, the <G>round layer can be generated by the Auto command under the Thermo menu. It will provide all the connections to the Ground plane. The <G> gadget in the DISPLAY area of the Entry Bar controls the visibility of markings on this layer. Highlight There are two meanings to `highlight'. One meaning is that a Selected IFK will `light up' to indicate that it is active. The other meaning describes actions to take. Several screens display lists of PCB data or Library Part files, or Device Groupings. The highlight bar identifies the current file or Device to be affected by the command. The IFKs <Pg Up Arrow> and <Pg Down Arrow> move through pages of file listings. <Up Arrow> and <DownArrow> move the highlight bar. The mouse can also move the highlight bar by first placing it over the highlight and then moving it over the desired file. In Edit, Clicking the LMB or pressing the Pick IFK will load the file. In File, invoke Delete, Copy, or Rename to start the desired operation. Pro-Board Demo manual P. 9 Section 3: Terms and Conventions Intelligent Function Keys (IFKs) Intelligent Function Keys are context sensitive. As a Menu is entered or command is invoked, some or all of the IFKs will change to support the new operational mode or command. IFKs are Selected by positioning the mouse cursor over the gadget at the bottom of the screen and Clicking with the Left Mouse Button or by pressing the corresponding function key. Some commands do not have any subordinate IFKs to support their operation (i.e. they are mouse-driven in the main screen area); the IFK will highlight and the other IFKs will not disappear. From here, you may complete the operation, Select another IFK, or Exit to the parent menu. <L>abel layer The <L>abel layer is also known as the Silk Screen layer. Common Device Labels will be marked on this layer. Text is usually inserted on this layer, but may be drawn on the Component, Solder, <V>oltage, and <G>round layers. The DISPLAY gadget <L> controls the visibility of markings on this layer, which are displayed in Purple. LMB The Left Mouse Button is used to Add Devices, Traces, etc. or specify Items (the diagonals of a Box, the center and radius of a Circle, etc.) Simply Click the Button when the cursor is at the desired location. Menu A Menu envelopes a class of operations under its heading. The purpose is to consolidate functions supporting a type of operation (manual routing, drawing, etc.) in one area. mil(s) A mil is a unit of length. It means 0.001 inches. Its use dates back quite a while and is not a contraction of millimeters. Metric and English coordinates are switched with the Alt-M Hot Key. Net A Net is a sequence of Pins to be connected; all of the Nets comprise the Net List. The connections are made by Traces between pairs of Pins. Each Pin is an endpoint for two Traces, except for those at the beginning and end of the Net. Net List The Net List is contained in the file <NETname>.NET. It is used by Pro-Board's Design Rule and also by Foot-P when creating the Part List. The Net List format is shown in the Appendix. It lists a series of Nets, each with connections to various Device Pins. The Device Labels must be cross-referenced in the Part List with a physical description of the Device or the Net List will be ignored. Pro-Board Demo manual P. 10 Section 3: Terms and Conventions Odd layer With 8 pairs of Signal layers supported in the latest version of Pro-Board, the phrase `Component layer' is of marginal value and is used only to specify one of the two layers which allows SMD mounting. Therefore, each Signal layer pair is differentiated by its modulo 2 result and the Odd numbered layers are displayed in Green. The display of Traces, Devices, and other markings on this layer is determined by the odd number (1, 3, 5, 7, 9, 11, 13, or 15) to the left of the PAIR gadget on the Entry Bar. See also Even, Component, and ad Master layers. Option An IFK marked as an Option specifies a design choice made by you to control the operation of a Function. The orientation of a Device when it is placed is one example. ad Master layer The ad Master layer specifies holes (both Pad and Via) which are present on every layer of the PCB. DIPs, SIPs, 2-Pins, and any Library Parts with PadPins will be entered on the ad Master layer. A Trace on any Signal layer may route to any Pin or Pad. Connections to these holes on the Power and Ground layers are by Thermos. Devices, and other markings on this layer, are displayed in Yellow and their visibility is determined by the DISPLAY gadget. Traces may not be made on this layer. Pad A Pad is an unmarked hole that is provides an electrical connection It is present on every PCB layer, but will normally be masked so that it does not connect to the Power and Ground layers. It is unlabelled and has no number assigned to it. It differs from Vias, which are (usually) smaller. See also Pin. Part List The Part List is contained in the file <NETname>.PAT, where <NETname> is the base name for the Net List. Created by the Foot-P function, it provides a physical description of every Device Label specified in the Net List. If Pro-Board does not find a cross-reference for every Device Label, the Net List will be ignored. The Part List is not related to the Bill of Materials (BOM) generated by Pro-Net's Post Processor. Pin A Pin is a circular hole (like a Pad) or a rectangular box (Surface Mount) used as an electrical connection point. It is numbered and is associated with a Device Label. See also Pad. Pro-Board Demo manual P. 11 Section 3: Terms and Conventions Place Placement Refers to the action or process of putting a Device on a PCB by entering the mode to Add the type of Device (DIP, SIP, 2-Pin, Pad, or Library Part), specifying the Device (number of Pins, Library Part name, etc.), Dragging the ghost outline of the Device to the desired location, setting the Orientation, and Settling the Device by Clicking with the Left Mouse Button. RMB The Right Mouse Button is used to Delete Devices, Traces, etc., Exit, or Back Up from certain operations. If you are in the mode to Add a Device (DIP, 2-Pin, etc.) or Trace, you can Delete the same type of item by moving the cursor over the item and Clicking the RMB. Devices like DIPs, SIPs, and 2-Pins require that you place the cursor over the Pin#1 position (marked by the square Pad) to be Deleted. Library Parts require only that you Click with the RMB inside the Bound. If you are manually routing a Trace and you have clicked on several points to Guide (or Train) the Trace, Clicking on the RMB will UnDo (Delete) the last Trace segment, allowing you to correct part of the Trace without having to start all over. If you wish, you can Click with the RMB several times to completely undo the operation (before it has been completed, of course). This applies to Drawing Boxes and Circles, as well. If you move the cursor over the IFK region at the bottom of the screen, Clicking the RMB will usually Exit up to the parent menu as if you had pressed the Escape key. You cannot Exit from the middle of certain operations (Drawing a Box or Circle, for example). See Delete Button. Scroll Walls The Scroll Walls, when displayed, are located in the center of each of the four sides of the screen. Each 'hit' (with the cursor) on a Wall scrolls the view screen towards the Wall. The Del key toggles activation and display of the Scroll Walls. The Scroll Walls must be visible to function. The arrow keys between the main and numeric keypads function regardless of the status of the Scroll Walls. Pro-Board Demo manual P. 12 Section 3: Terms and Conventions Select The word `Select' is used to mean that a Pin, Device, or IFK is chosen for an immediate or pending operation or that an item from a list is specified. The procedure to Select can be by mouse and/or keyboard, depending on the operation. The mouse is used by moving the cursor over the Pin, IFK, or whatever and Clicking the Left Mouse Buttom (LMB or Add button). The keyboard is used by pressing the Function Key corresponding to the IFK displayed on the screen or by entering text into a requester. Pins are Selected for manual routing. Devices are Selected in order to be Moved, Rotated, Swapped, etc. An IFK is Selected to: enter a Menu, specify an Option, or invoke a Function. An item could be one of several Trace Widths in the Width screen. Signal layers Traces may only be routed on the Signal layers. This excludes Traces on the ad Master, <L>abel, <V>oltage, and <G>round layers. Only two Signal layers are presented for routing at a time. The Pair in use is displayed to the left of the PAIR gadget at the right of the Entry Bar. Switch among the available layers by Clicking on the PAIR gadget. Solder layer The Solder layer is the Signal layer opposite the side of the PCB on which Devices are (usually) placed. It is also referred to as Signal layer #2. As Pro-Board now supports 16 Signal layers, the letter <S> has been replaced in the DISPLAY and WORK gadgets with even numbers (depending on the current Signal Pair in use). It is still used in Pro-Lib, however. With the advent of PCBs with SMD components on both sides, this term may soon become archaic but is still in use. It is marked on the screen by the color Red. Only the Component and Solder layers may have SMD Devices Placed on them. See also Even, Odd, ad Master, and Component layer descriptions. Trace A Trace is an electronic connection between Pins and is used to route a Net. Vias and Pads can be intermediate points along the Trace, but if a Pad, Via or Tile is an endpoint, it is considered to be a Trace segment, not a Trace. While you can Draw on a Signal layer, Drawings which happen to overlap two Pins will not be considered a Trace. In fact, you will get a prompt if your Drawing will intersect a Pin. Train a Trace When manually routing a Trace in 1Layer mode, you can Click at intermediate locations to force the Trace through a particular path. Pro-Board Demo manual P. 13 Section 3: Terms and Conventions Via A Via (pronounced `Vee-ya') is an unmarked hole used for connecting Traces on different layers. They can be Added manually while Training a Trace to switch layers or automatically in 2Layer mode. <V>oltage layer If a Power Plane is specified in the Net List and Power/Ground was turned On in the Design Rule, the <V>oltage layer can be generated by the Auto command under the Thermo menu. It will provide all the connections to the supply voltage. The <V> gadget in the DISPLAY range on the Entry Bar determines visibility of this layer. The <V> gadget in the WORK range must be activated for any operation other than the Thermo commands Auto and DelAll to have any effect. Keep in mind that some operations, such as routing a Trace, cannot be done on the Voltage layer. Pro-Board Demo manual P. 14 Section 4: Installation v"z4.v"z v"zInstalling and starting Pro-Boardv"z This demonstration version of the software is divided into two archives for installation on two floppies. As an alternative, you may extract the files to one or two sub-directories on your hard disk. v"zExtracting the filesv"z The archives were created with the LhA program written by Stefan Boberg. To extract them, change directory to the location of the archive files and enter the command: v"zASSIGN A: ""v"z Now change to the directory where you want the files (from either archive) and enter the command: v"zLhA x A:<filename>v"z where <filename> is one of the two archives. If your are installing to fresh floppies, be sure to format them first. If you are installing to hard disk, make the directories first. v"zUsing ASSIGNv"z Pro-Board uses two directories for its work, Data and Lib. It is most convenient to assign Volume names in User-StartUp (StartUp-Sequence for users of AmigaDOS V1.3). I use PCB: and assign it to SC1:CAD/Data. v"zStarting the programv"z v"zCLI Startupv"z v"zFrom hard diskv"z If you have installed Pro-Board on a hard disk, enter the following commands at the CLI prompt: v"zcd dh0:Pro-Board <CR> [*]v"z v"zStack 80000 <CR>v"z v"zPro-Board <CR>v"z to work on your PCB. Note that the stack is 80,000, not 8,000. Do not enter the comma in the Stack command, however. With a stack of only 20000, you can enter "Pro-Lib" to create or edit Library Parts, or "Pro-Plot" to generate a hard-copy and/or photo plot file. Both programs can be run concurrently (assuming you have sufficient memory) such that you can work on one PCB file and produce a hard copy for another PCB at the same time. _________________________ * Your system or installation may require a disk or volume designation other than "dh0:", such as "dh2:", "Work:", or "Sys:". A standard technique is to Assign a path designation in the v"zStartUp-Sequencev"z. See your v"zAmigaDOSv"z manual for more information. Pro-Board Demo manual P. 15 Section 4: Installation v"zFrom floppyv"z If you have installed (copied) Pro-Board on floppy disk, put it in a drive and, at the CLI prompt, enter: v"zcd Pro-Demo:<CR>v"z v"zStack 80000 <CR>v"z v"zPro-Board <CR>v"z v"zWorkbench Startupv"z Starting from the Workbench is somewhat simpler. Click on the disk icon to open the disk window. If there is a drawer for Pro-Board, click on it to open the drawer; then click on the appropriate icon to run the program. The Stack size has already been set in the Pro-Board and Pro-Lib icons. v"zOpening screenv"z Upon starting a program, you will see the opening screen with no IFKs active. Click in the screen or press any key to activate the program and see the IFKs. Select (press the IFK or Click at its icon) <Config> and verify that the program will access the desired data disk. Specify the desired work drive or volume name. Set the hard copy preferences for your configuration. Either Save or Use will return to the root menu. <Save> will set your current settings as the default. <Use> is for this session only. The disk or volume you select under IFK-Config will be checked for the proper directory structure. If not present, you will be asked by Pro-Board whether to prepare it. Note that a disk must be formatted* under AmigaDOS or Workbench before use by Pro-Board or the other programs. From this point on, each program will have its own IFKs governing operations. The following tutorials in the next chapter will familiarize you with some of them. The IFK descriptions for each program provide in-depth descriptions. _________________________ * If you are unfamiliar with formatting disks, refer to your v"zAmigaDOSv"z manual. It will only be required if your data and library disks are on floppy. The hard drive will have already been formatted before v"zPro-Boardv"z was installed. Pro-Board Demo manual P. 16 Section 5.1: Preparation v"z5.v"z v"zTop-Down Approachv"z In this chapter, we will provide the series of steps you will have to take for your design projects. We will start out with the minimum steps required to lay out a simple PCB and progress to more advanced topics. The description for individual IFKs are not included here, but can be described at most menus by pressing the <Alt><Help> hot key combination. At the end of this chapter, we have provided a Tips and Tricks section to provide useful suggestions for situations you are likely to encounter. The following steps will list guidelines for PCB generation. If you want specific examples, please see Section 7: Tutorials. v"z5.1v"z v"zRequired files and preparationv"z Prior to any PCB layout, you must know some basic information: 1. The components on your PCB (known as the Bill of Materials or BOM), used to help build the Part List. 2. The interconnection between the components (referred to as the Net List). 3. The Footprint or shape of the components to be placed on your PCB (contained in the Part List). 4. The size and shape of your board (big enough to place all the components without wasting too much space), as well as any physical obstructions and the number of layers. v"zGenerating the Net Listv"z The Net List can be generated with a simple text editor, but is best done with Pro-Net, Prolific's Schematic Capture program. Once you have designed your schematic, the Post Processing module will generate the Bill Of Materials (BOM) and the Net List. The Net Lists required for the tutorials in this manual are included in the data disk. v"zGenerating the Part Listv"z Once you have the Net List, you will have to generate a Part List. The Part List is a cross-reference between the Device Labels specified in the Net List and the physical description of each part. The Device associated with each Device Label is described in the BOM. The Part Lists required for each Net List in the tutorials are included. Use the v"zFoot-Pv"z (Foot Print) function to generate the Part List file. Foot-P is one of the IFKs available on the root menu of Pro-Board (the first one you see after you start the program). Copy the Net List from the PNPOST sub-directory of the volume you specified in the Post processor. Enter the Net List name (v"z<NETName>... do not use the .NETv"z v"zsuffixv"z). Pro-Board Demo manual P. 17 Section 5.2: Simple example As an alternative, you can use the ARexx program BOMtoPL.REXX to read the Bill Of Materials. This utility is recommended if you have many repetitions of the same Device, such as in a design for a memory board. Foot-P will search the Net List for all Device Labels and present them in order of occurrence. The Bill of Materials (aka BOM... an optionally-created file under Pro-Net) will be useful in this process as it includes the Device Type for each Device Label. Cycle through each Device Label and specify its type (DIP, SIP, 2-Pin, or Library Part) and enter the required data (number of Pins, separation, width, or name, as required). The data you enter for each type will be the default for any subsequent Parts of the same type. You will have to delete the prompts to use new values. For each Device Label, you will provide the Type. Depending on your answer, you will be presented with one or two more questions to fully specify the part. The four allowed Types are: DIP Dual In-line Package SIP Single In-line Package 2-Pin Two-Pin (resistor, capacitor, etc.) Lib Library Part (see Pro-Lib) When complete, you will have a Part List file named <NETname>.PAT. Your Net List must always have a Part List with the same base name (everything to the left of the `.') which cross-references every Device Label in the Net List or Pro-Board will not use the Net List. The Part List, like the Net List, is a simple ASCII file. Refer to the Appendix for the format. If you prefer, you can create or modify the Part List with a text editor. v"z5.2v"z v"zSimple autoplace and autoroutev"z This overview of the most basic operations assumes you have a simple circuit to be autorouted and autoplaced to familiarize yourself with Pro-Board's capabilities. Circuits which require components to be manually placed (such as connectors) or areas of the PCB which cannot accept parts (heighth clearance, for instance) and other, more advanced, topics are covered later. A tutorial is at the end of the manual. If you want more specific guidance, please refer to Section 7: Tutorials. If you start Pro-Board from the CLI, remember that it requires a Stack of 80,000 to work properly. If you start from Workbench (the Icon- based operating system), the program Stack is set automatically. When the program first boots, there will be a prompt on the Entry Bar to either press the mouse button or hit any key to continue. Once done, you will see the Welcome screen (see Section 3: Screens). Pro-Board Demo manual P. 18 Section 5.2: Simple example Press Function Key F10 or move the mouse cursor over <Config> at the lower right of the screen and Click the LMB. The Configuration screen is the same for Pro-Board, Pro-Lib, Pro-Plot, and Pro-Drill*. v"zSpecifying your PCBv"z Now that Pro-Board knows your configuration, you are ready to start. Invoke Edit and Select New. You are now in the Design Rule screen. While you can return to the Design Rule at any time while editing your PCB, there are a few items which cannot be changed once you have exited this screen for the first time; specifically Fine Line, Trace Orientation, and Signal Layer Pairs. In addition, the PCB Width and Length may be increased, but not decreased. Fine Line mode reduces the Trace Width and Separation from 12 and 13 mils, respectively, to 8 mils each. Selecting Fine Line will automatically reduce the Pad and Via sizes. You may, if you wish, increase their sizes. The default reduction is added as a safety measure which may not be needed for your PCB production. Check with your PCB production facilities for recommended values for Pad and Via sizes; Power, Ground, & Solder mask clearances; as well as whether to Solder mask Vias. Two Fine Line traces can be routed through a gap of 40 mils (two Trace Widths of 8 mils and three Trace Separations of 8 mils). Standard mode requires a gap of 38 mils for 1 trace and 63 mils for two traces. The Power/Ground layer and Solder Mask clearances again depend on your production facilities. The defaults are standard and will cause no problem with most facilities. As with most other items on this menu, they can be changed as needed. Width and Length are the dimensions of the PCB. Width will be displayed horizontally on the screen. If you have enough memory, your PCB can be up to 32 inches on each side. The number of Signal layer Pairs, which cannot be changed later on, specifies the maximum number of layers. If you really want to do a 5 layer board, specify 3 Pairs and remember to avoid routing on one of the layers. When entering the name of your PCB, do not include the ".APCB" suffix; it will be added automatically. Included spaces are not allowed, nor are lower case letters (the spaces are ignored and the letters converted). You may use numerals anywhere in the PCB's name. Maximum file name length is 12 characters. _________________________ * v"zPro-Drillv"z is a separate Prolific product that generates PCB drill sizes and positions from your PCB data file. Contact Prolific for more details. Pro-Board Demo manual P. 19 Section 5.2: Simple example The Net List must be in the Data disk directory specified in the Configuration screen. The base names for the PCB (<PCBname>) and the Net List (<NETname>) do not have to be the same, but for every Net List used, you must have a Part List with the same base name (<NETname>.NET and <NETname>.PAT, respectively). The Part List must cross-reference every Device Label contained in the Net List. Foot-P will generate this file from some input by you. The Net List and Part List are simple ASCII files with formats listed in the Appendix. Press OK to continue to the main menu. The Net List will be checked against the Part List. If there are any errors, you will be given the option of remaining in the Design Rule or continuing to the main menu without any Net List support (i.e. no autoplacement and no autorouting). Note ==== At most levels and in most operations, you can exit to the next higher level or cancel the operation by pressing the <Escape> key or by placing the cursor over the IFK region at the bottom of the screen and clicking the Right Mouse Button. v"zMain menuv"z The IFKs at this level are as follows: v"zRule SetRef Border Place Auto-P Route Auto-R Draw Save Postv"z Rule will return you to the Design Rule you just left. SetRef allows you to specify a point other than the lower left corner as the origin for coordinate display and some operations. It is useful before heading on to the next step. Border is a requirement. It limits the area used by the placement, routing, autoplacement, and autorouting functions. If not used, parts and traces could extend beyond the boundaries of the PCB. Click just inside the four corners of your PCB and Select <Next> to set the Border. The line segments which have been drawn in Purple will now be Yellow. If the last point Clicked did not overlap the first, a final line segment will be drawn to close the polygon. Click in sequence so none of your Border lines cross. v"zAdjusting the screen viewv"z If you could not see the entire PCB outline to perform the above step, you will have to scroll or zoom the screen. The cursor keys between the main and numeric keypads move the screen view in the direction of the arrow until you hit a boundary. The four Cyan bars at the center of each edge of the main display also scroll the screen, if they are visible. The <Del> key toggles their display. Pro-Board Demo manual P. 20 Section 5.2: Simple example Zooming out to view more of the screen is done with the <Alt><Z> hot key. Every function can be performed in Zoom mode, but Text is not visible. Repeated Zooms will reduce the size of the displayed image until it is completely displayed on screen. To return to normal viewing size, press Alt-N. Now that you have a border for your PCB, you can proceed to the autoplacement menu, Auto-P. The IFKs under Auto-P are as follows: v"zF-Area Orient Glue PGrid Auto-P Group Pass1 Pass2 -Part Improvv"z For this simple exercise, we will not need F-Area, Glue, PGrid, Group, Pass2, or -Device. Descriptions for them are in the next section. Depending on the size of your PCB and the speed of your system, this next step could take a while. If the entire outline of your PCB cannot be seen on-screen, enter the Hot Key combination <Alt><Z> (Zoom). Enter Pass1 and see the following icons: v"zGroup0 Group1 Group2 Group3 Group4 Group5 Group6 Group7 Pass1 Gov"z Press Go. You will see a prompt about deleting Unglued parts and continuing. This is a warning so you will not lose the position and orientation of parts you forgot to lock in place. We are not considering that now, so don't worry about it. Press `Y' to continue. A 3"x2" PCB with 5 DIPs running on an Amiga 3000 or equivalent will autoplace the components in about 4 seconds. Autoplacement will take into account the interconnections between the parts, but will also consider the difficulty in routing many connections through closely grouped parts. So your initial placement will not be as tight as possible, but as tight as the algorithm thinks practical. If you did not change the default orientations allowed for autoplacement, all the parts will be aligned either vertically with Pin#1 at the upper left or horizontally with Pin#1 at the lower left. Exit Pass1 by tapping the Escape key or moving the mouse cursor over the IFK region and Clicking the RMB. Select Improv, Swap, and Nest. With the Rat's Nest now displayed, you may see some obvious problems. The autoplacement algorithm does not consider whether traces will cross each other to make their connections. Select HistGr to see a Histogram of the routing difficulty. Yellow is a caution and Red means that routing will probably be very difficult. Even if the Histogram says `OK!' (for very low channel density), you may still not be able to autoroute the PCB due to the order of the connections in the Net List. Pro-Board Demo manual P. 21 Section 5.2: Simple example While still in the Swap menu, Click on the ad Master layer next to the WORK layer label if it is not already activated. Now Click within the Bound of a part. It will ghost and Guide Lines denoting Net connections between the Device and other parts will be displayed. Click with the Right Mouse Button and note that the Device is shown normally. This is an example of Exiting an operation instead of completing it. Most operations can be Exited in this manner. Click on the part and another part to Swap positions. With both parts ghosted, Guide Lines will display from the proposed new positions of the parts to other parts so you can guage the usefulness of the Swap. Note that the two parts will not display any Guide Lines between them. Use the Move, Rotate, and Swap commands to play with the parts until you are familiar with them. Note that a part cannot be modified such that its Bound crosses another Device Bound or a Pin overlays a trace or another Pin. Remember to Exit from one function to enter another. v"zPreparing to autoroutev"z To get to the autoroute menu, Auto-R, Exit until you reach the main menu: v"zRule SetRef Border Place Auto-P Route Auto-R Draw Save Postv"z Do not worry about Exiting too far. A prompt to Save, Quit, or Continue occurs when you try to Exit from the main menu. Upon entering Auto-R, you will see the following IFKs: v"zF-Area R-Rule SelNet SetWei RipUp Auto-R Go ReRout ViaOptv"z As before, we will not use some of the options and menus. F-Area has the same effect on traces here that it had on parts under Auto-P. SetWei allows setting Weighting priorities to individual Pins or to entire Nets associated with a Pin. This allows `fine-tuning' the autorouting process to accomodate special cases. RipUp is an option that allows the autorouter to Rip Up all connected traces if any Nets fail to route and start over. Enter R-Rule to see the Routing Rule screen. Via Number determines the autorouting method. The first four make use of the Channel algorithm. The fifth, 1Lay, makes use of the Maze algorithm. The Channel algorithm is used for all two-layer autorouting methods because of the exponential increase in processing time that would be consumed by a multi-layer Maze autorouter. Trace Width allows full autorouting in any of ten Trace Widths. Currently, only the 12 mil traces will be autorouted at 45° angles. Speed trades off `thoroughness' against speed. `5' is the fastest. For simple boards, you will not notice a difference in either speed or Pro-Board Demo manual P. 22 Section 5.3: Typ. autoplacement simple boards, you will not notice a difference in either speed or results. As your projects become more complex, you may want to experiment with this setting. Channel Width influences the autorouter's decision to switch layers in order to make a connection. When routing traces which have both vertical and horizontal moves required to connect the Pins, it is usually more successful to route the vertical trace segments on one layer and switch between layers depending on the direction. Automatic connections between layers are made with Vias which, though usually smaller than Pads, will still force traces in the two adjacent channels to make a course correction. The Channel Width setting controls how much deviation from vertical or horizontal is allowed before switching layers. The larger the number, the greater the allowable deviation. The setting which is best for your PCB will depend on the layout and is best found by experimentation. The Nets to be autorouted are Selected in SelNet. For now, just Select AllNet, answer the prompt with `y', and Exit to the Auto-R menu. v"zAutorouting the PCBv"z Press Go. v"zEvaluating the resultsv"z Your PCB may or may not completely autoroute. This will be a function of component layout, density, orientation, and the Net connections which have to be made as well as the order in which they are made. If your PCB did not completely autoroute, you have four main options from here: manually Moving, Swapping, or Rotating components to improve the layout; manually Deleting and Adding traces in Route/1Layer mode; manually altering traces in Route/Modify mode; or using SetWei to alter the order in which the Nets or Pins are presented for autorouting. Only a practiced eye can tell which approach is best for a given situation. v"z5.3v"z v"zTypical autoplacementv"z Here we will expand on the simple design process covered in the previous section. It is assumed you are sufficiently familiar with the basic functions already presented. In most PCB designs, certain parts will have to be in specific locations. Examples include goldfinger edge connectors, input and output Jacks, and ICs which you know beforehand would be best located in a certain position and orientation. In addition, some areas of the PCB have to be kept clear to allow for mounting holes, brackets, or height restrictions. If your PCB is designed to be mated with a motherboard, it will also have to conform to certain size and shape restrictions. Pro-Board Demo manual P. 23 Section 5.3: Typ. autoplacement v"zOutlining your PCBv"z Assuming you have followed the instructions in Section 5.1: Required Files and Preparation, we are ready to begin. You should have the manufacturing blueprints for the board with the measurements available. After Exiting the Design Rule screen, Select SetRef. Scroll the screen as needed and Click at a location that corresponds to the corner of your PCB from where most measurements are made. Be sure to leave room for the goldfinger edge connector, normally 0.3" below the main edge of the PCB. Using the relative coordinate display, Click at the corners to specify the outline of the PCB. Forming 45° angles at the corners of the goldfinger connector area will make insertion easier. When finished, Select Next to finish the Border. Exit the Border function and Select Place. v"zManually placing partsv"z Referring to your BOM and remembering the cross-reference information you specified in Foot-P, Select DIP, SIP, 2-Pin, or Lib* to enter the corresponding Device and enter the Device Label (U1, C4, etc.). Pro-Board will supply the rest of the information (number of pins, row separation, pin separation, and/or Library Part index) from the Part List. Pads and Thermos are not labelled Devices; they will never be referenced in a Net List. If you want a one pin Device, specify a SIP with one pin. Now that you have entered the Device Label, the Device will appear ghosted on screen with its Pin#1 at the location of the mouse cursor (if the cursor was not over the IFK region or the Entry Bar). If there are other Devices already placed, Guide Lines will be displayed for any pins sharing the same Net. While the Device is ghosted, you can alter its orientation by Selecting the corresponding IFK arrow. Drag the Device by pressing and holding the Left Mouse Button while moving the mouse. To Settle the Device, position the mouse cursor within the Device's Bound and Click the LMB without moving the mouse. Once you have manually placed all the Devices with required locations, Exit to the main menu and Select Auto-P. F-Area sets forbidden areas which will be ignored by the autoplacement routine. Forbidden areas can be formed from circles and boxes on the ad Master, Component, and Solder side layers**. Select one of these layers by Clicking on the P gadget to the right of the WORK label or one of the numbers to the left of the PAIR gadget. Screw holes and space set aside for brackets can be marked so the autoplacement routine will avoid them. A forbidden area will prevent a Device from being autoplaced within its area even if only part of its Bound overlaps the _________________________ * Library Parts are created in v"zPro-Libv"z. ** See v"zTerms and Conventionsv"z for a description of the layers. Pro-Board Demo manual P. 24 Section 5.3: Typ. autoplacement if only part of its Bound overlaps the area. If you later enter Place and try to manually position a Device so that it overlaps a forbidden area, you will receive a prompt asking if you wish to continue. v"zGuiding autoplacementv"z Glue locks in place components you have positioned manually. Upon entering Glue, every Device which is not Glued will ghost. Select the proper Work layer (usually ad Master... SMD parts will be on the Component or Solder layers) and Click the LMB within the Bound of the Devices you wish to Glue. Click the RMB for any Device you wish to UnGlue (ghost again). When finished, Exit to the Auto-P menu. Orient sets options on how you want Devices Settled. Forcing every Device to be horizontal and point to the right will generate a placement which is very regular and looks very nice, but may not be ideal for routing. Allowing every orientation may give you a board which is easier to route, but can cause problems when you go into mass production and are relying on a bleary-eyed assembler to meet your deadline. The defaults allow two of the four possible orientations that are used on most boards. You may change them at your leisure (and risk). v"zPlacement Gridsv"z PGrid allows you to define a Placement Grid which controls the autoplacement process. Devices will be positioned only on grid intersections in one of the orientations allowed in Orient. The Device's Pin#1 will be at the grid intersection. When specifying a Placement Grid, you must take into account the area covered by the Devices. It is possible that Devices already placed will obscure several grid intersections. If you don't provide enough intersections, the autoplacement process will stop. PGrids may be saved and loaded with unique names. It is feasible to use several PGrids dedicated to specific Groups of components (see the description for Group which follows). If you have similar boards with slight modifications, you may use the same PGrid over and over on different boards. If you decline to use a PGrid, Pro-Board will dynamically generate a placement grid based on the components to be placed and the interconnecting Nets. Parts will usually not be placed in line with each other, so be warned if you want your PCBs to look orderly. v"zGrouping to control autoplacementv"z Group is useful for more complex PCBs with many Devices. When placing Devices, the autoplacement algorithm considers every Device in the group which has already been placed in addition to the Device it is attempting to place and evaluates them for the lowest Cost. Assigning Devices a Group Number reduces the number of other Devices the algorithm has to consider when placing each Device. Used in conjunction with PGrid (which can reduce the area to be considered for placing the Device), the autoplacement process can be considerably faster. Pro-Board Demo manual P. 25 Section 5.5: Library Part Design Grouping is best done manually by looking at your schematic and using the Device command to assign each Device Label a Group Number. A semi- automated process would be to assign Group Numbers to larger parts as `seed' values and using the AutoGp function to assign the rest. A wholly automated process would be to use AutoGp without first assigning the seed values. The reliability of this approach will depend on the Net List. After Group Numbers are assigned, the Pass1 function is used for specific groups, perhaps with different PGrids for each group. v"zOptimizing intergroup connectionsv"z Pass2 is used after all the groups are placed. Its purpose is to adjust the position and orientation of groups so that the interconnections with other groups are optimized. Deciding how many groups to optimize at one time depends on the specific circuit. If your groups have distinct interconnections to some, but not all, other groups, choosing which groups to optimize is fairly obvious. If the Net List is a web of interconnections, your task becomes more complex. v"z5.4v"z v"zRouting a single layer boardv"z The example in Section 5.2 used the standard autorouting method for connecting Pins; routing vertical connections on one layer and switching layers when changing direction. This is not always the best method. Vias add inductance, a drawback for high frequency designs, and increase manufacturing costs (slightly). On some boards, adding Vias will actually decrease the routability of a layout. Proper layout of a single layer board requires a closer inspection of the Net List and Device Footprints. While both placement and Net routing order affect your results, the most important consideration is the Pinout of the Devices. Careful selection (and proper design if you are using Programmable Logic) goes a long way to increasing the success of your project. A series of examples showing the effect of part placement and Net weighting on the success of an autoroute is shown in Section 7: Tutorials. Most routing failures occur because other traces were routed on either side of the Pin. Try using SetWei to alter the routing order or the functions in the Route/Modify menu to alter the traces. v"z5.5v"z v"zLibrary Part Designv"z Library Part design is performed in the separate utility, Pro-Lib. Pins can be defined as regular PadPins (circular and present on every layer) or as rectangular BoxPins (which are present on only one layer). Either type of Pin can have arbitrary size and separation, with the defaults being commonly used settings for thru-hole pins and goldfinger boxes. You do not have to assign a number to every Pin. Some of the PadPins you define may be for mechanical mounting instead of electrical connections. They will not require numbers. Pro-Board Demo manual P. 26 Section 5.5: Library Part Design Library Part names are Case Sensitive. You can do what you want, but I keep all my Library Part names lower case. Note: ===== Pro-Lib supports dual-layer Library Part design, which is useful for Goldfinger edge connectors. If you want a Surface Mount Device to be used on the Solder layer, it has to be defined on the Solder layer. v"zCustom Headerv"z PCB mount Headers (used as cables connectors or as jumper blocks) are similar to DIPs with a row separation of 0.1" except that Pins are numbered differently; odd on one row and even on the other. The following instructions show how to create a header with a 0.1" row separation and 36 Pins. Start Pro-Lib, specify New, and enter the name `header2x18' and a 25 mil grid. Select SetRef and Click in the left center of the screen to specify a convenient starting point. Select PadPin and Size to review the defaults, then Exit. Select Comm. As you have already specified a local origin with SetRef, enter 0 for `X' and `Y', and 18 for the `Repeat time' prompt. Enter Comm again and enter the row separation value in `Y' (this assumes you have kept the default orientation to the right... if you are defining your Library Part vertically, enter the row offset value in `X') and the same number of Pins (18) in `Repeat time'. You now have 36 Pins on screen waiting to be numbered. Exit back to the main menu and Select PinNum. Click on any Pin in the first row. Enter the initial Pin number (1) and the Increment (2). All of the Pins which were created in one operation will be numbered. Only the first and last Pins of the sequence will display the numbers, however. As this manual is written, the PadPins associated with a specified PadPin are not highlighted. Click on any Pin in the next row and enter 2 and 2 for the prompts. Exit to the main menu. If desired, you can Draw an outline for the header or add text to identify some of its Pins. Exit to the main menu and Select Bound. Click to specify the diagonal of the rectangular Device boundary, and Drag and Settle the Device name (displayed as `XXX'). Save the Library Part and it is ready for use in Pro-Board. v"zGoldfinger edge connectorv"z Specify a unique name for the goldfinger edge connector, preferably one that will remind you of its purpose next year, and a 25 mil Grid. Select SetRef and Click in the center left of the screen. Select BoxPin and Click on the <S>older side layer. Pro-Board Demo manual P. 27 Section 5.5: Library Part Design To create 31 Pins, you can Click at any convenient location and Select the Repeat key 31 times, or you can Select Comm, enter 0 for `X' and `Y' and 31 for `Repeat time'. Select the <C>omponent layer and use Comm to create another 31 Pins at the same location. The Pins on the Component layer should overlay the Pins on the Solder layer. The resulting display will be Yellow (yeah... we know it's the ad Master color, but Red and Green add up to Yellow). Now that you have already created the run of goldfingers, you remember that the pins are usually numbered from right to left with Odd numbers on the Component layer and Even numbers on the Solder layer. You could Delete the two sets of Pins and start over with the <Left Arrow> orientation (remembering to SetRef on the right of the screen to give you enough room to Repeat to the left), but there is a simpler solution. Exit to the main menu and Select PinNum. Verify that you have specified the Component layer in the WORK gadgets and Click on any of the Pins. The sequence of BoxPins to be numbered will highlight in Cyan and the prompt will ask you for `PinNum' and `Inc'. Enter 61 and -2. The first Pin will be assigned the number given `PinNum' and the rest will be incremented or decremented according to `Inc'. Switch to the Solder layer by either Clicking on <S> in the WORK gadgets or hitting the <Alt><T> hot key. Click on any Pin and enter 62 and -2. With the operational basics covered in the previous two examples, we will cover the points to consider when creating the following devices. v"zPGA Devicev"z The main drawback to creating PGA devices is the fact that Pro-Board deals with Pins by number only and many PGA devices specify Pin location by means of an alphanumeric grid with rows marked with letters and columns marked with numbers. You will have to develop a cross-reference between the PGA's alphanumeric designation and a Pin number which will be used by Pro-Board. There are three solutions. One is to number each PGA Pin in sequence as each new Pin is encountered. There are at least 2 variations of every NxN package size from 11x11 up to 15x15, each with a different number of Pins. When you create the Device in Pro-Net, that will not be a problem as the display of the gate functions will not look like the physical layout. But to have two 13x13 PGA Devices with the upper right Pin numbered either 114 or 121, depending on the package, can be confusing. The second method is to create the NxN PGA with the configuration that Pro-Board Demo manual P. 28 Section 5.6: Tips and Tricks that has the most Pins and use it for every NxN PGA Device. This leaves unused Pads on your PCB for those Devices with fewer Pins. This can be confusing, will raise the cost of producing your PCB, and could make it more difficult to route. The third approach would be to assign a numeric value to each row (i.e. a 14x14 PGA would have rows A thru N given values of 0, 14, 28, 42..., 182) and add the Pin column to yield a unique number. With this approach, the same number will always correspond to a given alphanumeric grid location. Note ==== Users of earlier versions of Pro-Board may be confused by the way Repeated Pins are treated. Prior to V3.0, you could create a sequence and Delete individual Pins from the sequence. Deleting any Pin in Pro-Lib now Deletes the entire sequence of Pins that was created along with the Deleted Pin. When creating Pin sequences, the temptation is to create the longest, fewest sequences. This will require extra computations to determine the correct starting number and increment for each sequence. A drawback is that you may overlook a Pin (by thinking it is included in another sequence) and not number it. You may be more comfortable creating many smaller sequences and proceeding row by row. Remember that Pin sequences are numbered only at the ends. v"zPLCC Devicesv"z Creating PLCCs is a bit less arduous than creating PGAs. The numbering sequence is numeric and there are no gaps in the Pins to consider. The only point to remember is that Pin #1 is usually Top Dead Center, so you have to create two sequences of Pins on the top row in order to number them correctly. v"z5.6v"z v"zTips and Tricksv"z The solution to a design goal may not be so obvious at first glance. In this section, we cover some common applications and an approach to the solution. v"zTwo layer boardsv"z When routing a two layer PCB, there are no Power or Ground planes for the supply and return paths. That means that Voltage and Ground will be routed as Signals just as the other Nets. The drawback comes in automatic placement (Auto-P) when the Power and Ground signals affect the placement algorithm. There are two methods to avoid this problem. One is to create two Net Lists in Pro-Net, with and without Power Planes. Use the Net List that includes the Power Planes to autoplace your components. Then enter the Design Rule and change the Net List name to the one which has no Power Planes to continue with the (auto)routing. Pro-Board Demo manual P. 29 Section 5.6: Tips and Tricks The other method, required if you have more than one voltage supply on your board, is to edit the Net List in the text editor of your choice and eliminate any Power and Ground Nets (which will always be at the top of the Net List when you do not have Power Planes). v"zGround plane on a 2 layer boardv"z In Pro-Net's Post Processor, specify an unused voltage as the Power Plane. Only the Ground plane will be generated in the Net List, while the +5V power supply connections will be treated as a Signal Net to be routed along with all the other Signal Nets. In Pro-Board's Design Rule, specify 1 Signal Pair with Power and Ground planes (as if you were designing a standard 4 layer board). Route on the Solder side layer only. If you cannot completely route on the Solder side, there are two solutions. One is to Place some Pads and route between them on the Component layer. When you are stuffing your board, use jumpers to make the connections between those Pads. If you are going into production, it would be a good idea to plan ahead and use zero-resistance Devices which will be included in the BOM. The other approach would be to Draw lines on the Ground layer around the desired connection (i.e. etch a path around the copper that will make the desired connection). This is more difficult and requires more care. In addition, Pro-Board will not consider the connection to be a trace and will flag it as an error during Check. v"zMultiple Power Planesv"z Multiple Power Planes require some tricks with a text editor. First, be sure that each Device in your schematic has the proper voltage specified for power pins which are not displayed (check the Attributes under DefDev in Pro-Net). When a Net List is generated in Pro-Net's Post Processor, the default Power Plane Voltage is +5V. Left as-is, the Nets labelled +5V and +0V will be placed in the Power Plane. If, say, the +12V supply is specified as the Power Plane voltage in Pro-Net's Post Processor, that Net will be in the Power Plane and the +5V Net will be in the Signal Nets along with the regular Nets. Knowing how the Power Plane is specified, we now know what to do... Generate a Net List with one of the supplies as the Power Plane. Copy the Net List to another name and edit the new file. Find the Signal Net for the other power supply and move it to the end where the Power Plane is specified. Delete the first supply's Net from the Net List and save the new file. If you have more than two power supplies, make new Net Lists for each supply as the Power Plane. Start Pro-Board and generate a Part List for one of the Net Lists, then copy it for each of the other Net Lists. Now, load the Net List which has had all the supply voltage Nets removed (from the Signal Net area as well as the Power Plane). Use this Net List to place and route the board, then save this PCB data file under a unique name. Pro-Board Demo manual P. 30 Section 5.6: Tips and Tricks When your PCB is placed and routed, return to the Design Rule and load one of the Net Lists with a Power Plane. Then Select Place/Thermo/DelAll, then Auto. Save this PCB with a name that references the value of the Power Plane voltage. Repeat for each Net List which has a different Power Plane voltage. After you have created all your PCB data files, use Pro-Plot's Photo capability to generate Gerber photo plotter files for each of the PCB data files. Use all of the Gerber files generated from your first PCB data file (the one without any power supply voltage Nets), the .GND file from any of the Power Plane PCB data files, and the .PWR files from each of the PCB data files which included a Power Plane. v"zPseudo Ground Planev"z A two layer PCB with traces on both sides can have sections of the Component layer set aside as a pseudo ground plane. When routing (auto or manual), set a Forbidden Area on the Component layer around the area to be the pseudo ground plane. After all the Devices are placed and traces routed, Draw the pseudo ground plane on the Component layer, avoiding the Pins and Vias which are not grounded. v"zAutorouting Power & Ground tracesv"z Autorouting Wide traces presents some difficulties. A complete autoroute will attempt to minimize Channel allocation. The PinRou function in Route/Wide uses the Channel algorithm, which only routes from Pin to Pin. The Maze algorithm, however, will route from a Pin to an existing trace if it makes the lowest Cost connection. Manually routing the skeleton of a power distribution buss and letting the autorouter connect the Pins to it would provide the best solution. Therefore, the approach would be to manually route Wide traces to form the skeleton of the buss, then shift to the autoroute menu, Auto-R. Select 1Lay in the Routing Rule. Be warned... the Maze algorithm takes much longer than the Channel algorithm. v"zSingle-ended Ground Tracesv"z In low noise analog applications, it is often useful to isolate a trace with one or two grounded traces that are only connected at one end to avoid ground loops. There are two ways to accomplish this. After Training the signal trace (to make sure you have enough room on either side), you can manually route the ground trace alongside the signal trace. There are two means of defining an open-ended trace. The first is to use Route/Wide with a 12 mil Trace Width to frame the trace and Next to end the trace without connecting it to a Pin, Via, Pad, or Tile. The drawback is that Wide traces only connect in straight lines, so Training it is not as easy. The second method is to use Route/1Layer, ending the trace with a Tile or Via. Training the trace is easier, but room must be set aside for the Tile or Via that ends the trace. Pro-Board Demo manual P. 31 Section 5.6: Tips and Tricks v"zMultiple PGrids for autoplacementv"z For advanced users. Suppose you have a schematic with 4 ICs, each with 4 associated resistors and 3 capacitors. It is feasible to put the ICs into Group 1 for an initial Placement on a large Grid, Glue them, then reassign the ICs into Groups 1-4 and Group the resistors and capacitors into Groups 1-4 to be with their IC. Then apply separate 100 mil PGrids around each Group for actual Placement. Pro-Board Demo manual P. 32 Section 6: Pro-Lib v"z6.v"z v"zPro-Libv"z Defining Library Parts for some Devices is not always straightforward. Some PGAs, for instance, have a Pin designation scheme which is alphanumeric. In instances like this, you must develop a cross- reference between the PGA Device and the Library Part that represents it. See Section 5.5: Library Part Design. On a related note, it is not necessary to number every Pin in a Library Part. Some Pins may be needed only for mechanical mounting, not electrical connections. Pro-Lib will remind you if there are any unnumbered pins when you save the Library Part, but you are allowed to save definitions with unnumbered pins. You should note, however, that Pro-Board PCB data files maintain a copy of all Library Parts, as well as the Net List, for portability. A PCB data file can be sent via network, modem, or disk without having to copy the Library Part file and index (afilib and afiind) or the Net and Part Lists. If you change a Library Part, you will have to Delete all instances of the obsolete Library Part in your PCB AND re-load the Net List (under Rule) before the new Library Part definition will be loaded. Pro-Lib allows you to create custom Library Parts for use on Fine Line or Standard PCBs. Pins can be Through-hole Pads or Surface Mount Technology boxes, but any electrical path can be drawn using the various tools in the Draw menu. Once the electrical pathways are drawn, labels and outlines can be drawn on the <L>abel layer to provide orientation information during assembly. After the Library Part has been drawn, a Bound must be added before the part can be Saved. The Bound is used during the (auto)placement process to insure that parts do not overlap. The Bound does not have to surround the entire Part. It is common for the Label artwork to extend beyond the Bound to provide orientation information. Pro-Board Demo manual P. 33 Section 7: Tutorials v"z7.v"z v"zTutorialsv"z With the release of Version 3.0, Pro-Board provides unprecedented power for placing and routing Printed Circuit Boards. As with any high-end productivity program, some experience is required to get past the learning curve. We have provided several tutorials to demonstrate the capabilities and power of Pro-Board to get you up and running in a short time. The PCB file TUTORIAL.APCB is provided on the second distribution disk, Pro-Data. If you are running from floppy, place your back-up of Pro-Data in DF1: (or DF0: after you have booted Pro-Board if you only have one floppy). If you are running from hard disk, the PCB data file should be in the directory you specified in Data. If you updated an existing Pro-Board installation, the Tutorial data files and Library Parts will not be available unless you copied them manually via Pro-Board's and Pro-Lib's File Management utilities. The simplest method would be to adjust <Config> to point to your floppy drive (DF0: or DF1:) and use a backup copy of Pro-Data. The reason is that, if our installation procedure copied the Library Part file and index as part of an update, those that you already created would be destroyed. Start Pro-Board*, Click the mouse or press a key to get to the first menu, and Select (press the corresponding Function Key or move the mouse cursor over the IFK and Click the Left Mouse Button) <Config>. The Plotter, Photo Plotter, and Drill file selections will not affect anything in these tutorials. If running from floppy, enter DF1: in the Data: and Lib: prompts. Or enter DF0: if that is the drive you used. You could also enter the volume name of the floppy disk, Pro-Data:. If that doesn't work, either you didn't put in the correct floppy or it was misnamed when you copied it. Switch to the Workbench screen (Left Amiga-N hot key combination) and check. It may read as Copy_of_Pro-Data. In this case, single click on the disk icon and select Rename from the pull- down menu (under Workbench in AmigaDOS V1.3 and under Icon in AmigaDOS V2.0) If running from hard disk, enter the disk or volume used in your installation. Select Use to Exit back to the opening menu and then Edit. Use the IFKs to Highlight the file TUTORIAL.APCB and Select Pick, or move the mouse cursor over the Highlight bar and then so that it overlays the file TUTORIAL.APCB and Click the Left Mouse Button (LMB). _________________________ * CLI and Workbench startup described in Section 4. Pro-Board Demo manual P. 34 Section 7.1: Simple autoplacement v"z7.1v"z v"zSimple autoplacementv"z You will notice right off that there are no Devices placed on the PCB. All you see is a Yellow box surrounded by a Purple box. The Yellow box is the Border which limits placement and routing. It is drawn to the form factor of your PCB, including any cutouts for Goldfinger edge connectors, etc. The Purple box is the physical range of the PCB itself, which extends slightly beyond the dimensions specified in the Design Rule. The schematic which was used to generate the Net List in Pro-Net is a nonsensical collection of five ICs with no particular meaning in their interconnections. I tried designing a circuit that would actually do something, but it kept getting bigger and bigger or using Library Parts, so that wasn't going to work. Then I thought of expropriating a design from an electronics magazine, but didn't want to worry about the copyright restrictions. Then I thought about what we actually want to learn and came up with what you see. It actually works rather well for demonstrating various aspects of Pro-Board. The Design Rule for this PCB specifies a 4-layer PCB, comprised of 1 Signal Pair (giving 2 Signal layers) and Power & Ground Planes; Standard Trace mode (no Fine Line activated for this example), and is 3" wide by 2" high (chosen so that it will fit on the screen). Seeing as how we are already 3 pages into the tutorial, let's see how this autoplacement routine we've been bragging about really works! The Net List and Part List have already been attached to the file, even though nothing shows on the screen. Select Auto-P to enter the Automatic Placement menu. There are several functions available, but we will just use two. Select Orient and verify that only the orientation options <Right Arrow> and <Down Arrow> are activated. Select an arrow to switch it On or Off. Then Exit (the <Esc> key or place the mouse cursor over the IFKs and Click the Right Mouse Button) and Select the autoplacer, Pass1. All Group numbers should be Highlighted (Group is explained in the Top Down Design section) and Select Go. Answer `y' for the "Delete UnGlued Parts?" prompt. You will see the five ICs placed on the PCB with U3 in the upper left corner. U3 is placed first because it is the largest IC in the Groups which are being placed. By `largest', we do not mean the physical size (obviously... because there are two other 16-pin DIP ICs). We are referring to the number of Nets which connect to the IC. As this manual is being written, the automatic placement algorithm is still being fine tuned. It is probable that the results you obtain will differ from mine. You can continue with the autorouting example by loading the PCB data file TUTORIAL2.APCB. Pro-Board Demo manual P. 35 Section 7.1: Simple autoplacement This is as good a place as any to discuss how the autoplacement routine works. As you may have noticed when the ICs were being placed, an IC could be picked up and put somewhere else when another IC is placed on the PCB. The Pass1 autoplacement routine evaluates the Cost of the total placement every time it brings in a new Device, taking into account not only the Devices which connect to each other, but the number of interconnections. Devices are not placed as close to each other as possible as it would increase the difficulty of routing between the Devices in all but very special circumstances (i.e. custom ICs designed to connect their Pins in sequence). The Cost function estimates the number of routing Channels necessary to route the Devices and places them accordingly. Now let's quickly see just how useful this is to us by checking the autorouter. The autorouter is usually not the best way to evaluate a placement, but we figure you are eager to see what you've got in this version of Pro-Board. Return to the Main Menu by Exiting twice. Don't worry... you can't lose your PCB without answering a prompt. If you use the Exit function too many times and get the "Save, Quit, or Continue? (s/q/c)" prompt, just enter `c'. The Main Menu will have Auto-R in the seventh IFK. Select Auto-R and R-Rule to alter the settings. Use the mouse to Select 1LAY. Leave Trace Width on 12, set Speed to 3, and leave Channel Width at 7. You have just specified the Single Layer autoroute. It is the slowest, but provides the best results on individual traces. If we were to use the other methods (except 0Via), we would be hard pressed to come up with a simple PCB layout that would not completely autoroute, so we will use a single layer to demonstrate the basics that will apply to all situations. We won't be worried about the speed here as the task is so small. An unaccelerated Amiga 500 will take about 45 seconds. A 25 MHz 68030 machine will take less than 5 seconds. Select Nest, AllNet, then `y'. Exit once and Select Go. The autorouter will now kick in. When it is finished, you should see something like the arrangement in TUTORIAL3.APCB. v"zImproving autoplacementv"z There are several ways of improving the results of an autoroute. You may think that a completed route doesn't need to be improved, but that will not always be the case. Look at the traces on the PCB. The layout is somewhat convoluted and three traces failed to route. One option for improving the routing is to alter the order in which the traces are routed. Another would be to adjust the placement of the Devices or altering their orientation. To get an idea which would be better, take a look at the Rat's Nest. The quickest way to see it from the Auto-R menu is to Select SelNet, then Nest, AllNet, and `y'. Pro-Board Demo manual P. 36 Section 7.1: Simple autoplacement To see the Guide Lines more easily, Click on the DISPLAY gadgets , <1>, and <2> to turn display of these layers Off. Tap the <Enter> key on the numeric keypad to refresh the screen so the Guide Lines will show. Note the connections to the left side of U3 that connect to the right side of U1. U3 was placed first because it has the most connections. But because it wasn't Glued in place (a topic to be covered later), it was placed in the upper left corner in an attempt by the autoplacement algorithm to minimize the required board space. It is readily apparent that, for this circuit, adjusting the positions of the ICs will be of more use than altering the order in which traces are routed. Exit to the Main Menu and Select Auto-P, then PGrid. Select Ver and Click the mouse when `x' is at 0.5, 1.4, and 2.275 inches (12.70, 35.56, and 57.78 mm). Select Hor and Click the mouse at `y' values of 0.475, 1.0, and 1.475 inches (12.06, 25.40, and 37.46 mm). Exit once and Select Orient. Set the orientation option <Right Arrow> On and the others Off. You have now specified a Placement Grid which restricts the available locations for an IC and restricted the Orientation so that ICs will only point to the right. Don't forget to turn the DISPLAY gadgets , <1>, and <2> On. Exit once, re-enter Pass1 and Select Go followed by a `y' for the prompt. U3 will still be placed in the upper left available grid location. The results will now be better ordered, but will it help our autoroute? The first time, we used the autorouter to evaluate the usefulness of the autoplacement. That was so you could see the autorouter in action. This time, we will use the tools designed to improve placement. Exit Pass1 and Select Improv, then Swap followed by Nest. Notice that U3 was, again, placed in the upper left of the available area. Because of this, the proposed connections have other ICs between them. There was a reason you were steered to the Swap menu. Make sure the WORK gadget is activated (if you remained on one of the Signal layers, you could only Swap SMT Devices) and Click on U3, then U5. The Devices will swap positions and be ghosted. Click again to verify the swap. We could, if we chose, move each of the Devices manually for what our eyes would tell us to be the best placement, but where's the fun in that? It certainly doesn't help to show off the features of Version 3.0. Exit twice to the Auto-P menu and Select Glue. Every Part which is not Glued in position (that is to say, all of them) will ghost. Remember which outline corresponds to U3 and Click within its Bound. It will now display normally. Pro-Board Demo manual P. 37 Section 7.1: Simple autoplacement Select Pass1, Go, and `y' for the prompt. All of the Devices which are not Glued (U1, U2, U4, & U5) will be deleted and the autoplacement process will start. With the PGrid we set up, these ICs are arranged around U3. The file TUTORIAL4.APCB corresponds to this image (after a successful routing). Switch back to Auto-R, verify that all the Nets are Selected for autorouting in SelNet, Exit out of SelNet, and Select Go. The PCB autoroute will now fail on three traces. Select SelNet, Remain, NoNet, and `y'. The tell-tale hint is the pair of Guide Lines from U2 heading over to the left side of U3. Unfortunately, U5 has a higher placement priority vis-a-vis U3 because there are more connections between the two than between U3 and U2. As usual, there is more than one means of dealing with this situation. We'll take a look at both. v"zSwap to improve routingv"z The simple solution is to Swap U2 and U5. Exit back to the Main Menu and Select Auto-P, Improv, and Swap. Make sure the gadget is activated on the WORK layer and Click within the Bounds of U2 and U5, and again to verify the Swap. Traces with only one end connecting to either U2 or U5 will disappear. Traces which begin and end at the same IC will move along with it. Now return to Auto-R, make sure that all the nets are Selected by entering SelNet, then Selecting Nest and AllNet, followed by `y', then Exit and Select Go. The remaining Nets will be autorouted. If you had Selected ReRout, all of the routed traces would have been deleted prior to autorouting and the Net from U1 Pin 8 most likely will have failed. Here, the simplest solution is to adjust the routing priority with SetWei. Unless you have used the AllNet function to change the Weights of all the Nets, the default Weight will be `0'. Click on U1 Pin 8 and change the prompt to `1'. Hit return, Exit, and ReRout. The PCB will now route successfully. We now have a completely autorouted PCB, but with a better layout than when we started. v"zAdjust PGrid for improved autoplacementv"z It is obvious that U5 should have been placed to the right of U3 by the autoplacement routine. The questions are; "Why wasn't it?" and "How do we fix it?" The autoplacement routine takes into account not only the Cost of placement, but the perceived difficulty in routing. If feasible, it will avoid placing a Device too close to the Border as well as too close to another Device. We can compensate for this protective measure by altering the placement grid. Quit the current PCB and load TUTORIAL4.APCB. Select Auto-P and PGrid. If a grid is displayed, Clear it and Select Ver to enter vertical Grid lines for the `x' values of 0.3, 1.2, & 2.1 inches (7.62, 30.48, & 53.34 mm). Select Hor and enter `y' values of 0.475, 1.0, & Pro-Board Demo manual P. 38 Section 7.2: Define a PLCC Select Hor and enter `y' values of 0.475, 1.0, & 1.475 inches (12.06, 25.40, and 37.46 mm). Remember that U3 is Glued. Exit PGrid and Select Glue. Click with the Right Mouse Button within the Bound of U3 to ghost (UnGlue) it (if nothing happened, make sure that is the active WORK gadget). U3 will have to be Glued on the new grid or it will be placed in the upper left position, as usual when the largest Device in a Group is not Glued. However, U5 would have to be deleted before you could move U3 over to the desired location and the PGrid is not visible during Move so you would have to remember the coordinates (variable Grid Snapping is not available for manual placement). It is better to take advantage of the functions that have been provided. Now that U3 is UnGlued and the new PGrid is set, Select Pass1 and look at the new placement. U3, as expected, is in the upper left grid and U5 is where we want U3 to be. Exit Pass1, Select Improv and Swap. Click within the Bounds of U3 & U5, and again to verify the Swap prompt. Exit to the Auto-P menu and Select Glue. Click within the ghosted Bound that you know corresponds with U3 so that it becomes visible. If you Glue the wrong Device, you can UnGlue it by Clicking within the Bound with the Right Mouse Button. Now Select Pass1 and Go. After entering `y' for the prompt, the autoplacement routine will place the ICs. Switch over to the Auto-R menu, Select SelNet and AllNet, answer `y' and Exit, verify that the Routing Rule is still 1LAY, and Go. Your PCB should route completely. v"z7.2v"z v"zDefine a PLCCv"z With the new commands added for creating Library Parts, Pro-Lib supports SMT Devices much more easily. This example will detail the definition of an 84-Pin PLCC (also known as a Plastic J-Lead) IC that will Place on the Component layer. Pro-Lib requires 135,600 Bytes of Chip memory and 172,000 Bytes of Fast memory to start. Depending on your system, you may have to kill Pro-Board to get enough room. Start Pro-Lib and specify the same Data and Lib disks as in the Pro-Board tutorial of the previous section (if Pro-Lib is in the same directory as Pro-Board and you saved the configuration from Pro-Board, Pro-Lib will automatically load the same settings). Select Edit and New. When entering the Library Part name, remember that names are case-sensitive. For this example, enter `plcc_84'. Enter `20' for the Grid size. You are now at Pro-Lib's main menu. Move the mouse cursor to the upper right of the screen and note that you can create a Library Part of up to 3.180" by 1.840" (80.77mm x 46.73mm) without having to scroll the screen (on an NTSC display... more heighth is available on a PAL screen). The Library Part we are creating is less than 1.20" on a side. Select SetRef and Click at a point near the center of the Pro-Board Demo manual P. 39 Section 7.2: Define a PLCC screen. This will provide enough room around the origin for the actual construction of the PLCC Pins. v"zPreparationv"z Before creating a Library Part, you will have to collate information about the package, including its dimensions and the arrangement, number, and separation of Pins. The package drawings in the manufacturer's specs provide the information we need, but only after some calculations. Simple algebra will provide the numbers to be used. Remembering that Pin#1 in a PLCC is in the center of one row (usually shown at the top of the package), the coordinates and orientation to lay down the pins are as follows: v"zCoordinatesv"z v"zOrientationv"z v"zNumberv"z v"zXv"z v"zYv"z v"z of pinsv"z 0.008 0.595 Left 11 -0.595 0.508 Down 21 -0.507 -0.592 Right 21 0.595 -0.508 Up 21 0.508 0.595 Left 10 The numbers provide a coordinate location (English units) for the first BoxPin in each sequence and the number of Pins in the sequence. Some simple calculations and we see that each Pin extends 18 mils (0.46mm) beyond the package and the center of the first Pin of a row is 79.5 mils (2.02mm) from the corner. The width of a Pin where it contacts the PCB is 16 mils (0.41mm). You may have the idea to define a Pad area wider than the PLCC's Pin width to provide some hedge against an imprecise placement. This is not necessary and may be counterproductive. With a Pin separation of 50 mils and a Fine Line trace requiring 24 mils (8 mils for the trace and 8 mils on each side for clearance), you would think that the maximum Pin width could be 26 mils (0.66mm). What this fails to take into account is the fact that traces are routed on a 20 or 25 mil grid, depending on whether Fine Line is specified in the Design Rule. Even with a 16 mil Pin width, you will only be able to route between every other pair of Pins in Fine Line mode, as shown in Fig. T8, because the off-grid definition of the Pin Widths places some Pins too close to a channel. Pin length will be 65 mils (1.65 mm). v"zCreating the PLCCv"z First, Select BoxPin and Size. You will now see the prompts for the Pad size and separation: Enter the values .016, .065, and .050 inches (or 0.40, 1.65, 1.27 mm if in Metric) and Exit. Because the pin coordinates are not on a 20 mil grid (meaning we cannot use the mouse to create the parts at the desired locations), we will Pro-Board Demo manual P. 40 Section 7.2: Define a PLCC will use the Comm function to define a High Resolution Library Part with a resolution of 0.001" (.025 mm). We will create the sequence of Pins which includes Pin#1 first. Select <Left Arrow> orientation, then Comm. Enter the coordinates and number of Pins as shown in the table on the previous page. Now Select <Down Arrow> orientation and enter the coordinates and number of Pins for the left side. Continue around the PLCC. Remember that the <Enter> key on the Numeric Keypad at the right of the keyboard is the Screen Refresh function. To enter the values in a prompt, hit the <Carriage Return> key. When you have finished creating the Pins, Exit and Select PinNum. Click on a Pin at the left of the top row and the sequence of Pins will highlight in Cyan. Enter `1' for PinNum and Inc. Click on any Pin in the left row and enter `12' (one more than the highest number of the previous sequence) for PinNum and `1' for Inc. Continue on around the PLCC until each Pin sequence is numbered. Exit and Select Draw, then Circle. Click on the <L>abel gadget for WORK layer and move the cursor to 0.000, 0.480 and create a small circle to mark Pin#1. If you wish, you may also draw the outline of the PLCC's case. Exit one level and Select Line to draw the case outline. Don't use Box because there is a beveled corner at the top left corner of the PLCC which acts as an orientation key. Draw the line one grid location inside the pins to approximate the dimensions of the case. Exit and Select Bound. Use the mouse to specify a border for the Library Part. This border will determine how close other Devices can be placed. In this example, the Bound is 1 grid away from the Library Part. It is not required that the Bound completely surround the Device. Edges of lines drawn as an outline can extend to, and over, the Bound, as can Box or Pad Pins. Remember to Save your Library Part definition for use by Pro-Board. Pro-Board Demo manual P. 41 Section 7.3: Memory Card layout v"z7.3v"z v"zMemory card layoutv"z This section will be more of a Real World example of the process of laying out a PCB. It will include both automatic and manual placement and routing. The project is a 16-bit dynamic memory card with a refresh oscillator circuit. The circuit is intentionally incomplete, but still serves as a good educational tool. Sections of the schematic are included in the Pictures sub-directory. An HPGL plot of the schematic is also included, along with the PLT: device from Fred Fish #575 for those of you (like me) who don't have a plotter at home. The PCB will be a generic Plug-In Card (PIC) 8.6"x4.7", with a 0.3"x2.825" extrusion for the goldfinger edge connector. As you probably guessed from seeing the PCB list during earlier tutorials, the basic PCB definition is in MEMORY-BARE. Enter the Rule screen and notice that the PCB already has a Net List attached. The Net List, Part List, and Library Part definitions are included in a PCB data file so that it can be transportable (i.e. you don't have to copy a lot of incidental files along with a PCB data file when it is copied. If you have a 68030 machine and some time, you may want to enter the Auto-P routine and place the parts without using Glue, PGrid, Group, or the other tools which will improve the results. The file MEMORY1 shows the results I obtained. MEMORY2 shows what the board looked like after the autorouter got done with it. Obviously, the board would not be useful. Not only are there incomplete traces, but the Goldfinger edge connector isn't in a useful position. v"zCreating Library Partsv"z The custom parts required for this project have already been designed, but we will review the process. The Goldfinger edge connector has 56 pins arranged in two rows of 28 pins each. Their size and separation is standard (0.050"x0.300", with a 100 mil separation). Start Pro-Lib, Select New and enter a name (I used gf-56b, the third of three similar parts) and grid size (25). gf-56b has extra connections which may not seem obvious. While the fingers are expected, I added the through-hole pads to improve connectivity. PadPins provide a connection point on every Signal layer, while BoxPins connect only on the Component or Solder side layer. By adding PadPins, I made it easier to connect to the rest of the circuit. The connections between the PadPins and BoxPins were Drawn on the appropriate layer. Most connections used Lines (be sure to end each Line with the Next command or the segments will be joined). Those pins Pro-Board Demo manual P. 42 Section 7.3: Memory Card layout Those pins which are known to be connected to power or ground were drawn with boxes (boxes are automatically filled when drawn on the Component or Solder layers) for the higher current handling ability. For this project, almost every finger has an electrical connection. In many designs, you will connect only to a few fingers, so adding a PadPin for every finger would be a waste of money. When placed in Pro-Board, the orientation of a Library Part will be the same as when drawn when the Orientation selection is <Right Arrow>. This can be confusing if the part must be rotated for proper placement. If you desire, you can create a Goldfinger which is vertically aligned as easily as the one I created horizontally. The Resistor Packs (RP1, RP2, & RP3) are not simple DIPs. Although the Pin Separation is 0.1" and the DIP definition allows a Row Separation of 0.1", the pin number sequence has odd numbered pins on one row and even numbers on the other, which is the same as most in-line headers. The parts I created were header_2x4 and header_2x5. Both were created on a 25 mil grid. After you have Selected New and entered the name and grid size, enter SetRef and click the cursor at a convenient location. Select PadPin. You now have the option of using either the mouse or the Comm function to lay down the Pins. Clicking the mouse will Place a PadPin. Hitting the Repeat IFK will add another PadPin at the distance specified in the Size menu and in the direction set by the Orientation arrow. Selecting Comm will bring up a requester on the Entry Bar allowing you to specify the X & Y coordinates, along with the number of Pads to lay down. Comm is required for those Library Parts which do not fit on a 25 or 20 mil grid, but can be used whenever desired. Enter 0, 0, & 4, then Select Comm again and enter 0, 0.1, & 4. Remember that the numeric keypad's <Enter> key is used as a Screen Refresh. Use the main keyboard's <Carriage Return> key to enter values. A diode is a simple 2-Pin device, but requires polarization markings for correct installation. Use Pro-Lib to create a 2-Pin device and Draw the outline and polarity band. Polarized capacitors have the same requirements. v"zPreparing for placementv"z The difference between a successful layout and a woeful mess lays in preparation. The positioning of parts should take into account the interconnections which have to be made when routing. Although Pro- Board can automatically add a Via and switch layers to make connections, doing so can make it more difficult to route subsequent traces. In addition, Vias add inductance, which can be a problem if your project uses high frequencies. Of the 17 ICs, 16 of them of are tightly interconnected. It is logical to group them separately from the other components. Except for the Pro-Board Demo manual P. 43 Section 7.3: Memory Card layout three resistor packs (RP1, RP2, & RP3), all the discrete components are part of the circuit including U17. This is another logical group. The 56 pin Goldfinger edge connector must be positioned manually and is not tied to any one group moreso than any other, so its Group setting can be left at 0. For the group of 16 memory chips, connections are to the Resistor Packs and to the Goldfinger edge connector. While each of the Resistor Pack connections go to 8 or 16 pins in the memory chips, each connection from the edge connector goes to one IC. The higher pins on the edge connector connect to the higher numbered ICs. To prevent the need for crossed traces, U16 should be to the left of U1. Load MEMORY-BARE.APCB. Select Auto-P, then Group. A table will display the component labels, types, number of pins, width (where applicable) and Group. A Group setting of `*' is applied when the only connections made are to power and ground. This is most commonly used for bypass capacitors. The Up and Down Arrow IFKs can adjust the Highlight so that the Group number can be entered, but it is faster to slide the cursor over the highlight bar (thus grabbing it) and sliding it over the component list. Press and hold the number of the Group to be applied while sliding the Highlight bar. Apply Group 1 to U1 through U16, Group 2 to U17 and the discrete components, and Group 3 to RP1, RP2, & RP3. Keep CNY1 in Group 0. Press OK. v"zPlacing the componentsv"z First, we will place the Goldfinger edge connector, CNY1. From the main menu, Select Place, followed by Lib, and enter `CNY1' at the prompt. Because the Part List cross-references the Device Label, the Library Part is automatically loaded in outline form. The first thing to notice is that the orientation is probably not correct (unless <Up Arrow> is set). Notice that the part is initially placed with the lower left corner at the cursor. While it is a good idea to position the cursor before calling the part, you can Drag the part before Placing it. Click the mouse without moving in order to settle the part. The Border prevents parts from being placed beyond or on the edge of the PCB. The cutout has been sized so that the edge connector will fit with a gap of 1 grid on each side. For the memory chips, we will use automatic placement. Exit to the main menu, then Select Auto-P, PGrid, and Ver. Hold down the Shift key and press the left and down cursor keys (this will move the display to the left and bottom edges). Move the cursor to the lower left corner and verify it shows (0.0, 0.0), which will be the case unless you have been playing with SetRef. Scroll the screen and move the cursor to set the X-coordinate to 2.300 and Click the mouse button. A vertical Cyan line will appear. Move the cursor so that the X-coordinate is 2.700 and Click again. Now press the Repeat IFK 14 times (makes a total of 16 vertical lines). The <Alt><Z> hot key will zoom out so you can see more of the board. Pro-Board Demo manual P. 44 Section 7.3: Memory Card layout Select the Hor IFK and Click the cursor at the Y-coordinate of 3.000. This sets 16 grid locations which will control the auto-placement algorithm. The X-value was chosen to place enough room between the DIPs and the Goldfinger edge connector for the Resistor Packs. The Y- value is high enough so that the bottom of the ICs is above the highest pin on the edge connector which will be connecting to them. Exit PGrid. Select Orient, and make sure that only <Down Arrow> is Highlighted before returning to the Auto-P menu. If you have not already done so, use <Alt><Z> and the cursor keys to adjust the view so that all the PGrid locations are displayed. Select Pass1 and deactivate all the Group IFKs except Group1 (the Group assigned to U1-16), and Select Go. You will receive a prompt to "Delete UnGlued Parts? (Y/N)". Press `Y'. The automatic placement algorithm will now place the 16 DIPs such that their Pin#1 positions are on the PGrid intersections. On a 25 MHz 68030 Amiga, the process will take about 4 seconds. Exit Pass1, Select Improv, then Swap. Hit <Alt><N> for a normal view (text is not displayed in Zoom modes). Check the sequence of Device Labels. Fortuitously, the sequence will be almost what we decided we needed back in the Preparation. The only IC which is out of sequence is U9. Making use of the Swap function, we will adjust the sequence of the memory chips. If the WORK layer is not highlighted, Click it. Because the ICs are placed so closely, the Device labels overlap the Pins of adjacent ICs. Click on the DISPLAY gadget to turn the ad Master layer off, making the Labels more visible. Now Click within the boundary of U9 and U16. Click a third time to finalize the Swap. Continue swapping U9 with the IC to its right until the sequence is correct. Next, place the oscillator parts associated with U17. For this Group, we will manually position U17, Glue it in place, then auto-place the components around it. Exit to the main menu and Select Place, followed by DIP. Enter U17 at the prompt. Again, the Part List provides the rest of the information and the DIP is shown in outline form on the screen, waiting to be positioned. Note that Guide Lines showing connections to be made to other parts (in this case, the edge connector) are displayed. Select the 4 Orientation arrows to see which orientation displays the cleanest Guide Lines. This time, the best orientation will be <Left Arrow>. Drag U17 to a position midway between the top of the PCB and the top of the row of memory chips, and give it enough room for the traces to be routed from the edge connector on the left. I had placed the cursor at (2.800, 4.100) before entering U17 at the prompt. If you want to quickly re-position, move the cursor over Pin#1 (the only square pin) and Click the RMB. Move the cursor to the desired position and re- Pro-Board Demo manual P. 45 Section 7.3: Memory Card layout the RMB. Move the cursor to the desired position and re-enter U17 at the prompt. After U17 is placed, exit twice to the main menu, then Select Auto-P and Glue. All the parts should ghost. Remember which part is U17 and Click within its outline. It will now display normally (if it does not, make sure the WORK layer gadget is ). Select PGrid and Clear. If you followed my suggestion, all of U17's pin locations are at 0.1" multiples. Select Ver and click on the 2nd pin from the left side of U17, then at the 3rd pin. Select Repeat 12 times. Now Select Hor, and Click the cursor at Y= 3.4 and 3.5, then Select Repeat 12 times. Exit to the Auto-P menu. Select Orient and Click to highlight all the Arrow IFKs. Exit and Select Pass1, then set Group 2 as the only highlighted IFK and Go. The discrete components associated with U17 will be placed at PGrid locations around the IC. The automatic placement algorithm will consider the connections to be made and may choose to place parts further apart than seems necessary based on the perceived routing difficulty. Modification tools are provided to manually improve placement. You can place the components as you wish. I used the arrangement shown in MEMORY3.APCB. To move the components, I generally used Rotate (which allows you to move a part as well as rotate it). Move (with the All IFK highlighted) can reposition all the components in a rectangular area. Use the (Rat's) Nest to display the connections to be made. The NetOpt function (in the parent menu of the Rotate function) will adjust the Guide Lines according to the new placement. Finally, we have to place RP1, RP2, & RP3. These three components are electrically between the edge connector and the memory chips, so it is logical to place them physically between them as well. We COULD place them manually, but dragging parts and trying to align them on a 25 mil grid can be a pain, so we are going to use the tools available to place them automatically and manually adjust them in such a way that they will be aligned. Adjust the screen display to show the region between the edge connector and the memory chip array. Get to the PGrid function, Clear the existing PGrid, Select Ver, and lay down a vertical line at X= 1.200. Two of the three RPs are 8-pin headers and the third is a 10-pin header. These three components can be laid with a separation of 0.4" (if RP3 is placed at the top or bottom PGrid intersection). Select Hor and Click at 3.000, 2.600, then hit Repeat. Move to Orient and Select <Down Arrow>. This is because the Library Parts defined for the RPs were laid out horizontally to the right and we are going to use them pointing down. If you had designed these parts down instead of to the right, you would be using the <Right Arrow> (i.e. no rotation) orientation. Move to Pass1 and set Group3 as the only highlighed IFK. Press Go and Pro-Board Demo manual P. 46 Section 7.3: Memory Card layout and enter `y' for the prompt. If you get the same results I got, RP3 will overlap two PGrid intersections and will prevent RP1 from being placed. You COULD call out the parts manually, but the following sequence will show you how to use the modification tools to your advantage for a quicker and easier result. Delete RP2 and RP3. In Orient, Select <Right Arrow> and return to Pass1. This time, all three RPs will be positioned. Now enter Improv and Swap. Click on two of the RPs and adjust them so the Guide Lines leading to the edge connector are cleanest. This will result in RP3 being placed at the top and RP1 at the bottom. Now, use Rotate on each of the RPs to make them vertical (this works because Library Parts are placed with the lower left corner of the Boundary at the PGrid intersection). v"zRouting the Tracesv"z We have now placed all the components. It is now time to route the traces. Exit to the main menu and Select Auto-R, then R-Rule. Use the mouse to specify AnyVia, 12 mil Trace Width, Speed 1, and Channel Width 50. AnyVia will allow Pro-Board to change layers in order to route a connection. Channel Width specifies how much of a deviation from horizontal or vertical is allowed before a layer switch is forced. A Speed value of 1 sets the slowest speed allowing the most rigorous check for a path to make the connection. Select OK to return to the Auto-R menu. Select SelNet and ByPat. Click within the Bounds of U1 through U16. The Cyan Guide Lines indicate Nets which have been chosen for routing. Now Select ByPin and Click the Right Mouse Button on the Cyan pins of the RPs (we want to route them later). They will return to white. If you have difficulty telling the whether a pin is selected, you may want to turn the DISPLAY gadget off. Exit to the Auto-R menu. Use the <Alt><Z> hot key and the screen cursor controls to view all 16 memory chips. Select Go. The memory array will now be routed. The Entry Bar should display 195 Nets to be routed and provide a progress indicator. You may have noticed that the `Fail' counter occasionally gets reset to `0'. This happens because Pro-Board automatically tries simpler routing methods before progressing to more complex schemes. The first pass will be 0Via, which draws only horizontal or vertical traces. No layer switches are allowed. The Channel Width setting specifies the allowable deviation from horizontal or vertical in order to make a connection (useful for dodging around a Pad). After every connection has been attempted with 0Via, the 1Via approach is tried, then AnyVia (this is when the `Fail' counter resets). All 195 traces will be routed, but the results are not necessarily what we want. Notice that Vias were added so that Pin#2 of each IC could connect to Pin#14. While not fundamentally bad, Vias increase the cost of production. Not to fear... we have a simple means of minimizing them or eliminating them altogether. Select ViaOpt. All standard (i.e. not Wide) traces which have NOT been Pro-Board Demo manual P. 47 Section 7.3: Memory Card layout been Fixed (an option while manually routing a trace) will be analyzed to minimize the number of Vias necessary to make the connection. When finished, most of the traces will remain on the Solder layer (according to the configuration option set in the Rule screen), with the Vias totally eliminated and replaced with Component side traces (this won't happen with every PCB, of course, but it will for this case). The next group to route is U17 and the discrete parts arrayed around it. I decided to route using 25 mil traces because most of them carry power. The rest are analog and a wider trace has a lower characteristic impedance. Enter R-Rule and select a 25 mil Trace Width and 1LAY. In SelNet, Select Nest and NoNet, followed by `y' to deselect all Nets, then Select ByBox and Click to define a box around the parts. Select ByPin and Click the RMB over the pins on the edge connector (we wish to route them later). Exit to the Auto-R menu and Select Go. Because the circuitry around U17 is analog and the rest of the signals are digital, it is a good idea to isolate the two sections. We will draw wide traces around the analog circuitry, touching base on the ground connections. Exit to the main menu and Select Place, then Thermo and Auto. This will add Thermo patterns around those pins which connect to the Power and Ground planes as specified in the Net List. Exit twice to the main menu, then Select Route, Wide, Width, and 50 mils. Exit one level (to Wide), Click on either the <1> or <2> WORK gadgets. The <V>oltage Thermos can be turned off by Clicking on the DISPLAY gadget. Draw a pattern similar to that in MEMORY3.APCB. Next, we will route the connections to the Resistor Packs. Return to the R-Rule screen under Auto-R and set 1LAY and a 12 mil Trace Width. In the SelNet menu, Select Nest and NoNet to deselect all Nets, then ByPin and click on the pins on the left side of the RPs. Exit to the Auto-R menu, Click on the <2> WORK layer gadget (at the right of the Entry Bar next to the PAIR gadget), then Select Go. Routing the traces from the RPs to the ICs will be a bit more difficult because the Guide Lines cross so much. In the R-Rule screen, Click on AnyVia, make sure you have 12 mil Trace Width, Speed 3, and Channel Width 10 (as it turns out, 7 won't completely route and 20 & 50 allow too much deviation around pins). Under SelNet, use ByBox to select the pins on the right side of the RPs, then Exit to the Auto-R menu and Select Go. All 13 traces should be routed. You may, if you wish, ViaOpt to remove some Vias, although 8 should remain. The last group of traces to be routed connect U17 to the Goldfinger Pro-Board Demo manual P. 48 Section 7.3: Memory Card layout edge connector. There are two approaches to routing, automatic and manual. The design of the routing algorithms is to minimize either Trace Length (Single Layer Maze router) or Channel Usage (2 Layer Channel algorithm). With diagonal connections to be made from CNY1 to U17, it is probable that a trace will block one or more traces unless proper preparations are made. It would be a good idea to enter Route/1Layer and familiarize yourself with how the routing algorithm works. Select NoGuid and Guide+. After a few seconds, Guide Lines will appear for the first Net which is not completely routed. Select the <2> WORK layer (Red) and Click on the two highlighted pins. Delete the trace by placing the cursor over a section of the trace and Clicking the RMB. Route the trace again by Clicking on the two highlighted pins, but in reverse order. Notice the difference in the trace's appearance. In each case, the trace moved horizontally before making the diagonal transition towards the other pin. Get the next Net by Selecting Guide+ and Click to route the next Net. Eventually, you will not be able to route any more Nets. This will be the case regardless of which pin is selected first. Your only solution is to control the order in which traces are routed. For automatic routing, the SetWei function can control the order. The default weighting is 0. The range of numbers is 0-255. Higher numbers are routed first. Pins 41-49 on the Goldfinger connect to U17. Because pin#41 is below RP3 and is more likely to be blocked than pin#49, it should have the higher priority (although you are free to experiment... this IS a demonstration program, after all). From the Auto-R menu, enter SetWei. If you had experimented with RipUp, the weighting of traces could have been altered. Select AllNet and enter 0. Then Click on highlighted pins of the Goldfinger and enter the sequence 9-1 to pins 41-49, in that order. Exit SetWei and verify that 1LAY is set under R-Rule, also that the Nets have been selected under SelNet. Return to the Auto-R menu and Select Go. The traces will be routed in an order which will connect all of them. While automatic routing is possible, the best looking results will result from `training' traces (Clicking at points along the way to force the traces to follow a certain path). This is done under Route/1Layer. Exit to the main menu and Select Route and 1Layer. If you have not done so already, delete the traces from the Goldfinger to U17. Select Remain and adjust the screen view to see the area to be routed. Note that, with one exception, the Guide Lines are parallel. This will allow easy routing on one layer for these traces. To Train a trace, start at a pin, then Click at one or more points to control the direction of the trace as you continue towards the destination. If you don't like how one trace segment turns out, you can delete the segment by Clicking the RMB. Use Remain to see which Pro-Board Demo manual P. 49 Section 7.3: Memory Card layout which Nets have to be routed, then NoGuid to clear the Guide Lines. PinGui will display the Guide Lines for the Net which includes the selected pin. Enter the Device Label and Pin Number (useful if you want to find the Device because the screen will scroll to display it), or Click on the pin to display the Guide Line(s). Refer to MEMORY3.APCB to see how the traces will look after manual routing. Remember the results after the automatic router got done with them? v"zAlternate Solutionv"z The PCB data file MEMORY4.APCB shows the results if the memory chips had been divided into two banks. The preparation process this time required U9-16 to proceed from left to right because the connections to the Goldfinger edge connector now come from the top instead of from the bottom. The connections between the Resistor Packs and the two banks of ICs were done manually, then Via Optimized (Auto-R/ViaOpt). I used a trick which is useful from time to time by editing the Net List (which is a simple ASCII file) to adjust the order of the pins in the Nets. Use a text editor to change the Nets for the memory ICs so that the sequence was from U1 to U8 to RP? to U9 to U16. I used a macro in WordPerfect®. This made the Guide Lines display in a more convenient order. Pro-Board Demo manual P. 50 Appendix v"zA.1v"z v"zNet List formatv"z The Net List created by Pro-Net and used by Pro-Board is a modification of the Calay format with the addition of Signal Weighting priorities (ranging from 0-999) following the pin designation. There are two main forms of the Net List, depending on whether Power and Ground layers are specified. If Power Planes are generated, traces do not need to be routed as they can connect directly to the copper layer providing the specified voltage. Pro-Board provides direct support for two Power Planes, one of which is +0V (Ground). An abbreviated Net List showing Signal Nets and Power Planes: File name: AUTOLAYOUT.NET Date: Wed Jan 15 1992 :Signal Net /+12V CONN1(10/31,999); /PRO-NET#1 CONN1(29/31,0), U1(8/31,0), U1(19/31,0), U1(16/31,0); /PRO-NET#2 CONN1(27/31,0), U1(7/31,0); /Clock CONN2(17/31,0), U3(2/31,0), U4(2/31,0), U5(2/31,0), U6(2/31,0); /D00 U8(3/31,0), U3(14/31,0); /D0 U8(4/31,0), U3(13/31,0); /D02 U8(7/31,0), U3(12/31,0); :Power Plane /+5V U1(24/21), U2(24/21), U3(16/21), U3(10/21), U2(18/21), U2(19/21); /+0V U1(12/01), U2(12/01), U3(8/01), U6(5/01), U6(3/01), U4(3/01), U4(6/01), U3(6/01), U3(4/01); The beginning of each Net is noted with the `/'. Following is the Net Name. If one wasn't specifically applied under Signal, Pro-Net generates it. Then each Pin in the Net is listed. The descriptions and restrictions are listed here: In first column : Declaration / Start of a Net In any column except the 1st / Not allowed In any column $ Represents at least one space in the Net List. ; End of a Net. Pro-Board Demo manual P. 51 Appendix [] Bracket actually does not exist in Net List, used to indicate Key Words only. <> Indicates a single ASCII code, i.e. <CR> means a Carriage Return. NetNameX Arbitrary Signal neame created by user. Signal Names cannot have any embedded spaces, nor the special characters ";", ",", or "/" as they have special meaning in the Net List file. U2 Example of Device Label. RP or R Example of Device Label prefix. Power supply voltages which are not in the Power Plane are treated as Signals, but are given a priority of 999, the maximum, so that they will be presented for routing first. A Signal name is recognized as a Voltage and automatically assigned this weighting if it is of the form (+/-)nnV; such as +5V, -12V, +0V. Pro-Board Demo manual P. 52 Appendix v"zA.2v"z v"zPart List formatv"z The Part List cross-references the Device Labels in the Net List with a description of the physical device so Pro-Board knows how to use it in Placement. There are four Device Types allowed; DIP, SIP, 2-Pin, and Library Parts. Standard Through-hole ICs will be DIPs (Dual In-line Package). Resistor networks are usually SIPs (Single In-line Package). 2-Pin devices cover standard fixed capacitors, resistors, diodes, etc. Library Parts are custom definitions you create for Surface Mount Devices (like PLCCs) and odd devices, like ZIP package memory chips, transistors, etc. The format of the file is as shown: Part List: C1/t/0.5; CONN1/l/vconn1; CONN2/l/vconn2; R3/s/10; U1/d/24/0.3; U10/d/20/0.3; U2/d/24/0.3; U8/d/20/0.3; U9/d/24/0.3; DIPs and SIPs have a Pin Separation of 0.1" (2.54 mm). The separation for DIPs is for the Row Separation. A 2-Pin device requires only the separation between the two Pins. The Library Parts specify a case- sensitive name for a Device previously defined in Pro-Lib. Pro-Board Demo manual P. 53 Appendix v"zA.3v"z v"zPro-Drillv"z Pro-Net and Pro-Board work together to define a PCB. Pro-Plot generates Gerber Photo Plotter files which will specify the traces on the copper layers of the PCB. Pro-Drill performs the last step by reading PCB data files created by Pro-Board and specifying, first by default, and then under user control, the size of each hole to be drilled in the PCB. Prior to the introduction of this utility, each hole had to be marked on a test plot of the PCB so an operator at the Board house could specify the locations to drill. Typical charges for this service are in the $50 range, so you can see that Pro-Drill can pay for itself in short order. Pro-Drill displays the PCB data file in the same manner as seen in Pro-Board and identifies which holes are marked for drilling at each size. The Drill Hole size for individual or groups of Pins can be changed easily by either Clicking on the Pin or by specifying an area for the range of the operation. Support for True-Drill and Excellon (CNC) Drill File formats ensure campatibility with most Board houses. Contact Prolific for more details. Pro-Board Demo manual P. 54 Appendix v"zA.4v"z v"zContacting Prolificv"z We hope you liked this demo and that it answered most of your questions about the power and ease of use of Pro-Board. We will be happy to answer any questions by voice, FAX, mail, or E-Mail. Prolific, Inc. 6905 Oslo Circle, Suite B3 Buena Park, CA 90621 Phone: (714) 522-5655 FAX: (714) 994-6435 E-Mail: Internet: Prolific@cup.portal.com If you do not have direct access to InterNet, many local Bulletin Board Systems (BBSes) have access to UUCP via FIDO-Net, which has ports or gateways to InterNet. These gateways may only be updated once a day or so, but the messages will be delivered. To send E-Mail via UUCP under FIDO-Net, address your message to UUCP with our InterNet address as the first line of the message. ADDRESS HEADER: From: <your address> 1:103/208 [sample address] To: UUCP 1:103/208 [check BBS for] [actual address] MESSAGE TEXT: ========================================= To: Prolific@cup.portal.com <place your message here> Pro-Board Demo manual P. 55 zq(Bpwv"z Index .APCB 6 Option 11, 13 .NET 6, 10 .PAT 6, 11 Pad 7, 11-13 PAIR gadget 8, 11, 13 <G>round layer 9-10, 13 Part List 2-3, 5-6, 10-11 <L>abel layer 10 Pin 4, 7, 10-13 <NETname> 6, 10-11 Pin designation 33, 51 ad Master layer 8, 11 Pin#1 7, 12 <PCBname> 5-6 Place 4, 12 <V>oltage layer 14 Placement 2, 4-5, 12 A600 8 Rat's Nest 21, 36 Add Button 7-8, 13 Recommended values 19 Refresh the screen 8 Bill of Materials (BOM) 11 Repeated Pins 29 BOMtoPL.REXX 18 Right Mouse Button 4, 7, 12 Click 7-8, 10, 12-13 Screen Refresh 8 Component layer 7, 11, 13 Scroll Walls 12 Select 10, 13 Del key 12 Signal layers 7-8, 11, 13 Delete Button 7, 12 Silk Screen layer 10 DISPLAY gadgets 8 Solder layer 7-8, 13 Drag 7-8 Stack 15-16, 18 Dual-layer Library Part 27 Trace 4-5, 7, 9, 11-14 E-Mail via UUCP Train a Trace 13 under FIDO-Net 55 Entry Bar 8-9, 11, 13-14 UnDo 12 Escape key 9, 12 Even layer 8 Via 11, 13-14 Exit 9-10, 12 WORK gadgets 7-8, 13 Foot-P 17-18, 20, 24 Function 4-6, 8-13 High Resolution 41 Highlight 9-10 Intelligent Function Keys (IFKs) 10 Left Mouse Button 7 LMB 7-10, 13 Menu 2, 7, 9-10, 12-14 Menu (Right Mouse) Button 7 Metric and English Coordinates 10 mil(s) 10 Net 2-3, 5-6, 9-11, 13-14 Net List 2-3, 5-6, 9-11, 14 Pro-Board Demo manual