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Text File  |  1991-08-02  |  11KB  |  345 lines
  1. /*
  2.  *    @(#) clvga.xgi 1.0 91/08/01 
  3.  *
  4.  *    Copyright (C) The Santa Cruz Operation, 1989.
  5.  *    This Module contains Proprietary Information of
  6.  *    The Santa Cruz Operation, and should be treated as Confidential.
  7.  *
  8.  *      Copyright (c) Cirrus Logic, Inc., 1991 
  9.  *
  10.  */
  11.  
  12. /* ************************************************************************* *
  13.  * CIRRUS/CLVGA.XGI - XEGIA(tm) GrafInfo File for Cirrus Logic VGA - 6410    *
  14.  *                                                                           *
  15.  *  LAST UPDATE: 1 August, 1991 by Cirrus Logic                              * 
  16.  *                                                                           *
  17.  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -   *
  18.  *                                                                           *
  19.  *   CIRRUS.CLVGA.VGA.640x480-16       VGA 640x480 16-color                  *
  20.  *   CIRRUS.CLVGA.VGA.800x600-16       VGA 800x600 16-color                  *
  21.  *                                                                           *
  22.  * ************************************************************************* */
  23.  
  24. /* ********************************************************************* */
  25.  
  26. VENDOR CIRRUS      "Cirrus"
  27.  MODEL  CLVGA    "Logic VGA"
  28.   CLASS  VGA         "VGA"
  29.    MODE   640x480-16  "640x480 16-color"         /* VGA 640x480 16 color */
  30.  
  31.       MEMORY(0xA0000,0x10000);        /* Base Address, Length        */
  32.       PORT(0x3C2,0x3CA,0x3CC,0x3DA);  /* General/External registers  */
  33.       PORT(0x3C0,0x3C1);              /* Attribute                   */
  34.       PORT(0x3C4,0x3C5);              /* Sequencer                   */
  35.       PORT(0x3C7,0x3C8,0x3C9);        /* Color registers             */
  36.       PORT(0x3CE,0x3CF);              /* Graphics                    */
  37.       PORT(0x3D4,0x3D5);              /* CRTC                        */
  38.  
  39.       PROCEDURE InitGraphics
  40.          {
  41.          DEVCLASS    = 75;
  42.          DEVTYPE     = 01;
  43.          DEVTECH     = 0x0D;            /* VGA */
  44.          PIXBYTES    = 80;
  45.          PIXWIDTH    = 640;
  46.          PIXHEIGHT   = 480;
  47.          PIXRESX     = 68;
  48.          PIXRESY     = 68;
  49.          PIXBITS     = 1;
  50.          PIXPLANES   = 4;
  51.          MAPFLAGS    = 0;
  52.          BASEADDRESS = 0xA0000;
  53.          INTERLEAVE  = 1;
  54.          INTERSIZE   = 80;
  55.          }
  56.  
  57.     PROCEDURE   SetGraphics
  58.         {
  59.  
  60.         /* enable extended sequencer registers */
  61.         out(0x3CE,0xA);  out(0x3CF,0xEC);
  62.  
  63.         /* sequencer */
  64.         r0 = 0x1;   /* reset */
  65.         r1 = 0x1;
  66.         r2 = 0xF;
  67.         r3 = 0x0;
  68.         r4 = 0x6;
  69.         bout(5, 0x3C4, 0x3C5);
  70.  
  71.         /* misc output reg */
  72.         out(0x3C2,0xef);  
  73.  
  74.         /* select standard VGA clock frequency for 640x480 */
  75.         out(0x3CE, 0x84); out(0x3CF, 0x10);
  76.  
  77.         /* remove sequencer reset */
  78.         r0 = 0x3;
  79.         bout(1,0x3C4,0x3C5);
  80.  
  81.         /* unprotect crtc regs 0-7 */
  82.         out(0x3D4, 0x11);  out(0x3D5, 0x20);
  83.  
  84.         /* crtc */
  85.         r0  = 0x5f; r1  = 0x4f; r2  = 0x50; r3  = 0x82;
  86.         r4  = 0x54; r5  = 0x80; r6  = 0x0b; r7  = 0x3e;
  87.         r8  = 0;    r9  = 0x40; r10 = 0;    r11 = 0;
  88.         r12 = 0;    r13 = 0;    r14 = 0;    r15 = 0;
  89.         r16 = 0xea; r17 = 0xac; r18 = 0xdf; r19 = 0x28;
  90.         r20 = 0;    r21 = 0xe7; r22 = 0x04; r23 = 0xE3;
  91.         r24 = 0xFF;
  92.         bout( 25, 0x3d4, 0x3D5 );
  93.  
  94.         /* graphics controller */
  95.         r0 = 0x0;
  96.         r1 = 0x0;
  97.         r2 = 0x0;
  98.         r3 = 0x0;
  99.         r4 = 0x0;
  100.         r5 = 0x0;
  101.         r6 = 0x5;
  102.         r7 = 0xF;
  103.         r8 = 0xFF;
  104.         bout( 9, 0x3CE, 0x3CF );
  105.  
  106.         /* attribute controller */
  107.         in(r63,0x3DA);   /* reset f/f */
  108.  
  109.         /* palette */
  110.         r0  = 00;   r1  = 01;    r2  = 02;      r3  = 03;
  111.         r4  = 04;    r5  = 05;    r6  = 0x14;    r7  = 07;
  112.         r8  = 0x38;    r9  = 0x39;    r10 = 0x3A;    r11 = 0x3B;
  113.         r12 = 0x3C;    r13 = 0x3D; r14 = 0x3E;    r15 = 0x3F;
  114.  
  115.         /* attribute controller */
  116.         r16 = 01;    r17 = 00;    r18 = 0x0F;    r19 = 00;
  117.         r20 = 0;
  118.         bout( 21, 0x3C0, 0x3C0 );
  119.  
  120.         /* palette mask */
  121.         out( 0x3C6, 0xFF);
  122.  
  123.         /* enable palette */
  124.         out( 0x3C0, 0x20);
  125.  
  126.         /* protect extended regs */
  127.         out 0x3CE, 0xA  out 0x3CF, 0xCE
  128.  
  129.         }
  130.  
  131.     PROCEDURE SetText
  132.          {
  133.  
  134.          /* unprotect crtc regs 0-7 */
  135.          out( 0x3D4,0x11);   out(0x3D5,0x20);
  136.  
  137.          /* enable extended sequencer registers */
  138.          out(0x3CE,0xA);  out(0x3CF,0xEC);
  139.  
  140.          in(r63,0x3DA);                   /* reset attr F/F */
  141.          out(0x3C0,0);                    /* disable palette */
  142.  
  143.          r0 = 0x01;  r1 = 0x00;  r2 = 0x03;  r3 = 0x00;  r4 = 0x02;
  144.          bout( 5, 0x3C4, 0x3C5 )          /* sequencer regs */
  145.  
  146.          out(0x3C2,0x67);                 /* misc out reg   */
  147.  
  148.         /* set extended sequencer regs */
  149.         out(0x3CE, 0x84); out(0x3CF, 0x10);
  150.  
  151.          r0=0x03; bout(1,0x3C4,0x3C5);    /* sequencer enable */
  152.  
  153.          /* unprotect crtc regs 0-7 */
  154.          out(0x3D4, 0x11);  out(0x3D5, 0x20);
  155.  
  156.          r0  = 0x5F;  r1  = 0x4F;  r2  = 0x50;  r3  = 0x82; /* crtc */
  157.          r4  = 0x54;  r5  = 0x80;  r6  = 0x0b;  r7  = 0x3e;
  158.          r8  = 0x00;  r9  = 0x40;  r10 = 0x00;  r11 = 0x00;
  159.          r12 = 0x00;  r13 = 0x00;  r14 = 0x00;  r15 = 0x00;
  160.          r16 = 0xea;  r17 = 0xac;  r18 = 0xdf;  r19 = 0x28;
  161.          r20 = 0x00;  r21 = 0xe7;  r22 = 0x04;  r23 = 0xe3;
  162.          r24 = 0xFF;  bout(25,0x3D4,0x3D5);
  163.  
  164.          out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
  165.          r0  = 0x00;  r1  = 0x00;  r2  = 0x00;  r3  = 0x00;
  166.          r4  = 0x00;  r5  = 0x10;  r6  = 0x0E;  r7  = 0x00;
  167.          r8  = 0xFF;  bout(9,0x3CE,0x3CF);
  168.  
  169.          in(r63,0x3DA);                   /* reset attr F/F */
  170.  
  171.          r0  = 0x00;  r1  = 0x01;  r2  = 0x02;  r3  = 0x03; /* palette    */
  172.          r4  = 0x04;  r5  = 0x05;  r6  = 0x14;  r7  = 0x07;
  173.          r8  = 0x38;  r9  = 0x39;  r10 = 0x3A;  r11 = 0x3B;
  174.          r12 = 0x3C;  r13 = 0x3D;  r14 = 0x3E;  r15 = 0x3F;
  175.          r16 = 0x0C;  r17 = 0x00;  r18 = 0x0F;  r19 = 0x08; /* attr cntlr */
  176.          bout(20,0x3C0,0x3C0);
  177.  
  178.          out(0x3C0,0x20);                 /* enable palette */
  179.  
  180.          /* protect extended regs */
  181.          out 0x3CE, 0xA  out 0x3CF, 0xCE
  182.          }
  183.  
  184. /* ********************************************************************* */
  185.  
  186. VENDOR CIRRUS   "Cirrus"
  187.  MODEL  CLVGA "Logic VGA"
  188.   CLASS  VGA     "VGA"
  189.    MODE   800x600-16 "800x600 16 color"
  190.  
  191.       MEMORY(0xA0000,0x10000);        /* Base Address, Length        */
  192.       PORT(0x3C2,0x3CA,0x3CC,0x3DA);  /* General/External registers  */
  193.       PORT(0x3C0,0x3C1);              /* Attribute                   */
  194.       PORT(0x3C4,0x3C5);              /* Sequencer                   */
  195.       PORT(0x3C7,0x3C8,0x3C9);        /* Color registers             */
  196.       PORT(0x3CE,0x3CF);              /* Graphics                    */
  197.       PORT(0x3D4,0x3D5);              /* CRTC                        */
  198.  
  199.     PROCEDURE InitGraphics
  200.         {
  201.  
  202.         DEVCLASS    = 99;
  203.         DEVTYPE     = 01;
  204.         DEVTECH     = 0x0D;    /* VGA */
  205.         PIXBYTES    = 100;
  206.         PIXWIDTH    = 800;
  207.         PIXHEIGHT   = 600;
  208.         PIXRESX     = 64;
  209.         PIXRESY     = 54;
  210.         PIXBITS     = 1;
  211.         PIXPLANES   = 4;
  212.         MAPFLAGS    = 0;
  213.         BASEADDRESS = 0xA0000;
  214.         INTERLEAVE  = 1;
  215.         INTERSIZE   = 80;
  216.  
  217.     PROCEDURE   SetGraphics
  218.         {
  219.  
  220.         /* enable extended sequencer registers */
  221.         out(0x3CE,0xA);  out(0x3CF,0xEC);
  222.  
  223.         /* sequencer */
  224.         r0 = 0x1;   /* reset */
  225.         r1 = 0x1;
  226.         r2 = 0xF;
  227.         r3 = 0x0;
  228.         r4 = 0x6;
  229.         bout(5, 0x3C4, 0x3C5);
  230.  
  231.         /* misc output reg */
  232.         out(0x3C2,0x2B);  
  233.  
  234.         /* set extended sequencer regs */
  235.         out(0x3CE, 0x84); out(0x3CF, 0x9C);
  236.  
  237.         /* remove sequencer reset */
  238.         r0 = 0x3;
  239.         bout(1,0x3C4,0x3C5);
  240.  
  241.         /* unprotect crtc regs 0-7 */
  242.         out(0x3D4, 0x11);  out(0x3D5, 0x20);
  243.  
  244.         /* crtc */
  245.         r0  = 0x7f; r1  = 0x63; r2  = 0x64; r3  = 0x82;
  246.         r4  = 0x6b; r5  = 0x1b; r6  = 0x72; r7  = 0xf0;
  247.         r8  = 0;    r9  = 0x60; r10 = 0x0;  r11 = 0x0;
  248.         r12 = 0;    r13 = 0;    r14 = 0;    r15 = 0;
  249.         r16 = 0x5d; r17 = 0xa1; r18 = 0x57; r19 = 0x32;
  250.         r20 = 0x00; r21 = 0x5c; r22 = 0x70; r23 = 0xe3;
  251.         r24 = 0xFF;
  252.         bout( 25, 0x3d4, 0x3D5 );
  253.  
  254.         /* graphics controller */
  255.         r0 = 0x0;
  256.         r1 = 0x0;
  257.         r2 = 0x0;
  258.         r3 = 0x0;
  259.         r4 = 0x0;
  260.         r5 = 0x0;
  261.         r6 = 0x5;
  262.         r7 = 0xF;
  263.         r8 = 0xFF;
  264.         bout( 9, 0x3CE, 0x3CF );
  265.  
  266.         /* attribute controller */
  267.         in(r63,0x3DA);   /* reset f/f */
  268.  
  269.         /* palette */
  270.         r0  = 00;   r1  = 01;    r2  = 02;      r3  = 03;
  271.         r4  = 04;    r5  = 05;    r6  = 0x14;    r7  = 07;
  272.         r8  = 0x38;    r9  = 0x39;    r10 = 0x3A;    r11 = 0x3B;
  273.         r12 = 0x3C;    r13 = 0x3D; r14 = 0x3E;    r15 = 0x3F;
  274.  
  275.         /* attribute controller */
  276.         r16 = 01;    r17 = 00;    r18 = 0x0F;    r19 = 00;
  277.         r20 = 0;
  278.         bout( 21, 0x3C0, 0x3C0 );
  279.  
  280.         /* palette mask */
  281.         out( 0x3C6, 0xFF);
  282.  
  283.         /* enable palette */
  284.         out( 0x3C0, 0x20);
  285.  
  286.         /* protect extended regs */
  287.         out 0x3CE, 0xA  out 0x3CF, 0xce
  288.  
  289.         }
  290.  
  291.     PROCEDURE SetText
  292.          {
  293.  
  294.          /* unprotect crtc regs 0-7 */
  295.          out( 0x3D4,0x11);   out(0x3D5,0x20);
  296.  
  297.          /* enable extended sequencer registers */
  298.          out(0x3CE,0xA);  out(0x3CF,0xEC);
  299.  
  300.          in(r63,0x3DA);                   /* reset attr F/F */
  301.          out(0x3C0,0);                    /* disable palette */
  302.  
  303.          r0 = 0x01;  r1 = 0x00;  r2 = 0x03;  r3 = 0x00;  r4 = 0x02;
  304.          bout( 5, 0x3C4, 0x3C5 )          /* sequencer regs */
  305.  
  306.          out(0x3C2,0x67);                 /* misc out reg   */
  307.  
  308.         /* set extended sequencer regs */
  309.         out(0x3CE, 0x84); out(0x3CF, 0x10);
  310.  
  311.          r0=0x03; bout(1,0x3C4,0x3C5);    /* sequencer enable */
  312.  
  313.          /* unprotect crtc regs 0-7 */
  314.          out(0x3D4, 0x11);  out(0x3D5, 0x20);
  315.  
  316.          r0  = 0x5F;  r1  = 0x4F;  r2  = 0x50;  r3  = 0x82; /* crtc */
  317.          r4  = 0x54;  r5  = 0x80;  r6  = 0x0b;  r7  = 0x3e;
  318.          r8  = 0x00;  r9  = 0x40;  r10 = 0x00;  r11 = 0x00;
  319.          r12 = 0x00;  r13 = 0x00;  r14 = 0x00;  r15 = 0x00;
  320.          r16 = 0xea;  r17 = 0xac;  r18 = 0xdf;  r19 = 0x28;
  321.          r20 = 0x00;  r21 = 0xe7;  r22 = 0x04;  r23 = 0xe3;
  322.          r24 = 0xFF;  bout(25,0x3D4,0x3D5);
  323.  
  324.          out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
  325.          r0  = 0x00;  r1  = 0x00;  r2  = 0x00;  r3  = 0x00;
  326.          r4  = 0x00;  r5  = 0x10;  r6  = 0x0E;  r7  = 0x00;
  327.          r8  = 0xFF;  bout(9,0x3CE,0x3CF);
  328.  
  329.          in(r63,0x3DA);                   /* reset attr F/F */
  330.  
  331.          r0  = 0x00;  r1  = 0x01;  r2  = 0x02;  r3  = 0x03; /* palette    */
  332.          r4  = 0x04;  r5  = 0x05;  r6  = 0x14;  r7  = 0x07;
  333.          r8  = 0x38;  r9  = 0x39;  r10 = 0x3A;  r11 = 0x3B;
  334.          r12 = 0x3C;  r13 = 0x3D;  r14 = 0x3E;  r15 = 0x3F;
  335.          r16 = 0x0C;  r17 = 0x00;  r18 = 0x0F;  r19 = 0x08; /* attr cntlr */
  336.          bout(20,0x3C0,0x3C0);
  337.  
  338.          out(0x3C0,0x20);                 /* enable palette */
  339.  
  340.          /* protect extended regs */
  341.          out 0x3CE, 0xA  out 0x3CF, 0xCE
  342.          }
  343.  
  344. /* End of File - CLVGA.XGI */
  345.