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SIM - A simulator for register-transfer-nets Contents: 1 Introduction 2 Syntax rules for the VLI 3 Usage of the simulator 4 Devices 4.1 List of the available devices 4.2 Description of the devices 4.2.1 AND gate 4.2.2 NAND gate 4.2.3 OR gate 4.2.4 NOR gate 4.2.5 XOR gate 4.2.6 Inverter 4.2.7 Tristate buffer 4.2.8 Inverting tristate buffer 4.2.9 Multiplexer 4.2.10 Demultiplexer 4.2.11 Register, positive-edge-triggered 4.2.12 Register, negative-edge-triggered 4.2.13 J-K-Register, positive-edge-triggered 4.2.14 J-K-Register, negative-edge-triggered 4.2.15 Register, positive-level-triggered 4.2.16 Register, negative-level-triggered 4.2.17 Lamp board 4.2.18 Switch board 4.2.19 Adder 4.2.20 Counter 4.2.21 Comparator 4.2.22 Lead assignment 4.2.23 Left rotation 4.2.24 Read/Write memory 4.2.25 Read-only-memory 4.2.26 Stop condition 4.2.27 Pattern generator 4.2.28 Recorder 4.2.29 Register set, positive-level-triggered 4.2.30 Register set, negative-level-triggered 5 Warnings and Error messages 5.1 Warnings 5.2 Error messages 1 Introduction Register-transfer-nets are used to descripe hardware systems. A register-transfer-net can be compared with a digital circuit. Its devices are divided into three classes: - Registers, with an inner state (sequential logic systems) - Combinatorial cicuits, without an inner state - bundles of leads, for the connections between devices For the simulation of a register-transfer-net, a list of all devices and connections (called VLI) must exist. This happens by a call of the devices which are used. The connections are made with the names of the bundles of leads of the in- and out- puts of the devices. Every lead-name represents a 16-bit-wide bundle. Because the devices must be sequenzialised by force, which work parallel in reality, the resulting model system can be very susceptible for hazards and races. So it's better to used only hazard- and race-free circuits. 2 Syntax rules for the VLI Every call of a devices must start with the name of the device. The pre-defined device-names must be written in capitals and seperated from the list of the lead-names by one space or tab at least. Lead-names are freely eligible. SIM distinguish between lower and upper case of a letter. The following characters are allowed in lead-names: 'a'...'z', 'A'...'Z', '0'...'9', '_' The first character in a lead-name must be no digit. The lead-names must be seperated by commas. Additional spaces or tabs are permitted. If a device needs a list of lead-names of the same type with variable length, this list must be seperated by brackets ('(' and ')'). Inside the brackets, there must must one lead-name at least. It's also possible to define an input lead as a constant. This number is recognized as a hexadecimal if it starts with a '0', otherwise as a decimal number. Parameter in '[' ']' are optional. These are mostly initial values for an output lead. Missing initial values are set to 0. If the value of a lead is relevant as a number, this value is interpreted as a unsigned 16-bit-integer. The first not-space or not-tab character of a comment line must be a semicolon, this means that a comment cannot be appended behind the call of a device. Beside the user-defined lead-names exists a pre-defined clock lead 'CLOCK'. This lead should be used as the clock for all edge-triggered registers. It is realised as the output of a counter. So Bit 0 can be used for the clock input of the regi- sters. The CLOCK-lead is an output of the unit SWITCH. This device must be the first in the VLI. SWITCH and unit LAMP cannot be used more than one time in the VLI. 3 Usage of the simulator The simulator can be started only from the CLI with the follo- wing command: sim <name> name is the name of a text file, in which the VLI is defined. After the translation of an error-free VLI, two windows will be opened. The upper window is the switch board. It contains four 16-bit-wide switch panels and two hex-adjusters. At the begin of a simulation the outputs of switches and adjusters have low level. The levels of switches can be changed by clicking them. The digits of hex-adjuster can be incremented and decremented by clicking the plus- and minus-gadgets. Normaly every single mani- pulation of a switch or an adjuster is recognized and processed. For simultaneous change of more than one switch or adjuster, it is possible to change the Scan-Mode. When the corresponding gad- get is clicked, the Scan-Mode turns to 'all'. In this mode, eve- ry manipulation of a switch or adjuster is saved but mot opera- ted in the simulator. When the Scan-Mode-gadget is activated again, the mode is changed back to single and the current set- tings of the switch board are transfered to the simulator. The lower window is the lamp board. It contains four 16-bit-wide level displays and two hex-displays. Until the first values are computed irrelevant levels are shown. The Run-Mode-gadgets lie above the displays. The one of the following states is possible: RUN Continuous simulation of the register-transfer-net CYCLE All devices are computed until the next increment of the model time CLOCK. Then the simulation enters the STOP mode. STEP Only the next device is computed and the simulation stops. STOP The simulation is stopped. The first three states are shown with borders surrounding the specified gadget. In the STOP mode, no gadget is surrounded. The change between the different modes can be made by one of the gadgets. When clicking the DEBUG gadget, a requester appears. Inside this requester, a lead-name can be typed. After the use of the ENTER key or the show gadget, the levels and the hexadecimal value of this lead is shown. The use of the DEBUG gadget stops the simu- tion. The manipulation of the RESET-Gadget resets the simulator to the state immediate after the program was loaded. A logical high level of bit 0 of CLOCK is shown with the word 'CLOCK' in right upper edge of the LAMP window. The simulator can be leaved with the CLOSE gadget in the SWITCH window. In the STOP mode the simulator waste actively no CPU time. 4 Devices 4.1 List of the available devices AND (in0,in1,...,inx),out[,init] NAND (in0,in1,...,inx),out[,init] OR (in0,in1,...,inx),out[,init] NOR (in0,in1,...,inx),out[,init] XOR (in0,in1,...,inx),out[,init] NOT in,out[,init] BUFFER in,ctrl,out[,init] BUF_INV in,ctrl,out[,init] MUX (in0,in1,...,inx),slct,out[,init] DEMUX in,slct,(out0,out1,...,outx)[,init_slct,init] REG_PE clk,in,out,not_out[,init] REG_NE clk,in,out,not_out[,init] JK_REG_P clk,j,k,s,r,out,not_out[,init] JK_REG_N clk,j,k,s,r,out,not_out[,init] REG_PL clk,in,out,not_out[,init] REG_NL clk,in,out,not_out[,init] LAMP B0,B1,B2,B3,H0,H1 SWITCH B0,B1,B2,B3,H0,H1 ADD in0,in1,c_in,out,c_out[,init[,c_init]] COUNT clk,set,delta,reset,load,dir,out[,init] COMPARE llimit,hlimit,in,out[,init] ASSIGN in_maske,out_maske,in,out[,init] ROTATE in,bits,out[,init] RAM ([name]),len,write,cs,addr,data[,init] ROM name,len,cs,addr,data[,init] STOP ((in0,cond,in1),(in2,cond,in3),...,(inx-1,cond,inx)) PAT_GEN name,len,repeat,clk,out[,init] RECORDER name,clk,in REG_SET_P len,wrclk,wraddr,rdaddr,in,out[,init] REG_SET_N len,wrclk,wraddr,rdaddr,in,out[,init] 4.2 Description of the devices 4.2.1 AND gate AND (in0,in1,...,inx),out[,init] in0,...,inx Inputs out Output init Initial value for out (constant) Function: The inputs are AND-combined bit by bit. The result is transfered to the output. 4.2.2 NAND gate NAND (in0,in1,...,inx),out[,init] in0,...,inx Inputs out Output init Initial value for out (constant) Function: The inputs are NAND-combined bit by bit. The result is transfered to the output. 4.2.3 OR gate OR (in0,in1,...,inx),out[,init] in0,...,inx Inputs out Output init Initial value for out (constant) Function: The inputs are OR-combined bit by bit. The result is transfered to the output. 4.2.4 NOR gate NOR (in0,in1,...,inx),out[,init] in0,...,inx Inputs out Output init Initial value for out (constant) Function: The inputs are NOR-combined bit by bit. The result is transfered to the output. 4.2.5 XOR gate XOR (in0,in1,...,inx),out[,init] in0,...,inx Inputs out Output init Initial value for out (constant) Function: The inputs are XOR-combined bit by bit. The result is transfered to the output. 4.2.6 Inverter NOT in,out[,init] in Input out Output init Initial value for out (constant) Function: The input is inverted bit by bit. The result is transfered to the output. 4.2.7 Tri-state-buffer BUFFER in,ctrl,out[,init] in Input ctrl Control for output out Output init Initial value for out (constant) Function: The value of in is transfered to out as long as bit 0 of ctrl has high level. There is no connection between in and out, if bit 0 has low level. Then out can be used as an out- put by another device. Until this happens, out keep the last assign value. 4.2.8 Inverting tri-state-buffer BUF_INV in,ctrl,out[,init] See BUFFER. Before the value of in is transfered to out, it is inverted bit by bit. 4.2.9 Multiplexer MUX (in0,in1,...,inx),slct,out[,init] in0,...,inx Inputs slct Selected input out Output init Initial value for out (constant) Function: The inputs are numbered in its order in the input list (start with 0). The value of that Input, which has the same number as the value of slct, is transfered to the output. If the value of slct characterize no present input, the output is set to 0. 4.2.10 Demultiplexer DEMUX in,slct,(out0,out1,...,outx)[,init_slct,init] in Input slct Selected output out0,...,outx Outputs init_slct Number of the output to be initialized (const.) init Initial value for the selected ouput (const.) Function: The outputs are numbered in its order in the output list (start with 0). The value of in is transfered to that output, which has the same number as the value of slct. All other output are set to 0. If the value of slct charactize no present output, all output are set to 0. 4.2.11 Register, positive-edge-triggered REG_PE clk,in,out,not_out[,init] clk Clock in Input out Output not_out Inverted output init Initial value for out (constant) Function: The register consists of 16 D-flip-flops. The value of in is transfered to the output with a 0-1-edge on bit 0 of clk and saved until the next 0-1-edge. For a correct function, it's necessary to use CLOCK as the clk lead. 4.2.12 Register, negative-edge-triggered REG_NE clk,in,out,not_out[,init] See REG_PE. The register is triggered with a 1-0-edge. 4.2.13 J-K-Register, positive-edge-triggered JK_REG_P clk,j,k,s,r,out,not_out[,init] clk Clock j J-input k K-input s Asynchronous set r Asynchronous reset out Output not_out inverted output init Initial for output (constant) Function: Bit 0 (-----------Bit i-----------) clk j k s r out | out+ ------------------------------+------ x x x 0 0 q | q x x x 0 1 x | 0 x x x 1 0 x | 1 x x x 1 1 q | ? ^ 0 0 0 0 q | q ^ 0 1 0 0 x | 0 ^ 1 0 0 0 x | 1 ^ 1 1 0 0 q | -q ?: undefined level x: irrelevant level ^: 0-1-edge The register consists of 16 J-K-flip-flops. A single flip-flop works indepently from the others except the common clock. 4.2.14 J-K-Register negative-edge-triggered JK_REG_N clk,j,k,s,r,out,not_out[,init] See JK_REG_N. The register is triggered with a 1-0-edge. 4.2.15 Register, positive-level-triggered REG_PL clk,in,out,not_out[,init] clk Clock in Input out Output not_out Inverted output init Initial value for out (constant) Function: The Register consists of 16 D-flip-flops. The value of in is transfered to the output as long as bit 0 of clk lies on logical high level. After a 1-0-edge the last assigned value is saved. 4.2.16 Register, negative-level-triggered REG_NL clk,in,out,not_out[,init] See REG_PL. The transfer from the input to the output happens on a logical low level on bit 0 of clk. 4.2.17 Lamp board LAMP B0,B1,B2,B3,H0,H1 B0,...,B3 Inputs for binary display H0,H1 Inputs for hexadecimal display Function: The values of the inputs ar displayed in the lamp window of the simulator. LAMP can be used only one time in a VLI. 4.2.18 Switch board SWITCH B0,B1,B2,B3,H0,H1 B0,...,B3 Outputs of the binary switch strips H0,H1 Outputs of the hex-adjusters Function: The settings of the switch board is polled on each change of CLOCK and transfered to the outputs. SWITCH must be the first device and can be used only one time a VLI. 4.2.19 Adder ADD in0,in1,c_in,out,c_out[,init[,c_init]] in0,in1 Inputs c_in Input carry out Output c_out Output carry init Initial value for out (constant) c_init Initial value for c_out (constant) Function: out := in0 + in1 + (bit 0 of c_in) The carry of the result affects bit 0 of c_out. 4.2.20 Counter COUNT clk,set,delta,reset,load,dir,out[,init] clk Clock set Input for setting delta Input for increment/decrement reset Reset the counter load Load the counter dir Increment/decrement out Output init Initial value for the counter (constant) Function: bit 0 of the leads | reset load dir clk | out -----------------------+---------- x x x 0 | out x x x 1 | out 1 x x ^ | 0 0 1 x ^ | set 0 0 1 ^ | out+delta 0 0 0 ^ | out-delta x : irrelevant level ^ : 0-1-edge For a correct function, it's necessary to use CLOCK as the clk lead. 4.2.21 Comparator COMPARE llimit,hlimit,in,out[,init] llimit Lower limit hlimit Upper limit in Input out Output init Initial value for out (constant) Function: If the value of in is larger or equal than llimit and smaller or equal than hlimit, all bits of out are set to 1. Otherwise all bits of out are set to 0. 4.2.22 Lead assignment ASSIGN in_mask,out_mask,in,out,[,init] in_mask Input-bit-mask (constant) out_mask Output-bit-mask (constant) in Input out Output init Initial value for out (constant) Function: With this device it's possible to simulate the assignment of single bits of a lead to another lead. The bits of in, specified by in_mask, are assigned to the bits of out, specified by out_mask. The assignment starts with the least significant bits. Example: in_mask = 4a1a (hex) = 0100101000011010 (bin) out_mask = 90c5 (hex) = 1001000011000101 (bin) input lead: output lead: 15 +---------------> 15 14 -----------------------+ 14 13 13 12 +---------> 12 11 -----------------------------+ 11 10 10 9 --------------+ 9 8 | 8 7 +------------------------> 7 6 +---------------------------> 6 5 | 5 4 -----------+ 4 3 --------------------------+ 3 2 +------------> 2 1 --------------------+ 1 0 +------------------> 0 4.2.23 Left rotation ROTATE in,bits,out[,init] in Input bits Number of bits to rotate (constant) out Output init Initial value for out (constant) Function: The value of in is rotated left as long as it is given by bits. The bits, which are shifted out left, are shifted in right. The result of the operation is transfered to out. The constant bits must lie in the range 0..15. Example: in = 369b (hex) bits = 5 out = d366 (hex) 4.2.24 Read/Write memory RAM ([name]),len,write,cs,addr,data[,init] name Name of the data file len Number of storage cells (16-bit-wide) (const.) write Read/write lead cs Chip select addr Address of a cell data Input or output of the memory init Initial value of data (constant) Function: The memory is only active, if bit 0 of cs has logical high level. If bit 0 of write has high level, on a 0-1-edge of cs the actual value of data is written in that cell that is selected by the value of addr. If bit 0 of write has low level, the va- lue of the selected cell is transfered to the data lead. A optional pre-allocation of the memory can be defined in a file with the given name. This file contains the pre-allocation as 16-bit numbers. These are interpreted as hexadecimal values and must be seperated at least by a tab, space or carriage return ("whitespace"). Example: 3f5a 126c d094 73e1 893a b012 Not pre-allocated cells are initialized with 0. This happens also if no name of a file is gi- ven. If the value of addr leaves the range 0..len-1, the memory becomes inactive. 4.2.25 Read-only-memory ROM name,len,cs,addr,data[,init] See RAM. The pre-alloction file must exist and there is no write access possible. 4.2.26 Stop condition STOP ((in0,cond,in1),(in2,cond,in3),...,(inx-1,cond,inx)) in0,...,inx Inputs cond Conditions Function: If all listed conditions are fulfilled, the simulation enters the STOP mode. The following conditions are possible: == : equal != : not equal > : larger >= : larger or equal < : smaller <= : smaller or equal The stop condition should be used only for troubleshotting, because it slows down the speed of the simulation. 4.2.27 Pattern generator PAT_GEN name,len,repeat,clk,out[,init] name Name of the file containing the pattern len Length of the file (constant) repeat Mode on overflow (constant) clk Clock out Output init Initial value of out (constant) Function: This device allows to generate a pattern on the output lead. The sequence is defined in the file. The contents of this file must correspond to the requirements of RAM/ROM files. With every change of a bit of the clock lead a new pattern is writ- ten to the output. If the end of the file is rea- ched, repeat defines the next pattern. On repeat equal 0, the output holds its last value. On re- peat unequal 0, the next pattern is again the first pattern of the data file. 4.2.28 Recorder RECORDER name,clk,in name Name of the file containing the record after the simulation clk Clock in Input Function: With every change of a bit of the clock lead the value on the input lead is written to the file. 4.2.29 Register set, positive-level-triggered REG_SET_P len,wrclk,wraddr,rdaddr,in,out[,init] len Number of registers (constant) wrclk Write clock wraddr Write address rdaddr Read address in Data input out Data output init Initial value of out (constant) Function: The register set can be read and write at the time. The value of in is transfered to the regi- ster wraddr as long as bit 0 of clk lies on logi- cal high level. After a 1-0-edge the last assigned value is saved. The contents of register rdaddr is transfered to the output. If the value of wraddr or rdaddr leaves the range 0..len-1, the register becomes inactive for that function. 4.2.30 Register set negative-level-triggered REG_SET_N len,wrclk,wraddr,rdaddr,in,out[,init] See REG_SET_P. The transfer from the input to the register hap- pens on a logical low level on bit 0 of wrclk. 5 Warnings and error messages 5.1 Warnings - Warning: Lead <name> is only used as an output This can be the succession of misspellings in the VLI. Although the simulation will be started. 5.2 Error messages - Bad statement The call of the simulator doesn't correspond to: sim <name> - File not found : <name> The given file, that contains the VLI, doesn't exist. - LOW MEMORY There's not enough memory available to translate the VLI. - '(' expected - ')' expected - ',' expected Lead names must be seperated by commas. - Lead name expected - Output lead name expected - Init value expected - Constant expected - Condition expected (==,!=,>,>=,<,<=) - No constant allowed as output lead - Too many characters (max. 255) - Unknown device - Too many lead names - Out of range (0..0FFFF) - Out of range (0..0F) - Device cannot be used more than one time The devices SWITCH or LAMP are used more than one time. - SWITCH must be used - SWITCH must be the first device - No such data file for RAM/ROM/PAT_GEN - Error in data file for RAM/ROM/PAT_GEN - Unable to write to recorder file - Bad statement The device definition doesn't correspond to the given syntax. Mostly an illegal character is used. - Error while opening intuition.library - Error while opening graphics.library - Error while opening LAMP-window - Error while opening SWITCH-window - Error while creating new task - Unable to load/create process - Different version of Sim and external device definition On errors, that occur during the translation of the VLI, the in- correct line is shown (an extract) and the wrong place is marked. The error lies directly at the marked place, at the character ahead or in the name ahead. Only the first error in a line is recognized. After every five errors is asked if the translation should conti- nue. On abortion, the number of the errors, that are detected until this point, is shown.