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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                           Motorola                           |
  5. |                                                              |
  6. |              666      88888      000     5555555             |
  7. |             6        8     8    0   0    5                   |
  8. |            6         8     8   0   0 0   5                   |
  9. |            666666     88888    0  0  0   555555              |
  10. |            6     6   8     8   0 0   0         5             |
  11. |            6     6   8     8    0   0          5             |
  12. |             66666     88888      000     555555              |
  13. |                                                              |
  14. |         6805 MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_                  |
  22. |             Vss |_|1                   40|_| PA7 <-->        |
  23. |           _____  _|                      |_                  |
  24. |       --> RESET |_|2                   39|_| PA6 <-->        |
  25. |             ___  _|                      |_                  |
  26. |         --> INT |_|3                   38|_| PA5 <-->        |
  27. |                  _|                      |_                  |
  28. |             Vcc |_|4                   37|_| PA4 <-->        |
  29. |                  _|                      |_                  |
  30. |       --> EXTAL |_|5                   36|_| PA3 <-->        |
  31. |                  _|                      |_                  |
  32. |        --> XTAL |_|6                   35|_| PA2 <-->        |
  33. |                  _|                      |_                  |
  34. |             NUM |_|7                   34|_| PA1 <-->        |
  35. |                  _|                      |_                  |
  36. |       --> TIMER |_|8                   33|_| PA0 <-->        |
  37. |                  _|                      |_                  |
  38. |        <--> PC0 |_|9                   32|_| PB7 <-->        |
  39. |                  _|                      |_                  |
  40. |        <--> PC1 |_|10     MC6805U2     31|_| PB6 <-->        |
  41. |                  _|                      |_                  |
  42. |        <--> PC2 |_|11                  30|_| PB5 <-->        |
  43. |                  _|                      |_                  |
  44. |        <--> PC3 |_|12                  29|_| PB4 <-->        |
  45. |                  _|                      |_                  |
  46. |        <--> PC4 |_|13                  28|_| PB3 <-->        |
  47. |                  _|                      |_                  |
  48. |        <--> PC5 |_|14                  27|_| PB2 <-->        |
  49. |                  _|                      |_                  |
  50. |        <--> PC6 |_|15                  26|_| PB1 <-->        |
  51. |                  _|                      |_                  |
  52. |        <--> PC7 |_|16                  25|_| PB0 <-->        |
  53. |                  _|                      |_                  |
  54. |        <--> PD7 |_|17                  24|_| PD0 <-->        |
  55. |            ____  _|                      |_                  |
  56. |   <--> PD6/INT2 |_|18                  23|_| PD1 <-->        |
  57. |                  _|                      |_                  |
  58. |        <--> PD5 |_|19                  22|_| PD2 <-->        |
  59. |                  _|                      |_                  |
  60. |        <--> PD4 |_|20                  21|_| PD3 <-->        |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        August 1981                                    |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemon.|Op|HINZC|IXED#RBT|Description            |Notes       |
  83. |-------+--+-----+--------+-----------------------+------------|
  84. |ADC   s|F9|*-***| XXXX   |Add with Carry         |A=A+s+C     |
  85. |ADD   s|FB|*-***| XXXX   |Add                    |A=A+s       |
  86. |AND   s|F4|--**-| XXXX   |Logical AND            |A=A&s       |
  87. |ASL   d|78|--***| X X    |Arithmetic Shift Left  |d=d*2       |
  88. |ASLA   |48|--***|X       |Arithmetic Shift Left  |A=A*2       |
  89. |ASLX   |58|--***|X       |Arithmetic Shift Left  |X=X*2       |
  90. |ASR   d|77|--***| X X    |Arithmetic Shift Right |d=d/2       |
  91. |ASRA   |47|--***|X       |Arithmetic Shift Right |A=A/2       |
  92. |ASRX   |57|--***|X       |Arithmetic Shift Right |X=X/2       |
  93. |BCC   a|24|-----|X       |Branch if Carry Clear  |If C=0      |
  94. |BCLR  b|11|-----|      X |Bit Clear              |b=0         |
  95. |BCS   a|25|-----|     X  |Branch if Carry Set    |If C=1      |
  96. |BEQ   a|27|-----|     X  |Branch if Equal        |If Z=1      |
  97. |BHCC  a|28|-----|     X  |Branch if Half C. Clear|If H=0      |
  98. |BHCS  a|29|-----|     X  |Branch if Half C. Set  |If H=1      |
  99. |BHI   a|22|-----|     X  |Branch if Higher       |If CvZ=0    |
  100. |BHS   a|24|-----|     X  |Branch if Higher/Same  |If C=0      |
  101. |BIH   a|2F|-----|     X  |Branch if Int. High    |If I=1      |
  102. |BIL   a|2E|-----|     X  |Branch if Int. Low     |If I=0      |
  103. |BIT   s|F5|--**-| XXXX   |Bit Test               |A&s         |
  104. |BLO   a|25|-----|     X  |Branch if Lower        |If C=1      |
  105. |BLS   a|23|-----|     X  |Branch if Lower or Same|If CvZ=1    |
  106. |BMC   a|2C|-----|     X  |Branch if Mask Clear   |If I=0      |
  107. |BMI   a|2B|-----|     X  |Branch if Minus        |If N=1      |
  108. |BMS   a|2D|-----|     X  |Branch if Mask Set     |If I=1      |
  109. |BNE   a|26|-----|     X  |Branch if Not Equal    |If Z=0      |
  110. |BPL   a|2A|-----|     X  |Branch if Plus         |If N=0      |
  111. |BRA   a|20|-----|     X  |Branch Always          |PC=a        |
  112. |BRN   a|21|-----|     X  |Branch Never           |No operation|
  113. |BRCLR c|01|-----|       X|Test for Bit Clear     |If b=0      |
  114. |BRSET c|00|-----|       X|Test for Bit Set       |If b=1      |
  115. |BSET  b|10|-----|      X |Bit Set                |b=1         |
  116. |BSR   a|AD|-----|X       |Branch to Subroutine   |-[SP]=PC,BRA|
  117. |CLC    |98|----0|X       |Clear Carry            |C=0         |
  118. |CLI    |9A|-0---|X       |Clear Interrupt Mask   |I=0         |
  119. |CLR   d|7F|--010| X X    |Clear                  |d=0         |
  120. |CLRA   |4F|--010|X       |Clear Accumulator      |A=0         |
  121. |CLRX   |5F|--010|X       |Clear Index register   |X=0         |
  122. |CMP   s|F1|--***| XXXX   |Compare                |A-s         |
  123. |COM   d|73|--**1| X X    |Complement             |d=~d        |
  124. |COMA   |43|--**1|X       |Complement Accumulator |A=~A        |
  125. |COMX   |43|--**1|X       |Complement Index reg.  |X=~X        |
  126. |CPX   s|F3|--***|X       |Compare Index register |X-s         |
  127. |DEC   d|7A|--**-| X X    |Decrement              |d=d-1       |
  128. |DECA   |4A|--**-|X       |Decrement Accumulator  |A=A-1       |
  129. |DECX   |5A|--**-|X       |Decrement Index reg.   |X=X-1       |
  130. |EOR   s|F8|--**-| XXXX   |Logical Exclusive OR   |A=Axs       |
  131. |INC   d|7C|--**-| X X    |Increment              |d=d+1       |
  132. |INCA   |4C|--**-|X       |Increment Accumulator  |A=A+1       |
  133. |INCX   |5C|--**-|X       |Increment Index reg.   |X=X+1       |
  134. |JMP   d|FC|-----| XXX    |Jump                   |PC=d        |
  135. |JSR   d|FD|-----| XXX    |Jump to Subroutine     |-[SP]=PC,JMP|
  136. |LDA   s|F6|--**-| XXXX   |Load Accumulator       |A=s         |
  137. |LDX   s|FE|--**-| XXXX   |Load Index register    |X=s         |
  138. |LSL   d|78|--0**| X X    |Logical Shift Left     |d={C,d,0}<- |
  139. |LSLA   |48|--0**|X       |Logical Shift Left     |A={C,A,0}<- |
  140. |LSLX   |58|--0**|X       |Logical Shift Left     |X={C,X,0}<- |
  141. |LSR   d|74|--0**| X X    |Logical Shift Right    |d=->{C,d,0} |
  142. |LSRA   |44|--0**|X       |Logical Shift Right    |A=->{C,A,0} |
  143. |LSRX   |54|--0**|X       |Logical Shift Right    |X=->{C,X,0} |
  144. |NEG   d|70|?-***| X X    |Negate                 |d=-d        |
  145. |NEGA   |40|?-***|X       |Negate Accumulator     |A=-A        |
  146. |NEGX   |50|?-***|X       |Negate Index register  |X=-X        |
  147. |NOP    |9D|-----|X       |No Operation           |            |
  148. |ORA   s|FA|--**-| XXXX   |Logical inclusive OR   |A=Avs       |
  149. |ROL   d|79|--***| X X    |Rotate Left            |d={C,d}<-   |
  150. |ROLA   |49|--***|X       |Rotate Left Accumulator|A={C,A}<-   |
  151. |ROLX   |59|--***|X       |Rotate Left Index reg. |X={C,X}<-   |
  152. |ROR   d|76|--***| X X    |Rotate Right           |d=->{C,d}   |
  153. |RORA   |46|--***|X       |Rotate Right Acc.      |A=->{C,A}   |
  154. |RORX   |56|--***|X       |Rotate Right Index reg.|X=->{C,X}   |
  155. |RSP    |9C|-----|X       |Reset Stack Pointer    |SP=007EH    |
  156. |RTI    |80|?????|X       |Return from Interrupt  |{regs}=[SP]+|
  157. |RTS    |81|-----|X       |Return from Subroutine |PC=[SP]+    |
  158. |SBC   s|F2|--***| XXXX   |Subtract with Carry    |A=A-s-C     |
  159. |SEC    |99|----0|X       |Set Carry              |C=1         |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemon.|Op|HINZC|I#DEXRBT|Description            |Notes       |
  163. |-------+--+-----+--------+-----------------------+------------|
  164. |SEI    |9B|-0---|X       |Set Interrupt Mask     |I=1         |
  165. |STA   d|F7|--**-| XXX    |Store Accumulator      |d=A         |
  166. |STX   d|FF|--**-| XXX    |Store Index register   |d=X         |
  167. |SUB   s|F0|--***| XXXX   |Subtract               |A=A-s       |
  168. |SWI    |83|-----|X       |Software Interrupt     |            |
  169. |TAX    |97|-----|X       |Transfer Acc. to Index |X=A         |
  170. |TST   s|7D|--**-| X X    |Test zero or minus     |s           |
  171. |TSTA   |4D|--**-|X       |Test Accumulator       |A           |
  172. |TSTX   |5D|--**-|X       |Test Index register    |X           |
  173. |TXA    |9F|-----|X       |Transfer Index to Acc. |A=X         |
  174. |----------+-----+--------+------------------------------------|
  175. | CC       |-*01?|        |Unaffect/affected/reset/set/unknown |
  176. | H        |H    |        |Half carry (Bit 4)                  |
  177. | I        | I   |        |IRQ interrupt mask (Bit 3)          |
  178. | N        |  N  |        |Negative (Bit 2)                    |
  179. | Z        |   Z |        |Zero (Bit 1)                        |
  180. | C        |    C|        |Carry/borrow (Bit 0)                |
  181. |----------------+--------+------------------------------------|
  182. |                |I       |Inherent                            |
  183. | X              | X      |Index (no offset, Op=X)             |
  184. | n,X            | X      |Index (8-bit offset, Op=X-10H)      |
  185. | nn,X           | X      |Index (16-bit offset, Op=X-20H)     |
  186. | nn,E           |  E     |Extended (Op=X-30H)                 |
  187. | nn             |  E     | ditto when EXTEND is default       |
  188. | n,D            |   D    |Direct (Op=X-40H)                   |
  189. | n              |   D    | ditto when DIRECT is default       |
  190. | #n             |    #   |Immediate (Op=X-50H)                |
  191. | a              |     R  |Relative (PC=PC+2+offset)           |
  192. | b              |      B |Bit set/clear                       |
  193. | c              |       T|Bit test and branch                 |
  194. |-------------------------+------------------------------------|
  195. |DIRECT                   |Direct addressing mode              |
  196. |EXTEND                   |Extended addressing mode            |
  197. |FCB      n               |Form Constant Byte                  |
  198. |FCC      'string'        |Form Constant Characters            |
  199. |FDB      nn              |Form Double Byte                    |
  200. |RMB      nn              |Reserve Memory Bytes                |
  201. |-------------------------+------------------------------------|
  202. | A                       |Accumulator (8-bit)                 |
  203. | CC                      |Condition Code register (8-bit)     |
  204. | PC                      |Program Counter (11-bit)            |
  205. | SP                      |Stack Pointer (11-bit, 61H to 7FH)  |
  206. | X                       |Index register (8-bit)              |
  207. |-------------------------+------------------------------------|
  208. | a                       |Relative address (-125 to +129)     |
  209. | b                       |Bit (0 to 7), byte (0 to 255)       |
  210. | c                       |Bit, byte, relative address         |
  211. | d                       |Destination                         |
  212. | n                       |8-bit expression (0 to 255)         |
  213. | nn                      |16-bit expression (0 to 65535)      |
  214. | r                       |Register A or X                     |
  215. | s                       |Source                              |
  216. | string                  |String of ASCII characters          |
  217. |-------------------------+------------------------------------|
  218. | +                       |Arithmetic addition                 |
  219. | -                       |Arithmetic subtraction              |
  220. | *                       |Arithmetic multiplication           |
  221. | /                       |Arithmetic division                 |
  222. | &                       |Logical AND                         |
  223. | ~                       |Logical NOT                         |
  224. | v                       |Logical inclusive OR                |
  225. | x                       |Logical exclusive OR                |
  226. | <-                      |Rotate left                         |
  227. | ->                      |Rotate right                        |
  228. | [ ]                     |Indirect addressing                 |
  229. | [ ]+                    |Indirect addressing, auto-increment |
  230. | -[ ]                    |Auto-decrement, indirect addressing |
  231. | { }                     |Combination of operands             |
  232. | {regs}                  |All registers {PC,X,A,CC}           |
  233. | $                       |Program Counter content             |
  234. |-------------------------+------------------------------------|
  235. | 0061H to 007FH          |Reserved for stack (see RSP)        |
  236. | FFF8H to FFF9H          |Hardware interrupt vector           |
  237. | FFFAH to FFFBH          |SWI instruction interrupt vector    |
  238. | FFFCH to FFFDH          |Non-maskable interrupt vector       |
  239. | FFFEH to FFFFH          |Reset vector                        |
  240. --------------------------------------------------------------- 
  241.