home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
ftp.pasteur.org/FAQ/
/
ftp-pasteur-org-FAQ.zip
/
FAQ
/
verilog-faq
< prev
next >
Wrap
Text File
|
1995-09-20
|
85KB
|
2,085 lines
Newsgroups: comp.answers,comp.lang.verilog,news.answers
Path: senator-bedfellow.mit.edu!bloom-beacon.mit.edu!spool.mu.edu!howland.reston.ans.net!swrinde!ihnp4.ucsd.edu!equalizer!timbuk.cray.com!ned.cray.com!sjp
From: sjp@cray.com (Steve Phillips)
Subject: FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
Message-ID: <1995Sep19.080200.14843@ned.cray.com>
Followup-To: comp.lang.verilog
Summary: This posting contains a list of Frequently Asked Questions (and
their answers) about Verilog HDL.
Lines: 2068
Nntp-Posting-Host: peanut.cray.com
Reply-To: sjp@cray.com
X-Newsreader: TIN [version 1.2 PL2-CRIa]
Date: 19 Sep 95 08:02:00 CDT
Approved: news-answers-request@MIT.EDU
Xref: senator-bedfellow.mit.edu comp.answers:14374 comp.lang.verilog:3743 news.answers:53338
Archive-name: verilog-faq
Version $Id: verilog-faq.html,v 2.15 1995/06/20 16:48:25 sjp Exp sjp $
This is the FAQ (Frequently Asked Questions) list for the newsgroup
comp.lang.verilog. It is an attempt to gather in one place the answers
to common questions and to maintain an updated list of publications,
services, and products. Please read this document before posting.
This article is posted bi-weekly. It is also available from the
archive for this group.
If you haven't already done so, reading the posts on
news.announce.newusers titled "A Primer on How Work With the Usenet
Community", "Answers to Frequently Asked Questions about Usenet" and
"Hints on writing style for Usenet" would be a good idea. They are "a
guide to using it [Usenet] politely, effectively and efficiently."
Your comments, additions, and corrections to this list are welcome:
Please send them to Steve Phillips <sjp@cray.com>.
P01: Table of Contents
Legend
+ new
- deleted
! changed
Preface
P01: Table of Contents
P02: Viewing this article
P03: ! Where to get the most recent version of this FAQ
P04: How does FTP work?
Introductory
I01: What is Verilog?
I02: Who's bright idea was this? (A short history)
I03: What is comp.lang.verilog?
I04: Is there an archive for this group?
I05: Is the archive available on the Web, through clients like
Mosaic and Lynx?
General Topics
G01: Is there a verilog.el for GNU emacs?
G02: What is PLI?
G03: Is there a version that runs on a IBM PC clone?
G04: What is the best PC clone simulator?
G05: What is the best workstation simulator?
G06: Is there a vgrind def file?
G07: Is there a free verilog parser available?
G08: Is there a free Verilog simulator?
G09: Is there a Verilog test suite?
G10: Where can I find a free Verilog quick reference card?
G11: Are there related Web sites?
Appendixes
A01: Verilog vendors and products
A02: Books and Reference material on Verilog
Subject: P02: Viewing this article
This article is now written as an HTML document. The plain text
version is generated by dump the HTML with lynx. This means that it is
no longer in digest format. This makes it a little less useable as a
plain text document, but a lot nicer as a web ducument.
To skip to a particular question numbered xxx, use "/xxx" with most
pagers. In GNU Emacs type "M-C-s xxx", (or C-r to search backwards),
followed by ESC to end the search.
Subject: P03: Where to get the most recent version of this FAQ
This FAQ is now available from the usual places:
o RTFM FAQ archives
ftp://rtfm.mit.edu/pub/usenet-by-group/comp.lang.verilog/FAQ:_Comp
.lang.verilog_Frequently_Asked_Questions_(with_answers)
o Ohio State Usenet FAQ archives
http://www.cis.ohio-state.edu/hypertext/faq/usenet/verilog-faq/faq
.html
It is also posted frequently to comp.lang.verilog, and is available
from the archive site (see I04: Is there an archive for this group? ).
Subject: P04: How does FTP work?
FTP is a way of copying files between networked computers. If you need
help in using or getting started with FTP, send e-mail to
mail-server@rtfm.mit.edu
with
send /pub/usenet-by-group/news.answers/ftp-list/faq
in the body.
Subject: I01: What is Verilog?
Verilog HDL is a hardware description language used to design and
document electronic systems. Verilog HDL allows designers to design at
various levels of abstraction. It is the most widely used HDL with a
user community of more than 15000 active designers.
Subject: I02: Who's bright idea was this? (A short history)
[contributed by Asad Khan <asad@Cadence.COM> ]
Verilog HDL originated circa 1983 at Gateway Design Automation, which
was then located in Acton, MA. The company was privately held at that
time by Dr. Prabhakar Goel, the inventor of the PODEM test generation
algorithm. Verilog HDL was designed by Phil Moorby, who was later to
become the Chief Designer for Verilog-XL and the first Corporate
Fellow at Cadence Design Systems.
Moorby built a simulator around Verilog-XL in 1984-85, and then went
on to make his second major contribution at GDA, viz. the XL algorithm
for every fast gate-level simulation, which was first productized in
1986.
Gateway Design Automation grew rapidly with the success of Verilog-XL
and was finally acquired by Cadence Design Systems, San Jose, CA in
1989. Up till this time, Verilog HDL was still a proprietary language,
being the property of Cadence Design Systems.
Cadence Design Systems decided to open the language to the public in
1990, and thus OVI was born.
[contributed by John Sanguinetti <jws@chronologic.com> ]
When OVI was formed in 1991, a number of small companies began working
on Verilog simulators. The first of these came to market in 1992, and
now there are mature Verilog simulators available from several souces.
As a result, the Verilog market has grown substantially. The market
for Verilog-related tools in 1994 was well over $75m, making it the
most commercially significant hardware description language on the
market.
Verilog is now in the process of being standardized by the IEEE. There
is an IEEE working group established under the Design Automation
Sub-Committee which was established in 1993 to produce the IEEE
Verilog standard 1364. This working group is currently active and
expects to produce a draft standard for balloting sometime in 1995.
Subject: I03: What is comp.lang.verilog?
[extracted from ftp.uu.net:/usenet/control/comp/comp.lang.verilog.Z]
comp.lang.verilog is an unmoderated newsgroup which passed its vote
for creation by 332:9 as reported in news.announce.newgroups on 12 Dec
1991.
For your newsgroups file:
comp.lang.verilog Discussing Verilog and PLI.
The charter, culled from the call for votes:
The USENET group is intended at providing a forum for the discussion
of topics specific to Verilog, PLI (programming language interface),
SDF (Standard delay file format), Synthesis guidelines, compliance and
Verilog modeling. It will also provide users with an ability to share
Verilog/PLI utilities. Users can also use the forum to discuss any
Verilog related issues proposed by Open Verilog International and its
organizational and technical committees.
Subject: I04: Is there an archive for this group?
Yes. Out of the goodness of our hearts, we here at Cray Research
provide an anonymous ftp archive for the postings to comp.lang.verilog
and related files and information. This archive is read only; Cray
does not allow non-employees to write into its file systems. If you
have something to contribute, send it to me (sjp@cray.com) and I will
upload it.
ftp.cray.com:/pub/comp.lang.verilog/
In addition, the University of Windsor maintains an archive of
postings to several of the CAD related newsgroups. One of these is
comp.lang.verilog:
ftp.cs.uwindsor.ca:/pub/local/vlsi/comp.lang.verilog/
Subject: I05: Is the archive available on the Web, through clients like Mosaic
and Lynx?
Cray also provides space on the Cray Research Web Server for the
Comp.lang.verilog home page:
http://www.cray.com/verilog/archive.html
In fact, this FAQ is actually a html document. The text version is
created by dumping the html version with lynx. The html version can be
accessed from the archive home page, or directly at:
http://www.cray.com/verilog/verilog-faq.html
Subject: G01: Is there a verilog.el for GNU emacs?
The archives contain no less than three verilog modes for emacs:
ftp.cray.com:/pub/comp.lang.verilog/verilog.el.Z
Rick Eversole at Cadence maintains a verilog mode and occasionally
posts it to comp.lang.verilog. At this time it supports only FSF
18.xx and Epoch. FSF 19.xx and Lucid Emacs (lemacs) are not
supported. It is available at the archive site, or send email to
eversole@cadence.com to request a copy if you have missed the
posting and can not get it from the archive of comp.lang.verilog.
ftp.cray.com:/pub/comp.lang.verilog/verilog-mode.Z
This one was written by Michael McNamara (mac@chronologic.com). I
grabbed this off the net last fall.
ftp.cray.com:/pub/comp.lang.verilog/vlog-mode.tar.Z
This one was written by Phil Welling (Philip.Welling@tek.com) and
was also grabbed from a posting.
In addition, Cadence is now shipping an LSE (Language Sensitive
Editor) that appears to consist of Lucid Emacs with a set of elisp
files to implement the verilog mode.
Subject: G02: What is PLI?
PLI stands for Programming Language Interface. The PLI consists of an
interface mechanism, a set of routines to interact with the simulation
environment, and a set of routines to access the Verilog internal data
structures. These allow user supplied C code to interact dynamically
with the simulation and data structures.
Subject: G03: Is there a version that runs on a IBM PC clone?
See section A01: Verilog vendors and products
Subject: G04: What is the best PC clone simulator?
The answer, of coarse, depends on what you are looking for. However,
Yatin Trivedi has made available a summary of an evaluation of the PC
clone verilog simulators currently available:
Here is the summary of the PC_based Verilog simulator
Product Evaluation results. These results and a discussion
of the evaluation appeared in ASIC & EDA Magazine, (Product
Evaluation, PC based Verilog Simulators, April 1994,
pages 12-36), and Electronic Engineering Times (Verilog
Simulators get benchmark grilling, April 25, Page 114).
A detailed report of raw performance numbers and the
scoring schemes are available in a report from Seva
Technologies (510-249-9085 or 408-223-1231).
The evaluation was ranked using SEVA Evaluation Index (SEI)
derived by talking with more than 50 different users.
SEI Criteria Weight
============ ======
Performance 40%
Debugging 20%
Environment
Language 15%
Compliance
Design Envr 10%
Integration
Tech Doc & 5%
Support
PLI Implem 4%
Specify Block 4%
Installation 2%
& Licensing
Performance was measured in terms of compile time, run time,
and memory used.
There were 9 different models run with small, medium, and
large number of vectors.
The 9 models were divided in small, medium, and large models
at gate level, RTL, and mixed.
More than 125 compliance test cases were run.
Run time was at least 3 minutes for the fastest simulator
to avoid any measurement inaccuracies.
Simulator/Vendor SEI Score SEI/$1,000
================ ========= ==========
VeriBest/Intergraph 73.9 4.93
FinSim/Fintronic 63.7 9.10
SILOS III/Simucad 62.3 20.77
Baseline/Frontline 61.9 10.32
Veriwell/Wellspring 29.7 29.85
Viper/InterHDL 25.9 26.03
Seva EValuation Academy Awards 1994 (SEVA Awards) goes to
(drum rolls, please...)
Serious User's Simulators ==> VeriBest, Silos III, Baseline
Best Price/Performance ==> Silos III, Baseline
Cost-conscious User's choice ==> Veriwell, Viper
Best Performance ==> VeriBest, Silos III
Most Compliant ==> Baseline, VeriBest
Best Documentation ==> Baseline, Silos III
Macintosh Compatibility ==> Veriwell
Note: VeriBest uses Finsim as its core simulator.
We hope this was a useful evaluation. The detailed report
is published for EDA managers who wish to make an informed
decision of purchasing large quantity of simulators for
their companies. Most individual users are better off just
buying the simulator from the above information rather
than spending $3,000 for the report.
If you happen to quote the information from this posting,
we request you to maintain the integrity of the information
in tact, and credit Seva Technologies as the source.
A VHDL simulator evaluation is near completion, and FPGA based
synthesis tools evaluation is planned for.
If you care to voice your opinion, we would like to know what
you thought of SEI criteria and weights for Verilog simulators
(VHDL are similar, and will be published in July issue of
ASIC & EDA magazine).
The designs we used for performance measurements were received
from REAL users under NDA, and most are in production. If you
would like your design to be part of a comprehensive evaluation
process, we would certainly welcome your participation.
Please read the articles in ASIC & EDA and EETimes.
Thank you for your interest. We look forward to your comments
directly by email to trivedi@netcom.com, lfs@mcimail.com, and
skk@netcom.com.
If you are in Europe, you may contact Mr. Jon Howes, NEuW, for
the availability of the report. His coordinates are:
Jon C Howes jchowes@neuw.demon.co.uk CIS: 100120,2101 Japan:SGS0220
1
NEuW Limited, PO Box 8, Greenfield Innovation Centre,Greenfield,Oldham,
OL3 7LZ, UK Tel:+44 (0) 457 820 326 Fax:+44 (0) 457 820 304
Subject: G05: What is the best workstation simulator?
The answer, of coarse, depends on what you are looking for. However,
Yatin Trivedi has made available a summary of an evaluation of the
workstation based verilog simulators currently available:
SEVA Technologies, Inc. co-founders Yatin Trivedi and Larry
Saunders, well-known industry consultants, organized and conducted these
evaluations, third in an ongoing series. The evaluations are based on the
SEVA Evaluation Index (SEI), which is a comprehensive set of evaluation
criteria developed by SEVA. The relative importance of the criteria is
derived from inputs of end users/designers, project managers at system
houses, and EDA tool developers. The SEI is continually refined with
inputs received from previous Verilog and VHDL evaluations. Besides
raw performance, the index is weighted by measures such as language
compliance, debugging capability, integration with the design
environment, programming language interface (PLI), ability to handle a
design's timing data (SDF), product documentation, installation and
licensing, and technical support.
SEVAFs evaluation criteria and results, including the SEI distribution
and ranking based on the SEI, are summarized below.
SEI Criteria Weight Vendor SEI Score
Performance 50 Chronologic 82.14
(Compile+Run+Memory) Cadence 69.31
Language Compliance 20 Intergraph 47.24
Debug Commands 10 Simucad 36.86
Design Env Integration 6 CAD Artisans 23.49
PLI Support 6 Wellspring 23.15
SDF and Timing 6 interHDL 22.96
Documentation & 2
Technical Support
An article outlining the evaluation results are published in the March,
1995 issue of "Integrated System Design" magazine. Complete results
and the details of the evaluation methodology can be obtained by
subscribing to SEVA's Newsletter The Ultimate EDA Tool.
Subject: G06: Is there a vgrind def file?
Yes. Available in the archives as:
ftp.cray.com:/pub/comp.lang.verilog/verilog-vgrind-def.Z
Subject: G07: Is there a free verilog parser available?
Yes. There are two known public domain parsers.
ftp.cray.com:/pub/comp.lang.verilog/hdl.y.Z
This one was donated by Frank Bennett (fwb@hpfcso.FC.HP.COM).
Here's what Frank had to say about it:
hdl.y below is a verilog parser written using the Unix utility -
yacc. It by no means is a complete verilog parser. This only
represents a few nights of effort in front of the ole PC. This is
donated in the hope that this will enable additional work by
individuals interested in learning verilog & yacc.
ftp.cray.com:/pub/comp.lang.verilog/verilog_parser.tar.Z
The second is from Michael A. Riepe (riepe@eecs.umich.edu). Here's
what he had to say about it:
I ran across a verilog-HDL parser authored by
stcheng@ic.berkeley.edu. It is available by anonymous FTP from
ic.berkeley.edu in directory /pub/stcheng/vl2mv.tar.Z. It is part of
a verilog->bliff translator. It comes complete with a wrapper for
the translator, and contains the parser and code to build the parse
tree. One of the handiest things is a traverse routine which echoes
the input file back to the output by traversing the data structures,
thus giving you a template to base your own application on.
The parser itself seems to contain most of the verilog-HDL grammar,
though many behavioral constructs are unimplemented in the data
structure routines. It is still under development, so there are
bugs. I spent a few days hacking the code and removed a lot of hooks
to berkeley OCTTOOLS code that wasn't included with the
distribution. The code as I downloaded it didn't compile. I'll place
this on the anonymous FTP site here (ftp.eecs.umich.edu in
people/riepe) - you'll get a version that compiles (at least it does
on my decstation) and a list of bug fixes that have been sent to me
other people I've given it to.
Bug reprts/fixes should be sent both to riepe@eecs.umich.edu, and
stcheng@ic.berkeley.edu (the author of the original version)
Subject: G08: Is there a free Verilog simulator?
There is a free, copylefted Verilog simulator called "vbs", written by
Jimen Ching and Lay Hoon Tho as a senior design project in the
electrical engineering curriculum of the University of Hawaii, College
of Engineering.
It is available from the archive at:
* FTP: ftp://ftp.cray.com:/pub/comp.lang.verilog/vbs-1.2.tar.gz
It appears that Veriwell/386 and Veriwell/Sparc are now shareware. Use
is free for source files under 1000 lines. For larger files, a
hardware dongle is required for the MS-DOS version, a license for the
Sparc version. The simulator is available for downloading from the
Wellspring Solutions BBS or via ftp:
* BBS: 1-508-865-1113 (8-N-1)
* FTP: ftp://iii.net:/pub/pub-site/wellspring/
InterHDL also has shareware version. Eli Sternheim says "This is a
full Verilog simulator with the following exceptions: no PLI, specify
blocks are ignored, no switch level constructs but gates and
primitives are supported. Also there is a size limitation on the
design."
* FTP: ftp://ftp.netcom.com/pub/el/eli
InterHDL's simulator can also be had through their mailserver. send an
e-mail to request@interhdl.com with the word "help" in the body of the
message.
Subject: G09: Is there a Verilog test suite?
[contributed by Rich Kolb <rich@systems.com>]
The OVI Test and Compliance Committee has acquired Verilog HDL tests
and organized them into a test suite. Most of the tests are very small
"atomic" tests that test one particular portion of the language. Each
test consists of the Verilog circuit file and the simulation output
file produced by OVISIM. OVISIM is the Verilog clone produced by
Cadence and contributed to OVI.
To induce organizations to contribute additional tests, the entire
test suite is available to anyone who contributes 25 tests or tests
with at least 1000 lines of Verilog code. Currently there are more
than 400 tests in the test suite (9/12/84). Naturally, OVI would
appreciate it if even more tests were submitted. OVI would like to see
as many tests shared by the Verilog community as possible.
The test submission system is set up to automatically function by
e-mail. Tests can be mailed to the test system and it will run the
simulations and send back the results.
OVI welcomes all contributed tests. If a developer is only interested
in the simulation results from a single circuit, that circuit can be
sent to the test system and the simulation results will be returned.
For more information on the test submission format and procedure, send
mail to rich@systems.com
Subject: G10: Where can I find a free Verilog quick reference card?
In the archive, of coarse! A postscript quick reference card has been
donated by Rajeev Madhavan. It is available in the archive:
ftp.cray.com:/pub/comp.lang.verilog/ref.tar.Z
Subject: G11: Are there related Web sites?
Here are some links to Verilog related sites:
Cadmazing's DA-Related Information on the Web
http://www.cadmazing.com/cadmazing/pages/da.html
EE Times
http://techweb.cmp.com/eet/
Electronic Design Automation Companies
http://www.edac.org
IVC (International Verilog Conference)
http://www.e2w3.com/ivcconf.html
DAC (Design Automation Conference)
http://www.dac.com/dac.html
Subject: A01: Verilog vendors and products
Caveat: Many of these product descriptions were written by the vendor.
They may contain hype.
Alta Group (formerly Comdisco Systems) of Cadence Design Systems
Alternative System Concepts, Inc.
Attest Software Inc.
Cadence Design Systems, Inc.
Caesium Inc.
Chronologic Simulation
Design Acceleration, Inc.
DS Diagonal Systems Inc.
Fintronic USA, Inc.
FrontLine Design Automation Inc.
i-Logix Inc.
Intellitech Corporation
Intergraph Electronics
interHDL, Inc.
Library Technologies, Inc.
Precedence Incorporated
Pragmatic C Software Corp.
Simucad
SpeedSim, Inc.
Sunrise Test Systems
Synopsys Inc
Systems Science Inc.
Verilog Consulting Service
Veritools Inc.
Vista Technologies, Inc.
Wellspring Solutions, Inc.
_________________________________________________________________
Vendor:
Alta Group (formerly Comdisco Systems) of Cadence Design
Systems
919 E. Hillsdale Blvd. Suite #300
Foster City, CA 94404
Phone: (415) 574-5800
FAX: (415) 358-3601
Email: talkalta@csi.com
URL:
Product:
Hardware Design System (HDS)
Description:
The Hardware Design System (HDS) is a companion product to
Alta's Signal Processing Worksystem (SPW). Designers of DSP,
Communication and Multimedia systems use SPW/HDS to capture and
analyze algorithms and behavior at the system level. Once the
behavior/algorithm is verified, designers proceed to define the
Hardware Architecture of their system using a powerful set of
parameterized architectural blocks.
HDS includes a library-based HDL generator which generates
optimized Verilog (VHDL) code, targetted for specific synthesis
tools. In addition, HDS includes an HDL-Import capability,
which allows designers to co-simulate system-level diagrams
with Verilog (VHDL) code.
Supports:
SPARC, HP700, IBM RS600
_________________________________________________________________
Vendor:
Alternative System Concepts, Inc.
P.O BOX 128
Windham, NH 03087 USA
Phone: (603) 437-2234
FAX: (603) 437-2722
Email: info@ascinc.com
URL: http://www.ascinc.com
Product:
verilog2vhdl
Description:
verilog2vhdl translates Verilog HDL to IEEE1076-1987 compliant
VHDL using the Standard Logic 1164 package. The present form of
verilog2vhdl can perform a full structural translation and
partial translation of RTL constructs in Verilog. The tool can
also provide a software procedural interface to output VHDL.
Future releases will support full RTL and behavioral
translation of Verilog. IEEE1076-1993 compliance is also
expected soon.
The product will be available in the first quarter of 1995.
Supports:
SunOS 4.1.x, MS-DOS
_________________________________________________________________
Vendor:
Attest Software Inc.
4677 Old Ironsides Drive, Suite 100
Santa Clara CA 95054
Phone: (408) 982-0244
FAX: (408) 982-0248
Email: info@attest.com
URL: ftp://ftp.netcom.com/pub/at/attest
Product:
TDX (R)
Description:
TDX is a high-performance, interactive fault simulation and
automatic test generation software system for Verilog.
The software is built around a high-performance concurrent
fault simulator that supports all of the unidirectional
primitives, wire types, and gate/net delays defined in the
Verilog 2.0 LRM. UDPs are also supported, along with optimized
built-in models for single and multi-port RAMs.
It is not necessary to sacrifice accuracy for fast fault
simulation.
The software supports the detailed pin timing and strobing
features found on "tester-per-pin" ATE.
TDX_FSIM - highly accurate, fast fault simulator with full
timing and states/strengths.
TDX_IDDQ - flexible, programmable transistor-short fault
simulation and vector selection for current measurement
testing.
TDX_STEP (TM) - static and dynamic testability analysis, and
test improvement program that supports both scan and non-scan
designs.
TDX_ATG - sequential test generation for scan and non-scan
designs. Tightly integrated with tdx_fsim, tdx_step, and
tdx_iddq.
Free demo executables are available by anonymous ftp from
ftp://ftp.netcom.com/pub/at/attest. The demo software runs on
any small circuit, and also on an 8085 microprocessor clone
model that is available at the ftp site.
Supports:
Sun Sparc, HP PA-RISC, and Windows NT.
_________________________________________________________________
Vendor:
Cadence Design Systems, Inc.
555 River Oaks Parkway
San Jose, CA 95134
Phone: (408) 943-1234
Fax: (408) 943-0513
email: ?
URL:
Product(s):
Verilog-XL
Description:
The industry standard Verilog simulator.
Supports:
most workstations
_________________________________________________________________
Vendor:
CAESIUM, Inc.
3542 Earl Drive
Santa Clara, CA 95051
Phone: (408) 492 9511
(408) 248 4603
Fax: (408) 248 6012
email: caesium@btr.com
URL:
Product(s):
Verilog HDL Model Libraries (Custom VLSI & ASIC model
development)
Description:
CAESIUM, Inc. provides Verilog HDL Model Libraries.
CAESIUM works with the customer to provide all the 'Missing
Models' (sm) for the customer's current and next projects.
Features Include:
1. Full Function.
2. Accurate Timing.
3. Synthesizable.
4. Intelligent X-handling.
5. Verilog HDL Source Code models.
6. Fast Execution.
7. Low Cost.
ABT, ACT, ALS, AS, BCTTTL, HCT, F, S, LS Series Glue logic
parts.
FIFOs, MEMORIES and PAL models are available for some families,
others can readily be developed on needed basis.
Partial Function or Bus Function Models can be developed at a
nominal cost.
Supports:
Models will work under LRM compatible Verilog simulators.
Verilog-XL, VCS, SILOS III, Viper, etc.
_________________________________________________________________
Vendor:
Chronologic Simulation
5150 El Camino Real
Los Altos, CA 94022
Phone: (800) VERILOG or (415) 965-3312
FAX: (415) 965-2705
email: info@chronologic.com
URL: http://www.chronologic.com/
Product(s):
VCS, Verilog Compiled Simulator
Description:
Product is a Verilog Compiler offering 10x speed improvement on
behavioural code, and 1/10 memory usage; all as compared to
Verilog-XL 1.6. Supports the complete language, as well as
interactive debugging. Also supports SDF and the full PLI, and
offers incremental compilation. Compiles to machine code on
Sparc and HP machines, compiles to C on others.
Supports:
Sparc SunOS, Sparc Solaris, HP PA-RISC, SGI, IBM RS6000, Sony
NeWS, DEC Alpha
Product(s):
VMC, Verilog Model Compiler
Description:
Product takes Verilog HDL source models and compiles them to C
object modules for use with VCS, Verilog-XL and other Verilog &
VHDL simulators. Allows component builders to release high
performance, low memory, proprietary models to their customers
- as object form - ie providing a very attractive alternative
to source protection/encryption.
Supports:
Sparc SunOS, Sparc Solaris, HP PA-RISC
_________________________________________________________________
Vendor:
Design Acceleration, Inc.
2105 Hamilton Ave., Suite 370
San Jose, CA 95125
Phone: (408) 559-8500
Fax: (408) 371-5196
email: info@designacc.com
URL: http://www.designacc.com
Product(s):
Signalscan 4.0 & Pro
Description:
Signalscan is a complete waveform viewing, simulation analysis
and tightly coupled source code debugging environment for
Verilog and mixed Verilog/analog simulation. Signals may be
backtraced from the waveform or source code views without need
to refer to a schematic. Signals load from the SST simulation
database in a fraction of the time it takes for conventional
solutions. Signalscan includes Sequence Time (patent pending):
a new time domain that gives graphical visibility into a
Verilog-specific problem of sequence order dependent results.
Signalscan supports simultaneously viewing signals from mixed
simulation environments, including Cadence's Verilog,
Chronologic's VCS, Fintronic's FinSim, Frontline's BaseLine and
SimLine, Ikos' Gemini, SIMUCAD's SILOS, EPIC's TimeMill and
PowerMill and Meta Software's HSPICE.
Supports:
SPARC, HP, SGI, RS/6000, Windows
_________________________________________________________________
Vendor:
DS Diagonal Systems Inc.
800 El Camino Real, Suite 180
Mountain View, CA 94040
Phone: (415) 903 2255
Fax: (415) 903 2237
email: info@diagonal.com
Phone (Europe): +41 1 810 91 11
Fax: (Europe): +41 1 810 98 58
email (Europe): info@diagonal.ch
URL: http://www.diagonal.com/
Product(s):
WAVE-Link, CHECK-Link, CAT-Link
Description:
WAVE-Link
WAVE-Link is a highly interactive, graphical toolset for
generating digital stimulus waveforms and defining
expected responses that are simulator and ATE system
independent. Stimulus creation is fast and and visual -
free from the specific syntax of any simulator or ATE
system. WAVE-Link is your common front-end tool for VHDL,
Verilog and gate level simulators.
CHECK-Link
Design verification according to company's guidelines;
testability verified during design.
CAT-Link
Design and layout consistency verification; design and
layout data transfer to manufacturing (ATE & Pick/Place)
Supports:
SUN, HP, SCO UNIX, RS/6000, Windows (soon)
_________________________________________________________________
Vendor:
Fintronic USA, Inc.
1360 Willow Road, Suite 205
Menlo Park, CA 94025
Phone: (415) 325-4474
FAX: (415) 325-4908
Email: info@fintronic.com
URL:
Product(s):
FinSim Verilog Simulation Environment
Description:
FinSim is a high performance Verilog simulation environment. It
features full language implementation including support for PLI
1.0, VCD, PLA, and SDF. FinSim has a very fast Verilog analyzer
with extensive error checking and recovery mechanism. FinSim
simulator can run in both compiled or interpreted mode as well
as mixed mode. Compatibility with Verilog-XL is excellent.
FinSim 2.0 was rated the fastest PC-based Verilog simulator in
the published benchmark comparison from Integrated Design
System (formerly ASIC & EDA). With FinSim 4.0, simulator run up
to 40x faster while utilizing less memory. PLI and SDF access
is greatly optimized. In addition, FinSim 4.0 has several new
features including incremental compilation and full support for
source level debugger from Design Acceleration Signalscan and
Veritools Undertow.
FinSim supports VCD waveform display tools from Design
Acceleration, Veritools, and Systems Science. Schematic capture
system is supported from Data I/O. FinSim is also the core
simulation engine in the Intergraph Veribest Design System.
FinSim has a list price from $995 to $10,000 for all platforms.
Prices reflect single license per machine. Multiple and
educational discounts are available. Evaluation version of
FinSim is available upon request.
Supports:
Solaris 1.1, Solaris 2.4 (Sun, Intel x86), Dec Unix, HP-UX, SGI
Irix, Sony NEWS, Windows NT (Intel x86, Alpha, MIPS, PowerPC),
OS/2, Window 95, Windows 3.1/DOS, Unixware, and Linux.
_________________________________________________________________
Vendor:
FrontLine Design Automation Inc.
2860 Zanker Road, Suite 203
San Jose CA 95134
Phone: (408) 456 0222
FAX: (408) 456 0265
Email: sales@frontline.com
URL:
Product(s):
SimLine (Compiled Verilog Simulator)
Description:
In one powerful simulation environment, SimLine provides the
benefits of a very fast RTL level simulation with a compiled
engine, fast turn around with aninterpreted engine and fast
gate level simulation with a XL engine. In addtiotion SimLine
has enhanced timing accuracy over current Verilog
implementations to handle deep submicron ASIC technologies.
SimLine's debug and analysis environment makes HDL based design
easier with tools like a Source Level Debugger, Design
Analyzer, Hierarchy Manager and Waveform and Register displays.
In addition, SimLine is the highest compatibility Verilog
simulation solution on the market today.
Supports:
Sun, HP
Product(s):
BaseLine (Interpretive Verilog Simulator)
Description:
BaseLine provides a full featured, highest com[patibility,
Verilog simulation environment for both PCs and Workstattions.
BaseLine has a powerful design and debug environment featuring
a Source level debugger, Hierarchy Management and both Waveform
and register display tools. BaseLine offers very competitive
performance and capacity making it ideal for the FPGA designer
or thise looking to extend their Verilog environments.
Supports:
PC (Windows 3.1, NT), Sun, HP
_________________________________________________________________
Vendor:
i-Logix Inc.
22 Third Avenue
Burlington, MA 01803
Phone: (508) 682-2100
FAX: ?
Email: ?
URL:
Product(s):
ExpressV-HDL
Description:
Provides a graphical environment to develope Statecharts.
Equivalent Verilog or VHDL is automagically generated.
Supports:
?
_________________________________________________________________
Vendor:
Intellitech Corporation
66 Route 25
Meredith, NH 03253
Phone: (603) 279-6308
FAX: (603) 279-5135
Email: info@intellitech.com
URL:
Product(s):
BSDLMaker
Description:
BSDLMakerTM is a design-for-test tool for creating BSDL
(Boundary Scan Description Language) files from Verilog
netlists. BSDLMakerTM will compile your structural Verilog
netlist (including flattening of hierarchical designs) and
silicon package pin file, perform a number of 1149.1 design
compliance checks, generate a BSDL file and produce a design
warning/error message file. It supports libraries from multiple
silicon vendors, multiple synthesis vendors and user defined
1149.1 designs.
Supports:
PC, SUN
_________________________________________________________________
Vendor:
Intergraph Electronics
Huntsville, Al 35894-0001
Phone: 1-800-VERIBEST
FAX : (205) 730-8543
email: tfloodee@ingr.com
URL: http://www.ingr.com
Product(s):
VeriBest Design System
Description:
The VeriBest suite of products provides an easy to use
ASIC/FPGA design environment. The environment will be sold in a
software only form as the VeriBest Designer and will be bundled
with Intergraph's TD1 hardware platform as the VeriBest Design
System. VeriBest Designer has the following software
components:
Electronics Desktop Manager - Our electronics specific
graphical desktop which organizes design data and launches
applications. The Electronics Desktop manager includes the
Design Methodology Manager, a tool that allows software
products to be organized into an enforced process oriented flow
(e.g., the steps required to build an ASIC or FPGA as specified
by a silicon vendor).
ACEPlus Design Entry System - Our front-end design entry editor
that utilizes hierarchical design to organize the use of
primitive symbols and representative blocks for Verilog source
files or State diagrams.
ACEPlus Designer - Our automatic HDL generator that takes
schematics and state diagrams created with ACEPlus Design Entry
System and automatically generates simulatable VHDL, Verilog
HDL, or ABEL HDL.
VeriBest Simulator - Our high performance, high capacity
Verilog-XL compatible simulator which includes VeriScope, our
graphical waveform viewer and simulation controller.
Supports:
Sun Sparc, Intel 486 & Pentium
_________________________________________________________________
Vendor:
interHDL, Inc.
4984 El Camino Real, Suite 210
Los Altos, CA 94022-1433
Phone: (415) 428-4200
Fax: (415) 428-4201
email: info@interhdl.com
URL:
Product(s):
Veribase, Verinet, Verilint, Viper, interFlat, interVHDL
Description:
Veribase
Reads a Verilog HDL design, builds an internal database
and provides a set of database access functions for
developing in-house EDA tools. This tool supports full
set of the Verilog language.
Verinet
A subset of Veribase which handles only the gate level
Verilog. It also has a flattener which can flatten the
design hierarchy and/or busses in an orhtogonal way,
i.e., the two expansions are two separate functions.
Both Veribase and Verinet are toolkits which have a
library of API/PLI functions for accessing the design
database.
Verilint
A semantic, synthesis, and design rules checker for
Verilog designs. It has its own graphical user interface
and a text editor. The tool allows designers to
interactively find and fix design errors prior to
simulation and synthesis.
Viper
A full Verilog HDL simulator that supports behavioral,
RTL, logic gates, and UDPs. It is fully compatible with
OVI's LRM 1.0 specs and Verilog-XL in terms of results
and usage. Uses existing scripts and makefiles for
verilog-XL simualtion. Interfaced to popular waveform
displays: SignalScan, UnderTow and Megallan. Available in
three versions: Viper/DOS (Personal), Viper/Windows
(FPGA/PLD), and Viper/UNIX (ASIC/FPGA).
interFlat
Reads hierarchical Verilog netlists, flattens the
hierarchy and writes a flat Verilog, VHDL, EDIF, or
FutureNet file. The operation of flattening is extremely
fast. This is also available in the form of a toolkit,
Verinet, to build in-house tools.
interVHDL
Converts Verilog HDL designs into functionally equivalent
VHDL designs. If a Verilog design is synthesizable then
the translated VHDL design will also synthesize and the
simulation results will be the same except for the
simulator dependencies. Does not support fork-join and
disable statements.
Supports:
Sun, HP, IBM/RS6000, DEC/Alpha, SGI.
_________________________________________________________________
Vendor:
Library Technologies, Inc.
18837 Casa Blanca Lane
Saratoga, CA 95070
Phone: (408) 741-1214
Fax: (408) 741-1214
email: sales@libtech.com
URL:
Product(s):
Libchar, Stimgen, Verigen, Veritest, Syntest
Description:
ASIC library generation tools, based on synthesizing ACDL
description of the cells into target simulation and synthesis
libraries. ACDL is ASIC Cell Description Language, proprietary
to Library Technologies.
Stimgen automatically synthesizes the timing behavior of the
ASIC cell and generates stimuli for characterizing each of the
timing and electrical parameters of the cell.
Libchar is the automatic characterizer, which measures each of
the electrical parameters and fits them into one of several
delay models. Verigen converts ACDL descriptions into
structural verilog complete with specparams and pin-to-pin
paths using the parameters calculated by libchar.
Syntest converts ACDL descriptions into RTL verilog, to be used
for verifying synthesis libraries and technology mapping.
Veritest generates a testbench to verify the functionality of
the verilog representations of the cell.
Supports:
Sparc
_________________________________________________________________
Vendor:
Precedence Incorporated
4675 Stevens Creek Blvd., Suite 250
Santa Clara, CA 95051
Tel: (408) 345-4880
Fax: (408) 345-4884
email: kevinj@precedence.com
URL:
Product(s):
SimMatrix co-simulation products:
Cadence Verilog / Vantage Spreadsheet Co-simulation
Cadence Verilog / QuickVHDL hardware emulator Co-simulation
Cadence Verilog / EPIC Design TimeMill and PowerMill Co-sim
Cadence Verilog / Mentor Lsim Co-simulation
Cadence Verilog / Silvaco SmartSpice Co-simulation
Mentor Graphics Quicksim II / Cadence Verilog-XL
Viewlogic Viewsim - VHDL / Cadence Verilog-XL
Description:
Precedence co-simulation products allow designers to
concurrently simulate using both Verilog-XL and the specialized
design verification tools as shown above, simultaneously and
transparently. This is useful for IC, ASIC and PCB simulation
which includes blocks or models in a variety of simulators
and/or languages. At the heart of this integrated simulation
environment is Precedence's extensible SimMatrix simulation
backplane.
Supports:
Sun, HP, other workstations
_________________________________________________________________
Vendor:
Pragmatic C Software Corp.
220 Montgomery Street, Suite 925
San Francisco, CA 94104
Tel: (800) 223-5017
Fax: (415) 781-1116
email: pverhelp@crl.com
URL: under construction
Product(s):
Pver (Interpretive Verilog Simulator)
Description:
Complete Verilog simulator now OVI LRM compliant will be IEEE
1364 compliant. Pver offers a Verilog simulator for large ASIC
design at 1.5 to 2 times the cost of commercial programming
language compilers to allow every designer to have unlimited
access to a Verilog simulator. Price performance is at least 3
times any other full featured Verilog simulator. Pver is
intended to include provisional features that may later be
added to the standard. Some features are:
1. Fast one pass source translation.
2. Efficient memory use - packing to the bit and only one
instance of each module stored unless copies are required
because of defparams.
3. Programming language style debugger: GDB syntax modified for
instance trees in addition to statement debugger.
4. Alternative debugging features: enhanced parallel activity
tracing and control thread and post-mortem dumping.
5. Spike analysis with unknown injection.
6. Added mechanism for per instance distributed primitive
delays.
7. Includes PLI tf_ routines but also contains features to allow
implementation in Verilog instead of requiring PLI.
8. Most features from Vcmp: gate eater, circuit content tables,
lint style checking during translation and simulation, and
warning/inform suppression by number.
9. Good simulator for beginners because error messages explain
what is expected and because edge processing is regular and
complete.
10. Good simulator for experts because Pver contains features for
command and script based debugging.
11. Full featured PC (Linux/OS2/DOS) and Macintosh personal
licenses that may only be used by one designer in any 30 day
period but do not require dongles.
12. Geographically unlimited CPU architecture fungible floating
workstation licenses.
Thirty day free trial. Detailed release notes emailed upon request.
Supports:
PC (OS2, Linux Unix, VCPI compliant DOS), Macintosh (Machten
BSD Unix), Sparc (SunOS 4.1x), others upon request.
_________________________________________________________________
Vendor:
Simucad
32970 Alvarado-Niles Road
Union City, CA 94587
Phone: (510) 487-9700
Fax: (510) 487-9721
email: silos@simucad.com
URL:
Product(s):
Silos III
Description:
Silos III is the next generation of Simucad's Silos simulator
which was first introduced in 1983. It is an integrated logic
and fault simulation environment. Silos III used Verilog to
support top-down methodology.
Supports:
Sun, VAX, HP, RS6000, MIPS, PC
_________________________________________________________________
Vendor:
SpeedSim, Inc.
234 Littleton Road, Suite 2E, PO Box 4035
Westford, MA 01886
Phone: 508-692-3737
FAX: 508-692-1640
Email: info@speedsim.com
URL: http://www.speedsim.com/speedsim/
Product:
SpeedSim/3 Cycle-based Simulator; Simultaneous Test Option; &
SMP Option
Description:
SpeedSim/3 is a Cycle-based simulator. It accepts Verilog
gate-level, & synthesizeable subset of Verilog & VHDL RTL (Rel.
2.0). Compliant with OVI PLI. Performance is 10 to 100 times
faster than Chronologic (RTL level), using 1/5th the memory.
Produces up to 2,000 cycles per second throughput on simulation
of large designs. Compiles 1M gate design in 10 minutes into 16
MB runtime image; SAVE/RESTORE in 4 seconds.. Detects
Asynchronous logic & tri-state bus contentions.
Simultaneous Test (TM) Option, a unique SpeedSim/3 option,
allows up to 32 different tests, such as diagnostics or
application program streams, to run simultaneously on the same
image of a design model. Simultaneous Test boosts performance 5
to 32 times over the base SpeedSim/3 product.
Symmetric Multi-Processing (SMP) option was built from the
start to get the most out of SMP technology. It's unique
Multithread management techniques can deliver near linear
performance gains on up to eight processors implemented in a
single system. These processors work in tandem simulating a
single model that yields great efficiency on a shared memory
system. Users can economically increase performance simply by
plugging in additional processors. This is particularly
attractive for designs over 500,000 logic gates where engineers
can get much faster turnaround on a long test using the
SpeedSim/3 SMP option. With large designs, SpeedSim/3 users
will realize near linear performance increases with minimal
memory impact when they add additional processors.
Supports:
UNIX workstations from Sun Microsystems (SunOS, & Solaris),
IBM, & Hewlett Packard.
_________________________________________________________________
Vendor:
Sunrise Test Systems
2730 SanTomas Expressway #200
Santa Clara, CA 95051
Phone: 408-980-7600
Fax: 408-980-7630
email: info@srtest.com
URL:
Product(s):
TestGen (TM), FaultSim, START, IddQTest, PathTest (TM),
ParallelTestgen
Description:
Sunrise Test Systems offers Test Synthesis, Design for test
tools and Testability analysis tools based on Verilog. Its
products include Automatic Test Pattern Generation tools for
stuck-at, IddQ and path delay faults. Verilog drivers are
created for the vectors generated by the tool for verification
using verilog simulator. Test vector interfaces are provided to
support most of the ASIC vendor simulators (LSI, Toshiba,
Motorola, VLSI, Fujitsu, Mitsubishi, NEC etc.) and commercial
simulators such as verilog XL, Zycad, Ikos. TSSI WGL format is
also supported.
TestGen
Automatic Test Pattern Generator which generates high
coverage tests for stuck-at-fault models. Testgen is
complemented by a high performance test vector compactor
that leads to lowered test application times. Testgen is
an industry standard test generation tool that
incorporates patented test generation algorithms. It has
been successfully used on a wide variety of
design-for-test methodologies such as full scan, almost
full scan and partial scan circuits.
FaultSim
High performance fault simulation tool that uses the
least amount of memory and run time. Can be used
stand-alone or with the Testgen tool.
START
Sunrise Testability Analysis and Rule checking tool is a
collection of programs used for testability analysis and
test logic synthesis. START includes LITE program that
can stitch scan chains, insert structured non-scan test
logic such as control and observe logic with the least
impact on area and performance. Any netlist modifications
are done preserving the design hierarchy. START can be
used to identify flops to be scanned for partial scan
design-for-test methodology. START includes a design rule
check program that can verify scan chains, check for
various design-for-test rules. IEE1149.1 (JTAG) standard
compliance checking software is a part of START. START
also contains an interactive logic simulator and a
circuit browser.
IddQtest
An automatic test pattern generator for IddQ faults. It
generates a compact setof test vectors yet achieving high
IddQ fault coverage. It can also be used to identify IddQ
strobe points in a user supplied vector set such as
fucntional vectors.
PathTest
An automatic test pattern generator for path delay (slow
to rise/fall) faults. This is very useful for part
binning and design debugging.
Parallel Testgen
Automatic test pattern generator that exploits a network
of heterogeneous UNIX work stations. Test generation time
on sequential circuits can be significantly reduced by
using this product.
Supports:
Sun Sparc, HP PA-RISC, IBM RS6000, SGI
_________________________________________________________________
Vendor:
Synopsys Inc
700 East Middlefield Road
Mountain View, CA 94043
Phone: (415) 962-5000
Fax: (415) 965-8637
email: ?
URL:
Product(s):
HDL Compiler(tm) for Verilog
Description:
The HDL Compiler family provides translation and architectural
optimization of Verilog design descriptions prior to logic
synthesis. It's architectural optimization is based on resource
selection and implementation of DesignWare(tm) Synthetic
Designs. The HDL Compiler family works with the
industry-leading logic synthesis and test synthesis product
lines, Design Compiler(tm) and Test Compiler(tm), to quickly
produce designs that are often smaller and faster than is
possible using schematic capture techniques.
Supports:
Most workstation platforms
_________________________________________________________________
Vendor:
Systems Science Inc.
1860 Embarcadero Rd., Suite 260
Palo Alto, CA 94303
Phone: (415) 812-1800
Fax: (415) 812-1820
email: info@systems.com
URL:
Product(s):
MAGELLAN, POWERFAULT, POWERSIM, VERA, VERITY
Description:
MAGELLAN - Graphic source-level debugger and waveform display.
Runs with interactive Verilog, from VCD dumps, or from SSI's
VCD++ binary, indexed files. Can load and display files of over
200Mb almost instantaneously. Loaded with powerful features.
POWERFAULT - A push-button IDDQ solution for Verilog designs.
It finds near-optimal IDDQ vectors, and generates detailed
fault coverage reports. It can be used in conjunction with
conventional fault simulators to increase the coverage, or
independently, by itself. Handles both "stuck-at" and "short"
faults.
POWERSIM - Get accurate power information, at an early stage in
the design. Use your unmodified Verilog-HDL sources, plus
backannotated capacitance and voltage information. Compute the
dynamic power usage for the whole circuit, or for portions of
the hierarchy. Avoid heat, power, and metal migration problems.
VERA - A design verification system, which allows design and
verification engineers to thoroughly exercise complex Verilog
circuits. Users create compact and powerful test benches in the
high level Vera language. Vera verifies the design by
simulating the test bench, while it talks via PLI with a
Verilog simulator that simulates the design.
VERITY - A kit for tool developers that handles the full
Verilog-HDL language, and provides the following self-contained
modules with their corresponding APIs: (a) parser, (b)
hierarchical database builder and navigator, (c) elaborator and
flattener, (d) behavioral to compiled code (machine code for
SPARC, C for other architectures), and (e) fault divergence and
convergence.
Supports:
SPARC, HP700
_________________________________________________________________
Vendor:
Verilog Consulting Service
885 N. San Antonio, Suite S
Los Altos, CA 94022
Phone: 1-415-917-3800
FAX:
Email: vcs-info@webnexus.com
URL: http://www.vcs.webnexus.com
Product:
Consulting Services
Description:
Verilog Consulting Service was created by more than a dozen
members of Chronologic Simulation, who left that company, which
was then a subsidary of Viewlogic Systems, in a sercurities
fraud allegation against Viewlogic Systems, relating to the
merger of Chronologic Simulation and Viewlogic.
First and foremost, V.C.S. apologizes deeply for the
inconvenience and concern that this action may have caused you,
the VCS user community. We feel a strong loyalty to you and
know that our leaving does not make your job easier.
We are available to help you with any questions you may have
about VCS. We cannot make enhancements or changes to the
product -- we don't have the source code. However, we are
available to answer questions on general usage, ways to use VCS
more efficiently or suggestions on how to work around the
occasional bug. We don't want you to be dead in the water.
We are also available for general Verilog HDL consulting and
training. We represent experts in Verilog HDL, auxiliary
programs using PLI and of course, a lot of knowledge about how
to best use VCS. While we are working on an agreement with
Viewlogic, we are available to help on your projects. We have a
lot of energy and want to devote it to solving problems
important to our customers. We look forward to hearing from
you.
This offer of help should in no way be construed as competitive
to VCS or Viewlogic. We are not currently available to write a
new simulator or consult on how to make a competing simulator
faster. We hope to apply that knowledge to VCS again one day
soon.
Please feel free to contact any of us with questions.
_________________________________________________________________
Vendor:
Veritools Inc.
161 S. San Antonio Road, Suite 6A
Los Altos, CA 94022
Phone: (415) 941-5050
Fax: (415) 941-5552
email: inquiry@veritools.com
URL:
Product(s):
Undertow, veriLINT, Snapsim, VLTool, Nettool, interVHDL, Vflat,
openHDL Toolkit, Typetool, Metatools, VerilogSIMULATOR, flowHDL
Description:
Veritools software products are software tools specifically
designed for verilog users or CAD groups using Verilog.
Veritools software is available via anonymous ftp at
netcom.netcom.com (192.100.81.100) in the directory
pub/veritools.
Supports:
Sun, HP, PC?
_________________________________________________________________
Vendor:
Vista Technologies, Inc.
1100 Woodfield Road
Schaumburg, IL 60173-5121 USA
Phone: (708) 706-9300
FAX: (708) 706-9317
email: info@vistatech.com
URL:
Product(s):
StateVision, DesignVision, Vista Model Creator
Description:
All of Vista's tools generate Verilog suitable for simulation,
with optional generation specifically for synthesis. All of
Vista's tools allow users to import Verilog include files so
that custom parameters, functions and tasks can be utilized.
DesignVision and StateVision can be integrated with
off-the-shelf Verilog simulators for a complete design and
debug environment (set breakpoints in the diagram, step with
animation, etc.)
StateVision (tm) for Verilog(r)
Graphical state machine editor. Generates Verilog from
bubble diagrams of concurrent state-machines. Open and
customizable system. Shipping 4Q94.
DesignVision (tm) for Verilog(r)
Graphical behavior modeling editor. Uses the DesignVision
methodology ("threads") for specifying behavior
graphically. Open and customizable system. Users can
customize the generated Verilog to their own style and
build their own graphical primitives (including how the
primitives generate Verilog). Shipping now.
Vista Model Creator (tm) for Verilog(r)
Spreadsheet-like interface that generates Verilog for
simulation or synthesis. Compact representation ideal for
ALUs, instruction decoders, etc. Designers have control
over the Verilog datatypes used. Files developed with the
Verilog Model Creator can be read into the Vista Model
Creator for VHDL. Shipping now.
Supports:
Sparc, DECstation (Ultrix), IBM RS/6000, HP 9000/7xx
_________________________________________________________________
Vendor:
Wellspring Solutions, Inc.
P.O. Box 150
Sutton, MA 01590
Phone: (508) 865-7271
Fax: (508) 865-1113
email: info@wellspring.com
URL:
Product(s):
VeriWell, Gates & Timing Preference Module, Standard Delay
Format (SDF) Preference Module, VeriWaves Preference Module
Description:
VeriWell
The EDA industry's lowest cost Verilog simulator,
VeriWell is an interactive Verilog HDL Simulator for
multiplatforms that provides full implementation of
behavioral- and RTL-level simulation, OVI LRM 1.0
compliance, and XL compatibility and performance.
Wellspring's Modular Architecture unbundles major aspects
of the core simulator that allows user to add Preference
functionality as design process changes, saving tool and
development costs. VeriWell also features timescales,
VCDs, synthesis syntax checking, 1st-pass semantic
checking, and debugging features.
VeriWell/Free for MS-DOS, Windows, Macintosh, Sparc, and
Linux is a full-featured free version of the VeriWell
simulator available via BBS at 1-508-865-1113 and via
anonymous ftp at
ftp://iii.net/pub/pub-site/wellspring/...
Gates & Timing Preference
This option adds User-Defined Primitives (UDPs) and
Specify Blocks. The implementation of UDPs is optimized
for performance, utilizing state-of-the-art scheduling
and table-lookup techniques. The Gates & Timing
Preference is available for all supported environments.
Standard Delay Format (SDF) Preference
The SDF optional module will be available soon for all
supported platforms and environments.
VeriWaves Preference
Wellspring's enhanced, full-featured waveform viewer will
be available soon as an optional module for MS-DOS,
Windows, Macintosh, and OS/2 (as a seamless Windows
application).
Supports:
386-, 486-, Pentium-based PCs running MS-DOS 5
Macintosh running System 7
Sparc and Sparc-compatible stations running SunOS and Solaris
Windows 3.1, Windows NT, Windows '95
OS/2 Warp 3.0
Linux
_________________________________________________________________
Subject: A02: Books and Reference material on Verilog - REF_FAQ v1b0
[provided by Cliff Cummings - cliffc@qualis.com]
Alphabetical listing of materials by category:
* New or revised since REF_FAQ v1b0
(acknowledgement to Fjthomas@aol.com for corrections)
VERILOG REFERENCE MATERIALS
===========================
*(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by
E. Sternheim, R. Singh, Y. Trivedi, R. Madhavan and
W. Stapleton
*(R2) "DIGITAL DESIGN WITH VERILOG HDL", by
E. Sternheim, R. Singh and Y. Trivedi
*(R7) Feature Columns by L. Saunders and Y. Trivedi, regular
columns in Integrated System Design Magazine
(formerly ASIC & EDA Magazine)
(R4) "QUICK REFERENCE FOR VERILOG HDL", by
R. Madhavan
*(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by
D. Thomas and P. Moorby
NEW*(R8) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE, Second
Edition", by D. Thomas and P. Moorby
*(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by
Sutherland HDL Consulting
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
(O6) "1993 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL"
*(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0
(O7) "OPENEXCHANGE"
(O8) "OPENEXCHANGE" (Back Issues)
*(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING"
*(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF."
NEW*(O9) "PROCEEDINGS FROM '94 INT'L VERILOG HDL CONF."
*(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0
*(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0
VENDOR REFERENCE MATERIALS
==========================
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS"
(V3) "CADENCE VERILOG-XL TRAINING COURSE"
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE"
(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
(V1) "VERILOG-XL REFERENCE MANUAL"
REF_FAQ REFERENCE-INCLUSION POLICY
==================================
VERILOG REFERENCE MATERIALS
===========================
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by D. Thomas
and P. Moorby.
ISBN 0-7923-9126-8
: | :
Kluwer Academic Publishing Co. | Kluwer Academic Publishers Group
Order Department | Order Department
P.O. Box 358 | P.O. Box 322
Hingham, MA 02018 | 3300 AH Dordrecht
| The Netherlands
Phone: 617-871-6600 | Phone: +31 78 524400
FAX: 617-871-6528 | FAX: +31 78 524474
e-mail: kluwer@world.std.com | e-mail: services@wkap.nl
- Text examples are available upon e-mail request to
thomasmoorbybook@cadence.com
- A personal favorite. Good insights into the Verilog
language by P. Moorby, one of the original authors of
Verilog. (Submitted by Cliff Cummings)
(R2) "DIGITAL DESIGN WITH VERILOG HDL", by E. Sternheim, R. Singh
and Y. Trivedi.
ISBN 0-9627488-0-3
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., Bldg. A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: >
Or Contact Raj Singh, Phone: 415-428-4200
E-mail: rajvir@interhdl.com
- Comes with a DOS-format floppy disk which includes all text
examples.
- Only complaint is that the book has no index.
- Y. Trivedi has a regular column in Integrated System Design
magazine.
(Submitted by Cliff Cummings)
(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by E. Sternheim,
R. Singh, Y. Trivedi, R. Madhavan and W. Stapleton.
ISBN 0-9627488-2-X
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: >
Or Contact Raj Singh, Phone: 415-428-4200
E-mail: rajvir@interhdl.com
- Revised edition of (R2) with added 75 page Synthesis
chapter, 60-page Verilog HDL semantics chapter, and can
be purchased with a PC Verilog Simulator.
- This book DOES have an index.
- PC Simulator: "This is a full Verilog simulator with the
following exceptions: no PLI, specify blocks are ignored,
no switch level constructs but gates and primitives are
supported. Also there is a size limitation on the design."
(from Eli Sternheim).
(R4) "QUICK REFERENCE FOR VERILOG HDL", by R. Madhavan
ISBN 0-9627488-4-6 - 1993
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., #A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
E-mail: help@apc.com
Or Contact Raj Singh, Phone: 408-749-8775, FAX: 408-749-8823
E-mail: rajvir@interhdl.com
Automata Verilog Quick Reference
================================
Advantages: - 24 pages - Spiral Bound.
- Intended to provide a quick reference for
semantics and examples.
- 3-page section on Synthesis supported/unsupported
constructs.
Disadvantages: - 24 Table of Content entries. No index.
- Synthesis section reportedly differs from the OVI
synthesis guidelines.
- Lists Net data types but not all of the Reg data
types, pp 2-3.
- Missing keywords: casex, casez, edge, endspecify,
macromodule, strength, xnor, xor, pg 4.
- Only lists 4 compiler directives, omits `timescale
(among others), pp 3-4
- Lists only three $system tasks ($time, $finish,
$setuphold scattered throughout examples).
- Typo: Combinational 3:1 MUX UDP example mis-labeled
as "inverted out", pg 7.
- Other minor omissions.
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Note from Rajeev Madhavan: many of the above issues will be
addressed in the pending next revision)
(Submitted by Cliff Cummings)
(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by Sutherland HDL
Consulting - Nov 1994
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
E-mail: stuart@sutherland.com (Stuart Sutherland)
Sutherland Verilog Quick Reference
==================================
Advantages: - 24 pages.
- Intended to be a quick reference language
syntax guide.
- Lists 16 compiler directives including `timescale.
- Lists ~25 $system tasks, including 7
specify-block timing checks, $monitor,
$display, $stop, file-I/O tasks.
- Based on March 1993 - OVI 2.0 Spec (includes
some newer Verilog constructs)
Disadvantages: - 44 Table of Content entries. No index.
- No Synthesis section (but not necessarily
useful to, or needed by all Verilog users).
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Submitted by Cliff Cummings)
(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck.
ISBN 0-442-00312-9
Mark Rosneck's e-mail address: mark_rosneck@mentorg.com
Van Nostrand Reinhold
Mail Order Department
P.O. Box 668
Florence, KY 41022-0668
1-800-354-9706
(The material in this book is) not limited to Verilog, but
it does give a good, practical introduction to the processes
and tradeoffs involved in designing an ASIC. (Submitted by
Daniel Sears)
(R7) Feature Columns by L. Saunders and Y. Trivedi, regular columns
in Integrated System Design Magazine (formerly ASIC & EDA Magazine)
Integrated System Design
5150 El Camino Real Ste D31,
Los Altos, CA 94022-9873
Free subscription for qualified readers:
To qualify by phone: (800) 643-READ (7323)
Subscribe onlnie to http://www.netline.com/isd
Interactive online subscription number: telnet asic.com 2110
Monthly (occasionally missed) column covering Verilog and
VHDL modeling topics. Well worth reading. (Submitted by Cliff
Cummings)
(R8) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE, Second Edition",
by D. Thomas and P. Moorby.
ISBN 0-7923-9523-9
: | :
Kluwer Academic Publishing Co. | Kluwer Academic Publishers Group
Order Department | Order Department
P.O. Box 358 | P.O. Box 322
Hingham, MA 02018 | 3300 AH Dordrecht
| The Netherlands
Phone: 617-871-6600 | Phone: +31 78 524400
FAX: 617-871-6528 | FAX: +31 78 524474
e-mail: kluwer@world.std.com | e-mail: services@wkap.nl
This fully revised Second Edition features:
-- new and more detailed examples
-- a more formal presentation of the language
-- comprehensive cross-references for each section
-- a disk containing a DOS version of the VeriWell(tm)
Verilog simulator as well as examples from the book.
The simulator can be used to solve the examples.
(Submitted by Eric Maki of Kluwer Academic Publishers)
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
OVI is the organization charged with Verilog standardization
and language enhancements. OVI is currently pursuing Verilog
IEEE and ISO standardization.
For the following publications contact Lynn Horobin at the
OVI office.
Open Verilog International
Lynn Horobin
15466 Los Gatos Blvd., Suite 109-071
Los Gatos, CA 95032
Phone: (408) 353-8899 -- FAX: (408) 353-8869
e-mail: ovi@netcom.com
(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0*
- $100 per copy, plus local sales tax
(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0*
- $150 per copy, plus local sales tax
(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0*
- $100 per copy, plus local sales tax
(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING",
(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF.",
(O6) "1994 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL",
- No charge
(O7) "OPENEXCHANGE", monthly OVI publication,
- No charge
(O8) "OPENEXCHANGE" (Back Issues), monthly OVI publication,
- $5 per copy
(O9) "PROCEEDINGS FROM '94 INT'L VERILOG HDL CONF.",
- $50 per copy, plus local sales tax
* Versions 1.0 of the LRM, PLI and SDF are still available.
VENDOR REFERENCE MATERIALS (Have requested an update from Cadence)
==========================
(V1) "VERILOG-XL REFERENCE MANUAL", 3 Volumes, Version 1.6c June
1993 (Contact your local Cadence sales office)
- A good set of reference manuals with examples, after you
have learned Verilog, or if you have a specific question.
(Submitted by Cliff Cummings)
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE
MANUAL", Version 1.1f September 1989, Version 1.1f September
1989 Release notes, Version 1.2b November 1990 Release notes.
(Contact your local Cadence sales office)
- Explains the commands that are used with the GR_WAVES graphics
package. (Submitted by Cliff Cummings)
(V3) "CADENCE VERILOG-XL TRAINING COURSE", Version 3.3, August 1991.
(Contact your local Cadence sales office)
- Reasonable training materials.
- A number of the training slides contain examples with minor
syntax errors and other examples that must be corrected before
they will run (it is obvious that not all of the training
examples were tested).
- The training course notebook does not have an index and really
needs one. (Submitted by Cliff Cummings)
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS", Release 3.3.a
April 14, 1992. (Contact your local Cadence sales office)
- No index, but a good set of labs to accompany the training
course. (Submitted by Cliff Cummings)
(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
E-mail: stuart@sutherland.com (Stuart Sutherland)
REF_FAQ REFERENCE-INCLUSION POLICY
==================================
If anyone is aware of other Verilog reference materials, please
forward the information to Cliff Cummings -
cliffc@qualis.com
REF_FAQ Reference-Inclusion Policy:
(1) Materials should be released and publicly available
(pre-release announcements will no longer be included in
REF_FAQ).
(2) Publisher/Vendor pricing information will be added only upon
Publisher/Vendor request (exception: OVI published prices
have been noted).
(3) Reviews, if added, will be credited to the reviewer.
(4) Magazines will only be listed if they carry a regular
Verilog-related column (such as Integrated System
Design(R7)).
(5) These policies are subject to suggestions and change!
--
Steve Phillips (715) 726-5412 sjp@cray.com