The Bandit chip acts as a bridge for information between two busses in various Apple computers. The "upstream" bus is the CPU bus. The CPU bus is Apple's implementation of the PPC bus and is known as the ARBUS. The ARBUS is an arbitrated bus. This means that any Master device on the ARBUS may request and be granted control of the bus by an arbiter device.
In the Apple Network Server, the CPU Bus arbiter is contained in the Hammerhead Memory controller.
Arbitration on a bus requires that each device on that bus have a dedicated line (wire) used for requesting mastery of the bus and a dedicated line indicating to the device that it has control of the bus. The ARBUS is more complex in that it treats the data and address busses separately and has Masters and Slaves.
The Bandit's five control lines for bus arbitration are
Lines for Masters: BusRequest (BR), BusGrant (BG), Data Bus Grant (DBG)
Lines for Slaves: Read Data Available (RDDA), Source/Sink Data (SSD)
There is also a line shared amongst all the bus occupants called Data Bus Write Only (DBWOL).
Each of these lines runs to the Hammerhead so that the Hammerhead can receive bus mastering requests and grant bus mastery according to algorithms built into it.
The above information on arbitration is less certain than most of this document. The line names above come from the table System Bus Arbitration on pages 17 and 18 of Apple's "ANSHardwareDevNotes.pdf". However, the patent for the techniques used in the Hammerhead Memory Controller/CPU Bus Arbiter (patent # 5,592,631) describes the CPU bus arbitration lines as being BR, BG, SACK, RDDA, SSD and DBG. Somewhere along the way from patent to implementation one signal was disposed of, or there may be some other explanation for the inconsistency.
The Apple patent that appears to cover the methods used in the Bandit CPU bus - PCI bus bridge chip is #5,692,137. Patents back to the 70's are available on line at the US Patent office's web site.
In any case, I can only find five lines that run from the Bandit to the Hammerhead Memory Controller and I have not identified any common line that could be DBWOL. Motorola's document MPC601EC.pdf shows a DBWOL pin on the PPC 601 processor (pin 297) but that line does not appear to run to any of the pins on the PPC601 CPU daughter card.
Additionally, on the Power Macintosh 7200 there does not appear to be any connection between the soldered down PPC601's DBWOL pin and the CPU bus arbiter. Note that the 7200 uses a different chip (non-Hammerhead) for bus arbitration.
Moving downstream, the PCI bus has its own much simpler arbitration scheme. PCI bus arbitration is a simple matter of PCI devices requesting bus mastery on their REQ lines and being granted mastery by a central bus arbiter on their GNT lines. PCI Bus arbitration is not handled by the Bandit. In this sense the Bandit is not a complete PCI controller. PCI bus arbitration is handled by a small 28 pin PLCC chip near the Bandit labeled 343S0182-1 (or on some machines 343S0018-01).
REQ and GNT are optional lines in the PCI specification, but they must be present on a slot for that slot to be a "Bus Mastering" slot. All slots in Apple's implementations of PCI are Bus Mastering slots. This implies that the PCI Bus Arbiter has as many as six lines for REQ and GNT because Bandit 1 on the ANS has six PCI devices connected to it. At least one of the lines has a higher priority than the other, because the Grand Central chip (a PCI device itself) has a higher bus mastering priority than other PCI devices on Bandit 1.
Another support chip for the Bandit's PCI bus is a clock buffer. Apple has used at least two different models and manufaturers of this chip. The most common is the Motorola MPC904. The clock buffer takes a 33.3333 MHz input (or any clock input, but 33.3333 is used for PCI) and reproduces it without skew (or with minimal skew) on multiple output pins. Each pin can support a load from up to two devices. So a clock buffer with six output pins might support up to twelve devices needing a synchronized clock signal. The other clock buffer used seems to be a Cypress part with number W40C06A or 337S6553. Pinout for these parts can often be found with a search on http://www.icmaster.com.
The PCI line known as IDSEL is another line that is unique for each PCI slot. I guess I left some detail out or assumed that one has read the PCI spec. For most of the signals on the PCI bus, a single wire (per signal) goes to all the slots. So in a three PCI slot bus, all three slots share the address lines, AD[0], AD[1], etc to AD[31]. Likewise for FRAME, IRDY and TRDY, etc. However, each slot has its own unique REQ and GNT lines, which makes logical sense. When a slot is given Grant it needs to be the only slot seeing the signal making it the bus master.
Another signal that is unique for each slot is IDSEL. However, at the Bandit end, each IDSEL is tied to an address line on the Bandit. This is commonly done in PCI implementations, but I haven't read enough to explain it. Apple's machines typically start with AD[13] for the IDSEL of slot 1 and work their way up from there.
The Bandit is a 208 pin quad flat pack with 52 pins on each side. Each of the PCI bus pins has a 47 ohm resistor between it and its destination. CPU bus pins are wired directly into the CPU bus without intervening components unless noted. The part number written on the package of every Bandit I have ever seen is 343S0020 <newline> F642070APPM.
Okay, I thinks that's all that requires exposition. On to the pinout. After the pinout there'll be a few notes on pins that I'm not certain about.
1 AD[0]
2 AD[1]
3 AD[2]
4 AD[3]
5 5V
6 AD[4]
7 AD[5]
8 AD[6]
9 AD[7]
10 CBE[0]
11 GND
12 AD[8]
13 AD[9]
14 AD[10]
15 AD[11]
16 AD[12]
17 AD[13]
18 5V
19 AD[14]
20 AD[15]
21 CBE[1]
22 GND
23 LOCK, 4.7Kohm to 5V; Note 1
24 STOP
25 DEVSEL
26 GND
27 CLK (from MPC904 or equivalent)
28 GND
29 TRDY
30 IDRDY
31 FRAME
32 GND
33 AD[16]
34 AD[17]
35 5V
36 AD[18]
37 AD[19]
38 AD[20]
39 AD[21]
40 AD[22]
41 AD[23]
42 GND
43 CBE[3]
44 AD[24]
45 AD[25]
46 AD[26]
47 AD[27]
48 5V
49 AD[28]
50 AD[29]
51 AD[30]
52 AD[31]
53 GND
54 GND
55 DL31
56 DL30
57 DL29
58 DL28
59 5V
60 DL27
61 DL26
62 DL25
63 DL24
64 GND
65 DL23
66 DL22
67 DL21
68 DL20
69 DL19
70 5V
71 DL18
72 DL17
73 DL16
74 DL15
75 DL14
76 GND
77 DL13
78 DL12
79 DL11
80 DL10
81 DL9
82 5V
83 DL8
84 DL7
85 DL6
86 DL5
87 DL4
88 GND
89 DL3
90 DL2
91 DL1
92 DL0
93 DH31
94 GND
95 DH30
96 DH29
97 DH28
98 DH27
99 5V
100 DH26
101 DH25
102 DH24
103 DH23
104 GND
105 DH22
106 DH21
107 DH20
108 GND
109 DH19
110 DH18
111 DH17
112 DH16
113 5V
114 DH15
115 DH14
116 DH13
117 DH12
118 GND
119 DH11
120 DH10
121 DH9
122 DH8
123 DH7
124 5V
125 DH6
126 DH5
127 DH4
128 DH3
129 DH2
130 GND
131 DH1
132 DH0
133 A0
134 A1
135 A2
136 5V
137 A3
138 A4
139 A5
140 A6
141 GND
142 A7
143 A8
144 A9
145 A10
146 GND
147 A11
148 A12
149 A13
150 A14
151 5V
152 A15
153 A16
154 A17
155 A18
156 GND
157 A19
158 A20
159 A21
160 5V
161 A22
162 A23
163 A24
164 A25
165 GND
166 A26
167 A27
168 A28
169 A29
170 GND
171 A30
172 A31
173 CPU bus arbitration line; Hammerhead pins 118 or 119
174 CPU bus arbitration line; Hammerhead pins 137 or 138
175 CPU bus arbitration line; Hammerhead pins 127 or 128
176 5V
177 TEA
178 TA
179 CPU bus arbitration line; Hammerhead pins 124 or 125
180 CPU bus arbitration line; Hammerhead pins 143 or 144
181 TS
182 GND
183 CPU Clk (Sysclk, bus speed of motherboard)
184 GND
185 ARTRY
186 Choose memory decode,1Kohm to GND or 4.7Kohm to 5V; note 2
187 Choose memory decode,1Kohm to GND or 4.7Kohm to 5V; note 2
188 GND
189 CI
190 5V
191 TBST
192 TSIZ2
193 TSIZ1
194 TSIZ0
195 TT3
196 GND
197 TT1
198 GND
199 REQ; note 3
200 RST
201 5V
202 PERR, 4.7Kohm to 5V; note 1
203 GND
204 SERR, 4.7Kohm to 5V; note 1
205 GNT; note 3
206 PAR
207 CBE[2]
208 GND
note1: LOCK, PERR and SERR are optional PCI signals which are not supported in the ANS or most Apple computers. However, according to Apple documentation, they are supported in the PM7200 and the 7200 does use the same Bandit controller as the ANS. Hence these signals must be available on the Bandit and these are the pins they track to from the PCI slots in the 7200. In the ANS and Power Surge architecture machines these pins are tied as noted.
note 2: The ANS and the Power Surge architecture supposedly support up to four Bandit chips each occupying a different memory space. Each Bandit needs some way of knowing what memory space it is occupying. By tying these two pins to 5V or GND in the possible combinations, you can tell a Bandit which of the four possible memory spaces it should decode. This is largely supposition on my part. But Bandit 1 and Bandit 2 are tied in different ways, and the 7200 is tied in yet another way and these pins don't seem to go anywhere else.
note 3: Yes the Bandit has a REQ and GNT line just like any PCI device. It's periods as Bus Master are controlled by the PCI Bus arbiter chip just like any other PCI device.
A note on Copyright. This document probably isn't copyrightable by me, since much of this is Apple information. Feel free to spread it freely to anyone you think it will help with their development efforts, but I'd appreciate it if you credit me with its origination. I worked very hard to discover this information. I spend upwards of 60 hours reading PCI specs, reading Motorola documents and coming up to speed, not to mention hours on end with a multimeter checking which little pin connected to which other little pin. When there are 52 pins in an inch that's some eye-straining work.
And if anyone has a Hammerhead or Grand Central pinout I'm still looking.
