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- Start with mem.doc for an overview of the project. This document will
- explain the other files.
-
- If you have any comments or questions about the documentation, leave me
- Email on the Denver Amiga BBS, (303) 693-4735. If you cannot get the board
- to work, please try to get local help from some technical type. I cannot
- debug miswiring over the phone.
-
- Several people have asked about expanding the board. I have two
- suggestions. If you can, the easy thing to do would be to use 1 meg chips.
- These are very expensive at present, but would give you a 4 meg board. The
- extra address multiplexer is already there, only a little rework of the
- select lines is needed. A second copy of the memory array is possible,
- including the drivers. If you do this, you must add another chip to develop
- more ras lines. Also, you will have to add a power supply since the Amiga
- cannot handle more chips than are on the present design.
-
- This project is released to the public domain for non commercial use. This
- entire archive file is copyright 1986 by Michael W. Fellinger, 1590 Quince
- Ave. Boulder, Co 80302. Any contributions cheerfully accepted at that
- address. Anyone interested in commercial use should contact me first.
-
- Please feel free to post this INTACT set of files to other bulletin boards,
- but do not alter or delete anything. I will only be able to update the
- documentation if comments and suggestions can get back to me! Please see
- the updates below.
-
- My next hardware project for the Amiga will be a cheap hard disk interface.
- Anyone interested should leave me Email. At this time, the hardware has been
- figured out, but I need a device driver. Help would be appreciated.
-
- UPDATES!!!!
-
- re-release of 22-jun-86
-
- 1. Caution about memory power pins in mechanical.
-
- 2. Deletions in schematic file fixed, including source for MCYC* and RFRQ*
-
- 3. Simplification to acknowledge circuit.
-
- Note, the acknowledge circuit change is to make the circuit conform to the
- intentions of Amiga for expansion boards. I must urge everyone to change
- their boards to match, since the old way might cause a bus contention
- problem (which I can find no evidence for with a scope) so lets not take
- chances. This demonstrates one of the hazards of trying to build addons for
- an "open bus" machine that seems to have secret documentation.
-
- Also, the need for the above change got to me in a most remarkable way. Henry
- Birdseye picked up a suggestion that the problem existed from a national net
- where it was placed by Kelly McArthur (thanks to both). However, Mr.
- McArthur is commenting on "an article by Louis Mamakos", who apparantly
- placed the project on the net. I don't know if Louis "filed the serial
- numbers off" or not, but the information very nearly didn't get back to me
- because the above information about how to get in touch with me was missing.
- I can only incorperate feedback from users if I can get it.
-
-
- Re-release of 06-Jul-86
-
- 1. Some more deletions fixed in schematic
-
- 2. Control circuit substantially revised to improve memory address setup
- times. This modification affects A2, A3, A4, A5, B1, B2, B3, B4, B5,
- B6(deleted), D5, and p2,p14 of C1-5. Most of the connections to these chips
- are the same, so substantial time can be saved by being careful that a wire
- does need to be removed. The chip at B1 becomes a 74LS00 taken from B6. B6
- remains empty. All other chips are as before.
-
- 3. The parts list has been updated to show one less 74LS10 (was at B1).
-
- 4. The programs have been included in both source and object form. Also,
- minor changes have been made to improve these programs. In particular, the
- clock have date and time set independently, even if the clock chip has
- invalid data. The memory test can be aborted using control C (may take a
- little time - lean on the key).
-
-