Explore the World of Soft…e: Engineering & Science/Explore_the_World_of_Software_Engineering_and_Science_HRS_Software_1998.iso/programs/electrnc/digisim.txt

Text File | 1997-09-18 | 32KB | 1,085 lines

Digital Design Laboratory
Computer Science Department
Michigan State University
East Lansing, MI 48828

July 1, 1986

Contact me, Professor Richard J. Reid, at the above address, or
phone me at [phone], to discuss troubles or report
successes. Please include a SASE for correspondence.  You will
probably wish to print a hardcopy of this file for reference in
performing the included experiment and in using the various
components in experiments of your own design.  Column one is used
for  print control in this file:

                 S  New Page
                 +  Suppress Line Advance
            <blank> New Line

I believe this diskette is sufficient basis to launch a one or
two term laboratory in digital logic and computer design.  You
would choose the textbook and present the theoretical basis.
Unfortunately, I have not yet prepared as elaborate documentation
as I or my students would like, so you'll also have to suffer
through discovering most things yourself. As I've probably told
you before, there is a series of seven video tapes supporting
this laboratory that are available.

To create networks of your own design you will need an editor
that will allow you to prepare ASCII files similar to the data
files included on this disk.

The files on this distribution include:

     This file:                         README
     The simulator:                     SIM.EXE
     The data for Exp1:                 EXP1DATA
     Data for an advanced experiment:   HBO

 This file contains:
     A copy of a sample first experiment.
     A listing of individual component characteristics.
     A listing of command-line flags that control the input phase.
     A listing of keyboard actions that are possible during
   simulation.
     A listing of the contents of the video-tape series.



                   DIGITAL DESIGN LABORATORY, CPS 417


Experiment 1.                                           Fall 1986



Begin this experiment by using the simulator with the command
line:

                                sim exp1data

On your screen you will see the following list of components roll
by as the input processor does its task.

                      /* Experiment  1  Data */

  Switch 1a s0 ZERO;       And 1b s0 s1 aout;    Probe 1c aout;
  Switch 1a s1 ONE;

  Switch 2a s2 ZERO;        Or 2b s2 s3 Oout;    Probe 2c Oout;
  Switch 2a s3 ONE;

  Switch 3a s4 ONE;         Mux2 3b s4 pa s5 mout;  Probe 3cmout;
       Pulser 3a pa ONE 100;
  Switch 3a s5 ZERO;

  Switch 4a s6 ONE; Counter 4b s6 clock | O2 O1 O0;  Probe 4c O2;

  Clock 4a clock ZERO 100 0 200;                     Probe 4c O1;

                                                     Probe 4c O0;


Next, enter the experimental phase and observe the components'
behaviors as you  change  the  switch  values and cause the
pulser to cycle.  Verify the proper logical operation of each of
the components.

Note, in the upper  left  corner  of  the  screen  that  the
time  display indicates  time  passing furiously.  Immediately to
its right is the length of the queue of gates waiting  to  be
evaluated  because  they  have  been activated by one of their
inputs having changed.  Depress one of the Switch keys for an
extended period and note the queue-length grow.  Then when  the
Switch is released the simulation will catch up with the queued
changes and the queue will shrink.

Use the "G" option and a redraw "r" to place the names on the
gates.

Type a "T" and the time display will no  longer  be  updated
although  the simulation will continue.  Notice that the Clock
appears to be cycling more rapidly when there's less display
activity  for  the  computer  to  manage.  Give  another  "T"
and the time display will be reactivated.  The toggling action
you have just observed with the "T" is a property  of  many  of
the  interactive  keys,  i.e.   alternate  key  activations
start and stop some  feature.

Next type a "t" and notice the "throbing" of the Counter
activated  by  the Clock.   Activate  the  other  gates  (by
changing their inputs), and their "throbs" will appear also.  The
throb-mode allows a quick examinination  of gate  outputs without
having to add probes to a network, and can be helpful in
debugging.  The next "t" will toggle the "throb" back to off.
When the network is first displayed, the entire circuit is on
the  screen, but  it  is  possible  to view only a sub-region of
the network.  The arrow  keys on the right of the keyboard
control the  boundaries  of  the  viewing window.   If  you  try
the arrow key now, the window can't expand, because it's already
full size.  If you hold down the "Ctrl" key  while  you  press
one  of  the  right  or left arrow keys, the corresponding
boundary will be contracted.  Unfortunately the "Ctrl"  action
is  not  available  for  the  up/down  arrow  keys and you must
instead use the "Home" key to the left of the up arrow to
contract the upper boundary, and the "End" key to the  left of
the  down  arrow  to  contract  the  lower  boundary.   Use
these  key  combinations to experiment with moving the window
over  the  network.   The  adjusted  size  of the new network
display area is shown on the top line of  the display.  The
network is redrawn in the newly-sized  window  using  the  "r"
command.

As you see the signals appear in the "panes" of some of the
components  you will  notice them passing through an intermediate
uncertain state for every transition  between  the  logical
values.   This  uncertain  condition  is indicated  visually  by
a  diagonal  line  in  the  panes.  To aid in this  observation
you can slow down the simulation  by  introducing  a  real-time
wait loop by typing a number of "z"'s.  Each "z" doubles a wait
loop count.  The minus sign in the upper left corner indicates
"slow".  The  slowing  by  "z"'s can be countered with speed-ups
from typed "y"'s.  The plus sign will reappear when the wait loop
is minimized.

 As a single, integrated DEMO session show your TA the following:


      1.  And and Or gates treating uncertainties differently.

      2.  The addressing and routing capabilities of the
 multiplexer.

      3.  The Counter portion of the network filling up the
entire           screen.

      4.  The effect of indeterminate values  on  the  reset
input  to  the Counter.   Why  is  there  such  a drastic action
on the Counter's contents even if the reset doesn't make it all
the way to ZERO?
       5.  A  network  you've  created  using  the Editor.  Have
your network consist of two Switches, an Xnor, and a Probe.

If time remains during this period, do some work on  the  next
experiment. In any case, plan on using the "arranged" hours of
your lab BEFORE the next scheduled laboratory period to be
certain that you'll be able  to  complete  your  demonstration
of  the  next lab exercise early in the next scheduled  period.

                     DIGITAL DESIGN LABORATORY, CPS 417

                              SIM  Version  6.0

                                 Components


The input to  SIM  consists  of  a  list  of  components
indicating  their interconnections.  The input is free-form.
White-space and comments may be  used freely to enhance
readability.  Comments are  bracketed  with  /*  */.  Comments
may be nested but may not be included within tokens. Fields are
delimited by spaces, tabs and newlines.

 Individual components have the form:

    <Name> [ !<label> ] <cell-designator> [ <input-list> ] [ | ]
      [ <output-list> ] [ <symbolic-parameters> ] [
<numeric-parameters> ] ;

where [..] indicates a field that may not be present in all
record types.

The record fields are case sensitive, and all  primitives  have
a  leading capital letter.

A range for the components' delays is given in the descriptions
below.  The smaller  end  of  the  range is indicative of the
most rapid propagation of input effects to the output for the
given type of device.  The  higher  end of the range represents
the maximum delay the given type may exhibit.


And
Variable number of inputs.
Delay: 15-22
Example: (With five inputs)
    And 2K a b c d e Out;


Arm
Four inputs, six outputs.
The falling edge of the drive signal moves the arm according to:
    c1,c0: (0,0) (0,1) (1,0) (1,1) :: (up) (right) (left) (down)
C1 and C0 must not be in transition when the drive makes its
transition.  Horizontal and vertical 3-bit outputs give the
current position.
The output values are coded so: (down) > (up) and (right) >
(left)
The reset signal currently has no effect.
Delay: 20-30
Example:
    Arm 2b c1 c0 drive reset h2 h1 h0 v2 v1 v0;

Clock
One output, one symbolic parameter, three integer parameters.
The symbolic parameter specifies  the  quiescent  value  of  the
output.   The  integer  parameters are: "on" duration, offset
from t = 0, and period.
Delay: 10-15
Example:
    Clock 4W-5X Clk ONE 200 100 500;


 Counter
+_______
 Two inputs, variable number of outputs.
 A synchronous counter with active-low reset signal.  The  count
occurs  on
 the falling edge.
 Delay: 15-22
 Example: (With five outputs)
    Counter aB Reset Count | O4 O3 O2 O1 O0;


 Dec2x4
+______
 Two  inputs  to  be  decoded, one active-low input for enabling.
There are
 four active-low outputs.
 Delay: 15-22
 Example:
    Dec2x4 2A I1 I0 Enable O3 O2 O1 O0;


 Dec3x8
+______
 Three  inputs  to be decoded, one active-low input for enabling.
There are
 eight active-low outputs.
 Delay: 15-22
 Example:
    Dec3x8 4X I2 I1 I0 Enable O7 O6 O5 O4 O3 O2 O1 O0;


 Die
+___
 Seven LED-like spots in a Die configuration.
    Spot configuration:      a     e

                             b  d  f

                             c     g
 Example:
    Die 9x a b c d e f g;


 Disk
+____
 There  are  two  inputs  and  no  outputs.   The  first  input
controls the
 direction of spin, one for counterclockwise, and the second
input activates
 the   spin  when  high.   Only  the  graphical  presentation  is
currently
 implemented.
S



         5


 Example:
    Disk 2b ccw spin;


 End
+___
 Terminates the body of the corresponding Module.
 Example:
    End ;


 Endm
+____
 Terminates the Macro body.
 Example:
    Endm ;


 Gate
+____
 Two  inputs  and  one  output.  A clock signal is gated to the
output under
 control of a gating signal.  Only complete, positive clock
pulses appear at
 the  output  regardless  of  the  timing  of  the  gate  signal.
 Gate  is
 high-active.
 Delay: 10-15
 Example:
    Gate 2b clk2 gate g-clock;


 Hexobot
+_______
 Four inputs, six outputs, and one integer parameter.
 The falling edge of the drive signal causes a move as:
     c1,c0 : (0,0) (0,1) (1,0) (1,1) :: (BK) (CW) (CCW) (FWD)
 c1 and c0 must not be  in  transition  when  the  drive  makes
its  active
 transition.   The  six  outputs  are activated by switches on
the hexobot's
 skirt.  These switches close as on-screen objects are bumped.
The  integer
 parameter  is  the  size  of  step  (in screen dots) the hexobot
takes when
 moving forward or backward.
 Delay: 20-30
 Example:
    Hexobot 2b c1 c0 drive reset o5 o4 o3 o2 o1 o0 3;


 Jkff
+____
 Master/slave  flip-flop  with  asynchronous, active-low Set and
Clear.  The
 clock input is normally low.  The master rank accepts inputs
when the clock
 is  high,  and  the falling edge of the clock gates the master
to the slave
 rank.  This is a pre-defined Macro of eight Nands.
 Delay: As determined by the Nand network.
 Example:
    Jkff aa Set J Clk K Clr Q Q';



S



         6



 Local
+_____
 This optional statement must immediately follow a Macro
statement.
 A variable number of node labels may be declared.
 Example:
    Local x3 x2 x1 x0;


 Logic-analyzer
+______________
 Variable  number  of inputs.  The inputs are displayed as
functions of time
 using the character set {0,?,1}.  A transition to ONE  of  the
reset  line
 re-initializes  the display.  The first numeric parameter sets
the sampling
 time.  The second numeric parameter gives the character
dot-width  of  each
 display sample.
 Example: (With three inputs to be displayed)
    Logic-analyzer 4x I2 I1 I0 reset 10 7;


 Macro
+_____
 This  header  statement introduces a Macro form.  The subsequent
statements
 until the corresponding Endm; defines the body of the macro.
 Example: (With five formal parameters)
    Macro Name-one pa pb pc pd pe;


 Module
+______
 This header statement introduces a Module.  The subsequent
statements until
 the corresponding End; define the components within this
Module.   Modules
 may  be  nested and have variable numbers of inputs and outputs.
This is a
 graphical organization device only without any logical
significance.
 Example: (With five inputs and three outputs)
    Module 4S Ia Ib Ic Id Ie | Ox Oy Oz;


 Mux2
+____
 This  multiplexer  has  two  data inputs and an address input.
The address
 selects between the data inputs and routes that value to the
single output.
 Delay: 20-30
 Example:
    Mux2 2A I1 I0 Addr Out;


 Mux4
+____
 This  multiplexer has four data inputs and two address inputs.
The address
 selects the data input and routes that value to the single
output.
 Delay: 20-30
 Example:
    Mux4 3G I3 I2 I1 I0 a1 a0 Out;



S



         7



 Mux8
+____
 This  multiplexer  has  eight  data  inputs  and three address
inputs.  The
 address selects the data input and routes that value to the
single output.
 Delay: 20-30
 Example:
    Mux8 23 I7 I6 I5 I4 I3 I2 I1 I0 a2 a1 a0 Out;


 Nand
+____
 Variable number of inputs.
 Delay: 10-15
 Example: (With three inputs)
    Nand 4E a b c d;


 Nor
+___
 Variable number of inputs.
 Delay: 10-15
 Example: (With five inputs)
    Nor 4E a b c d e f;


 Not
+___
 Delay: 10-15
 Example:
    Not 1W Sig Sig';


 One-shot
+________
 This  device  emits  a  single pulse for each edge-trigger
activation.  The
 first symbolic parameter is the quiescent output, and  the
second  is  the
 triggering  direction for the input.  The integer parameter is
the duration
 of the emitted pulse.
 Delay: 10-15
 Example:
    One-shot 2x in out ZERO ONE 50;


 Or
+__
 Variable number of inputs.
 Delay: 15-22
 Example: (With two inputs)
    Or 3J A B Or(A,B);


 Power-on
+________
 The  single  output  is normally used for state initialization.
The single
 symbolic parameter is the quiescent value immediately upon start
up.   The
 integer  parameter  gives  the  time  at  which  the  output
changes to the
 complement of the quiescent value to remain there for the
remainder of  the
S



         8


 simulation.
 Example:
    Power-on 3Z clr ZERO 100;


 Presettable-counter
+___________________
 This  variable-length  counter  has asynchronous, active-low
load and reset
 signals.  The count occurs on the falling edge of the clock
signal.
 Delay: 15-22
 Example: (As a four-bit counter)
    Presettable-counter aB I3 I2 I1 I0 Load Reset Count | O3 O2
O1 O0;


 Probe
+_____
 A logic probe with a single input.
 Example:
    Probe 3D Sig;


 Pulser
+______
 A  momentary  switch.   The symbolic parameter is the quiescent
value.  The
 integer parameter is the duration of the output.  There  is  a
maximum  of
 eight pulsers which may be used.
 Delay 10-15
 Example:
    Pulser 2C Pa ZERO 100;


 Ram16x4
+_______
 Random  access  memory:  16  words by 4 bits.  Active-low write
and enable.
 Outputs are zero when not enabled.
 Delay: 10-15
 Example:
    Ram16x4 2B I3 I2 I1 I0 a3 a2 a1 a0 R/W' Enable O3 O2 O1 O0;


 Ram16x8 Ram32x4 Ram32x8 Ram64x4 Ram64x8
+_______ _______ _______ _______ _______
 Additional  Ram's  available.   The  number  of data and address
lines vary
 according to size.


 Register
+________
 This  is  a  variable-width  register.   The  inputs  are
captured  by  an
 active-low load signal.
 Delay: 10-15
 Example: (With a width of three bits)
    Register 5R I2 I1 I0 Load | O2 O1 O0;




S



         9



 Rom16x4
+_______
 A  read-only  memory  with  16  words  by  4 bits.  Active-low
enable.  The
 outputs are zero when the Rom is not enabled.  The contents are
listed from
 low to high address.
 Delay: 10-15
 Example: (With contents set equal to address)
    Rom16x4 2B a3 a2 a1 a0 enable O3 O2 O1 O0 0 1 2 3 4 5 6 7 8 9
10  11  12
 13 14 15;


 Rom16x8 Rom16x12 Rom16x16 Rom32x4 Rom32x8 Rom32x12 Rom32x16
Rom64x4 Rom64x8
+_______ ________ ________ _______ _______ ________ ________
_______ _______
 Rom64x12 Rom64x16
+________ ________
 Additional Rom's available.  The number  of  address  lines,
outputs,  and
 contents vary according to size.


 Scope
+_____
 There  may  be  a  variable number of inputs and these will be
displayed as
 function of time.  The last input causes a recording sweep to
occur  on  a
 transition to ONE.  The first integer parameter sets the
sampling time, and
 the second gives the trace length (in screen dots) for each
display value.
 Example: (With three traces)
    Scope 4x I2 I1 I0 reset 20 3;


 Seven-segment
+_____________
 The segments turn on when their corresponding input is a ONE.
   Segment configuration:
                               a
                              ---
                            f| g |b
                              ---
                            e| d |c
                              ---

 Example:
    Seven-segment 9w a b c d e f g;


 Shift-register
+______________
 This  is  a  universal synchronous shift register of variable
length.  Both
 parallel and serial input and output are provided.  The
mode-control inputs
 select the function according to:
 M1,M0: (0,0)-hold; (0,1)-SR; (1,0)-SL; (1,1)-Load.
 the mode-selected action occurs on the falling edge of the
clock.  Reset is
 active-low and asynchronous.
 Delay: 15-22
 Example: (With three-bit width)
    Shift-register aB SRin I2 I1 I0 SLin M1 M0 reset clock | O2
O1 O0;

S



        10



 Sound
+_____
 The  four-bit  input  selects  the  pitch of the note played on
the micro's
 speaker.  The rising edge of the gating signal causes  the  note
to  play.
 Successive  pitches  have  a  ratio  equal to the twelfth-root
of two.  The
 enable is low-active.
 Example:
    Sound 5G I3 I2 I1 I0 Gate Enable;


 Switch
+______
 Switches  have  a  single  output that initially has the value
of the given
 symbolic parameter.  The first switch in the source file is
assigned to the
 "0"  key  of  the  keyboard,  the second to "1", etc.  The
eleventh through
 sixteenth to ":;<=>?".  There is a limit of 16 switches.
 Delay: 10-15
 Example:
    Switch 3A Sw1 ONE;


 Sync
+____
 This  synchronizing  element  transfers the data input to the
output at the
 falling edge of the clock.  The input may be asynchronous.
 Delay: 10-15
 Example:
    Sync 1b data clk s-data;


 Time-probe
+__________
 This component gives a digital readout of the time a given value
is reached
 by the sampled input.  The capture must  be  suitably  armed.
The  single
 input  is  the signal to be monitored.  The first symbolic
parameter is the
 threshold being monitored  for  the  input  signal.   The
second  symbolic
 parameter is the value of the input signal that will re-arm the
capture.
 Example:
    Time-probe 2a sigx ???  ONE;
 This example  displays  the  time  when  sigx  comes  to  the
value  "???"
 (uncertain).  Re-arming occurs when sigx becomes ONE.


 X-stepper
+_________
 This  positioning  device has asynchronous control inputs.  The
rising edge
 of C0 followed by the rising edge of C1 gives a positive
increment  to  the
 X-position.   The  opposite  phasing  in  the  changes of C0 and
C1 gives a
 decrease in the position.  The current position  is  given  as
a  four-bit
 output.   Whenever  one  of the control signals is in
transition, the other
 must be stable.
 Delay: 20-30
 Example:
    X-stepper 7b C1 C0 o3 o2 o1 o0;

S



        11



 Xnor
+____
 Exclusive-nor  (equivalence)  gate.  If there are more than two
inputs, the
 function is that of even-parity.
 Delay: 15-22
 Example: (With three inputs)
    Xnor 5J a b c d;



 Xor
+___
 Exclusive-or gate.  If there are more than two inputs, the
function is that
 of odd-parity.
 Delay: 15-22
 Example: (With five inputs)
    Xor 9Q a b c d e f;


 Y-stepper
+_________
 See the description of the X-stepper.
 Delay: 20-30
 Example:
    Y-stepper 7b c1 c0 o3 o2 o1 o0;




                                Command Line
+                               ____________

 The command line can have  a  supplementary  parameter  that
controls  the
 actions of SIM.  For example,

     sim <infile> <flags (hex)>   {generic}

             or

     sim EXP1DATA 3C74


 If the flag field is omitted the default flag used is 3.

 The flags are composed as the union of the desired bits from
below:

   Flag Name            Value      Action (if bit is set).

   Time_Disp_flag         0x1      Turns on the time display.
   Mem_Part_flag          0x2      Displays the segment register
contents.
   Throb_flag             0x4      Turns on the icon
oscillograph.
   Q_Audit_flag           0x8      Enables auditing of the event
queue.
   CompIO_flag           0x10      Provides commentary on the
input.
   A_lists_flag          0x20      Lists the activation sets.
S



        12


   Audit_Tab_flag        0x40      Enables auditing of the
interconnections.
   Sub_Cell_flag         0x80      Displays the packing of screen
cells.
   Manhattan_flag       0x100      Enables Manhattan-type
interconnections.
   Scrn_Cell_flag       0x200      Shows the screen-grid
allocations.
   Sig_Q_flag           0x400      Displays the length of the
event queue.
   Echo_flag            0x800      Enables echoing of keyboard to
screen.
   M_Audit_flag        0x1000      Enables auditing of memory
allocation.
   Symbol_flag         0x2000      Shows symbol table operations.

   Node_label_flag     0x4000      Disables the labeling of
interconnections.
   Dynamic_alloc_flag  0x8000      Enables comments on heap
actions.
   Interconnect_flag  0x10000      Turns off the drawing of
interconnections.
   Stack_flag         0x20000      Enables comments on stack
allocation.
   Gate_Decal         0x40000      Enables the labeling of
primitive gates.
   Q_Warp             0x80000      Provides disgnostic for
time-warp.
   Hash_flag         0x100000      Dumps the hash table.
   Echo_comp_flag    0x200000      Turns off the echoing of the
source file.
   MAC_DEF_FLAG      0x400000      Dumps the macro definitions.
   MAC_VERBOSE       0x800000      Enable comments during macro
formation.


 The above flags which apply to the simulation interval can also
be  toggled
 by interactive keyboard entries.




                     DIGITAL DESIGN LABORATORY, CPS 417

                        SIM    Version 6.0    6-9-86

                             Interactive Control

 During simulation the network may be logically stimulated  or
the  display
 may be controlled.  The following single-key actions are
provided:

            Key  Action
             +   Double the window-growth increment--F1..F8
effect.
             -   Halve the window-growth increment.
             A   Cycle through foreground colors (needs color
monitor).
             B   Toggle the window border drawing option.
             C   Toggle the window foreground/background color.
             D   Toggle the auditing of dynamic (HEAP)
allocation.
             E   Toggle echo of key to screen.
             H   Toggle the "Halt" of the simulation.
             I   Toggle the drawing of interconnections.
             K   Toggle the auditing of stack usage.
             L   Toggle the window labeling option.
             l   Toggle the the option of including node labels.
             M   Toggle Manhattan/point-to-point
interconnections.
             m   Set the Module display hierarchy to the next
higher level.
             n   Set the Module display hierarchy to the next
lower level.
S



        13


             Q   Toggle  Q-Warp  (Q  entries  in  reverse   time
 sequence)
 reporting.
             q   Toggle auditing (error checking) of event queue.

             R   Reset the simulation to time zero.
             r   Redraw the network in the current window.
             S   Toggle print of diagnostics of signal queueing.
             s   Toggle print of diagnostics of cell divisions.
             T   Toggle time display.
             t   Toggle "throb" display.  This is an
                 oscillographic-type display that is drawn
                 within the icon of each component.
             W   Advance to the next window.
             w   Wipe the current window to the background color.

             x   Exit SIM.
             y   Decrease the delay loop.
             z   Increase the delay loop, i.  e.  slow down the
screen
                 presentation so you can watch the changes.
         Arrow   Move window boundary with respect to the
                 virtual circuit space in the direction
                 indicated.
    Ctrl-Arrow   Contract window edge indicated.
          Home   Contract top window edge.  Ctrl Up and Down
                 Arrow are stripped off by the DOS keyboard
processor.
           End   Contract bottom window edge.
    0..9:;<=>?   Toggle the logic state of the switch with the
                 corresponding screen label.  If presently
indeterminate,
                 change to one.
    "Alt"-0..9   If corresponding switch is at zero or one change

                 its output to indeterminate.  If indeterminate,
                 change to zero.
          a..h   Activate the pulser with the corresponding
label.




















S



        14



 The function keys control the physical screen size of the
windows  through
 which  the virtual circuit is viewed.  The labels below indicate
the action
 of these keys in moving window edges in either of two modes.

                |
             F5 ^                                           F5
F7
                |                                           |
 |
             F7 v corner                                    ^
 v
                | position                                  |
 |
       ---<--->-*---------------   ---
----*------*----
         F1  F2 |              |    ^ F6                |
     |
                |              |    |height   OR   F1-<-*->-F2
F3-<-*->-F4
                |              |    v F8     <-->       |
     |
                ----------------   ---
----*------*----
                     width                                  |
 |
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S


                      COMPUTER SCIENCE DEPARTMENT


                       DIGITAL DESIGN LABORATORY


    The following video tapes are available for review in the
audio-visual
 section of the main library or they can be purchased for
off-campus use.
 One is broadcast each week on the campus video network on
Mondays at 9:00
 a.m.  Lecture 1 is broadcast on the first Monday of the term.

    The files listed below are available from the TA or can be
obtained to
 accompany off-campus purchases.  These are most of the files
used in the
 video-taped demonstrations.  You are encouraged to use these
files to
 clarify netlist specifications, to experiment with networks, and
to form
 the basis of networks you need to create for the various
experiments.


  Lecture   Topics
Files

     1      Introduction, single-output combinational
NT1, FIBOC,
            networks, oscilloscope instrumentation.
FIBOMUX

CNTSCOPE

     2      Logic analyzer, multiple-output combinational
CATDOG
            networks, static hazards.
ALL3

CHAINLA

     3      Latches, flip-flops, simple machines,
LATCH
            event-driven simulation.
JKHIER

FFGG

     4      Initialization, synchronization with asynchronous
TCSYNC
            external inputs, feedback error control,
ANDCHAIN
            conservative simulation and waveform dispersion.
DISPER

     5      Tone generation, sequential controllers, stepper
DORA
            motors, stack machine and periodicity in event
STACK
            queues.
DISKS

     6      The 4B1 computer:  instruction set, timing,
4B1ROM
            hard-wired control, executing a program from ROM,
4B1
            manual program entry and execution using RAM.

     7      A micro controller for the 4B1, microprogramming,
MCNTRL
            discarding the hard-wired control and merging.
4B1&UC
            Writing netlist generators in a high-level
BIG200
            language.