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The 80386 has no machine dependent options.
In order to maintain compatibility with the output of gcc,
as supports AT&T System V/386 assembler syntax. This is quite
different from Intel syntax. We mention these differences because
almost all 80386 documents use Intel syntax. Notable differences
between the two syntaxes are:
Opcode names are suffixed with one character modifiers which specify the
size of operands. The letters `b', `w', and `l' specify
byte, word, and long operands. If no suffix is specified by an
instruction then as tries to
fill in the missing suffix based on the destination register operand
(the last one by convention). Thus, `mov %ax, %bx' is equivalent
to `movw %ax, %bx'; also, `mov $1, %bx' is equivalent to
`movw $1, %bx'. Note that this is incompatible with the AT&T Unix
assembler which assumes that a missing opcode suffix implies long
operand size. (This incompatibility does not affect compiler output
since compilers always explicitly specify the opcode suffix.)
Almost all opcodes have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two opcode suffixes in AT&T syntax. Base names for sign extend and zero extend are `movs...' and `movz...' in AT&T syntax (`movsx' and `movzx' in Intel syntax). The opcode suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are `bl' (from byte to long), `bw' (from byte to word), and `wl' (from word to long).
The Intel-syntax conversion instructions
are called `cbtw', `cwtl', `cwtd', and `cltd' in
AT&T naming. as accepts either naming for these instructions.
Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, but are `call far' and `jump far' in Intel convention.
Register operands are always prefixed with `%'. The 80386 registers consist of
Opcode prefixes are used to modify the following opcode. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to give operand and address size (16-bit operands are specified in an instruction by prefixing what would normally be 32-bit operands with a "operand size" opcode prefix). Opcode prefixes are best written on the same line as the instruction they act upon. For example, the `scas' (scan string) instruction is repeated with:
repne scas %es:(%edi),%al
You may also place prefixes on the lines immediately preceding the
opcode, but this circumvents checks that as does with
prefixes, and will not work with all prefixes.
Here is a list of opcode prefixes:
.code16 section) into 32-bit operands/addresses. These prefixes
must appear on the same line of code as the opcode they modify.
For example, in a 16-bit .code16 section, you might write:
addr32 jmpl *(%ebx)
An Intel syntax indirect memory reference of the form
section:[base + index*scale + disp]
is translated into the AT&T syntax
section:disp(base, index, scale)
where base and index are the optional 32-bit base and
index registers, disp is the optional displacement, and
scale, taking the values 1, 2, 4, and 8, multiplies index
to calculate the address of the operand. If no scale is
specified, scale is taken to be 1. section specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax must
be preceded by a `%'. If you specify a section override which
coincides with the default section register, as does not
output any section register override prefixes to assemble the given
instruction. Thus, section overrides can be specified to emphasize which
section register is used for a given memory operand.
Here are some examples of Intel and AT&T style memory references:
Absolute (as opposed to PC relative) call and jump operands must be
prefixed with `*'. If no `*' is specified, as
always chooses PC relative addressing for jump/call labels.
Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, or long) with an opcode suffix (`b', `w', or `l', respectively).
Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long (32-bit) displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the `data16' opcode prefix), since the 80386 insists upon masking `%eip' to 16 bits after the word displacement is added.
Note that the `jcxz', `jecxz', `loop', `loopz',
`loope', `loopnz' and `loopne' instructions only come in byte
displacements, so that if you use these instructions (gcc does
not use them) you may get an error message (and incorrect code). The AT&T
80386 assembler tries to get around this problem by expanding `jcxz foo'
to
jcxz cx_zero
jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:
All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an opcode suffix and a constructor associated with it. Opcode suffixes specify operand's data types. Constructors build these data types into memory.
Register to register operations should not use opcode suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as if you wrote `fst %st, %st(1)', since all register to register operations use 80-bit floating point operands. (Contrast this with `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location `mem')
While as normally writes only "pure" 32-bit i386 code,
it also supports writing code to run in real mode or in 16-bit protected
mode code segments. To do this, put a `.code16' directive before
the assembly language instructions to be run in 16-bit mode. You can
switch as back to writing normal 32-bit code with the
`.code32' directive.
The code which as generates in 16-bit mode will not
necessarily run on a 16-bit pre-80386 processor. To write code that
runs on such a processor, you must refrain from using any 32-bit
constructs which require as to output address or operand
size prefixes.
Note that writing 16-bit code instructions by explicitly specifying a prefix or a suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine instruction sequence `66 6a 04', which pushes the value `4' onto the stack, decrementing `%esp' by 2.
pushw $4
The same code in a 16-bit code section would generate the machine instruction sequence `6a 04' (ie. without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.
The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.
For example
fsub %st,%st(3)
results in `%st(3)' being updated to `%st - %st(3)' rather than the expected `%st(3) - %st'. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is `%st' and the destination register is `%st(i)'.
There is some trickery concerning the `mul' and `imul'
instructions that deserves mention. The 16-, 32-, and 64-bit expanding
multiplies (base opcode `0xf6'; extension 4 for `mul' and 5
for `imul') can be output only in the one operand form. Thus,
`imul %ebx, %eax' does not select the expanding multiply;
the expanding multiply would clobber the `%edx' register, and this
would confuse gcc output. Use `imul %ebx' to get the
64-bit product in `%edx:%eax'.
We have added a two operand form of `imul' when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying `%eax' by 69, for example, can be done with `imul $69, %eax' rather than `imul $69, %eax, %eax'.
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