Next | Prev | Up | Top | Contents | Index

R8000 and R4400 Implementations

The R4000 already made a step in the direction of Performance Mode by defining the FS bit in the FSR, the floating-point control and status register. When FS is set, denormalized results are flushed to zero or minN depending on current Rounding Mode instead of causing an unimplemented operation exception. This feature eliminates the most objectionable aspect of Precise Exception Mode, namely the slow propagation of denormalized intermediate results via softfp. However, it does not eliminate the need to precisely trap floating-point exceptions because denormalized input operands must still be handled by softfp.

The R8000 extends the R4000 floating-point architecture to include another control bit whose states are labeled PERF and PREX, for Performance Mode and Precise Exception Mode, respectively. In Performance Mode the R8000 hardware (see Table 5-3) does the following:

R8000 Performance Mode
ValueInputResultFlags
A:TooSmall-0 or minNU=1, I=1 E=1 if FS=0
B:ExactDenorm00 or minNU=1, I=1 E=1 if FS=0
C:InexactDenorm-0 or minNU=1, I=1 E=1 if FS=0
D:ExactNormDDU=0, I=0
E:InexactNorm-rnd(E)U=0, I=1

The E bit, which becomes sticky in Performance Mode, signifies that a denormalized number was mapped to 0 or minN. Note that the R8000 can only flush denormalized input operands to zero, as opposed to either zero or minN. This deviation is unfortunate but unlikely to be noticeable and is not scheduled to be fixed.

In Precise Exception Mode the R8000 hardware (see Table 5-4) does the following:

R8000 Precise Exception Mode
ValueInputResultFlags
A:TooSmall-trapU=1, I=1
B:ExactDenormtraptrapU=1, I=1
C:InexactDenorm-trapU=1, I=1
D:ExactNormDDU=0, I=0
E: InexactNorm-rnd(E)U=0, I=1

Unlike the R4400, the R8000 totally ignores the FS bit in this case and relies on softfp to emulate the result. This simplification degrades the performance of Precise Exception Mode but does not alter the results.

Performance Mode is retrofitted on the R4400 by enhancing the kernel and softfp. The emulation of Performance Mode deviates from the definition in that the cause bits of the FSR are not cleared by every floating-point operation, but instead continue to be updated based on the result of the operation. This deviation is necessary to achieve acceptable performance.


Next | Prev | Up | Top | Contents | Index