Language/OS - Multiplatform Resource Library/LANGUAGE OS.iso/self/contrib.lha/contrib/simulator/lib.self

Text File | 1991-05-23 | 13.8 KB | 362 lines

"$ Revision: 1.0 $"
"Copyright 1990:
    Jecel Mattos de Assumpcao Jr.
    LSI - EPSUP, Sao Paulo, SP, Brasil"

    " Simulation Libraries "

library _DefineSlots: ( |
    basic* = ( |
        pfet = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = 'p channel MOS transistor'.
                drain. source. gate.
                declare = (
                        drain: input.
                        source: input.
                        gate: input.
                ).
                behave = (
                        gate net value isLow ifTrue: [
                            set: gate To: oddballs levels chargeLow.
                            set: drain To: source net value weaker After: 1.
                        ].
                        gate net value isHigh ifTrue: [
                            set: gate To: oddballs levels chargeHigh.
                            set: drain To: oddballs levels highImpedance.
                        ].
                        gate net value isUnknown ifTrue: [
                            | z = oddballs levels highImpedance. |
                            set: gate To: z.
                            set: drain To: ( oddballs levels unknown
                                merge: z
                                   To: z
                                 With: source net value highest weaker
                                   To: source net value lowest weaker ).
                        ].
                ).
        | ).
        nfet = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = 'n channel MOS transistor'.
                drain. source. gate.
                declare = (
                        drain: input.
                        source: input.
                        gate: input.
                ).
                behave = (
                        gate net value isHigh ifTrue: [
                            set: gate To: oddballs levels chargeHigh.
                            set: drain To: source net value weaker After: 1.
                        ].
                        gate net value isLow ifTrue: [
                            set: gate To: oddballs levels chargeLow.
                            set: drain To: oddballs levels highImpedance.

                        ].
                        gate net value isUnknown ifTrue: [
                            | z = oddballs levels highImpedance. |
                            set: gate To: z.
                            set: drain To: ( oddballs levels unknown
                                merge: z
                                   To: z
                                 With: source net value highest weaker
                                   To: source net value lowest weaker ).
                        ].
                ).
        | ).
        bdirNfet = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = 'bidirectional n channel MOS transistor'.
                drain. source. gate.
                declare = (
                        drain: input.
                        source: input.
                        gate: input.
                ).
                behave = (
                        gate net value isHigh ifTrue: [
                            | v. s. d. |
                            s: source net value.
                            d: drain net value.
                            set: gate To: oddballs levels chargeHigh.
                            v:  s resolve: d.
                            set: source To: v weaker After: 1.
                            set: drain To: source net value"v weaker" After: 1.
                        ].
                        gate net value isLow ifTrue: [
                            set: gate To: oddballs levels chargeLow.
                            set: drain To: oddballs levels highImpedance.
                            set: source To: oddballs levels highImpedance.
                        ].
                        gate net value isUnknown ifTrue: [
                            | z = oddballs levels highImpedance. |
                            set: gate To: z.
                            set: drain To: ( oddballs levels unknown
                                merge: z
                                   To: z
                                 With: source net value highest weaker
                                   To: source net value lowest weaker ).
                            set: source To: ( oddballs levels unknown
                                merge: z
                                   To: z
                                 With: drain net value highest weaker
                                   To: drain net value lowest weaker ).
                        ].
                ).
        | ).
        inverter = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = 'inverter'.
                in. out.
                declare = (
                        in: input.
                        out: output.
                       ).
                behave = ( set: out To: (in not) After: 2 ).
                n1. p1.
                netlist = (
                    n1: ( get: library basic nfet ).
                    p1: ( get: library basic pfet ).
                    n1 gate to: in.
                    p1 gate to: in.
                    n1 drain to: out.
                    n1 source to: gnd.
                    p1 drain to: out.
                    p1 source to: vdd.
                ).
        | ).
        nor2 = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = '2 input NOR'.
                in1. in2. out.
                declare = (
                        in1: input.
                        in2: input.
                        out: output.
                       ).
                behave = ( set: out To: (in1 || in2) not After: 3 ).
                n1. n2. p1. p2.
                netlist = (
                    n1: ( get: library basic nfet ).
                    n2: ( get: library basic nfet ).
                    p1: ( get: library basic pfet ).
                    p2: ( get: library basic pfet ).
                    n1 gate to: in1.
                    n2 gate to: in2.
                    p1 gate to: in1.
                    p2 gate to: in2.
                    n1 drain to: out.
                    n2 drain to: out.
                    n1 source to: gnd.
                    n2 source to: gnd.
                    p1 drain to: out.
                    p2 drain to: p1 source.
                    p2 source to: vdd.
                ).
        | ).
        nand2 = ( |
                  parent* = traits simulation component.
                  sim**.
                  dad.
                  leaf.
                  type = '2 input NAND'.
                  in1. in2. out.
                  declare = (
                          in1: input.
                          in2: input.
                          out: output.
                         ).
                  behave = ( set: out To: (in1 && in2) not After: 3 ).
                n1. n2. p1. p2.
                netlist = (
                    n1: ( get: library basic nfet ).
                    n2: ( get: library basic nfet ).
                    p1: ( get: library basic pfet ).
                    p2: ( get: library basic pfet ).
                    n1 gate to: in1.
                    n2 gate to: in2.
                    p1 gate to: in1.
                    p2 gate to: in2.
                    n1 drain to: out.
                    n2 drain to: n1 source.
                    n2 source to: gnd.
                    p1 drain to: out.
                    p2 drain to: out.
                    p1 source to: vdd.
                    p2 source to: vdd.
                ).
        | ).
        or2 = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = '2 input OR'.
                in1. in2. out.
                declare = (
                        in1: input.
                        in2: input.
                        out: output.
                       ).
                behave = ( set: out To: (in1 || in2) After: 5 ).
                nor. inv.
                netlist = (
                    nor: ( get: library basic nor2 ).
                    inv: ( get: library basic inverter ).
                    nor in1 to: in1.
                    nor in2 to: in2.
                    nor out to: inv in.
                    inv out to: out.
                ).
        | ).
        and2 = ( |
                parent* = traits simulation component.
                sim**.
                dad.
                leaf.
                type = '2 input AND'.
                in1. in2. out.
                declare = (
                        in1: input.
                        in2: input.
                        out: output.
                ).
                behave = ( set: out To: (in1 && in2) After: 5 ).
                nand. inv.
                netlist = (
                    nand: ( get: library basic nand2 ).
                    inv: ( get: library basic inverter ).
                    nand in1 to: in1.
                    nand in2 to: in2.
                    nand out to: inv in.
                    inv out to: out.
                ).
        | ).
    | ).
    ttl* = ( |
    | ).
    processor* = ( |
    | ).
    memory* = ( |
        ocLatch = ( |
                   parent* = traits simulation component.
                   sim**.
                   dad.
                   leaf.
                   type = 'one phase clock latch'.
                   in. phi. out.
                   declare = (
                           in: input.
                           phi: input.
                           out: output.
                   ).
                   p1. p2. p3. p4. n1. n2. n3. n4. n5.
                   netlist = (
                       p1: ( get: library basic pfet ).
                       p2: ( get: library basic pfet ).
                       p3: ( get: library basic pfet ).
                       p4: ( get: library basic pfet ).
                       n1: ( get: library basic nfet ).
                       n2: ( get: library basic nfet ).
                       n3: ( get: library basic nfet ).
                       n4: ( get: library basic nfet ).
                       n5: ( get: library basic nfet ).
                       "first stage"
                       p1 source to: vdd.
                       p1 drain to: p2 source.
                       p2 drain to: n1 drain.
                       n1 source to: gnd.
                       p1 gate to: in.
                       p2 gate to: phi.
                       n1 gate to: in.
                       "second stage"
                       p3 source to: vdd.
                       p3 drain to: n2 drain.
                       n2 source to: n3 drain.
                       n3 source to: gnd.
                       p3 gate to: phi.
                       n2 gate to: n1 drain.
                       n3 gate to: phi.
                       "third stage"
                       p4 source to: vdd.
                       p4 drain to: n4 drain.
                       n4 source to: n5 drain.
                       n5 source to: gnd.
                       p4 gate to: n2 drain.
                       n4 gate to: phi.
                       n5 gate to: n2 drain.
                       out to: n4 drain.
                   ).
        | ).
        camCell = ( |
                   parent* = traits simulation component.
                   sim**.
                   dad.
                   leaf.
                   type = 'one bit of Content Addressable Memory'.
                   bit. bitb. word. match.
                   declare = (
                           bit: input.
                           bitb: input.
                           word: input.
                           match: input.
                   ).
                   p1. p2. n1. n2. n3. n4. n5. n6. n7.
                   netlist = (
                       p1: ( get: library basic pfet ).
                       p2: ( get: library basic pfet ).
                       n1: ( get: library basic nfet ).
                       n2: ( get: library basic nfet ).
                       n3: ( get: library basic bdirNfet ).
                       n4: ( get: library basic bdirNfet ).
                       n5: ( get: library basic nfet ).
                       n6: ( get: library basic nfet ).
                       n7: ( get: library basic nfet ).
                       p1 source to: vdd.
                       p1 gate to: p2 drain.
                       p1 drain to: p2 gate.
                       p2 source to: vdd.
                       n1 source to: gnd.
                       n1 gate to: p1 gate.
                       n1 drain to: p1 drain.
                       n2 source to: gnd.
                       n2 gate to: p2 gate.
                       n2 drain to: p2 drain.
                       n3 drain to: n1 drain.
                       n3 gate to: word.
                       n3 source to: bit.
                       n4 drain to: n2 drain.
                       n4 gate to: word.
                       n4 source to: bitb.
                       n5 drain to: n6 drain.
                       n5 gate to: n1 drain.
                       n5 source to: bit.
                       n6 drain to: n7 gate.
                       n6 gate to: n2 drain.
                       n6 source to: bitb.
                       n7 drain to: match.
                       n7 source to: gnd.
                   ).
        | ).
    | ).
    examples* = ( |
    | ).
| )