Language/OS - Multiplatform Resource Library/LANGUAGE OS.iso/self/contrib.lha/contrib/simulator/README

Text File | 1993-06-25 | 7.8 KB | 180 lines

These files are part of a simple digital circuit simulator. It was written
for Self 1.0 and adapted to run in Self 1.1 ( or was it 1.1 and 1.2
respectively? ). It should be easily ported to 2.0 or later simply by
changing the _DefineSlots: in all of the files. I don't think any or
features are version dependent. The "askSim" method uses _ReadInto:Count:
which might have to be rewritten.

The program is not at all elegant and users should be warned that sim.self
creates "global" parent slots in "prototypes simulation": simRoot** and
fsmRoot***. This is so the Self command line can find the components and
pins defined in the circuit being simulated. There is a graphical display
of waveforms, but it writes directly to the screen and is plain horrible.

-----------------------------------
The files are:

   Lines   Name
      23 allSim.self
      12 batch1.self
       5 batch2.self
      12 batch3.self
     126 examples.self
     265 levels.self
     361 lib.self
     528 sim.self
    1332 total

allSim.self reads in the other files.

The batchX.self can save some typing when trying out some examples.

sim.self is the "main" program, with all kinds of objects.

levels.self defines 27 logic "levels" used to model CMOS circuits.

lib.self sets up the names space for defining components and declares
the most basic CMOS transistors ( not really bidirectional! ) and
simple logic gates.

examples.self has some circuits to test several of the simulator's
features.
-------------------------------------
The key object is the component which must have these slots:

  parent* = traits simulation component. "where we get all our smarts"
  sim**.                          "this gets set to the runTime object
                                   so the component can name other
                                   components and global stuff"
  dad.                            "in a complex component hierarchy we
                                   need to know where this component
                                   is contained"
  leaf.                           "TRUE - this is a basic component.
                                   FALSE - this components is defined
                                           in terms of other components"
  type = 'circuit description'.   "just an optional comment"
  pin1. pin2.                     "define some pins so this component can
                                   be connected to others or controlled
                                   by the user"
  declare = ( ... ).              "this method initializes the pin slots
                                   creating input or output pins"
  u1. u2.                         "some slots to hold sub-components"
  netlist = ( ... ).              "this method initializes the sub-
                                   components and connects them to one
                                   another and to the pins"
  behave = ( ... ).               "this method sets the values of the
                                   output pins as a function of the inputs"

A component object can have a netlist slot, a behave slot or both. Sending
a "simulate" message to a component will create a new simulation with the
component expanded ( if it has netlist ) recursively. An "exert" message
does not expand the object ( if it has behave ). The exert is faster but
less precise, but the two simulations should agree rather closely if the
component's definitions are correct. The "askSim" message will give the
user a choice of expanding components which have both netlist and behave
but is not very clear about what component it is talking about.

The idea is to design circuit from the top down. Define the circuit in
Self using behave and test it. When it is right you define it with netlist
and "black box" subcomponents. If you get the same results as before you
choose one of the subcomponents and repeat the process.

As declare, netlist and behave can have any Self expression you wish, the
examples show what can be done with a little imagination.

Other objects are:
  levels - 27 logic levels ( with a wide range of unknowns )
  net - connects pins and resolves level conflicts
  simPin - stores output levels
  runTime - holds the event list and implements the simulation commands
  event - holds a level to be placed on a pin in a future instant
  wave - remembers level/time pairs for plotting waveforms
  fsm - implements finite state machines
-----------------------------------------------
To use the simulator type at the prompt:

'allSim' _RunScript

This will load the simulator if _SelfDir points to the right directory.
The most basic example is a simple combinational circuit with two ORs and
one AND. To start up a new simulation for this circuit type:

library cc simulate

This expands the circuit all the way down to the transistor level. You can
type help to see what commands are available at this point. Before any other
commands, you should type:

restart

The simulate command should probably be modified to do this automaticly but
the restart can be used any time to set the simulation to it's initial state.
You can save some typing by writting:

'batch1' _RunScript

Look in the batch1.self file to see what we did. First, a few watch: commands
created a list of the most interesting pins. Waves will be stored only for
those pins, and only they will be listed when you type:

watch

You can see why this is useful be trying:

all

The next rest of the lines in the file are set:To: or set:To:After: to set
the initial input values and to make a waveform for pin "d". To start the
simulation you can type:

step

This prints the current simulation time after one step. If you try this a
few more times you will see that sometimes the current time stays the same.
Use "watch" to see what is happening to the circuit. "stepTo:" will only stop
when the simulation time is equal to its argument. "stepBy:" used relative
times to tell when to stop. Finally, "run" keeps going until there are
no more event to simulate ( which might never happen in most circuits ). Try
"run" to see where it all ends. You could see the results graphicly with:

draw

I don't recommend it as it draws directly on the screen. The "scale:" and
"offset:" commands will change what is drawn so you can look at any level
of detail you want.
Try repeating the whole thing starting with:

library cc exert

The simulation will go much faster and "all" can show you why. The results
are not exactly the same but are close enough.

Other examples you can try are:

    ff  - it it an example of very high speed CMOS circuits using a single
          phase clock. The actual latch is "ocLatch" and ff just adds an
          inverter to the output so the dynamic circuit can work. File
          "batch3.self" tests the circuit to see if there are setup or
          hold time problems. This can only be simulated at the transistor
          level so "exert" and "askSim" will work exactly as "simulate".

    st - shows how to create a state machine. This divide by three circuit
         can be tested with "batch2.self" with a simple square wave as
         input.

    osc - uses a loop in netlist to connect the six inverters which are
          stored in a vector. Don't try run on this one! It just shows
          what you can do when Self is your circuit description language.
------------------------------------------
Finally, the usual:

This software is copyrighted 1990-1993 by Jecel Mattos de Assumpcao Jr.
The author grants everyone full use of all included software and files
for any purpose, but is not liable for any damages of any nature that
might occur as a result of the use of the software. In other words: if
anything happens, it's your fault.

This will be "cleaned up" and made truly useful sometime in the next
fifty years. When that happens, you can look for that release in the
same place where you got this and you might just be lucky.