DSP56001: 20.5, 27, or 32 MHz fixed point DSP. 24 bit data bus, 16 bit
address bus, 56 bit accumulators (2), host interface port, serial ports (2),
general purpose I/O pins, timer. Harvard architecture. 512 words program
RAM, 512 words data RAM on chip.
DSP56000: Mask-programmed version of DSP56001.
DSP56002: DSP56001 with On-Chip Emulation (OnCE) debug port and clock PLL.
Also has a four cycle double precision multiply and support for block
floating point. Available up to 40 MHz.
DSP56156: 40, 50, or 60 MHz fixed point DSP; 16 bit data bus, 40 bit
accumulators (2), host interface port, serial ports (2), timer, OnCE
debug port, clock PLL, 14 bit sigma-delta voice band CODEC, 2K words
program RAM, 2K words data RAM on chip.
DSP96002: IEEE format floating point DSP; 32 bit data and address bus, two
complete external buses; Harvard architecture.
-------------------------------------
AT&T:
DSP32C: floating point DSP; 32 bit floating point, 16/24 bit fixed point data.
DSP3210: floating point DSP; 32 bit floating point, 16/32 bit fixed point data;
32 bit address and data bus, serial port.
[and others; we don't have a good list, unfortunately].
-------------------------------------
Analog Devices:
ADSP2100: 32 and 50Mhz fixed point DSP (8 MIPS, 12.5MIPS). 16 bit registers
except for multiplyer-accumulate register which is 40 bits. No on chip memory
except for a 16 word instruction cache.
ADSP2101: Derived from ADSP2100, 16 bit registers except for the multiplier
accumulator which is 40 bits. 2Kx24 instruction/data ram in program memory
space, 1Kx16 data ram in data memory space. Adds memory, timer, serial ports,
etc. to the 2100. Fastest speed grade in production is 16.6 MHz (16.6MIPS).
ADSP2102: Ram/rom version of 2101; user selects how much of the 2kx24 program
memory is mask rom.
ADSP2103: 3V version of the 2101.
ADSP2105: 10Mhz fixed point DSP with 1 serial port, timer and 1kx24
instruction/data ram in program memory space, and 512 word data ram
in data memory space. This processor sells for US $9.90 in any quantity.
ADSP2111: adds a 8/16bit host interface port [to 2101?].
ADSP21msp50: ADSP2111 with an on chip a/d and d/a interface and additional
low power modes.
ADSP2161: has 8Kx24 mask rom.
DSP21020: 20/25/33 MHz floating-point DSP; Supports 32-bit fixed point, IEEE
format 32-bit floating point, and 40-bit floating point; 40-bit registers plus two 80-bit fixed-point multiply-accumulators; Harvard arch. with 32 word
instruction cache allows two data accesses in a single cycle; IEEE 1149.1 JTAG boundry scan; 33.3 MIPS @ 33.3 MHz.
ADSP21010: Slower and cheaper version of '020 (16 MHz). Limited to 32-bit
fixed and floating point.
All of the processors (except the 2100) use a 1X instruction clock and use an
on chip PLL to generate an internal 4X clock. All processors have an extended
Harvard architecture which allows two data fetches and an instruction fetch
every cycle in parallel with an alu or mac operation. All instructions
including accessing external memory can complete in 1 cycle.
