Monster Media 1994 #1

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Internet Message Format | 1994-03-06 | 46KB

Path: nlbbs!jaxsat!pagesat.net!news.cerf.net!ihnp4.ucsd.edu!swrinde!gatech!howland.reston.ans.net!math.ohio-state.edu!jussieu.fr!univ-lyon1.fr!swidir.switch.ch!scsing.switch.ch!news.dfn.de!news.coli.uni-sb.de!chris From: chris@pfsparc02.phil15.uni-sb.de (Chris Blum) Newsgroups: comp.os.msdos.programmer,comp.sys.ibm.pc.hardware.comm Subject: The Serial Port, rel. 12, part 2/3 Message-ID: <2l3c0u$jdg@coli-gate.coli.uni-sb.de> Date: 3 Mar 1994 00:46:22 GMT Organization: Institut fuer nutzlose Forschung und angewandte Energieverschwendung Lines: 1091 NNTP-Posting-Host: pfsparc02.phil15.uni-sb.de X-Newsreader: TIN [version 1.2 PL2] [... continued ...] Registers ========= First some tables; full descriptions follow. Base addresses as specified by IBM. COM1 COM2 COM3 COM4 Offs. DLAB Register ------------------------------------------------------------------------------ 3F8h 2F8h 3E8h 2E8h +0 0 RBR Receive Buffer Register (read only) or THR Transmitter Holding Register (write only) 3F9h 2F9h 3E9h 2E9h +1 0 IER Interrupt Enable Register 3F8h 2F8h 3E8h 2E8h +0 1 DL Divisor Latch (LSB) These registers can 3F9h 2F9h 3E9h 2E9h +1 1 DL Divisor Latch (MSB) be accessed as word 3FAh 2FAh 3EAh 2EAh +2 x IIR Interrupt Identification Register (r/o) or FCR FIFO Control Register (w/o, 16550+ only) 3FBh 2FBh 3EBh 2EBh +3 x LCR Line Control Register 3FCh 2FCh 3ECh 2ECh +4 x MCR Modem Control Register 3FDh 2FDh 3EDh 2EDh +5 x LSR Line Status Register 3FEh 2FEh 3EEh 2EEh +6 x MSR Modem Status Register 3FFh 2FFh 3EFh 2EFh +7 x SCR Scratch Register (16450+ and some 8250s, special use with some boards) 80h 40h 20h 10h 08h 04h 02h 01h Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ------------------------------------------------------------------------------- IER 0 0 0 0 EDSSI ELSI ETBEI ERBFI IIR (r/o) FIFO en FIFO en 0 0 IID2 IID1 IID0 pending FCR (w/o) - RX trigger - 0 0 DMA sel XFres RFres enable LCR DLAB SBR stick par even sel Par en stopbits - word length - MCR 0 0 0 Loop OUT2 OUT1 RTS DTR LSR FIFOerr TEMT THRE Break FE PE OE RBF MSR DCD RI DSR CTS DDCD TERI DDSR DCTS EDSSI: Enable Delta Status Signals Interrupt ELSI: Enable Line Status Interrupt ETBEI: Enable Transmitter Buffer Empty Interrupt ERBFI: Enable Receiver Buffer Full Interrupt FIFO en: FIFO enable IID#: Interrupt IDentification pending: an interrupt is pending if '0' RX trigger: RX FIFO trigger level select DMA sel: DMA mode select XFres: Transmitter FIFO reset RFres: Receiver FIFO reset DLAB: Divisor Latch Access Bit SBR: Set BReak stick par: Stick Parity select even sel: Even Parity select stopbits: Stop bit select word length: Word length select FIFOerr: At least one error is pending in the RX FIFO chain TEMT: Transmitter Empty (last word has been sent) THRE: Transmitter Holding Register Empty (new data can be written to THR) Break: Broken line detected FE: Framing Error PE: Parity Error OE: Overrun Error RBF: Receiver Buffer Full (Data Available) DCD: Data Carrier Detect RI: Ring Indicator DSR: Data Set Ready CTS: Clear To Send DDCD: Delta Data Carrier Detect TERI: Trailing Edge Ring Indicator DDSR: Delta Data Set Ready DCTS: Delta Clear To Send RBR (Receive Buffer Register) 3F8h 2F8h 3E8h 2E8h +0 r/o ------------------------------------------------------------------------------ This is where you get received characters from. This register is read-only. THR (Transmitter Holding Register) 3F8h 2F8h 3E8h 2E8h +0 w/o ------------------------------------------------------------------------------ Send characters by writing them to this register. It is write-only. IER (Interrupt Enable Register) 3F9h 2F9h 3E9h 2E9h +1 r/w ------------------------------------------------------------------------------ Enable several interrupts by setting these bits: Bit 0: If set, DR (Data Ready) interrupt is enabled. It is generated if data waits to be read by the CPU. Bit 1: If set, THRE (THR Empty) interrupt is enabled. This interrupt tells the CPU to write characters to the THR. Bit 2: If set, Status interrupt is enabled. It informs the CPU of occurred transmission errors during reception. Bit 3: If set, Modem status interrupt is enabled. It is triggered whenever one of the delta-bits is set (see MSR). Bits 4-7 are not used and should be set 0. DL (Divisor Latch) 3F8h 2F8h 3E8h 2E8h +0 r/w ------------------------------------------------------------------------------ To access this *WORD*, set DLAB in the LCR to 1. Then write a word (16 bits) to this register or write the lower byte to base+0 and the higher byte to base+1 (the order is not important) to program the bps rate as follows: xtal frequency in Hz / 16 / desired rate = divisor xtal frequency in Hz / 16 / divisor = obtained rate Your PC uses an xtal frequency of 1.8432 MHz (that's 1843200 Hz :-). Do *NOT* use 0 as a divisor (your maths teacher told you so)! It results in a rate of about 3500 bps, but it is not guaranteed to work with all chips in the same way. An error of up to 3-5 percent is irrelevant. Some values (1.8432 MHz quartz, as in the PC): bps rate Divisor (hex) Divisor (dec) Percent Error 50 900 2304 0.0% 75 600 1536 0.0% 110 417 1047 0.026% 134.5 359 857 0.058% 150 300 768 0.0% 300 180 384 0.0% 600 C0 192 0.0% 1200 60 96 0.0% 1800 40 64 0.0% 2000 3A 58 0.69% 2400 30 48 0.0% 3600 20 32 0.0% 4800 18 24 0.0% 7200 10 16 0.0% 9600 C 12 0.0% 19200 6 6 0.0% 38400 3 3 0.0% 57600 2 2 0.0% 115200 1 1 0.0% The 16450 is capable of up to 512 kbps according to NS. NS specifies that the 16550A is capable of 256 kbps if you use a 4 MHz or an 8 MHz crystal. But a staff member of NS Germany (I know that this abbreviation is not well-chosen :-( ) told one of my friends on the phone that it runs correctly at 512 kbps as well; I don't know if the 1488/1489 manage this, though. This is true for the 16C552, too. BTW: Ever tried 1.76 bps? Kindergarten kids write faster. The Microsoft mouse uses 1200 bps, 7n1, the Mouse Systems mouse uses 1200 bps, 8n1. See the Mouse chapter for details. IIR (Interrupt Identification Register) 3FAh 2FAh 3EAh 2EAh +2 r/o ------------------------------------------------------------------------------ This register allows you to detect the cause of an interrupt. Only one interrupt is reported at a time; they are priorized. If an interrupt occurs, Bit 0 tells you if the UART has triggered it. Follow the information in this register, then test bit 0 again. If it is still not set, there is another interrupt to be serviced. BTW: If you AND the value of this register with 06h, you get a pointer to a table of four words... ideal for near calls. Another hint: make sure your software reads this register just once and then follows the information it got before it is read again, otherwise your code won't work. The bits 6 and 7 allow you to detect if the FIFOs of the 16550+ have been activated. Bit 3 Bit 2 Bit 1 Bit 0 Priority Source Description 0 0 0 1 none no interrupt pending 0 1 1 0 highest Status OE, PE, FE or BI of the LSR set. Serviced by reading the LSR. 0 1 0 0 second Receiver DR or trigger level rea- ched. Serviced by read- ing RBR 'til under level 1 1 0 0 second FIFO No Receiver FIFO action since 4 words' time (neither in nor out) but data in RX-FIFO. Serviced by reading RBR. 0 0 1 0 third Transm. THRE. Serviced by read- ing IIR (if source of int only!!) or writing to THR. 0 0 0 0 lowest Modem One of the delta flags in the MSR set. Serviced by reading MSR. Bit 6 & 7: 16550A: set if FCR bit 0 set. 16550: bit 7 set, bit 6 cleared if FCR bit 0 set. others: clear. In most software applications bits 3, 6 & 7 should be masked when servicing the interrupt since they are not relevant. These bits cause trouble with old software relying on that they are cleared... NOTE! Even if some of these interrupts are disabled, the service routine can be confronted with *all* states shown above when the IIR is loop-polled until bit 0 is set (don't ask me why; it's just that I encontered this, and it's not much more work to play it safe). Check examples in the Programming section. FCR (FIFO Control Register) 3FAh 2FAh 3EAh 2EAh +2 w/o ------------------------------------------------------------------------------ This register allows you to control the FIFOs of the 16550+. It does not exist on the 8250/16450. Bit 0: FIFO enable. Bit 1: Clear receiver FIFO. This bit is self-clearing. Bit 2: Clear transmitter FIFO. This bit is self-clearing. Bit 3: DMA mode (pins -RXRDY and -TXRDY), see below Bits 6-7: Trigger level of the DR-interrupt. Bit 7 Bit 6 Receiver FIFO trigger level 0 0 1 0 1 4 1 0 8 1 1 14 Note: if bit 0 is cleared, all other bits are ignored. DMA mode operation is not available with your PC, but for the sake of completeness... here we go. If bit 3 is 0, DMA mode 0 is selected. The -RXRDY pin goes active-low whenever there is at least one character in the RX FIFO or in the RBR if the FIFO is disabled. -TXRDY goes active-low when the TX FIFO or the THR is empty. It goes high if one character is written to the THR (same as THRE, that's bit 5 of the LSR). If this bit is 1, DMA mode 1 is selected. The -RXRDY pin goes low if the trigger level of the RX FIFO is reached or if reception timed out (no characters received for a time that would have allowed to receive 4 characters). -TXRDY goes low when the TX FIFO is empty. It goes high again if the FIFO is completely full. If the FIFOs are disabled, DMA mode 1 operates in the same way as DMA mode 0. LCR (Line Control Register) 3FBh 2FBh 3EBh 2EBh +3 r/w ------------------------------------------------------------------------------ This register allows you to select the transmission protocol. It also contains the DLAB bit which switches the function of the addresses +0 and +1. Bit 1 Bit 0 word length Bit 2 Stop bits 0 0 5 bits 0 1 0 1 6 bits 1 1.5/2 1 0 7 bits (1.5 if word length is 5) 1 1 8 bits (1.5 does not work with some chips, see above) Bit 5 Bit 4 Bit 3 Parity type Bit 6 SOUT condition x x 0 no parity 0 normal operation 0 0 1 odd parity 1 forces TxD 'high' (break) 0 1 1 even parity Bit 7 DLAB 1 0 1 mark parity 0 normal registers 1 1 1 space parity 1 divisor at reg 0, 1 Mark parity: The parity bit is always '1' (the line is 'low'). Space parity: The parity bit is always '0' (the line is 'high'). MCR (Modem Control Register) 3FCh 2FCh 3ECh 2ECh +4 r/w ------------------------------------------------------------------------------ This register allows to program some modem control lines and to switch to loopback mode. Bit 0: Programs -DTR. If set, -DTR is low and the DTR pin of the port goes 'high'. Bit 1: Programs -RTS. dito. Bit 2: Programs -OUT1. Normally not used in a PC, but used with some multi-port serial adapters to enable or disable a port. Best thing is to write a '1' to this bit. Bit 3: Programs -OUT2. If set to 1, interrupts generated by the UART are transferred to the ICU (Interrupt Control Unit) while 0 sets the interrupt output of the card to high impedance. (This is PC-only). Bit 4: '1': local loopback. All outputs disabled. This is a means of testing the chip: you 'receive' all the data you send. LSR (Line Status Register) 3FDh 2FDh 3EDh 2EDh +5 r/w ------------------------------------------------------------------------------ This register allows error detection and polled-mode operation. Bit 0 Data Ready (DR). Reset by reading RBR (but only if the RX FIFO is empty, 16550+). Bit 1 Overrun Error (OE). Reset by reading LSR. Indicates loss of data. Bit 2 Parity Error (PE). Indicates transmission error. Reset by LSR. Bit 3 Framing Error (FE). Indicates missing stop bit. Reset by LSR. Bit 4 Break Indicator (BI). Set if RxD is 'high' for more than 1 word ('break'). Reset by reading LSR. Bit 5 Transmitter Holding Register Empty (THRE). Indicates that a new word can be written to THR. Reset by writing THR. Note that this bit works in a weird way when FIFOs are enabled: it goes 0 whenever there are characters in the TX-FIFO, not when the FIFO is full! Bit 6 Transmitter Empty (TEMT). Indicates that no transmission is running. Reset by reading LSR. Bit 7 (16550+ only) Set if at least one character in the RX FIFO has been received with an error. Cleared by reading LSR if there is no further error in the FIFO. Clear with all other chips. MSR (Modem Status Register) 3FEh 2FEh 3EEh 2EEh +6 r/w ------------------------------------------------------------------------------ This register allows you to check several modem status lines. The delta bits are set if the corresponding signals have changed state since the last reading (except for TERI which is only set if -RI changed from active-low to inactive-high, that is if the RI line at the port changed from 'high' to 'low' and the phone stopped ringing). Bit 0: Delta CTS. Set if CTS has changed state since last reading. Bit 1: Delta DSR. Set if DSR has changed state since last reading. Bit 2: TERI. Set if -RI has changed from low to high (ie. RI at port has changed from 'high' to 'low'). Bit 3: Delta DCD. Set if DCD has changed state since last reading. Bit 4: CTS. 1 if 'high' at port. Bit 5: DSR. dito. Bit 6: RI. If loopback is selected, it shows the state of OUT1. Bit 7: DCD. SCR (Scratch Register) 3FFh 2FFh 3EFh 2EFh +7 r/w ------------------------------------------------------------------------------ This is an all-purpose 8 bit store. NS recommends to store the value of the FCR (which is w/o) in this register for further use, but this is not mandatory and not recommended by me (see below). This register is only available with the 16450+; the standard 8250 doesn't have a scratch register (but then again some versions do). On some boards (especially RS422/RS485-boards), this register has a special meaning (enable receiver/transmitter drivers etc.), and with multi-port serial adapters it is often used to select the interrupt levels of the several ports and to determine which port has triggered interrupt. So you shouldn't use it for anything else in your programs. Excursion: Why and how to use the FIFOs (by Scott C. Sadow) ----------------------------------------------------------- Normally when transmitting or receiving, the UART generates one interrupt for every character sent or received. For 2400 bps, typically this is 240/second. For 115,200 bps, this means 11,520/second. With FIFOs enabled, the number of interrupts is greatly reduced. A transmitter holding register empty interrupt is not generated until the FIFO is empty (last byte is being sent). So if you know it's a 16550A and the FIFOs are enabled, your TX interrupt routine can write up to 16 characters to the THR. Monitoring bit 5 (THRE) of the LSR is _no_good_ because this bit will be cleared immediately after your routine has written the first character to the THR! The chip gives you no feedback at all. Thus, the number of transmitter interrupts is reduced by a factor of 16. For 115,200 bps, this means only 720 interrupts per second. For receive data interrupts, the processing is similar to transmitter interrupts. The main difference is that the number of bytes in the FIFO (the trigger level) can be specified. When the trigger level is reached, a receive data interrupt is generated; any other data received is just put in the FIFO. The receive data interrupt is not cleared until the number of bytes in the FIFO is below the trigger level again. To add 16550A support to existing code, there are 2 requirements to be met: 1) When reading the IIR to determine the interrupt source, only use the lower 3 bits. 2) After the existing UART initialization code, try to enable the FIFOs by writing to the FCR. (A value of C7 hex will enable FIFO mode, clear both FIFOs, and set the receive trigger level at 14 bytes). Next, read the IIR. If Bit 6 of the IIR is not set, the UART is not a 16550A, so write 0 to the FCR to disable FIFO mode. Multi-Port Serial Adapters -------------------------- This is material I received from Mike Surikov. I want to give you some information on Multi-Serial adapters that provide four or eight asynchronous serial communication ports. Some of them have an Interrupt Vector (one for each four channels). The Interrupt Vector is used to enable/disable global interrupt and to detect which of the four channels is creating the interrupt (one IRQ is used for a group of four channels). Bit 7 of the Interrupt Vector is used to enable or disable ALL four channels by writing a logical 1 to enable or 0 to disable interrupts. At the same time, each channel can be enabled or disabled separately by programming the OUT2 (and/or OUT1) signal in the 16450 chip. When you read the interrupt vector, you get an indication which port has triggered the interrupt, as it is shown below. [Since this may be different with each board, check your manual for details.] MSB LSB 7 6 5 4 3 2 1 0 <-- Interrupt Vector Register Channel 0 interrupt indicator (0-active) N/A Channel 1 interrupt indicator (0-active) Channel 2 interrupt indicator (0-active) Channel 3 interrupt indicator (0-active) Global interrupt: 1-enable; 0-disable For example, an 8 PORT RS-232 CARD can have the following configuration: Base IRQ Channel Interrupt Address Level Number Vector 2A0 7 0 2BF 2A8 7 1 2BF 2B0 7 2 2BF 2B8 7 3 2BF 1A0 5 0 1BF 1A8 5 1 1BF 1B0 5 2 1BF 1B8 5 3 1BF [The base addresses should be set by jumpers or DIP switches.] Note that the Interrupt Vector Registers overlap Scratch Registers, so the detect_UART routine must be changed for these boards. [See the Programming Section.] Some words about timing ----------------------- The 8250 is a rather slow peripheral chip; it has a cycle delay for both reading and writing of 500nsec, which means that after every read or write access to any of the chip's registers the CPU has to wait at least 500nsec before reading or writing a register again. Good thing that this chip is only used with some old XTs... the 8088/8086/V20/V30 family is slow enough for that. The 16450 and 16550A are rather fast; they need a delay of 125nsec after read access and 150nsec after write access before any other transfer. This means we have a problem with these fancy new machines that allow cycle times of 50nsec and less. Luckily they add wait states to I/O bus accesses (wait states are additional cycles during which the bus does not change its state) or use a slower clock speed for I/O transfers (8 or 12 MHz). So if you have 12 MHz I/O clock speed and one wait state for I/O transfers, you don't have to worry. Some people believe in delaying I/O operations by adding NOPs or JMP $+2 to every I/O instruction (both do nothing but wasting time), but I don't think that's any good with a chip that needs stable data lines for at least 100nsec (so the CPU or the bus controller has to add a wait state anyway). You can always blame the hardware or the setup if your program doesn't work for timing reasons. :) However, there may be a problem with block instructions, esp. OUTSB. This instruction allows you to fill the Tx fifo of the 16550A rather fast (just 5 cycles per transfer on the 286, others take longer), but even a 25MHz 286 takes 200nsec for each transfer, so this should be on the safe side, too. I don't use this instruction, but for other reasons than timing difficulties. It's just not very useful: it takes more time to make sure in advance that you don't overrun your buffer margins during an OUTSB than to check for the margins after every single transfer. Please note that all this relates to ISA boards. I don't have any experience with EISA or other fancy things like VLB! Handshaking ----------- The method of exchanging signals for data flow control between computers and data sets is called handshaking. The most popular and most often used handshaking variant is called XON/XOFF; it's done by software, while other methods are hardware-based. XON/XOFF Two bytes that are not mapped to normal characters in the ASCII charset are called XON (DC1, Ctrl-Q, ASCII 17) and XOFF (DC3, Ctrl-S, ASCII 19). Whenever either one of the sides wants to interrupt the data flow from the other (eg. full buffers), it sends an XOFF ('Transmission Off'). When its buffers have been purged again, it sends an XON ('Transmission On') to signal that data can be sent again. (With some implementations, this can be any character). XON/XOFF is of course limited to text transmission. It cannot be used with binary data since binary files tend to contain every single one of the 256 characters... That's why hardware handshaking is normally used with modems, while XON/XOFF is often used with printers and plotters and terminals. DTR/DSR The 'Data Terminal Ready' and 'Data Set Ready' signals of the serial port can be used for handshaking purposes, too. Their names express what they do: the computer signals with DTR that it's ready to send and receive data, while the data set sets DSR. With most modems, the meaning of these signals is slightly different: DTR is ignored or causes the modem to hang up if it is dropped, while DSR signals that a connection has been established. RTS/CTS While DTR and DSR are mostly used to establish a connection, RTS and CTS have been specially designed for data flow control. The computer signals with RTS ('Request To Send') that it wishes to send data to the data set, while the data set (modem) sets CTS ('Clear To Send') when it's ready to do one part of its job: to send data thru' the phone wires. A normal handshaking protocol between a computer and a modem looks like this: DTR ___--------------------------------------------------------------____ DSR _____-------------------------------------------------------------___ RTS ___________-----------------------_____----------------------________ CTS ____________-------____------------_____----------------------_______ (1)(2) (3)(4) (5) (6) (7)(8)(9)(10) (11)(12)(13) (1) The computer sets DTR to indicate that it wants to make use of the modem. (2) The modem signals that it is ready and that a connection has been established. (3) The computer requests permission to send. (4) The modem informs the computer that it is now ready to receive data from the computer and send it through the phone wires. (5) The modem drops CTS to signal to the computer that its internal buffers are full; the computer stops sending characters to the modem. (6) The buffers of the modem have been purged, so the computer may continue to send data. (7) This situation is not clear; either the computer's buffers are full and it wants to inform the modem of this, or it doesn't have any more data to be send to the modem. Normally, modems are configured to stop any transmission between the computer and the modem when RTS is dropped. (8) The modem acknowledges RTS by dropping CTS. (9) RTS is again raised by the computer to re-establish data transmission. (10) The modem shows that it is ready to do its job. (11) No more data is to be sent. (12) The modem acknowledges this. (13) DTR is dropped by the computer; this causes most modems to hang up. After hang-up, the modem acknowledges with DSR low. If the connection breaks, the modem also drops DSR to inform the computer about it. BIOS API (Application Programs Interface) ----------------------------------------- PC programs are meant to use the BIOS routines to program the UARTs. Even though this is *NOT RECOMMENDED* by me, I give you the BIOS calls as specified by Big Blue. Call INT 14h with: AH=00h Serial port - Initialize AL: see table DX: Port number (0-3; 0 equ. 0x3f8, 1 equ. 0x2f8, etc., see Hardware) Bit 7 Bit 6 Bit 5 Rate [bps] Bit 4 Bit 3 Parity 1 1 1 9600 0 0 none 1 1 0 4800 1 0 none 1 0 1 2400 0 1 odd 1 0 0 1200 1 1 even 0 1 1 600 0 1 0 300 Bit 1 Bit 0 Data bits 0 0 1 150 0 0 5 0 0 0 110 0 1 6 1 0 7 Bit 2 0 -> 1 stop bit, 1 -> 2 stop bits 1 1 8 Returns: AH: RS-232 line status bits Bit 0: RBF - input data is available in buffer 1: OE - data has been lost 5: THRE - room is available in output buffer 6: TEMT - output buffer empty AL: Modem status bits 3: always 1 7: DCD - carrier detect AH=01h Serial port - Write character AL: character to be sent DX: Port Returns: AH: Bit 7 clear if successful, set if not. Bits 0-6 see INT 14h AH=03h AH=02h Serial port - Read character DX: Port Returns: AH: Line Status (see AH=03h) AL: Received character (if AH bit 7 is clear) Note: This routine times out if DSR is not asserted, even if data is available! AH=03h Serial port - Get port status DX: Port Returns: AH: Line Status Bit 7: Timeout Bit 6: TEMT Transmitter empty Bit 5: THRE Transmitter Holding Register Empty Bit 4: Break (broken line detected) Bit 3: FE Framing error Bit 2: PE Parity error Bit 1: OE Overrun error Bit 0: RDF Receiver buffer full (data available) AL: Modem Status Bit 7: DCD Carrier detect Bit 6: RI Ring indicator Bit 5: DSR Data set ready Bit 4: CTS Clear to send Bit 3: DDCD Delta carrier detect Bit 2: TERI Trailing edge of ring indicator Bit 1: DDSR Delta data set ready Bit 0: DCTS Delta Clear to send BIOS variables in the Data Segment at segment 40h: Offset Size Description 00h WORD Base I/O address of 1st serial I/O port, zero if none 02h WORD Base I/O address of 2nd serial I/O port, zero if none 04h WORD Base I/O address of 3rd serial I/O port, zero if none 06h WORD Base I/O address of 4th serial I/O port, zero if none Note: Above fields filled in turn by POST as it finds serial ports. POST never leaves gaps. DOS and BIOS serial device numbers may be redefined by re-assigning these fields. [POST: Power-On Self Test. CB] [Madis Kaal told me that there are BIOSes that leave gaps in the table, and I know of some that don't recognize COM4 correctly.] This information is sneaked from Ralf Brown's famous interrupt list (hope he doesn't mind). If you want more detailed facts on this interrupt, refer to this list. It's available from several FTP sites. Mice ---- The Microsoft Serial Mouse (or compatibles) is the device that is most often used with the Serial Port of the PC; it's the one with the two buttons. Mouse Systems compatible mice have three buttons. Here's some information I received from Stephen Warner and Angelo Haritsis: Pins Used: TxD, RTS, DTR are used as power sources for the mouse. RxD is used to receive data from the mouse. Mouse reset: Set UART to 'broken line' state (set bit 6 of the LCR) and clear the bits 0-1 of the MCR; wait a while and reverse the bits again. Serial Data Parameters: Microsoft Mouse 1200 bps, 7 data bits, 1 stop bit, no parity Mouse Systems Mouse 1200 bps, 8 data bits, 1 stop bit, no parity Data packet format of the Microsoft mouse: The data packet consists of 3 bytes. It is sent to the computer every time the mouse changes state (ie. the mouse is moved or the buttons are released/ pressed) D6 D5 D4 D3 D2 D1 D0 1st byte 1 LB RB Y7 Y6 X7 X6 2nd byte 0 X5 X4 X3 X2 X1 X0 3rd byte 0 Y5 Y4 Y3 Y2 Y1 Y0 The byte marked with 1 is sent first and then the others. The bit D6 in the first byte is used for synchronizing the software to the mouse packets if it goes out of sync. LB is the state of the left button (1 being the LB is pressed) RB is the state of the right button (1 being the RB is pressed) X0-7 movement of the mouse in the X direction since last packet (+ right) Y0-7 movement of the mouse in the Y direction since last packet (+ down ) Data packet format of the Mouse Systems mouse: The data packet consists of 5 bytes. D7 D6 D5 D4 D3 D2 D1 D0 1st byte 1 0 0 0 0 LB MB RB 2nd byte X7 X6 X5 X4 X3 X2 X1 X0 3rd byte Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 4th byte equal to 2nd byte 5th byte equal to 3rd byte Bits 7-3 of the 1st byte are used for synchronization; it's rather improbable that they appear the same way in any of the other bytes. LB is the state of the left button (1 being the LB is pressed) MB is the state of the middle button (1 being the MB is pressed) RB is the state of the right button (1 being the RB is pressed) X0-7 movement of the mouse in the X direction since last packet (+ right) Y0-7 movement of the mouse in the Y direction since last packet (+ up ) The mouse should rather be used with the mouse driver software; this ensures compatibility to future changes and greatly reduces software overhead. See Ralf Brown's interrupt list, interrupt 33h. Modems ====== This chapter is rather brief for several reasons. I'm no modem expert at all and there exist better sources than this document if you want information on modems. Patrick Chen, the author of "The Joy of Telecomputing", has written such a file, and there's one available from Sergey Shulgin, too (I don't have their internet addresses). You can obtain these files from the AFD service; they are named "modem1" and "modem2". A modem (MOdualtor-DEModulator) is an interface between the serial port of your computer and the public telephone network. Modern modems are small computers of their own; they accept commands, do the dialing for you, buffer incoming data, perform data compression and such things. Several standards have been established (Bell, CCITT), and several "command languages" are in use, with the Hayes and Microcom commands being the most popular ones. Modems have two internal modes: the command mode and the data mode. After power-up, the modem is in the command mode, and this mode can be restalled by sending an 'escape sequence' (normally a pause of at least 1 second, then three '+' signs in one second, then a pause of at least 1 second). All I know about modems is some commands and some encoding schemes; I share this knowledge with you - please share yours with me! Encoding schemes ---------------- I've sneaked this table from the posting 'FAQ zu /Z-NETZ/TELECOM/ALLGEMEIN' of Kristian Koehntopp <kris@black.toppoint.de> in 'de.newusers.questions'. He has copyrighted his posting, so please contact him if you wish to reproduce this information in any commercial way. These are the schemes recommended by CCITT (more than one speed means auto-retrain speeds): Transmission speed in bps Baud Modulation duplex usage -------------------------------------------------------------------- V.17 14400 2400 TCM half FAX 12000, 9600, 7200 2400 TCM half FAX 4800 2400 QAM half FAX V.21 300 300 FSK full V.22 1200 600 DPSK full V.22bis 2400 600 QAM full V.23 1200/75 1200/75 FSK asymmetric BTX V.27ter 4800 1600 DPSK half FAX 2400 1200 DPSK half FAX V.29 9600 2400 QAM half FAX 7200 2400 QAM half FAX V.32 9600 2400 TCM/QAM full 4800 2400 QAM full V.32bis 14400 2400 TCM full 12000, 9600, 7200 2400 TCM full 4800 2400 QAM full FSK Frequency Shift Keying DPSK Differential Phase Shift Keying QAM Quadrature Amplitude Modulation TCM Trellis Coded Modulation Other V-Recommendations often heard of: V.24 - Meaning of the signals at the serial port. V.28 - Electrical levels (V.24, V.28, and ISO 2110 are equivlaent to EIA RS232.) V.42 - Data protection method, not dependening on the modulation scheme in use. V.42bis - Compression scheme, also called BTLZ. Hayes commands -------------- Each command line starts with 'AT', then several commands, then carriage return. The list is not comprehensive at all; most modems have several commands of their own, but these commands are available with most modems: A/ Repeat last command A Take over phone line (if you've already dialed with your phone or if you've picked up the phone). B Set communications standard. B0 - CCITT B1 - Bell C Switch carrier on/off. C0 - carrier off C1 - carrier on D Dial a number. Normally followed by T - tone dial P - pulse dial nothing - according to actual setting (see ATP/ATT) then a sequence of the follwing characters: 0-9 - the numbers to be dialed W - wait for dial tone , - wait 2 seconds @ - wait 5 seconds (?) ! - flash (put the phone on the hook for 1/2 second) > - earth key R - start connection right after dialing (eg. ATDPR equals ATA) E Echo on/off in the command mode E0 - no echo E1 - echo H Hang up L Volume control; followed by 0-3 (0 equ. lowest, 3 equ. highest volume) M Monitor M0 - Speaker off M1 - Speaker on while dialing and establishing a connection M2 - Speaker always on M3 - Speaker on while establishing a connection O Switch to data mode O0 - promptly O1 - with retrain (reduction of the data rate) P Pulse dial Q Responses to commands on/off Q0 - on Q1 - off S Set/read internal register, eg. S17=234 set reg. 17 to 234 S17? read reg. 17 T Tone dial V Verbose mode on/off V0 - short responses V1 - full responses X Phone tones recognition on/off X0 - Ignore busy sign, don't wait for dial tone, and just answer with "CONNECT" when a connection has been established (other settings produce more detailed messages) X1 - Ignore busy sign, don't wait for dial tone, but give full connect message X2 - Ignore busy sign but wait for dial tone X3 - Don't ignore busy sign, but don't wait for dial tone X4 - Don't ignore anything Y Break setting Y0 - Don't hang up when break signal is detected Y1 - Hang up when break is detected (&D2, &M0) Z Initialize modem Z - Default parameters Z0 - Setting 0 Z1 - Setting 1 &C DCD mode &C0 - always 1 &C1 - DCD according to carrier &D DTR mode &D0 - ignore DTR &D1 - switch to command mode when DTR goes 0 &D2 - hang up if DTR goes 0 &D3 - initialize modem when DTR goes 0 &F Set operation mode &F0 - according to Hayes, no data protocol &F1 - according to Microcom; MNP1-4 or MNP5 as specified by %C &F2 - according to Sierra; MNP1-4 or MNP5 as specified by %C &F3 - according to Sierra, V.42 or V.42bis as specified by %C These are the default settings: &F0 - B0, E1, L2, M1, P, Q0, V1, Y0, X1, &C1, &D0, &G0, &R0, &S0, S0=0, S1=0, S2=43, S3=13, S4=10, S5=8, S6=2, S7=30, S8=2, S9=6,S10=14, S11=75, S12=50, S14=AAh, S16=80h, S21=20h, S22=76h, S23=7, S25=5, S26=1, S27=40h &F1 - \A3, \C0, \E0, \G0, \K5, \N1, \Q0, \T0, \V0, \X0, %A0, %C1, %E1, %G0, &G1, S36=7h, S46=138h, S48=128h, S82=128h &F2 - \A3, \C2, \E0, \G1, \K5, \N3, \Q1, \T0, \V1, \X0, %A13, %C1, S36=7h, S46=138h, S48=128h, S82=128h &F3 - \A3, \C0, \E0, \G0, \K5, \N3, \O1, \T0, \V1, \X0, %A0, %C1, %E0, S36=7h, S46=138h, S48=7h, S82=128h &G Guard tone &G0 - off &G1 - 550 Hz &G2 - 1800 Hz &K Data flow control &K0 - none &K3 - bidirectional RTS/CTS handshaking &K4 - bidirectional XON/XOFF &K5 - unidirectional XON/XOFF &M Synchronous/asynchronous operation &M0 - asynchronous (the usual thing) &M1 - command mode asynchronous, data mode synchronous. &M2 - switch to synchronous mode, start dialing after DTR 0->1 &M3 - switch to synchronous mode, don't dial &Q Further specification of the communication &Q0 to &Q3 - no V.42bis &Q5 - V.42bis &Q6 - V.42bis off, buffer data &R CTS mode &R0 - CTS follows RTS with the delay time of S26 &R1 - CTS is 1 if the modem is in the data mode &S DSR mode &S0 - DSR always 1 &S1 - according to CCITT V.24 &T Test &T0 - normal operation (no test) &T1 - local analog loopback &T3 - local digital loopback &T4 - accept distant digital loopback &T5 - ignore distant digital loopback &T6 - start distant digital loopback &T7 - start distant digital loopback and self test &T8 - start distant analog loopback and self test &V Show modem status &Wn Save actual configuration (some modems only). Setting can be restored with ATZn. n normally ranges between 0 and 1. The following parameters are stored: B, C, E, L, M, P/T, Q, V, X, Y, &C, &D, &G, &R, &S, &T4/&T5, S0, S14, S18, S21, S22, S25, S26, S27 &X Specify clock source for synchronous operation &X0 - modem generates clock &X1 - modem synchronizes with local clock &X2 - modem synchronizes with distant clock &Y Define default setting (see &W and Z) &Y0 - setting 0 is default &Y1 - setting 1 is default &Z Store phone number in diary &Zn=XXXXXX stores phone number XXXXXX under index n, where XXXXXX can be up to 30 digits and n ranges between 0 and 3. Microcom commands ----------------- \A Set block length for MNP \A0 - 64 characters \A1 - 128 characters \A2 - 192 characters \A3 - 256 characters \Bn Send break signal for n times 100ms (MNP defaults to n=3). \C Set buffering \C0 - none at all \C1 - buffer data for 4 seconds as long as 200 characters aren't reached or as long as no MNP block is found \C2 - don't buffer. Switch back to normal operation after reception of the control character (fall-back, see %C) D/n Dial phone number n in the diary (see &Z) DL Redial last number \E Echo on/off in data mode \E0 - no echo \E1 - echo \G Data flow on/off (see \Q) \G0 - off \G1 - on \J Data rate adjust \J0 - the data rates computer-modem and modem-modem are independent \J1 - the data rate computer-modem follows the data rate modem-modem \Kn Break setting (don't know anything about this, just that it exists ;-) \N MNP select \N0 - standard mode, no MNP, data is buffered \N1 - direct mode, no MNP, no buffering \N2 - MNP, data is buffered \N3 - allow MNP on/off during connection, data is buffered \O Switch on MNP during connection (the rest of the line is being ignored!) \Pn Same as &Z \Q Set handshake (compare &K) \Q0 - no handshaking \Q1 - XON/XOFF \Q2 - modem controls data flow with CTS \Q3 - data flow control with RTS/CTS \S List complete configuration \Tn Set idle timer \T0 - timer off \Tnn - break connection after nn minutes without data exchange (1-90) \U Acknowledge MNP operation; rest of line is ignored! \V Verbose mode \V0 - messages according to Hayes, even if MNP (no \REL) \V1 - messages according to Microcom (\REL appended if MNP) \X Filter XON/XOFF characters \X0 - filter XOM/XOFF characters \X1 - don't filter them (the usual thing) \Y Same as AT\O\U with the difference that it is not necessary to first send AT\O to one modem and then AT\U to the other; just send AT\Y to each modem within 5 seconds %An Specify control character that provokes fallback from MNP to normal operation (see \C2). n=0..255 (ASCII code) %C MNP5 %C0 - not allowed %C1 - allowed %E auto-retrain %E0 - no auto-retrain allowed %E1 - auto-retrain allowed according to CCITT %R Show all S registers %V Same as I3 (but don't ask me what it is ;-) Gives info on the firmware version with some modems. [... continued ...] -- Chris Blum - finger chris@pfsparc02.phil15.uni-sb.de for details