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Text File  |  1993-12-06  |  18KB  |  553 lines
  1. :li
  2. ;**************************************************************
  3. ;SYMPHONY HAYDN, System: SL82C461, Bus: SL82C362 in SYM486.CFG
  4. ;**************************************************************
  5.  
  6. INDEXPORT=A8h    ; alternativ A2h
  7. DATENPORT=A9h    ; alternativ A3h
  8.  
  9. ;**************************************************************
  10. ; SL82C461
  11. ;**************************************************************
  12.  
  13. ;**************************************************************
  14.  
  15. INDEX =0         ; CHIP Control
  16. ;**************************************************************
  17.  
  18. BIT=7            ;WT3167 existence (ro)
  19.                  0=non existing
  20.                  1=existing
  21.  
  22. BIT=6            ;0/1 Cachemode   (ro)
  23.  
  24. BIT=5            ;CPU-TYP        (ro)
  25.                  0=486
  26.                  1=386DX
  27.  
  28. BIT=4            ;CPU ID (if 386)          (ro)
  29.                  0=386SX
  30.                  1=386DX
  31.  
  32. BIT=3            ;80387 existence (ro)
  33.                  0=non existing
  34.                  1=Existing
  35.  
  36. BIT=2            ;80387 Ready Source (if 386)
  37.                  0=from 80387
  38.                  1=from SL82C461
  39.  
  40. BIT=1            ;0/1 8042 RC emulation
  41.  
  42. BIT=0            ;Configuration Port address
  43.                  0=A8h/A9h (default)
  44.                  1=A2h/A3h
  45.  
  46. ;**************************************************************
  47. INDEX =1         ; ROM Control
  48. ;**************************************************************
  49.  
  50. BIT=7            ;ROM Data width (ro)
  51.                  0=8 bit
  52.                  1=16 bit
  53.  
  54. BIT=65           ;ROM Waitstates
  55.                  00=reserved
  56.                  01=1 wait
  57.                  10=2 waits
  58.                  11=3 waits
  59.  
  60. BIT=43           ;high/middle boot ROM disable
  61.                  00=enable high/middle Boot ROM
  62.                  x1=disable middle Boot ROM
  63.                  1x=disable high Boot ROM
  64.  
  65. BIT=2            ;0/1 Combined BIOS (ro)
  66.  
  67. BIT=1            ;0/1 Gate A20 emulation
  68.  
  69. BIT=0            ;0/1 Fast GateA20
  70.  
  71. ;**************************************************************
  72. INDEX =2         ; Clock Control
  73. ;**************************************************************
  74.  
  75. BIT=7            ;0/1 SLOW MODE
  76.  
  77. BIT=65           ;Slow speed selection for CCLK2
  78.                  00=CLK2/4  (default)
  79.                  01=CLK2/16
  80.                  10=BCLK
  81.                  11=reserved
  82.  
  83. BIT=432          ;BCLK speed selection
  84.                  000=CLK2/3
  85.                  001=CLK2/4 (default)
  86.                  010=CLK2/5
  87.                  011=reserved
  88.                  100=CLK2/6
  89.                  101=CLK2/4
  90.                  110=CLK2/2.5
  91.                  111=CLK2/2
  92.  
  93. BIT=1            ; must be 0
  94.  
  95. BIT=0            ; reserved must be 1
  96.  
  97.  
  98. ;**************************************************************
  99. INDEX=3         ; 82C461 Chip ID and Revision (ro)
  100. ;**************************************************************
  101.  
  102. BIT=7654        ; 82C461 Chip ID
  103.                 0000= SL82C461
  104.  
  105. BIT=3210        ; 82C461 Chip Revision
  106.  
  107.  
  108.  
  109. ;**************************************************************
  110. INDEX=4         ; 82C362 Chip ID and Revision (ro)
  111. ;**************************************************************
  112.  
  113. BIT=7654        ; 82C362 Chip ID
  114.                 0001= SL82C362
  115.  
  116. BIT=3210        ; 82C362 Chip Revision
  117.  
  118.  
  119.  
  120. ;**************************************************************
  121. INDEX=5         ; DMA Command Control
  122. ;**************************************************************
  123.  
  124. BIT=76          ; DMA Read command delay
  125.                 00= 0 cycles (default)
  126.                 01= 1 cycle
  127.                 10= 2 cycles
  128.                 11= 3 cycles
  129. BIT=54         ; DMA cycle Wait states
  130.                 00= 0 Waitstates
  131.                 01= 1 Waitstate (default)
  132.                 10= 2 Waitstates
  133.                 11= 3 Waitstates
  134.  
  135. BIT=3210        ; Reserved
  136.  
  137.  
  138. ;**************************************************************
  139. INDEX=6         ; Miscellaneous Control
  140. ;**************************************************************
  141.  
  142. BIT=7           ; must be 0
  143. BIT=6543        ; reserved
  144. BIT=2           ;0/1 decoupled refresh
  145. BIT=1           ;0/1 cache posted write buffer
  146. BIT=0           ; reserved
  147.  
  148. ;**************************************************************
  149. INDEX=7         ; Parity Check enable
  150. ;**************************************************************
  151. BIT=76543       ;reserved
  152. BIT=2           ;1/0 memory parity check
  153. BIT=1           ;reserved
  154. BIT=0           ;must be 0
  155.  
  156. ;**************************************************************
  157. INDEX=8         ; AT Bus Cycle Command Control
  158. ;**************************************************************
  159. BIT=7           ;command delay
  160.                 0= 0 Cycles for Mem 16 Bit, else 1 Cycle
  161.                 1= 2 Cycles for Mem 16 Bit, else 3 Cycles
  162.  
  163. BIT=6           ;16-bit AT Bus  cycle waitstate
  164.                 0= 1 Waitstate
  165.                 1= 3 Waitstates
  166.  
  167. BIT=5           ;8-bit AT Bus cycle waitstate
  168.                 0= 3 Waitstate
  169.                 1= 5 Waitstates
  170.  
  171. BIT=4           ;On Chipset I/O Waitstate
  172.                 0= 2 Waitstate
  173.                 1= 4 Waitstates
  174.  
  175. BIT=32          ;I/O recovery time
  176.                 00= 0 Sysclk
  177.                 01= 4 Sysclk
  178.                 10= 8 Sysclk
  179.                 11=12 Sysclk
  180.  
  181. BIT=1           ;0/1 Extended ALE
  182.  
  183. BIT=0           ;0/1 Extended Ready# (ro)
  184.  
  185. ;**************************************************************
  186. INDEX=20H       ; DRAM Configuration Bank 0/1
  187. ;**************************************************************
  188.  
  189. BIT=76          ;Bank 0 DRAM Typ
  190.                 00= disabled
  191.                 01= 256KBit (default)
  192.                 10= 1MBit
  193.                 11= 4MBit
  194.  
  195. BIT=5           ;0/1 Page Mode
  196.  
  197. BIT=43          ;Bank 1 DRAM Typ
  198.                 00= disabled
  199.                 01= 256KBit (default)
  200.                 10= 1MBit
  201.                 11= 4MBit
  202. BIT=210         ;reserved
  203.  
  204. ;**************************************************************
  205. INDEX=21H       ; DRAM Configuration Bank 2/3
  206. ;**************************************************************
  207.  
  208. BIT=76          ;Bank 2/3 DRAM Typ
  209.                 00= disabled
  210.                 01= 256KBit (default)
  211.                 10= 1MBit
  212.                 11= 4MBit
  213.  
  214. BIT=5           ;reserved
  215.  
  216. BIT=4          ;Bank 2/3 Number of banks used
  217.                 0= no or 1 bank (default)
  218.                 1= 2 banks
  219. BIT=3210       ;reserved
  220.  
  221. ;**************************************************************
  222. INDEX=22H      ; Bank 0 Ending Address
  223. BIT=76543210   ; A26..A19
  224. INDEX=23H      ; Bank 1 Ending Address
  225. BIT=76543210   ; A26..A19
  226. INDEX=24H      ; Bank 2 Ending Address
  227. BIT=76543210   ; A26..A19
  228. INDEX=25H      ; Bank 3 Ending Address
  229. BIT=76543210   ; A26..A19
  230. ;**************************************************************
  231. INDEX=26H      ; Refresh period
  232. ;**************************************************************
  233.  
  234. BIT=76         ; reserved
  235. BIT=54         ; Refresh period
  236.                00= 15 µs (default)
  237.                01= 30 µs
  238.                10= 60 µs
  239.                11= 120 µs
  240. BIT=3210       ; reserved
  241.  
  242. ;**************************************************************
  243. INDEX=27H      ; /RAS Timeout
  244. ;**************************************************************
  245. BIT=76         ;/RAS Timeout period:
  246.                00=10µs (default)
  247.                01=20µs
  248.                10=40µs
  249.                11=80µs
  250. BIT=543210     ;reserved
  251.  
  252.  
  253. ;**************************************************************
  254. INDEX=28H      ; x36SIMM-Support
  255. ;**************************************************************
  256.  
  257. BIT=765        ;reserved
  258.  
  259. BIT=4          ;DRAM/SIMM type
  260.                0=9 bit DRAM/SIMM installed
  261.                1=x36 SIMM installed
  262.  
  263. BIT=3          ;x36 SIMM Socket 3 density
  264.          0=Single Density, RAS of odd Bank on socket 3 is enabled
  265.          1=Double Density, RAS of both Banks on socket 3 are enabled
  266. BIT=2          ;x36 SIMM Socket 2 density
  267.          0=Single Density, RAS of odd Bank on socket 2 is enabled
  268.          1=Double Density, RAS of both Banks on socket 2 are enabled
  269. BIT=1          ;x36 SIMM Socket 1 density
  270.          0=Single Density, RAS of odd Bank on socket 1 is enabled
  271.          1=Double Density, RAS of both Banks on socket 1 are enabled
  272. BIT=0          ;x36 SIMM Socket 0 density
  273.          0=Single Density, RAS of odd Bank on socket 0 is enabled
  274.          1=Double Density, RAS of both Banks on socket 0 are enabled
  275.  
  276. ;**************************************************************
  277. INDEX=2DH      ; Memory Relocation/combined BIOS
  278. ;**************************************************************
  279.  
  280. BIT=76         ;Relocation:
  281.                00= disabled
  282.                01= illegal
  283.                10= 256 KB
  284.                11= 384 KB
  285.  
  286. BIT=5          ;0/1 Extended Combined BIOS
  287.  
  288. BIT=4          ;0/1 Extended Combined BIOS region E8000h-EFFFFh:
  289. BIT=3          ;0/1 Extended Combined BIOS region E0000h-E7FFFh:
  290. BIT=2          ;0/1 Extended Combined BIOS region C8000h-CFFFFh:
  291. BIT=1          ;0/1 Extended Combined BIOS region C0000h-C7FFFh:
  292. BIT=0          ;reserved
  293.  
  294. ;**************************************************************
  295. INDEX=2EH      ; Shadow RAM Enable 1
  296. ;**************************************************************
  297.  
  298. BIT=76         ;Shadow CC000h-CFFFFh:
  299.                00= Read from ROM/ATBUS, RAM disable
  300.                01= Read from ROM/ATBUS, Write to RAM
  301.                10= Read from RAM, Write protected
  302.                11= Read from RAM, Write to RAM
  303.  
  304. BIT=54         ;Shadow C8000h-CBFFFh:
  305.                00= Read from ROM/ATBUS, RAM disable
  306.                01= Read from ROM/ATBUS, Write to RAM
  307.                10= Read from RAM, Write protected
  308.                11= Read from RAM, Write to RAM
  309.  
  310. BIT=32         ;Shadow C4000h-C7FFFh:
  311.                00= Read from ROM/ATBUS, RAM disable
  312.                01= Read from ROM/ATBUS, Write to RAM
  313.                10= Read from RAM, Write protected
  314.                11= Read from RAM, Write to RAM
  315.  
  316. BIT=10         ;Shadow C0000h-C3FFFh:
  317.                00= Read from ROM/ATBUS, RAM disable
  318.                01= Read from ROM/ATBUS, Write to RAM
  319.                10= Read from RAM, Write protected
  320.                11= Read from RAM, Write to RAM
  321.  
  322.  
  323. ;**************************************************************
  324. INDEX=2FH      ; Shadow RAM Enable 2
  325. ;**************************************************************
  326.  
  327. BIT=76         ;Shadow DC000h-DFFFFh:
  328.                00= Read from ROM/ATBUS, RAM disable
  329.                01= Read from ROM/ATBUS, Write to RAM
  330.                10= Read from RAM, Write protected
  331.                11= Read from RAM, Write to RAM
  332.  
  333. BIT=54         ;Shadow D8000h-DBFFFh:
  334.                00= Read from ROM/ATBUS, RAM disable
  335.                01= Read from ROM/ATBUS, Write to RAM
  336.                10= Read from RAM, Write protected
  337.                11= Read from RAM, Write to RAM
  338.  
  339. BIT=32         ;Shadow D4000h-D7FFFh:
  340.                00= Read from ROM/ATBUS, RAM disable
  341.                01= Read from ROM/ATBUS, Write to RAM
  342.                10= Read from RAM, Write protected
  343.                11= Read from RAM, Write to RAM
  344.  
  345. BIT=10         ;Shadow D0000h-D3FFFh:
  346.                00= Read from ROM/ATBUS, RAM disable
  347.                01= Read from ROM/ATBUS, Write to RAM
  348.                10= Read from RAM, Write protected
  349.                11= Read from RAM, Write to RAM
  350.  
  351.  
  352. ;**************************************************************
  353. INDEX=30H      ; Shadow RAM Enable 3
  354. ;**************************************************************
  355.  
  356. BIT=76         ;Shadow E0000h-EFFFFh:
  357.                00= Read from ROM/ATBUS, RAM disable
  358.                01= Read from ROM/ATBUS, Write to RAM
  359.                10= Read from RAM, Write protected
  360.                11= Read from RAM, Write to RAM
  361.  
  362. BIT=543210     ;reserved
  363.  
  364. ;**************************************************************
  365. INDEX=31H      ; Shadow RAM Enable 4/ Flash EPROM Support
  366. ;**************************************************************
  367.  
  368. BIT=76         ;Shadow F0000h-FFFFFh:
  369.                00= Read from ROM, RAM disable
  370.                01= Read from ROM, Write to RAM
  371.                10= Read from RAM, Write protected
  372.                11= Read from RAM, Write to RAM
  373.  
  374. BIT=543        ;reserved
  375.  
  376. BIT=2          ; Pin 13 definition for non-cache system:
  377.                0= /NPRDY
  378.                1= /LDEV
  379.  
  380. BIT=1          ;Flash EPROM Support
  381.                0= Read Only EPROM
  382.                1=R/W EPROM
  383.  
  384. BIT=0          ;0/1 Inverted SA16 during ROM access cycle
  385.  
  386. ;**************************************************************
  387. INDEX=32H      ; DRAM Timing 1
  388. ;**************************************************************
  389.  
  390. BIT=76         ; /CAS Pulse width (depends on Reg 33, Bit 0)
  391.                00=reserved (33_0=0) / 5 CClK2 (33_0=1)
  392.                01=2 CCLK2  (33_0=0) / 6 CCLK2 (33_0=1)
  393.                10=3 CCLK2  (33_0=0) / reserved(33_0=1)
  394.                11=4 CCLK2  (33_0=0) / reserved(33_0=1)
  395.  
  396. BIT=543       ;/RAS Precharge
  397.               000= reserved
  398.               001= 2 CCLK2 Cycles
  399.               010= 3 CCLK2 Cycles
  400.               011= 4 CCLK2 Cycles
  401.               100= 5 CCLK2 Cycles
  402.               101= reserved
  403.               11x= reserved
  404.  
  405. BIT=210       ;/RAS Pulse width
  406.               000= reserved
  407.               001= reserved
  408.               010= 3 CCLK2 Cycles
  409.               011= 4 CCLK2 Cycles
  410.               100= 5 CCLK2 Cycles
  411.               101= 6 CCLK2 Cycles
  412.               11x= reserved
  413.  
  414. ;**************************************************************
  415. INDEX=33H      ; DRAM Timing 2
  416. ;**************************************************************
  417.  
  418. BIT=76        ;/RAS to column address
  419.               00=0.5 CCLK2 Cycle
  420.               01=1   CCLK2 Cycle
  421.               10=1.5 CCLK2 Cycle
  422.               11=2   CCLK2 Cycle
  423.  
  424. BIT=54        ;/RAS to /CAS
  425.               00=1 CCLK2 Cycle
  426.               01=2 CCLK2 Cycle
  427.               10=3 CCLK2 Cycle
  428.               11=4 CCLK2 Cycle
  429.  
  430. BIT=3         ; CAS Precharge
  431.               0= 1 CCLK2 Cycle
  432.               1= 2 CCLK2 Cycle
  433.  
  434. BIT=21        ;reserved
  435. BIT=0         ;/CAS Pulse width (together with reg 32, Bit=76)
  436.  
  437. ;**************************************************************
  438. INDEX=40H      ; SL82C465 Cache Controller
  439. ;**************************************************************
  440.  
  441. ;**************************************************************
  442. INDEX=40H      ; Burst & Flush
  443. ;**************************************************************
  444.  
  445. BIT=76         ; Burst Transfer:
  446.                00= disabled
  447.                01= 2 Cycle Burst
  448.                10= 4 Cycle Burst
  449.                11= reserved
  450.  
  451. BIT=54210      ; must be 0
  452.  
  453. BIT=3          ;0/1 Flush control
  454.  
  455. ;**************************************************************
  456. INDEX=43H      ; Non Cacheable Region 2 High Base Address
  457. ;**************************************************************
  458. BIT=76543210   ; A25..A18
  459.  
  460. ;**************************************************************
  461. INDEX=44H      ; Non Cacheable Region 2 Low Base Address
  462. ;**************************************************************
  463. BIT=76         ; A17..A16
  464.  
  465. BIT=543        ; Size
  466.                000= disabled
  467.                001= 64K
  468.                010=128K
  469.                011=256K
  470.                100=512K
  471.                101=1M
  472.                110=2M
  473.                111=4M
  474. ;**************************************************************
  475. INDEX=45H      ; Non Cacheable Region 3
  476. ;**************************************************************
  477. BIT=7          ; Turbo/Compatible Speed Control
  478.                0= Turbo
  479.                1= Compatible
  480. BIT=6          ;reserved
  481. BIT=5          ;0/1 F0000h-FFFFFh Cacheable (only if Shadow RAM)
  482. BIT=4          ;0/1 C8000h-CFFFFh Cacheable (only if Shadow RAM)
  483. BIT=3          ;0/1 C0000h-C7FFFh Cacheable (only if Shadow RAM)
  484.  
  485. BIT=210        ;maximal cacheable Address:
  486.                000= disabled
  487.                011= 32MB
  488.                010= 16MB
  489.                001=  8MB
  490.                101=  4MB
  491.                100=  2MB
  492.                111=  1MB
  493.                110=  512 KB
  494.  
  495. ;**************************************************************
  496. ; Cache-Konfiguration
  497. ;**************************************************************
  498. ; Ist nicht softwaremäßig konfigurierbar, wird bei Power-On
  499. ; durch Pegel an bestimmten Pins des SL82C465 festgelegt:
  500. ; 1= offen, 0= 4k7 Pull-Down
  501.  
  502. ; PIN=60      ;Clock Mode
  503. ;             0= 1X clock mode (bis 50/50 MHz)
  504. ;             1= 2X clock mode (bis 33/66 MHz)
  505.  
  506. ; PIN=37,31   ;Cache line size
  507. ;             00= 1 Dword
  508. ;             01= 2 Dwords
  509. ;             10= 4 Dwords
  510. ;             11= 1 Dword
  511.  
  512. ;PIN=76       ; SRAM banks
  513. ;             0= 1 bank or 4 banks
  514. ;             1= 1 bank or 2 banks
  515.  
  516. ;PIN=48      ; Burst fill rate
  517. ;            0=3-2-2-2-Burst
  518. ;            1=2-1-1-1-Burst
  519.  
  520. ;PIN=49      ; Write wait state
  521. ;            0= 0 Wait states
  522. ;            1= 1 Wait states
  523.  
  524. ;PIN=52     ; Combined Valid/tag SRAM
  525. ;            0= not combined
  526. ;            1= combined
  527.  
  528. ;**************************************************************
  529. ; Hardware-Konfiguration
  530. ;**************************************************************
  531. ; Ist nicht softwaremäßig konfigurierbar, wird bei Power-On
  532. ; durch Pegel an bestimmten Daten-Pins des SL82C461 festgelegt:
  533. ; 1= offen, 0= 4k7 Pull-Down
  534.  
  535. ;PIN=24,23  ; CPU-Type (XD1,XD0)
  536. ;              00= reserved
  537. ;              01= 486
  538. ;              10= 386SX
  539. ;              11= 386DX
  540.  
  541. ;PIN=25     ;1/0 Extended Ready (XD2)
  542.  
  543. ;PIN=26     ;EPROM Data Width (XD3)
  544. ;            0= 8 Bit
  545. ;            1=16Bit
  546.  
  547. ;PIN=31     ;EPROM Wait State (XD4)
  548. ;           0= 1 Wait state
  549. ;           1= 3 Wait states
  550.  
  551. ;PIN=35     ;1/0 Combined BIOS (XD5)
  552. ;PIN=37     ;1/0 Cache system  (XD6)
  553.