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Der Mediaplex Sampler - Die 6 von Plex
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SIS411.CFG
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Text File
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1993-12-06
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8KB
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219 lines
;*************************************************************
;SiS EISA-Chipsatz 85C411 etc. in Datei SIS411.CFG
;*************************************************************
INDEXPORT=C18h
DATENPORT=C1Ch
;*************************************************************
;Memory-Controller 85C411
;*************************************************************
;*************************************************************
INDEX=60h; Memory Configuration
;*************************************************************
BIT=76 ;DRAM Speed
00=Slowest (50MHz)
01=Slower (40MHz)
10=Faster (33MHz)
11=Fastest (25MHz)
Bit=7 ;Bit 7 also defines the first cache read cycle time of
; a burst
0=3-x-x-x-Burst
1=2-x-x-x-Burst
BIT=5 ;DRAM Write CAS Pulse Width
0=2T
1=1T
BIT=43210 ;DRAM Size Configuration, (I)= Dword-Interleave
00000= B1:1M B2:- B3:- B4:- Total:1M
00001= B1:1M B2:1M B3:- B4:- Total:2M (I)
00010= B1:1M B2:1M B3:2M B4:- Total:4M
00011= B1:1M B2:1M B3:4M B4:- Total:6M
00100= B1:1M B2:1M B3:2M B4:4M Total:8M
00101= B1:1M B2:1M B3:4M B4:4M Total:10M (I)
00110= B1:1M B2:1M B3:16M B4:- Total:18M
00111= B1:2M B2:- B3:- B4:- Total:2M
01000= B1:2M B2:2M B3:- B4:- Total:4M (I)
01001= B1:2M B2:4M B3:- B4:- Total:6M
01010= B1:2M B2:2M B3:4M B4:- Total:8M
01011= B1:2M B2:2M B3:4M B4:4M Total:12M (I)
01100= B1:2M B2:16M B3:- B4:- Total:18M
01101= B1:2M B2:2M B3:16M B4:- Total:20M
01110= B1:2M B2:2M B3:4M B4:- Total:24M
01111= B1:2M B2:2M B3:16M B4:- Total:36M (I)
10000= B1:4M B2:- B3:- B4:- Total:4M
10001= B1:4M B2:4M B3:- B4:- Total:8M (I)
10010= B1:4M B2:4M B3:4M B4:- Total:12M
10011= B1:4M B2:4M B3:4M B4:4M Total:16M (I)
10100= B1:4M B2:16M B3:- B4:- Total:20M
10101= B1:4M B2:4M B3:16M B4:- Total:24M
10110= B1:4M B2:16M B3:16M B4:- Total:36M
10111= B1:4M B2:4M B3:16M B4:16M Total:40M (I)
11000= B1:8M B2:- B3:- B4:- Total:8M
11001= B1:8M B2:8M B3:- B4:- Total:16M (I)
11010= B1:8M B2:8M B3:8M B4:- Total:24M
11011= B1:8M B2:8M B3:8M B4:8M Total:32M (I)
11100= B1:16M B2: B3:- B4:- Total:16M
11101= B1:16M B2:16M B3:- B4:- Total:32M (I)
11110= B1:16M B2:16M B3:16M B4:- Total:48M
11111= B1:16M B2:16M B3:16M B4:16M Total:64M (I)
BIT=43210 ; falls Register 63 Bit 6 = (1) enable dann:
11100= B1:64M B2: B3:- B4:- Total:64M
11101= B1:64M B2:64M B3:- B4:- Total:128M (I)
11110= B1:64M B2:64M B3:64M B4:- Total:192M
11111= B1:64M B2:64M B3:64M B4:64M Total:256M (I)
;*************************************************************
INDEX=61h ; Cache Konfiguration
;*************************************************************
BIT=7 ;0/1 Cache Enable
BIT=6 ;Write Back Enable
0=Disable (Write Through)
1=Enable (Write Back)
BIT=54 ;Cache Size
00= 64KB
01=128KB
10=256KB
11=512KB
BIT=3 ;0/1 Cache Interleave Enable
BIT=2 ;0/1 DRAM Interleave Enable (for 2/4 banks only)
BIT=1 ;Cache Write Cycle
0=3T
1=2T
BIT=0 ;Cache Burst Read Cycle
0=1T
1=2T
;*************************************************************
INDEX=62h; Shadow
;*************************************************************
BIT=7 ;0/1 Shadow RAM Read Enable
BIT=6 ;0/1 Shadow RAM Write Protection Enable
BIT=5 ;0/1 E8000h-EFFFFh Shadow RAM Enable
BIT=4 ;0/1 E0000h-E7FFFh Shadow RAM Enable
BIT=3 ;0/1 D8000h-DFFFFh Shadow RAM Enable
BIT=2 ;0/1 D0000h-D7FFFh Shadow RAM Enable
BIT=1 ;0/1 C8000h-CFFFFh Shadow RAM Enable
BIT=0 ;0/1 C0000h-C7FFFh Shadow RAM Enable
;*************************************************************
INDEX=63h ;
;*************************************************************
BIT=7 ;System BIOS ROM Size
0= 64K
1=128K
BIT=6 ;0/1 DRAM 16M x 36 Bank Enable
BIT=5 ;Length of Cache Tag Field
0= 8 Bits
1= 9 Bits
BIT=4 ;CPU Internal cache invalidation for EISA Burst
0=EADS
1=Flush
BIT=3 ;KBCLK Selection
0=BUSCLK
1=Faster
BIT=210 ;BUSCLK Selection
000=7.159 MHz
001=CPUCLK/8 (66 MHz => 8,25 MHz)
010=CPUCLK/6 (50 MHz => 8,33 MHz)
011=CPUCLK/5 (40 MHz => 8,00 MHz)
100=CPUCLK/4 (33 MHz => 8,25 MHz)
101=CPUCLK/3 (25 MHz => 8,33 MHz)
110=CPUCLK/2.5(20 MHz => 8,00 MHz)
111=CPUCLK/2 (16 MHz => 8,00 MHz)
;*************************************************************
INDEX=64h
;*************************************************************
BIT=7 ;Allocation of Non-cacheable Area #1
0=Local DRAM
1=AT Bus, local DRAM is disabled
BIT=654 ;Size of Non-cacheable Area #1
000= 0KB (disabled)
001= 64KB
010=128KB
011=256KB
100=512KB
101= 1MB
110= 2MB
111= 4MB
BIT=3210 ; A27-A24 of Non Cacheable Area #1
;**************************************************************
INDEX=65h
;**************************************************************
BIT=76543210 ;A23-A16 of Non-Cacheable Area #1
;**************************************************************
INDEX=66h
;*************************************************************
BIT=7 ;Allocation of Non-cacheable Area #2
0=Local DRAM
1=AT Bus, local DRAM is disabled
BIT=654 ;Size of Non-cacheable Area #2
000= 0KB (disabled)
001= 64KB
010=128KB
011=256KB
100=512KB
101= 1MB
110= 2MB
111= 4MB
BIT=3210 ; A27-A24 of Non Cacheable Area #2
;**************************************************************
INDEX=67h
;**************************************************************
BIT=76543210 ;A23-A16 of Non-Cacheable Area #2
;**************************************************************
INDEX=68h
;**************************************************************
BIT=7654 ;Reserved = 0
BIT=3 ;0/1 Cache Data RAM Test
BIT=2 ;0/1 F0000h-FFFFFh Shadow RAM Cacheable
BIT=1 ;0/1 C0000h-FFFFFh Shadow RAM Cacheable
BIT=0 ;Turbo Switch
0=Always Turbo, ignores the status of Turbo switch
1=Turbo Switch enable
;**************************************************************
;85C420 EISA-Bus-Controller
;**************************************************************
; Ist nicht softwaremäßig konfigurierbar, an den Pins
; IOREC0 (34) und IOREC1 (35) läßt sich jedoch die
; I/O Recovery Time für 8 Bit I/O festlegen
; (3 BCLKs bei 16-Bit I/O ist fest)
; IOREC1 IOREC0
; 0 0 = 3 BCLKs
; 0 1 = 4 BCLKs
; 1 0 = 5 BCLKs
; 1 1 =11 BCLKs