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- Chapter 2
-
- The Specification of POST
- -------------------------
-
- 1.Introdoction:
-
- POST (Power On Self Test) is a procedure in BIOS which initializes
- and diagnoses the resources of the system. Moreover, the operation of
- Power-On Password and the issue of booting are also done by POST.
-
- If the POST finds out errors on the resources of system, it will
- display error messages or generate beep codes or even halt the system
- during a fatal error.
-
- 2.External specification:
-
- The resources of the system handled by POST include main chips on the
- system board, I/O devices attatched to the system and any adapters
- which specifically designed for ISA compatible system.
-
- The following are the main chips on the system board which must be
- diagnosed or/and initialized by POST in order to ensure the system's
- functions.
-
- * After POWER-ON reset or reset button is pressed, the H/W reset
- signal is issued to the CPU and other chips after built-in self
- test (BIST) is completed. The result status code is stored in
- EAX register. It is zero if no error occurs. Please refer to i386
- specifications.
-
- * Intel 80386 system microprocessor
- . i386 performs a built-in self-test (BIST) after system
- power-on.
- . the BIST tests the non-random logic that controls the ROM.
- . the result of BIST is stored in EAX register, the content of
- the EAX register is zero when i386 has passed the BIST.
- * Eight channel direct memory access (DMA) controller
- * 16 edge-triggered interrupt system
- * Three programmable timers
- * Intel 82385 Cache controller
- * ROM subsystem, 128K bytes (K = 1,024)
- * Cache controller and cache SRAM test
- * RAM subsystem, 1M to 16M bytes (M = 1,048765)
- * CMOS RAM subsystem with battery backup
- - 64 bytes CMOS RAM with real time clock/calendar
- * Keyboard/Auxiliary device controller
-
- -- To be continued --
-
-
-
- Aside from the system board, POST also have to do some proper action
- to the following I/O devices and adapters.
-
- * Test keyboard & auxiliary devices.
- * Test diskette drive attachment if floppy disk adapter exists.
- * Test hard disk attachment if hard disk adapter exists.
- * Check address of ROM from 0C000h to 0DFFFh for any firmwares in
- that region. If the firmware has a valid ID and its checksum is OK,
- POST must call firmware's initial entry point to initialize it.
-
- During POST the following items should be considered for
- compatibility:
-
- * All RAM except interrupt vector & BIOS data area must be cleared
- (including video RAM).
- * Setup interrupt vector table & BIOS data area.
- * Display memory size .
- * Display error code messages on diagnostic LEDs or generate beep
- codes.
- * Prepare 12 routines for shutdown process (shutdown byte from 0 to
- 0Bh).
- * Boot from diskette or hard disk, if there is no REMOTE BOOT ROM on
- the LAN card.
-
- 3. Internal specification:
-
- There are many tasks in the POST. When POST executes a task, it
- would pre-set a number (check point number) to specific latch LEDs
- on system board to indicate the stage it is running now, and this
- latch can be any R/W port on the system board as long as it can
- store data.
-
- The following sections lists the definition of all the tasks in POST
- identified by a check point number. All of the check point number
- can be assigned at random, add or eliminate some check points and
- change the sequence of definition.
-
-
-
-
-
-
-
-
- -- To be continued --
-
-
-
-
-
- 4. Check point list:
-
- --------------------------------------------------------------------------
- CHECK POINT 04h Start
- Check shutdown byte & test CPU (real mode)
- Description:
-
- * Check the result of CPU BIST, if it fails then the system halts.
- * Clear all interrupt.
- * Set DS = segment of BIOS data area.
- * Verify flags & conditional jumps, if it fails halt the system.
- * Check for shutdown in process flag. If shutdown is in process,
- and the shutdown flag is not equal to 09 or 0Ah or 0Bh, then
- re-initialize the #1 of interrupt controller by following the
- steps below:
-
- ICW1 : edge triggered, all address internal, cascade mode,
- ICW4 need
- ICW2 : vector address = 8
- ICW3 : IRQ2 has a slave, i.e. ICW3 = 4
- ICW4 : special fully nested mode disabled, non buffer mode,
- normal EOI, 8086/8088 mode.
-
- and re-initialize the #2 of interrupt controller by following the
- steps below:
-
- ICW1 : edge triggered, all address internal, cascade mode,
- ICW4 need.
- ICW2 : vector address = 70h
- ICW3 : slave ID = 2
- ICW4 : not special fully nested mode, non buffer mode,
- normal EOI, 8086/8088 mode
-
- Finally, mask off all interrupts, clear shutdown flag and branch
- to each shutdown routine.
- If the value of shutdown byte is invalid, branch to shutdown 0
- routine.
- If the value of shutdown byte is 09, 0Ah or 0Bh, do not
- re-initialize interrupt system but branch to proper routine.
- NOTE:
- 1. BIOS data area address is 40:0h and size is 256 bytes.
- 2. Delay a short period of time for system power_on stability.
- 3. Check status byte of KB controller (port 64h). If bit 2 of status
- byte = 0, system does a cold start and clears system flag 40:72h.
- Otherwise the system shutdowns the processor or does a warm start.
- The processor shuts down when the shutdown byte of the CMOS isn't
- 0.
- 4. If the system is in shutdown, set POST stack at 0:400h.
-
-
- -- To be continued --
-
- ---------------------------------------------------------------------------
- SHUTDOWN ROUTINES
- Return control after a shutdown command is issued
- Description:
- * A test is made for the system flag being set. If the system flag
- is set, the shutdown byte in CMOS (addr. 0F) is used to determine
- where the control should be returned.
-
- CMOS = 0 soft reset or unexpected shutdown
- CMOS = 1 shutdown after memory size determination
- CMOS = 2 shutdown after memory successful test
- CMOS = 3 shutdown with memory test error
- CMOS = 4 shutdown with boot loader request
- CMOS = 5 jump dword request (interrupt chip are initialized)
- CMOS = 6 protected mode test3 passed
- CMOS = 7 protected mode test3 failed
- CMOS = 8 protected mode test1 failed
- CMOS = 9 block move shutdown request
- CMOS = A jump dword request
- CMOS = B jump dword request (turn off gate A20 & adjust IDTR to
- physical address 0)
-
- --------------------------------------------------------------------------
- CHECK POINT 08h (SHOUTDOWN 0 ROUTINE)
- Test CPU registers
- Description:
- * Test CPU registers and if it fails, halt the system.
- * Disable NMI interrupt.
- * Ensure that CMOS clock interrupt are disabled.
- * Reset I/O channel error and memory parity.
-
- NOTES:
- 1. Clear the display buffer
- 2. During POST, NMI must be disabled when accessing CMOS index
- register. Disable NMI interrupt by setting bit 7 of CMOS index
- port (70h).
-
- --------------------------------------------------------------------------
- CHECK POINT 0Ch
- ROM checksum test
- Description:
- * A checksum is performed for the 64K ROM from F0000 to FFFFF.
- If it fails, halt the system.
-
- NOTE:
- ROM BIOS checksum must be equal to 0.
- --------------------------------------------------------------------------
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 10h
- Verify CMOS shutdown byte
- Description:
- * Test shutdown byte (0Fh) of CMOS, if it fails, halt the system.
-
- NOTE:
- Clear shutdown byte after successful testing of the shutdown byte.
- --------------------------------------------------------------------------
- CHECK POINT 14h
- Test and initialize DMA controller
- Description:
- * Test page registers and transfer count registers and memory address
- registers of all DMA channel. If it fails, halt the system.
-
- * Program DMA's function by setting the following:
-
- DREQ signal sense active high
- DACK signal sense active low,
- late write,
- fixed priority, normal timing,
- Controller enable, channel 0
- Address hold disabled
- Memory to memory disabled.
-
- Set mode for channels 0,1,2,3,5,6,7 as demand mode
- Address increasing, auto-initialization disabled
- Verify transfer.
-
- Set mode for channel 4 as cascade mode.
-
- NOTES:
- 1. Clear all of the DMA page registers (port 80h to 8Fh) because some
- adapter uses these page registers.
-
- --------------------------------------------------------------------------
- CHECK POINT 18h
- System timer check
- Description:
- * Channel 0 and 2 are programmed to mode 0, binary counter 16 bits.
- * Test channel 0 and 2. If it fails, display error messages and halt
- the system.
- * Channel 0 is programmed to mode 3, binary counter 16 bits which
- will be used as system timer.
-
- --------------------------------------------------------------------------
-
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 1Ch
- Memory refresh test
- Description:
- * Verify refresh if it is occurrs. If it fails, halt the system.
-
- --------------------------------------------------------------------------
- CHECK POINT 20h
- Base 128K RAM test
- Description:
- * If warm start flag = 1234h, warm start
- = 1233h, RAM BIOS operation mode,
- just clear basic 64K RAM except WARM START FLAG & MEMORY SIZE.
- * If basic 64K RAM test fails, halt the system.
-
- NOTE:
- 1. Clear second 64k after 128k memory test and set real mode stack
- at 0:400h.
- 2. When in cold start, clear all 128k RAM after 128k test OK.
-
- --------------------------------------------------------------------------
- CHECK POINT 24h
- Keyboard/auxiliary device controller (8042) test
- Description:
- * Test controller's I/O buffer and issue a self test command (AAh)
- to the controller. Insure a no error code (55h) is received.
- If it fails, halt the system.
- * Write 8042 command byte as IBM keyboard translate mode, disable
- auxiliary device & keyboard, set system flag,
- disable auxiliary interrupt and enable keyboard interrupt.
-
- NOTE:
- 1. Ensure Gate A20 is reset (bit 1 = 0 of output port of 8042).
- 2. If system has fast GATE A20, the fast Gate A20 should be turn off
- with reset Gate A20 bit of 8042 after system shutdown is issued.
-
- --------------------------------------------------------------------------
- CHECK POINT 28h
- Verify CPU LGDT/SGDT & LIDT/SIDT instructions
- Description:
- * If the test fails, halt the system.
-
- NOTE:
- 1. This check point must be tested in real mode.
-
- --------------------------------------------------------------------------
-
-
-
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 2Ch
- Test 8259 & initialize system interrupt
- Description:
- * Reset Math coprocessor
- * Test interrupt mask register
- * Initialize interrupt controller #1 by following the steps below:
- ICW1 : edge triggered, all address internal, cascade mode
- ICW4 need
- ICW2 : vector address = 8
- ICW3 : IRQ2 has a slave
- ICW4 : not special fully nested mode, non buffer mode,
- normal EOI, 8086/8088 mode
- and initialize the #2 of interrupt controller as following
- ICW1 : edge triggered, all address internal, cascade mode
- ICW4 need
- ICW2 : vector address = 70h
- ICW3 : slave ID = 2
- ICW4 : not special fully nested mode, non buffer mode,
- normal EOI, 8086/8088 mode
- then mask off all interrupt.
- * Check for unexpected interrupts.
- * If error occurred, halt the system.
-
- --------------------------------------------------------------------------
- CHECK POINT 30h
- Set temporary interrupt service routines
- Description:
- * Clear all interrupt vector
- * Set POST interrupt vector internally by setting from vector
- INT 0 to vector 6Fh with a value of type 1.
- * Set POST interrupt vector internally by setting from vector
- INT 70h to vector 77h with a value of type 2.
-
- --------------------------------------------------------------------------
- CHECK POINT 34h
- Set BIOS interrupt service routines
- Description:
- * Set interrupt service routines of BIOS from vector 08h to vector
- 20h and 4Ah.
-
- --------------------------------------------------------------------------
-
-
-
-
-
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 38h
- Verify CMOS checksum/battery if it is OK and set CMOS driver
- Description:
- * Clear the diagnostic status byte of CMOS when system is in cold
- start.
- * Clear all except memory size bit of the diagnostic when system is
- in soft reset.
- * Check CMOS battery is bad or not. Set error status into CMOS RAM's
- diagnostic status byte if the battery of CMOS lost or bad, and
- leave for next checking.
- * Verify CMOS checksum from 10h to 2Dh. If checksum is an error, set
- checksum incorrect bit (bit 6) of diagnostic status byte and leave
- it.
- * Select 32.768 KHz time base, 1.024 KHz square-wave output frequency
- and 976.562 microsecond periodic interrupt rate.
-
- --------------------------------------------------------------------------
- CHECK POINT 3Ch (PROTECTED MODE TEST1)
- Protected mode test and memory size determination
- Description:
- * Enter protected mode
- * Check the machine status word (MSW) for protected mode. If it
- fails, issue shutdown 8 to halt the system.
- * Determine the basic memory size and save it into BIOS data area.
- * Determine memory size above 1M and save it into CMOS.
- * During soft reset, the memory size determination test checks for
- parity errors.
- * Test address line 0 - 31, if it fails issue shutdown 8.
- * Issue shutdown 1.
-
- NOTE:
-
- 1. This routine runs in protected mode in order to address all of
- the storage.
- 2. During power-up sequence, memory size determination is performed
- with memory and I/O parity checks disabled.
- 3. Parity check should be enabled after this check point.
-
- --------------------------------------------------------------------------
- CHECK POINT XX
- Starting address of shutdown 8
- Description:
- * Set LED to indicate which check point causes system halt
- (C0h or check point value)
- * Execute a halt instruction to halt the system
-
- --------------------------------------------------------------------------
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 40h
- Starting address of shutdown 1
- Description:
- * Set real mode stack.
- * Set divide 0 interrupt.
- * Set bit of incorrect configuration of CMOS diagnostic byte if
- CMOS has lost power or checksum is incorrect.
- * Set bit of diskette drives installed of equipment byte of BIOS
- data area.
- --------------------------------------------------------------------------
- CHECK POINT 44h
- Initialize & test video system
- Description:
- * Check I/O ROM from C0000h to C7FFFh
- * If video ROM exists, initialize I/O ROM and skip to the next check
- point.
- * Setup vectors of graphic character font and video parameters table
- into BIOS data area.
- * Initialize 6845
- * Test 6845, video buffer and vertical signal
- * Set video mode.
- * Generate 1 long and 2 short beeps if test fails.
- * Generate 1 long and 3 short beeps if vertical synchronization test
- fails.
- * If no video exists, generate 2 short beeps and set no console flag
- bit.
-
- NOTE:
- If system has built-in video, it must be disabled when it begins
- this check point. If video I/O ROM does not exist, enable built-in
- video, initialize and test it.
- --------------------------------------------------------------------------
- CHECK POINT 48h
- Additional read/write storage test
- Description:
- * If warm start flag equals 1234h
- clear extended memory & update ext. memory size
- display total memory size and then jump to shutdown 6.
- * Enter protected mode for storage testing (including addressability
- check)
- * If the real memory size does not match configuration, set this
- information into memory mismatch CMOS diagnostic status register.
- * Display size of good memory
- * When an error occurs, update real memory size in BIOS data area or
- CMOS, and issue shutdown 3.
- * Finally, the system issue shutdown 2 when memory test successfully.
- --------------------------------------------------------------------------
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 4Ch
- Starting address of shutdown 3
- Description:
- * Display error messages of additional read/write storage test.
- * Jump to shutdown 2.
-
- --------------------------------------------------------------------------
- CHECK POINT 50h
- Additional protected mode test (starting address of shutdown 2)
- Description:
- * Enter protected mode.
- * Check the machine status word.
- * Test programmed and exception interrupt.
- * Test LDT/SDT, LTR/STR and control flags.
- * Test the following instructions:
- BOUND, PUSHA, POPA, VERW, VERR, APRL, LAR, LSL.
- * Test that a write to address 1B0000 or 1A0000 does not write B0000
- or B8000 or A0000.
- * If any error occurs, issue shutdown 7.
- * Issue shutdown 6 for normal process.
-
- --------------------------------------------------------------------------
- CHECK POINT 54h
- Starting address of shutdown 7
- Description:
- * Display error messages for protected mode and test if it fails.
- * Jump shutdown 6.
- --------------------------------------------------------------------------
- CHECK POINT 58h
- Starting address of shutdown 6
- Description:
- * Turn off gate A20.
-
- --------------------------------------------------------------------------
- CHECK POINT 5Ch
- Keyboard device test
- Description:
- * Test keyboard device interface. If it fails, display error
- messages.
- * Test keyboard. If it fails, display error messages.
- --------------------------------------------------------------------------
-
-
-
-
-
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 5Dh
- Auxiliary device test
- Description:
- * Check existence of auxiliary device. If auxiliary device does not
- exist, leave for next check.
- * Test interface of auxiliary device. If it fails, display error
- messages.
- * Test auxiliary device. If it fails, display error messages,
- otherwise set bit of pointing device of equipment byte of BIOS
- data area.
-
- NOTE:
- 1. Disable auxiliary device interface after this check point pass
- successfully.
- 2. Set pointing device interrupt service routine ( INT 74h) when the
- auxiliary device is installed.
- --------------------------------------------------------------------------
- CHECK POINT 60h
- Setup hardware interrupt vector table
- Description:
- * Setup level 0 - 7 (vectors start at INT 8).
- * Setup level 8 - 15 (vectors start at INT 70h).
- * Setup NMI, print screen, RTC, KB interrupt vectors.
- * Fill interrupt 60h thru 67h with zero.
-
- --------------------------------------------------------------------------
- CHECK POINT 64h
- Check CMOS real-time clock and diagnostic status.
- Description:
- * Enable interrupt of system timer.
- * Check for any error bit set in CMOS diagnostic status register and
- the display error messages.
- * Test real-time clock updating. If it fails, display error messages.
- --------------------------------------------------------------------------
- CHECK POINT 68h
- Test attached diskette drive and initialize floppy diskette drive.
- Description:
- * Check if diskette drive is attached to system.
- * If it is attached, test it. If test fails, display error messages.
- * Determine how many drives and what type of drives are installed.
- * Update diskette drive number bits of equipment byte of BIOS data
- area.
- * If configuration of dikestte drive does not match, set
- configuration error bit of diagnostic status byte.
- NOTE:
- Check FDC status before turning on diskette motor. If status fails,
- reset diskette.
- --------------------------------------------------------------------------
-
- --------------------------------------------------------------------------
- CHECK POINT 6Ch
- Initialize hard disk drive
- Description:
- * Test attach hard disk and setup BIOS data area.
- * If any error occurs, display error messages.
-
- --------------------------------------------------------------------------
- CHECK POINT 70h
- Check parallel port
- Description:
-
- * Assign printer timeout value
- * Check the presence of parallel port
- * If parallel port exists, set port address to BIOS data area.
- * Assign number of parallel to equipment byte of BIOS data area.
-
- NOTE:
- 1. If system has built-in parallel port, disable on-board
- parallel port, and then check whether add-on parallel is present
- or not.
- 2. If add-on exists, disable on-board parallel port, otherwise
- enable on-board parallel port and check its presence.
-
- --------------------------------------------------------------------------
- CHECK POINT 74h
- Check serial port
- Description:
-
- * assign RS232 timeout value
- * check presence of serial port
- * If serial port exist, set port address to BIOS data area.
- * assign number of RS232 to equipment byte of BIOS data area.
- NOTE:
- 1. If system has built-in serial port, disable on-board
- serial port and then check the presence of an add-on serial.
- 2. If add-on exists, disable on-board serial port, otherwise enable
- on board serial port and check if it exist or not.
- --------------------------------------------------------------------------
- CHECK POINT 78h
- Check for optional ROM from C8000h to DFFFFh in 2K block
- Description:
- * A valid module has '55AA' in the first 2 locations, length
- indicator (length/512) in the 3rd location and test/init, and
- code starting in the 4th location.
- * Check optional ROM using the above criteria. If its checksum is OK,
- initialize it.
- --------------------------------------------------------------------------
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 7Ch
- Test MATH coprocessor installation
- Description:
- * Check MATH coprocessor if is good or not.
- * Set up equipment byte of BIOS data area and MP bit of CPU register.
-
- NOTE:
- Set ET bit of MSW in CPU when 80387 math_processor has been installed
-
- --------------------------------------------------------------------------
- CHECK POINT 80h
- Initialize keyboard
- Description:
- * Clear keyboard controller and LED flag of BIOS data area.
- * Enable keyboard and timer interrupt.
- * Read keyboard ID to initialize keyboard type and NUM lock state.
- * If it fails, display error messages.
- * Setup pointer of buffer head, buffer tail, buffer start, buffer end
- in BIOS data area.
-
- --------------------------------------------------------------------------
- CHECK POINT 84h
- Set time of day
- Description:
- * If CMOS RAM content is bad, set bit of invalid time of diagnostic
- status byte and display error messages then exit for the next
- check.
- * Convert HR:MIN:SEC from CMOS to timer ticks and store in BIOS data
- area.
-
- NOTE:
- 1. If the time of day in CMOS is failure, clear timer ticks of BIOS
- data area.
- 2. The timer ticks is counted by system timer (IRQ0) increase by 1
- when IRQ 0 interrupt occurred.
- The period of IRQ0 is 0.054925493 sec ( = 65536/1.19318 MHz), and
- the real timer ticks counter of one day (24 hours) is 1573040.045
- ( = 24 * 60 * 60 sec/ 0.054925493 sec) i.e. 24*65536 +176.045, so
- system timer has error value 176.045 that must be considered in
- converting HR:MIN:SEC of CMOS into timer ticks of BIOS data.
-
-
- --------------------------------------------------------------------------
-
-
-
-
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 88h
- Initialize system (I)
- Description:
- * Generate 1 short beep for successfull POST.
- * Clear any RAM that is temporarily used by POST.
- * Set POST system stack.
- * Ensure that master level 2 of interrupt system is enabled.
- * Unmask hardware auxiliary device interrupt (INT 74h) when
- pointing device has been installed.
-
- NOTES:
- 1. Display the number of hard disk, diskette and system configuration
- 2. Let user select the system setup configuration or bypass a system
- configuration error.
-
- --------------------------------------------------------------------------
- CHECK POINT 8Ch
- Initialize system (II) (Starting address of shutdown 4)
- Description:
- * Enable NMI, channel check and parity check.
- * Go to bootstrap loader.
- --------------------------------------------------------------------------
- CHECK POINT 90h
- Boot strap loader (INT 19H)
- Description:
- * Read track 0, sector 1 of diskette into the boot location
- (segment 0 offset 7C00). Transfer the control if no errors
- occurred.
- * If there is a hardware error while booting from the diskette, try
- to boot from the hard disk.
- * Check power-on password during system cold start and the password
- is enabled.
- NOTES:
- 1. Clear warm start flag.
- 2. System can boot from driver B on laptop machine for an external
- driver boot.
- --------------------------------------------------------------------------
- CHECK POINT 94h
- Starting address of shutdown 5
- Description:
- * Flush the keyboard buffer.
- * Flush last timer when request is pending in order to allow timer
- interrupt.
- * Issue a jump far instruction to the far pointer of 40:67 in the
- BIOS data area.
- * Jump to shutdown 0A.
- --------------------------------------------------------------------------
- -- To be continued --
-
- --------------------------------------------------------------------------
- CHECK POINT 98h
- Starting address of shutdown 0A
- Description:
- * Issue a jump far instruction to the far pointer of 40:67 in the
- BIOS data area.
- --------------------------------------------------------------------------
- CHECK POINT 9Ch
- Starting address of shutdown 0B
- Description:
- * Turn off gate A20.
- * Clear value of IDTR and set its limit to 3FFh.
- * Issue a jump far instruction to the far pointer of 40:67 in the
- BIOS data area.
-
- --------------------------------------------------------------------------
-
-