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1990-01-12
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18KB
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432 lines
82C212X Page/Interleave and EMS Memory Controller
1. Features
A. Page mode access includeing single bank, 2 way and 4 way page
interleaved, providing higher performance over conventional
DRAM accessing schemes
B. Supports 100ns DRAMs at 16MHz using page interleaved operation
C. Supports up to 8Mbytes of on board memory
D. Provides automatic remapping of RAM resident in 640K to 1Mbyte area
to the top of the 1Mbyte address space
E. Supports Lotus Intel Microsoft-Expanded Memory System (LIM-EMS 4.0)
address transiation logic
F. Shadow RAM feature for efficient BIOS execution
G. OS/2 optimization feature allows fast switching between protected
and real mode
H. Staggered refresh to reduce power supply
2. Register Description
Index register port: 22h
Data register port: 23h
A. PROCCLK Register RA0 - Index 60h
bit 7,6 - 82C211 revision number. 00 is the initial number
bit 5 - Alternate CPU reset. A low to high transition in this bit
activates a CPU reset. Once active, it remains active for
16 PROCCLK cycles and then goes low.
bit 4 - Processor clock select is by default set to zero and
selects PROCCLK = CLK2IN (high speed).
If high, it selects PROCCLK = BCLK (low speed).
bit 3 - Reserved.
bit 2 - Local bus READY timeout NMI enable. A one enables the NMI and
a zero disables it. Default is 0.
bit 1 - Reserved.
bit 0 - Local bus READY timeout. A one indicates that READY timeout
has occured 128 PROCCLK cycles has occured after -AF16 has
been asserted. A zero indicates that READY timeout has not
occurred.
B. Command Delay Register RA1 - Index 61h
bit 7 - Address hold time delay. A one enable extra address bus hold
time and A zero disables it. Default is 0.
bit 6 - Quick mode enable. A zero enables Quick mode and a one disables
it. Default is 1.
bit 5,4 - AT Bus 16 bit memory command delay. Specifies between 0 and 3
BCLK cycle command delays for 16 bit AT memory cycles. Default
is 0.
bit 3,2 - AT Bus 8 bit memory command delay. Specifies between 0 and 3
BCLK cycle command delays for 8 bit AT memory cycles. Default
is 1.
bit 1,0 - AT Bus I/O cycle command delay. Specifies between 0 and 3
BCLK cycle command delays for AT I/O cycles. Default is 1.
C. Wait State Register RA2 - Index 62h
bit 7,6 - Reserved.
bit 5,4 - 16 bit AT cycle wait state generation. Default is 11
00 - 0 wait state
01 - 1 wait state
10 - 2 wait states
11 - 3 wait states (default)
bit 3,2 - 8 bit AT cycle wait state generation. Default is 11.
00 - 2 wait state
01 - 3 wait state
10 - 4 wait states
11 - 5 wait states (default)
bit 1,0 - Bus clock (BCLK) source select. Default is 00.
00 - BCLK = CLK2IN/2 (default, SYNC)
01 - BCLK = CLK2IN
10 - BCLK = ATCLK (ASYNC)
11 - Reserved
D. Version Register RB0 - Index 64h
bit 7 - NEAT memory controller identifier. 0 = 82C212.
bit 6,5 - 82C212 revision number.
00 = initial revision number.
01 = 82C212B
bit 4-0 - Reserved and default to 0.
E. ROM Configuration Register RB1 - Index 65h
bit 7 - Shadow RAM at C0000h-CFFFFh in Read/Write mode.
0 - Read/Write (default), 1 - Read only (Write protected).
bit 6 - Shadow RAM at D0000h-DFFFFh in Read/Write mode.
0 - Read/Write (default), 1 - Read only (Write protected).
bit 5 - Shadow RAM at E0000h-EFFFFh in Read/Write mode.
0 - Read/Write (default), 1 - Read only (Write protected).
bit 4 - Shadow RAM at F0000h-FFFFFh in Read/Write mode.
0 - Read/Write (default), 1 - Read only (Write protected).
bit 3 - ROM at C0000h-CFFFFh (EGA).
0 - ROM enabled, Shadow RAM disabled. -ROMCS is generated.
1 - Shadow RAM enabled (Default).
bit 2 - ROM at D0000h-DFFFFh.
0 - ROM enabled, Shadow RAM disabled. -ROMCS is generated.
1 - Shadow RAM enabled (Default).
bit 1 - ROM at E0000h-EFFFFh.
0 - ROM enabled, Shadow RAM disabled. -ROMCS is generated.
1 - Shadow RAM enabled (Default).
bit 0 - ROM at F0000h-FFFFFh.
0 - ROM enabled, Shadow RAM disabled. -ROMCS is generated.
1 - Shadow RAM enabled (Default).
F. Memory Enable-1 Register RB2 - Index 66h
bit 7 - Address map RAM on system board is 80000h-9FFFFh area.
0 - on the I/O channel, 1 - on the system board
bit 6 - Address map RAM on system board is 40000h-7FFFFh area.
0 - on the system board, 1 - on the I/O channel
bit 5 - Address map RAM on system board is 00000h-3FFFFh area.
0 - on the system board, 1 - on the I/O channel
bit 4-0 - Reserved and default to 0.
G. Memory Enable-2 Register RB3 - Index 67h
bit 7 - Enable Shadow RAM in AC000h-AFFFFh area.
0 - Disable, 1 - Enable
bit 6 - Enable Shadow RAM in A8000h-ABFFFh area.
0 - Disable, 1 - Enable
bit 5 - Enable Shadow RAM in A4000h-A7FFFh area.
0 - Disable, 1 - Enable
bit 4 - Enable Shadow RAM in A0000h-A3FFFh area.
0 - Disable, 1 - Enable
bit 3 - Enable Shadow RAM in BC000h-BFFFFh area.
0 - Disable, 1 - Enable
bit 2 - Enable Shadow RAM in B8000h-BBFFFh area.
0 - Disable, 1 - Enable
bit 1 - Enable Shadow RAM in B4000h-B7FFFh area.
0 - Disable, 1 - Enable
bit 0 - Enable Shadow RAM in B0000h-B3FFFh area.
0 - Disable, 1 - Enable
H. Memory Enable-3 Register RB4 - Index 68h
bit 7 - Enable Shadow RAM in DC000h-DFFFFh area.
0 - Disable, 1 - Enable
bit 6 - Enable Shadow RAM in D8000h-DFFFFh area.
0 - Disable, 1 - Enable
bit 5 - Enable Shadow RAM in D4000h-D7FFFh area.
0 - Disable, 1 - Enable
bit 4 - Enable Shadow RAM in D0000h-D3FFFh area.
0 - Disable, 1 - Enable
bit 3 - Enable Shadow RAM in CC000h-CFFFFh area.
0 - Disable, 1 - Enable
bit 2 - Enable Shadow RAM in C8000h-CBFFFh area.
0 - Disable, 1 - Enable
bit 1 - Enable Shadow RAM in C4000h-C7FFFh area.
0 - Disable, 1 - Enable
bit 0 - Enable Shadow RAM in C0000h-C3FFFh area.
0 - Disable, 1 - Enable
I. Memory Enable-4 Register RB5 - Index 69h
bit 7 - Enable Shadow RAM in FC000h-FFFFFh area.
0 - Disable, 1 - Enable
bit 6 - Enable Shadow RAM in F8000h-FFFFFh area.
0 - Disable, 1 - Enable
bit 5 - Enable Shadow RAM in F4000h-F7FFFh area.
0 - Disable, 1 - Enable
bit 4 - Enable Shadow RAM in F0000h-F3FFFh area.
0 - Disable, 1 - Enable
bit 3 - Enable Shadow RAM in EC000h-EFFFFh area.
0 - Disable, 1 - Enable
bit 2 - Enable Shadow RAM in E8000h-EBFFFh area.
0 - Disable, 1 - Enable
bit 1 - Enable Shadow RAM in E4000h-E7FFFh area.
0 - Disable, 1 - Enable
bit 0 - Enable Shadow RAM in E0000h-E3FFFh area.
0 - Disable, 1 - Enable
J. Bank 0/1 Enable Register RB6 - Index 6Ah
bit 7,6 - The DRAM types used on the system board. POST/BIOS should
use the DRAM configuration data stored in the CMOS RAM of the
82C206 IPC
00 - Disable
01 - 256K and 64K bit DRAMs used (for 640 Kbyte combination only)
10 - 256K bit DRAMs used (default)
11 - 1M bit DRAMs used
bit 5 - Number of RAM banks used.
0 - one bank, non-interleaved mode (default)
1 - two banks
bit 4-0 - Reserved and default to 0.
H. DRAM Configuration Register RB7 - Index 6Bh
bit 7 - Page/Interleaved mode enable.
0 - disable (default), 1 - enable
bit 6 - 640Kbyte to 1Mbyte RAM relocation bit.
0 - not relocate local RAM.
1 - relocate local RAM from 0A0000-0F0000h to 100000-15FFFFh,
provided total local RAM is 1Mbyte only.
bit 5 - RAM access wait states.
0 - 0 wait state, 1 - 1 wait state
bit 4 - EMS enable bit.
0 - disable (default), 1 - enable
bit 3,2 - EMS memory access wait states.
bit 1,0 - ROM access wait states control.
11 - 3 wait states (default)
J. Bank 2/3 Enable Register RB8 - Index 6Ch
bit 7,6 - The DRAM types used on the system board.
00 - Disable (default)
01 - Reserved
10 - 256K bit DRAMs used (default)
11 - 1M bit DRAMs used
bit 5 - Number of RAM banks used.
0 - one bank, non-interleaved mode (default)
1 - two banks
bit 4 - 2-way/4-way page interleaved mode.
0 - 2-way page interleaved mode
1 - 4-way page interleaved mode
if all 4 banks are the DRAM type (default)
bit 3-0 - Reserved and default to 0.
K. EMS Base Address Register RB9 - Index 6Dh
bit 7-4 - select the expanded memory base addresses.
7 6 5 4 | EMS Base Addresses
-------------------------------------
0 0 0 0 | C0000h,C4000h,C8000h,CC000h
0 0 0 1 | C4000h,C8000h,CC000h,D0000h
0 0 1 0 | C8000h,CC000h,D0000h,D4000h
0 0 1 1 | CC000h,D0000h,D4000h,D8000h
0 1 0 0 | D0000h,D4000h,D8000h,DC000h
0 1 0 1 | D4000h,D8000h,DC000h,E0000h
0 1 1 0 | D8000h,DC000h,E0000h,E4000h
0 1 1 1 | DC000h,E0000h,E4000h,E8000h
1 0 0 0 | E0000h,E4000h,E8000h,EC000h
others | Reserved
-------------------------------------
bit 3-0 - the EMS page register I/O base address
3 2 1 0 | I/O Base Port
-------------------------------------
0 0 0 0 | 208h/209h
0 0 0 1 | 218h/219h
0 1 0 1 | 258h/259h
0 1 1 0 | 268h/269h
1 0 1 0 | 2A8h/2A9h
1 0 1 1 | 2B8h/2B9h
1 1 1 0 | 2E8h/2E9h
others | Reserved
-------------------------------------
L. EMS Address Extension Register RB10 - Index 6Eh
bit 7,6 - EMS Page 0 address extension bits
(A22,A21) Block of EMS Memory
0 0 - 0 Mbyte to 2 Mbyte
0 1 - 2 Mbyte to 4 Mbyte
1 0 - 4 Mbyte to 6 Mbyte
1 1 - 6 Mbyte to 8 Mbyte
bit 5,4 - EMS Page 1 address extension bits
(A22,A21) Block of EMS Memory
0 0 - 0 Mbyte to 2 Mbyte
0 1 - 2 Mbyte to 4 Mbyte
1 0 - 4 Mbyte to 6 Mbyte
1 1 - 6 Mbyte to 8 Mbyte
bit 3,2 - EMS Page 2 address extension bits
(A22,A21) Block of EMS Memory
0 0 - 0 Mbyte to 2 Mbyte
0 1 - 2 Mbyte to 4 Mbyte
1 0 - 4 Mbyte to 6 Mbyte
1 1 - 6 Mbyte to 8 Mbyte
bit 1,0 - EMS Page 3 address extension bits
(A22,A21) Block of EMS Memory
0 0 - 0 Mbyte to 2 Mbyte
0 1 - 2 Mbyte to 4 Mbyte
1 0 - 4 Mbyte to 6 Mbyte
1 1 - 6 Mbyte to 8 Mbyte
L. EMS Address Extension Register RB11 - Index 6Fh
bit 7-5 - to set the EMS memory space size
0 0 0 | 1 Mbyte to 1.5 Mbytes (0.5 Mbytes)
0 0 1 | 1 Mbyte to 2 Mbytes (1 Mbytes)
0 1 0 | 1 Mbyte to 3 Mbytes (2 Mbytes)
0 1 1 | 1 Mbyte to 4 Mbytes (3 Mbytes)
1 0 0 | 1 Mbyte to 5 Mbytes (4 Mbytes)
1 0 1 | 1 Mbyte to 6 Mbytes (5 Mbytes)
1 1 0 | 1 Mbyte to 7 Mbytes (6 Mbytes)
1 1 1 | 1 Mbyte to 8 Mbytes (7 Mbytes)
bit 4 - external EMS Mapper Enable
0 - disable (default), 1 - enable
bit 3 - Reserved
bit 2 - to enable the RAS time_out counter for page mode operation
0 - disable (default), 1 - enable
bit 1 - Address line A20 control and provides OS/2 optimization
while switching between real and protected modes
0 - A20 = CPUA20 (default), 1 - A20 = 0
bit 0 - Reserved
3. Programming flow
A. Main flow
(1). Disable NMI and Parity Check
(2). Initialize 82C206 (01h) and 82C212x (60-6Fh) chip's values
(3). Determine and set DRAM type
(4). Determine and set none/2-way/4-way Page Interleaved
(5). Determine and set EMS size
(6). Determine and set On system board/ On I/O channel
(7). Determine and set RAM BIOS/ ROM BIOS mode
(8). Determine and set relocatable/none-relocatable 640k-1Mbyte
B. Data area
(1). Index 34h of CMOS byte
bit 7 - 0 = EMS disable, 1 = EMS enable
bit 6,5,4 - EMS size (index 6Fh of 82C212x)
bit 3 - 0 = cannot set RAM BIOS, 1 = can set RAM BIOS
bit 2 - 1 = force cold start
bit 1 -
a. during NEAT testing interval
0 = check and initialize 82C212x, 1 = skip
b. during later POST testing interval
0 = normal keyboard, 1 = manufacture board test
bit 0 - 0 = ROM BIOS, 1 = RAM BIOS
(2). index 11h of CMOS byte
- functions in on_board base memory enable/disable
it will be stealed to save on_board base memory flag
bit 7 --- 512k to 640k (1:enable, 0:disable)
bit 6 --- 256k to 511k (0:enable, 1:disable)
bit 5 --- 0k to 255k (0:enable, 1:disable)
bit 4 --- reserved
bit 3 --- reserved
bit 2 --- reserved
bit 1 --- reserved
bit 0 --- hard_disk physical format (0:hd_1, 1:hd_2)
C. the DRAM types of possible combination of Bank 0,1,2,3
Bank0 Bank1 Bank2 Bank3
0 -- Disable Disable Disable Disable
1 -- 256K None None None
2 -- 256K 64K None None
3 -- 256K 256K None None
4 -- 1M None None None
5 -- 1M 1M None None
6 -- 256K 64K 256K None
7 -- 256K 64K 256K 256K
8 -- 256K 64K 1M None
9 -- 256K 64K 1M 1M
10 -- 256K 256K 256K None
11 -- 256K 256K 256K 256K
12 -- 256K 256K 1M None
13 -- 256K 256K 1M 1M
14 -- 1M 1M 1M None
15 -- 1M 1M 1M 1M
D. Program Description Language
Start:
Disable NMI
Disable parity check and Clear parity error
Set 82C206 initial value
( index 01h of Neat = 0C0h )
IF not warm boot THEN
Set PROCCLK = CLK2IN, Disable Local bus READY timeout NMI
( index 60h of Neat = 042h )
ENDIF
Enable extra address bus hold time and Quick mode,
AT Bus 16 bit memory command delay = 0 BCLK cycle,
AT Bus 8 bit memory command delay = 1 BCLK cycle,
AT Bus I/O cycle command delay = 1 BCLK cycle
( index 61h of Neat = 0C5h )
IF Version 82C212 THEN
16 bit AT cycle = 3 wait states
8 bit AT cycle = 3 wait states
Bus Clock (BCLK) = ATCLK (Asynchronous)
( index 62h of Neat = 03Eh )
EMS memory size = 1Mbyte to 2 Mbytes
Disable external EMS Mapper
Disable RAS time_out counter
A20 = CPUA20
( index 6Fh of Neat = 020h )
ELSE IF Version 82C212B or others THEN
16 bit AT cycle = 3 wait states
8 bit AT cycle = 3 wait states
Bus Clock (BCLK) = ATCLK (Asynchronous)
( index 62h of Neat = 0BEh )
EMS memory size = 1Mbyte to 2 Mbytes
Disable external EMS Mapper
Disable RAS time_out counter
A20 = 0
( index 06Fh of Neat = 022h )
ENDIF
( index 065h of Neat = 00Eh ) ; Enable ROM BIOS (F0000-FFFFFh)
( index 066h of Neat = 080h ) ; Enable On system board 640K
( index 067h of Neat = 000h ) ; Disable A0000-BFFFFh Shadow RAM
( index 068h of Neat = 000h ) ; Disable C0000-DFFFFh Shadow RAM
( index 069h of Neat = 000h ) ; Disable E0000-FFFFFh Shadow RAM
( index 06Ah of Neat = 0E0h ) ; bank 0/1 = 1M bit DRAMs used, 2 banks
( index 06Bh of Neat = 027h ) ; Disable Page/Interleaved mode,
; non_relocatable, 1 RAM wait state
; 3 ROM wait states
( index 06Ch of Neat = 000h ) ; Disable bank 2/3
( index 06Dh of Neat = 042h ) ; Select unsed combination of EMS
( index 06Eh of Neat = 000h ) ; EMS Page 0-3 addr = 0 Mbyte to 2 Mbyte
Check DRAM types of combination of Bank 0,1,2,3 and Set Neat
IF Bank 0,1,2,3 are same THEN
Set DRAM to 4-way page interleaved
Enable page interleaved
Set RAM = 0 wait state
ELSE IF Bank 0,1 are same or Bank 2,3 are same THEN
Set DRAM to 2-way page interleaved
Enable page interleaved
Set RAM = 0 wait state
ELSE
Set RAM = 1 wait state
ENDIF
IF Check CMOS sum (10h- 2Dh) error THEN
Set index 34h of CMOS byte = 0
ENDIF
IF bit 7 of index 34h of CMOS byte = 1 THEN
Enable EMS
Check ans set EMS size according to bit 6,5,4 of index 34h of CMOS byte
ELSE
Disable EMS
ENDIF
Enable on board system memory
Set bit 3 of index 34 of CMOS byte = 0 (cannot use RAM BIOS) (default)
IF bit 0 of index 34 of CMOS byte = 0 (ROM BIOS) THEN
IF memory = 1M byte THEN
Set relocatable
ELSE
Set non_relocatable
IF memory >= 1Mb THEN
IF move ROM BIOS to RAM BIOS no error THEN
Set bit 3 of index 34 of CMOS byte = 1 (can use RAM BIOS)
ENDIF
ENDIF
ENDIF
ENDIF
set [SS] = 0 ans [SP] = 08000h
End: