Collection of Hack-Phreak Scene Programs/cleanhpvac.zip/cleanhpvac/INTER53D.ZIP/PORTS.LST

File List | 1997-01-12 | 315KB | 8,342 lines

PORT LIST            Release 53        Last change 12jan97
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997 Ralf Brown
[This file originally by Wim Osterholt (2:512/56 or [e-mail]),
 though it has grown considerably since.]

        XT, AT and PS/2     I/O port addresses

Do NOT consider this information to be complete and accurate.  If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!).  Be aware that erroneous port programming
can put your data or even your hardware at risk.

There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.

---------------------------------------------
Note: the port description format is:

PPPPw RW  description

where:    PPPP    is the four-digit hex port number
    w    is blank for byte-size port, 'w' for word, and 'd' for dword
    R    is blank or dash if not readable, 'r' if sometimes readable,
        'R' if "always" readable, '?' if readability unknown
    W    is blank or dash if not writable, 'w' if sometimes writable,
        'W' if "always" writable, '?' if writability unknown
----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)

0000  RW  DMA channel 0     address byte  0, then byte 1
0001  RW  DMA channel 0 word count byte 0, then byte 1
0002  RW  DMA channel 1     address byte  0, then byte 1
0003  RW  DMA channel 1 word count byte 0, then byte 1
0004  RW  DMA channel 2     address byte  0, then byte 1
0005  RW  DMA channel 2 word count byte 0, then byte 1
0006  RW  DMA channel 3     address byte  0, then byte 1
0007  RW  DMA channel 3 word count byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P001)
0008  -W  DMA channel 0-3 command register (see #P002)
0009  -W  DMA channel 0-3 write request register (see #P003)
000A  RW  DMA channel 0-3 mask register (see #P004)
000B  -W  DMA channel 0-3 mode register (see #P005)

000C  -W  DMA clear byte pointer flip-flop
000D  R-  DMA read temporary register
000D  -W  DMA master clear
000E  -W  DMA clear mask register
000F  -W  DMA write mask register

Bitfields for DMA channel 0-3 status register:
Bit(s)    Description    (Table P001)
 7    channel 3 request active
 6    channel 2 request active
 5    channel 1 request active
 4    channel 0 request active
 3    channel terminal count on channel 3
 2    channel terminal count on channel 2
 1    channel terminal count on channel 1
 0    channel terminal count on channel 0
SeeAlso: #P002,#P078

Bitfields for DMA channel 0-3 command register:
Bit(s)    Description    (Table P002)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1 extended write selection
    =0 late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing
 2    =1 enable controller
    =0 enable memory-to-memory
 1-0    channel number
SeeAlso: #P001,#P004,#P005,#P079

Bitfields for DMA channel 0-3 request register:
Bit(s)    Description    (Table P003)
 7-3    reserved (0)
 2    =0 clear request bit
    =1 set request bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P004

Bitfields for DMA channel 0-3 mask register:
Bit(s)    Description    (Table P004)
 7-3    reserved (0)
 2    =0 clear mask bit
    =1 set mask bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P001,#P002,#P003,#P080

Bitfields for DMA channel 0-3 mode register:
Bit(s)    Description    (Table P005)
 7-6    transfer mode
    00 demand mode
    01 single mode
    10 block mode
    11 cascade mode
 5    direction
    =0 address increment select
    =1 address decrement select
 3-2    operation
    00 verify operation
    01 write to memory
    10 read from memory
    11 reserved
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P002,#P081
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
----------P0018------------------------------
PORT 0018 - PS/2 - EXTENDED FUNCTION REGISTER

0018  -W  PS/2 extended function register
----------P001A------------------------------
PORT 001A - PS/2 - EXTENDED FUNCTION EXECUTE
----------P0020003F--------------------------
PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020  -W  PIC initialization command word ICW1 (see #P006)
0020  -W  PIC output control word OCW2 (see #P011)
0020  -W  PIC output control word OCW3 (see #P012)
0020  R-  PIC  interrupt request/in-service registers after OCW3
        request register:
         bit 7-0 = 0  no active request for the corresponding int. line
             = 1  active request for corresponding interrupt line
        in-service register:
         bit 7-0 = 0  corresponding line not currently being serviced
             = 1  corresponding int. line currently being serviced

0021  -W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P007,#P008,#P009)
0021  RW  PIC master interrupt mask register OCW1 (see #P010)

Bitfields for PIC initialization command word ICW1:
Bit(s)    Description    (Table P006)
 7-5    0 (only used in 8080/8085 mode)
 4    ICW1 is being issued
 3    (LTIM)
    =0  edge triggered mode
    =1  level triggered mode
 2    interrupt vector size
    =0 successive interrupt vectors use 8 bytes (8080/8085)
    =1 successive interrupt vectors use 4 bytes (80x86)
 1    (SNGL)
    =0  cascade mode
    =1  single mode, no ICW3 needed
 0    ICW4 needed
SeeAlso: #P007,#P008,#P009

Bitfields for PIC initialization command word ICW2:
Bit(s)    Description    (Table P007)
 7-3    address lines A0-A3 of base vector address for PIC
 2-0    reserved
SeeAlso: #P006,#P008,#P009

Bitfields for PIC initialization command word ICW3:
Bit(s)    Description    (Table P008)
 7-0    =0 slave controller not attached to corresponding interrupt pin
    =1 slave controller attached to corresponding interrupt pin
SeeAlso: #P006,#P007,#P009

Bitfields for PIC initialization command word ICW4:
Bit(s)    Description    (Table P009)
 7-5    reserved (0)
 4    running in special fully-nested mode
 3-2    mode
    0x nonbuffered mode
    10 buffered mode/slave
    11 buffered mode/master
 1    Auto EOI
 0    =0  8085 mode
    =1  8086/8088 mode
SeeAlso: #P006,#P007,#P008

Bitfields for PIC output control word OCW1:
Bit(s)    Description    (Table P010)
 7    disable IRQ7 (parallel printer interrupt)
 6    disable IRQ6 (diskette interrupt)
 5    disable IRQ5 (fixed disk interrupt)
 4    disable IRQ4 (serial port 1 interrupt)
 3    disable IRQ3 (serial port 2 interrupt)
 2    disable IRQ2 (video interrupt)
 1    disable IRQ1 (keyboard, mouse, RTC interrupt)
 0    disable IRQ0 (timer interrupt)
SeeAlso: #P011,#P012,#P077

Bitfields for PIC output control word OCW2:
Bit(s)    Description    (Table P011)
 7-5    operation
    000 rotate in auto EOI mode (clear)
    001 (WORD_A) nonspecific EOI
    010 (WORD_H) no operation
    011 (WORD_B) specific EOI
    100 (WORD_F) rotate in auto EOI mode (set)
    101 (WORD_C) rotate on nonspecific EOI command
    110 (WORD_E) set priority command
    111 (WORD_D) rotate on specific EOI command
 4-3    reserved (00 - signals OCW2)
 2-0    interrupt request to which the command applies
    (only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P010,#P012

Bitfields for PIC output control word OCW3:
Bit(s)    Description    (Table P012)
 7    reserved (0)
 6-5    special mask
    0x  no operation
    10  reset special mask
    11  set special mask mode
 4-3    reserved (01 - signals OCW3)
 2    poll command
 1-0    function
    0x  no operation
    10  read interrupt request register on next read from PORT 0020h
    11  read interrupt in-service register on next read from PORT 0020h
Note:    the special mask mode permits all other interrupts (even those with
      lower priority) to be processed while an interrupt is already in
      service, but will not re-issue an interrupt for a particular IRQ
      while it remains in service
SeeAlso: #P010,#P011
----------P00220023--------------------------
PORT 0022-0023 - CHIP SET DATA

0022  -W  index for accesses to data port
0023  RW  chip set data
----------P00220023--------------------------
PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P013)
0023  RW  cache configuration register array (indexed by PORT 0022h)

(Table P013)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h    CR0 (see #P015)
 C1h    CR1 (see #P016)
 C4h    non-cacheable region 1, start address bits 31-24
 C5h    non-cacheable region 1, start address bits 23-16
 C6h    non-cacheable region 1, start addr 15-12, size (low nibble) (see #P014)
 C7h    non-cacheable region 2, start address bits 31-24
 C8h    non-cacheable region 2, start address bits 23-16
 C9h    non-cacheable region 2, start addr 15-12, size (low nibble) (see #P014)
 CAh    non-cacheable region 3, start address bits 31-24
 CBh    non-cacheable region 3, start address bits 23-16
 CCh    non-cacheable region 3, start addr 15-12, size (low nibble) (see #P014)
 CDh    non-cacheable region 4, start address bits 31-24
 CEh    non-cacheable region 4, start address bits 23-16
 CFh    non-cacheable region 4, start addr 15-12, size (low nibble) (see #P014)
SeeAlso: #P017,#P283

(Table P014)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h    disabled
 01h    4K
 02h    8K
 03h    16K
 04h    32K
 05h    64K
 06h    128K
 07h    256K
 08h    512K
 09h    1M
 0Ah    2M
 0Bh    4M
 0Ch    8M
 0Dh    16M
 0Eh    32M
 0Fh    4G
SeeAlso: #P013

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)    Description    (Table P015)
 0    "NC0" first 64K of each 1M noncacheable in real/V86
 1    "NC1" 640K-1M noncacheable
 2    "A20M" enables A20M# input pin
 3    "KEN"  enables KEN# input pin
 4    "FLUSH" enables KEN# input pin
 5    "BARB" enables internal cache flushing on bus holds
 6    "C0" cache direct-mapped instead of 2-way associative
 7    "SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P013,#P016

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)    Description    (Table P016)
 0    "RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P013,#P015
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P017)
0023  RW  configuration control register array (indexed by PORT 0022h)

(Table P017)
Values for Cyrix 5x86 configuration registers:
 20h    Performance Control (see #P022)
 C1h    Configuration Control #1 (CCR1) (see #P018)
 C2h    Configuration Control #2 (CCR2) (see #P019)
 C3h    Configuration Control #3 (CCR3) (see #P020)
 CDh    System Memory Management address region #0 (smar0) (see #P023)
 CEh    System Memory Management address region #1 (smar1)
 CFh    System Memory Management address region #2 (smar2)
 E8h    Configuration Control Register 4
 F0h    Power Management (see #P024)
 FEh R    Device Identification #0
    CPU device ID
 FFh R    Device Identification #1
    bits 3-0: revision
    bits 7-4: stepping
Note:    accesses to indices other than 20h,C0h-CFh, or F0h-FFh generate
      external I/O cycles
SeeAlso: #P013,#P283

Bitfields for Cyrix 5x86 Configuration Control Register 1 (CCR1):
Bit(s)    Description    (Table P018)
 0    reserved
 1    enable SMM pins
 2    system management memory access
 3    main memory access
 7-4    reserved
SeeAlso: #P019,#P020,#P021

Bitfields for Cyrix 5x86 Configuration Control Register 2 (CCR2):
Bit(s)    Description    (Table P019)
 0    reserved
 1    enable write-back cache interface pins
 2    lock NW bit
 3    suspend on HLT instruction
 4    write-through region 1
 5    reserved
 6    enable burst write cycles
 7    enable suspend pins
SeeAlso: #P018,#P020,#P021

Bitfields for Cyrix 5x86 Configuration Control Register 3 (CCR3):
Bit(s)    Description    (Table P020)
 0    SMM register lock
 1    NMI enable
 2    linear address burst cycles
 3    SMM mode
 7-4    map enable (0001 to enable several configuration registers)
SeeAlso: #P018,#P019,#P021,#P022,#P024

Bitfields for Cyrix 5x86 Configuration Control Register 4 (CCR4):
Bit(s)    Description    (Table P021)
 2-0    I/O recovery time
 3    enable memory-read bypassing
 4    enable directory table entry cache
 6-5    reserved
 7    enable CPUID instruction (stepping 1+ and Cx6x86)
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P018,#P019,#P020

Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)    Description    (Table P022)
 0    return stack enabled
 1    branch-target buffer enabled
 2    loop enable
 6-3    reserved (0)
 7    load-store serialization enabled
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P024,#P018

Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s)    Description    (Table P023)
 3-0    block size
 23-4    starting address

Bitfields for Cyrix 5x86 Power Management register:
Bit(s)    Description    (Table P024)
 1-0    core clock to bus clock ratio
 2    CPU running at half bus speed
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86"

0022  -W  index for accesses to next port (see #P017)
0023  RW  configuration control register array (indexed by PORT 0022h)

(Table P283)
Values for Cyrix 6x86 configuration registers:
 20h    Performance Control (see #P022)
 C0h    Configuration Control Register 0 (CCR0)
 C1h    Configuration Control #1 (CCR1) (see #P018)
 C2h    Configuration Control #2 (CCR2) (see #P019)
 C3h    Configuration Control #3 (CCR3) (see #P020)
 C4h    Address region 0 (bits 31-24)
 C5h    Address region 0 (bits 23-16)
 C6h    Address region 0 (bits 15-12 and size)
 C7h    Address region 1 (bits 31-24)
 C8h    Address region 1 (bits 23-16)
 C9h    Address region 1 (bits 15-12 and size)
 CAh    Address region 2 (bits 31-24)
 CBh    Address region 2 (bits 23-16)
 CCh    Address region 2 (bits 15-12 and size)
 CDh    Address region 3 (bits 31-24)
 CEh    Address region 3 (bits 23-16)
 CFh    Address region 3 (bits 15-12 and size)
 D0h    Address region 4 (bits 31-24)
 D1h    Address region 4 (bits 23-16)
 D2h    Address region 4 (bits 15-12 and size)
 D3h    Address region 5 (bits 31-24)
 D4h    Address region 5 (bits 23-16)
 D5h    Address region 5 (bits 15-12 and size)
 D6h    Address region 6 (bits 31-24)
 D7h    Address region 6 (bits 23-16)
 D8h    Address region 6 (bits 15-12 and size)
 D9h    Address region 7 (bits 31-24)
 DAh    Address region 7 (bits 23-16)
 DBh    Address region 7 (bits 15-12 and size)
 DCh    Region Control 0
 DDh    Region Control 1
 DEh    Region Control 2
 DFh    Region Control 3
 E0h    Region Control 4
 E1h    Region Control 5
 E2h    Region Control 6
 E3h    Region Control 7
 E8h    Configuration Control Register 4
 E9h    Configuration Control Register 5
 FEh R    Device Identification #0
    CPU device ID
 FFh R    Device Identification #1
    bits 3-0: revision
    bits 7-4: stepping
Note:    accesses to indices other than 20h,C0h-CFh, or F0h-FFh generate
      external I/O cycles
SeeAlso: #P013,#P017
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes:    this chip uses a chip ID of 01
    the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P025,#P276,#P277)
0023  RW  chip set data

(Table P278)
Values for Intel 82351/82359 chip ID:
 01h    82359 DRAM controller, general registers
 02h    82351 EISA local I/O support
 A1h    82359 DRAM controller, EMS registers
 FFh    no chip accessible (default)
SeeAlso: #P025,#P276,#P277

(Table P025)
Values for 82359 DRAM controller general register index:
 00h    DRAM bank 0 type
    bit 7    unknown
    bit 6-4    000 DRAM in bank 0 (standard)
        001 bank 1
        010 bank 2
        011 bank 3
        100 banks 0,1
        101 banks 2,3
        110 banks 0,1,2,3
        111 empty (standard for 1,2,3)
    bit 3-2    unknown
    bit 1-0    00 64K chips used
        01 256K
        10 1M
        11 4M
 01h    DRAM bank 1 type
 02h    DRAM bank 2 type
 03h    DRAM bank 3 type
 04h    DRAM speed detection/selection
 05h    DRAM interleave control
 06h    RAS line mode
 07h    cache-enable selection
 08h    mode register A (DRAM, cache)
 09h    mode register B (cache, burst modes, BIOS size)
 0Ah    mode register C (concurrency control, burst/cycle speed)
 10h    host timing
 11h    host-system delay timing
 12h    system timing
 13h    DRAM row precharge time
 14h    DRAM row timing
 15h    DRAM column timing
 16h    CAS pulse width
 17h    CAS-to-MDS delay
 21h    chip ID register -- selects which chip responds on these ports
    (see #P278)
 28h-2Ch    parity-error trap address
 30h    page hit cycle length (read)
 31h    page miss cycle length (read)
 32h    row miss cycle length (read)
 33h    page hit cycle length (write)
 34h    page miss cycle length (write)
 35h    row miss cycle length (write)
 40h    memory enable 00000h-7FFFFh
 41h    memory enable 80000h-9FFFFh
 42h    memory enable A0000h-AFFFFh
 43h    memory enable B0000h-BFFFFh
 44h    memory enable C0000h-CFFFFh
 45h    memory enable D0000h-DFFFFh
 46h    memory enable E0000h-EFFFFh
 47h    memory enable F0000h-FFFFFh
 4Eh    remap 80000h-FFFFFh to extended memory
 50h-53h    programmable attribute map 1
 54h-57h    programmable attribute map 2
 58h-5Bh    programmable attribute map 3
 5Ch-5Fh    programmable attribute map 4
 83h-84h    split address register (address bits A31-A20)
 85h    cache control
 8Bh    system throttle
 8Ch    host throttle
 8Dh    host memory throttle watchdog
 8Eh    host system throttle
 8Fh    host system throttle watchdog
 90h    RAM enable
 91h    RAM disable
 92h-93h    elapsed-time registers
 94h-95h    host memory ownership request
 96h-97h    system memory ownership request
 98h-99h    host memory ownership
 9Ah-9Bh    system bus ownership
 9Ch-9Dh    host system bus request
 9Eh-9Fh    memory ownership transfer
SeeAlso: #P276,#P277

(Table P276)
Values for Intel 82359 DRAM controller EMS register index:
 00h    EMS cotnrol
 21h    chip ID register -- selects which chip responds on these ports
    (see #P278)
 80h-8Fh    EMS page registers, pages 0-7
SeeAlso: #P025,#P277

(Table P277)
Values for Intel 82351 EISA Local I/O register index:
 21h    chip ID register -- selects which chip responds on these ports
    (see #P278)
 C0h    peripheral enable register A
 C1h    peripheral enable register B
 C2h    parallel configuration register
 C3h    serial configuration register A
 C4h    floppy disk controller configuration register
 C5h    serial configuration register B
 C6h    COM3 port address (low)
 C7h    COM3 port address (high)
 C8h    COM4 port address (low)
 C9h    COM4 port address (high)
 D0h-D3h    general chip select lines 0-3 (mask registers)
 D4h-D7h    general chip select line addresses 0-3 (low bytes)
 D8h-DBh    general chip select line addresses 0-3 (high bytes)
 DCh    extended CMOS RAM page port address (low)
 DDh    extended CMOS RAM page port address (high)
 DFh    extended CMOS RAM access select address (high byte)
 E8h-EBh    EISA ID configuration registers (reflect at PORT 0C80h)
SeeAlso: #P025,#P276
----------P00220023--------------------------
PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P026)

(Table P026)
Values for Etec Cheetah ET6000 chip set register index:
 10h    system configuration register (see #P027)
 11h    cache configuration & non-cacheable block size register (see #P028)
 12h    non-cacheable block address register
    bit 7-1    non-cacheable address, A25-A19
    bit 0    reserved
 13h    DRAM bank & type configuration register (see #P029)
 14h    DRAM configuration register (see #P030)
 15h    shadow RAM configuration register (see #P031)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)    Description    (Table P027)
 7-6    00 turbo/non-turbo
    01 local device supported
    10 suspend mode
    11 illegal
 5    reserved
 4    refresh selection
    0 = AT type refresh
    1 = concurrent refresh
 3    slow refresh  95mSec enabled
 2    fast reset delay
    0 = do not use delay
    1 = wait for 2mSec delay
 1    wait for HALT after KBDRST
 0    RAM at A0000-BFFFF
    0 = AT bus cycle
    1 = local bus cycle
SeeAlso: #P026

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)    Description    (Table P028)
 7-5    000 disabled
    001 512K
    010 1M
    011 2M
    100 4M
    101 8M
    110 16M
    111 32M
 4    DRAM banks
    0 = 2-bank DRAM
    1 = 4-bank DRAM
 3-0    reserved
SeeAlso: #P026

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)    Description    (Table P029)
 7-6    bank 3 DRAM type
    00 none
    01 256K
    10 1M
    11 4M
 5-4    bank 2 DRAM type
 3-2    bank 1 DRAM type
 1-0    bank 0 DRAM type
SeeAlso: #P026

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)    Description    (Table P030)
 7    on-board memory range 15M to 16M disabled
 6    on-board memory range 512K-640K disabled
 5    ROM chip select at C0000-DFFFF enabled
 4    RAS to CAS time
    0 = 1 SYSCLCK,    not for R0WS
    1 = 2 SYSCLCK
 3    RAS precharge time
    0 = 1.5 SYSCLCK
    1 = 2.5 SYSCLCK
 2-1    read cycle wait state
    00 = 0 wait state
    01 = 1 ws
    10 = 2 ws
    11 = 3 ws
 0    write cycle wait state
    0 = 0 ws
    1 = 1 ws
SeeAlso: #P026

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)    Description    (Table P031)
 7    shadow at C0000-FFFFF
    0 = non-cacheable
    1 = cacheable and cache-write-proteced
 6    access ROM/RAM at F0000-FFFFF
    0 = read from ROM, write to RAM
    1 = read from shadow, write is protected
 5    access ROM/RAM at E0000-EFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow E0000-EFFFF enabled
 4    RAM at E0000-EFFFF is read-only
 3    access ROM/RAM at D0000-DFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow D0000-DFFFF enabled
 2    RAM at D0000-DFFFF is read-only
 1    access ROM/RAM at C0000-CFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow C0000-CFFFF enabled
 0    RAM at C0000-CFFFF is read-only
SeeAlso: #P026
----------P00220023--------------------------
PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data

(Table P032)
Values for HP Hornet chipset register index:
 1Eh    buzzer volume/clock oscillator speed
    bit 7-6: buzzer volume
    bit 5-4: system oscillator speed
        00: 10.738636MHz
        01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
        10: 21.477272MHz
        11: 31.673550MHz
 21h    display timing???
 23h    LCD contrast (see INT15h AH=62h)
    valid values: 00h-1fh (1fh is the darkest)
 51h    power adapter status
    bit 7-1: ???
    bit 0: power adapter status(0=inactive/1=active)
 52h    nicad charge status
    bit 7-3: ???
    bit 2: battery charging status(0=???/1=slow charge)
    bit 1-0: ???
 53h    nicad charge status
    bit 7-1: ???
    bit 0: battery charging status(0=???/1=fast charge)
 80h    memory wait for internal ROM
    valid values: 00h-07h
 81h    memory wait for internal RAM
    valid values: 00h-03h
 82h    memory wait for external RAM
    valid values: 00h-0fh
 87h    battery status???
----------P00220024--------------------------
PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data
----------P00220025--------------------------
PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)

0022  -W  CPU write mode register
0023  R-  configuration status register
        bit 7: 82360 configuration is open
0024  -W  82360 configuration index
0025  RW  82360 configuration data

Bitfields for Intel 82360SL CPU write mode register:
Bit(s)    Description    (Table P033)
 0    unlock configuration space
 1    enable selected unit
 3-2    unit
    00 memory configuration
    01 cache
    10 internal bus
    11 external bus
----------P0022002B--------------------------
PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx
Note:    initialisation in POST will disable these addresses, only a hard
      reset will enable them again.

0022w RW  82335 MCR memory configuration register (if LOCK=0) (see #P034)
0024w RW  82335 RC1 roll compare register (if LOCK=0) (see #P035)
0026w RW  82335 RC2 roll compare register (if LOCK=0) (see #P035)
0028w RW  82335 CC0 address range compare register (if LOCK=0) (see #P036)
002Aw RW  82335 CC1 address range compare register (if LOCK=0) (see #P036)

Bitfields for 82335 MCR memory configuration register:
Bit(s)    Description    (Table P034)
 15-12    reserved
 11    "VRO"    video read only (0=r/w, 1=r/o)
 10    "EN#"
    0=enable video RAM accesses (A0000h-8FFFFh)
    1=disable accesses
 9    "ENADP#"
    0=enable adapter ROM accesses (C0000h-8FFFFh)
    1=disable adapter ROM accesses, shadow enabled
 8    "ROMSIZE" 0=256KB ROM, 1=512KB ROM
 7-6    "INTERL" memory interleaving
    00 = 1 memory bank installed (no interleave)
    01 = 2 memory banks installed
    10 = 3 memory banks installed
    11 = 4 memory banks installed
 5    reserved
 4    "DSIZE"     0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
 3    "S640"     base memory size is 0=512KB, 1=640KB
 2-1    reserved
 0    "ROMEN#" ROM enable
    0 enable BIOS ROM accesses (E0000h-FFFFFh)
    1 disable BIOS ROM accesses, enable shadow
Note:    One of the remaining reserved bits is the LOCK bit, which will be set
      during power on, disabling access to the 82335s registers.

Bitfields for 82335 roll compare register:
Bit(s)    Description    (Table P035)
 15-9    selects address range to be remapped (C23-C17)
 8    reserved
 7-1    selects address bits to be included in re-mapping comparision (M23-M17)
 0    "EN" enables roll address mapping

Bitfields for 82335 address range compare register:
Bit(s)    Description    (Table P036)
 15-11    specifies top of address range (C23-C19)
 10-8    reserved
 7-3    selects address bits to be included in address range comparision
      (M23-M19)
 2-1    reserved
 0    "EN" enable address range comparision
----------P00240028--------------------------
PORT 0024-0028 - HEADLAND HTK340 SHASTA 386/486 CHIPSET

0024  Rw  data port
0028  ?W  index port to chipset registers (see #P037,#P038)

(Table P037)
Values for Headland HT321 register index:
 00h R    chip/revision,read-only
      bit7-4: reserved (=0)
      bit3-0: chip revision, 0=A, 1=B, 3=D
 01h RW system clocking (default=00h)
      bit7-4: reserved (=0)
      bit3-0: ISA speed set
 02h RW system parameters (default=00h) (see #P039)
 04h RW co-processor (default=00h)
      bit7-3: reserved (=0)
      bit2=1: soft-NPU reset blocked (386 only)
      bit1=1: weitek installed
      bit0=1: 387 installed
 06h RW DMA (default=00h) (see #P040)
 07h RW EPROM (default=00h) (see #P041)
 08h RW I/O and memory map holes (default=00h)
      bit7-4: reserved (=0)
      bit3    : 0/1 I/O map hole-A
      bit2    : reserved (=0)
      bit1    : 0/1 memory map hole-B
      bit0    : reserved (=0)
 10h RW hole-A low address (default=00h)
 11h RW hole-A high address (default=00h)
 19h RW mem hole-B start address, lower (default=00h)
 1Ah RW mem hole-B start address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B start
 1Ch RW mem hole-B end address, lower (default=00h)
 1Dh RW mem hole-B end address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B end
SeeAlso: #P038

(Table P038)
Values for Headland HT342 register index:
 20h R    identifier port read
      bit7-4: DRAM controller identifier (0010b)
      bit3-0: revision number (0=A)
 21h R    feature port read    (default=00h)
 24h RW DRAM options port #1 (default=00h)
      bit7    : 0/1 staggered refresh
      bit6    : refresh type
      bit5    : 0/1 DRAM paging
      bit4-2: CAS interleave
      bit1-0: banks
 25h    DRAM options port #2 (default=00h)
      bit7-6: DRAM bank 1 type
      bit5-4: DRAM bank 2 type
      bit3-2: DRAM bank 1?? type
      bit1-0: DRAM bank 0 type
 26h RW DRAM options port #3 (default=FFh) (see #P042)
 27h RW DRAM options port #4 (default=FFh) (see #P043)
 28h RW data transfer control port (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7    : initiate transfer
      bit6    : read/write transfer
      bit5-4: reserved
      bit3-0: transfer/destination
 29h RW RAM address register (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-5: reserved
      bit4-0: RAM address registers contents
 2Ah RW data transfer port   (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-6: reserved
      bit5    : EMS translation
      bit4    : reserved
      bit3    : 0/1 cacheing
      bit2    : 0/1 write
      bit1    : 0/1 read
      bit0    : 0/1 shadow
 2Bh RW other options          (default=00h) (see #P044)
 2Dh RW DRAM options port #5 (default=03h)
      bit7-5: reserved
      bit4    : 0/1 10µs RAS timeout
      bit3-2: BUS speed
      bit1-0: BUS recovery for DRAM cycles
           00b=0: 4-1-1-1    10b=0.5
           01b=1: 4-2-2-2    11b=1??
 82h    read transfer
 C2h    write transfer
SeeAlso: #P037

Bitfields for Headland HT321 register 02h (system parameters):
Bit(s)    Description    (Table P039)
 7-6    IO recovery time (rev. D+)
 5    parity override
 4-3    cycle-width
 2    0/1 PORT 0092h functionality
 1    IO decode
 0    0/1 posted backplane MEMWN cycles
SeeAlso: #P037

Bitfields for Headland HT321 register 06h (DMA control):
Bit(s)    Description    (Table P040)
 7    reserved (=0)
 6    1/0 IOCHRDY during master cycle (rev. C+)
 5    0/1 fast sample DMA
 4-3    DMA waitstate 00b=3 .. 11b=0
 2    0/1 DMA flow-through mode
 1    0/1 extended DMA page register
 0    DMA clock
SeeAlso: #P037

Bitfields for Headland HT321 register 07h (EPROM control):
Bit(s)    Description    (Table P041)
 7-6    reserved (=0)
 5    0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
 4    0/1 ROMEN for EPROM writes (rev. C+)
 3    0/1 middle BIOS region of 64KB space below 16MB
 2    ROM-size (0=64KB, 1=128KB)
 1    V-BIOS-add (0=separate, 1=same device)
 0    ROM-access time (0=250ns, 1=125ns)
SeeAlso: #P037

Bitfields for Headland HT342 register 26h (DRAM CAS control):
Bit(s)    Description    (Table P042)
 7    CAS hold on RAS (CAS before RAS refresh)
 6    CAS precharge
 5    CAS burst delay
 4    CAS delay (writes)
 3    CAS delay (reads)
 2    CAS active time (writes)
 1-0    CAS active time (reads)
SeeAlso: #P038,#P043

Bitfields for Headland HT342 register 27h (DRAM RAS control):
Bit(s)    Description    (Table P043)
 7    RAS delay
 6-5    RAS active (writes)
 4-2    RAS active (reads)
 1-0    RAS precharge
SeeAlso: #P038,#P042

Bitfields for Headland HT342 register 2Bh (other options):
Bit(s)    Description    (Table P044)
 7    reserved
 6    0/1 middle BIOS
 5    0/1 data pipeline
 4    0/1 data pipeline
 3    IO-decode
 2    reserved
 1    16bit DMA bridge
 0    0/1 write buffering
SeeAlso: #P038
----------P00260027--------------------------
PORT 0026-0027 - INTEL 82347 POWER MANAGEMENT PERIPHERAL
SeeAlso: PORT 0178h-0179h

0026  -W  index for data port (see #P279)
0027  RW  power management data

(Table P279)
Values for Intel 82437 Power Management Peripheral register index:
 C0h    suspend/wakeup status, system state
 C1h    power supply and activity status, general-purpose output/control
 C2h    control bits
 C3h    activity mask
 C4h    NMI mask
 C5h    I/O range for activity monitor
 C6h    power output control bits, ON state
 C7h    power output control bits, Doze state
 C8h    power output control bits, Sleep state
 C9h    power output control bits, Suspend state
 CAh    power control bits polarity control
 CBh    current output bits
 CCh    Doze timeout
 CDh    Sleep timeout
 CEh    Suspend timeout
 CFh    LCD display power timeout
 D0h    EL display power timeout
----------P002E002F--------------------------
PORT 002E-002F - DELL ENHANCED PARALLEL PORT
SeeAlso: PORT 015Ch,PORT 026Eh,PORT 0398h

002E  -W  index for data port (see #P045)
002F  RW  EPP command data

(Table P045)
Values for Dell Enhanced Parallel Port register index:
 00h    bit 0: ???
 02h    bit 7: port in bidirectional mode
 04h    bits 0 and 2: ECP/EPP mode control
----------P002E002F--------------------------
PORT 002E-002F - Intel "Nonolet" Motherboard - POWER MANAGEMENT

002E  ?W  index for data port
002F  ?W  data port

code sequence posted in fido7.nice.sources by Konstantin Mohorea:
     out 2Eh,0Ch
     out 2Fh,75h
     out 2Eh,11h
     out 2Fh,00h
     out 2Eh,0Dh
     out 2Fh,A0h
----------P0038003F--------------------------
PORT 0038-003F - PC radio by CoZet Info Systems
Notes:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
    All of these addresses show a readout of FF in initial state.
    Once started, all of the addresses show     FB, whatever might happen.
----------P0040005F--------------------------
PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)
Note:    XT & AT use ports 40h-43h; PS/2 uses ports 40h, 42h-44h, and 47h
SeeAlso: PORT 0044h,PORT 0048h

0040  RW  PIT  counter 0, counter divisor          (XT, AT, PS/2)
0041  RW  PIT  counter 1, RAM refresh counter    (XT, AT)
            don't set below 3 on PCs (default 12h)
0042  RW  PIT  counter 2, cassette & speaker    (XT, AT, PS/2)
    During normal operation mode (8253) 40h-42h set the counter values on
    write and get the current counter value on read. In 16bit modes two
    consequtive writes/reads must be issued, first with the low byte,
    followed by the high byte. In 8254 read back modes, all selected
    counters and status are latched and must be read out completely
    before normal operation is valid again.     Each counter switches back
    to normal operation after read out.  In 'get status and counter'
    mode the first byte read is the status, followed by one or two
    counter values. (see #P046)
0043  RW  PIT  mode port, control word register for counters 0-2 (see #P047)
    Once a control word has been written (43h), it must be followed
    immediately by performing the corresponding action to the counter
    registers (40h-42h), else the system may hang!!

Bitfields for 8254 PIT counter status byte:
Bit(s)    Description    (Table P046)
 7    PIN status of OUTx Pins (1=high, 0=low)
 6    counter start value loaded
    =0: yes, so counter latch is valid to be read
    =1: no, wait for counter latch to be set (may last a while)
5-0    counter mode, same as bit5-0 at 43h
SeeAlso: #P047

Bitfields for 8253/8254 PIT mode control word:
Bit(s)    Description    (Table P047)
 7-6    counter select
    00  counter 0 select
    01  counter 1 select      (not PS/2)
    10  counter 2 select
    11  (8253) reserved
        (8254) read back counter (see #P046)
---if counter select---
 5-4    counter access
    00  counter latch command
        BUG:    Intel Neptune/Mercury Chipset 8237IB (SIO) needs a
              short delay after issueing this command, else the
              MSB may be outdated concerning the LSB, resulting
              in large measuring errors.
            Workaround: Check for this condition by comparing
              results with last results and don't use errornous
              results.
    01  read/write counter bits 0-7 only
    10  read/write counter bits 8-15 only
    11  read/write counter bits 0-7 first, then 8-15
 3-1    counter mode
    000 mode 0 select - zero detection interrupt
    001 mode 1 select - programmable one shot
    x10 mode 2 select - rate generator
    x11 mode 3 select - square wave generator
        divisor factor 3 not allowed!
    100 mode 4 select - software triggered strobe
    101 mode 5 select - hardware triggered strobe
 0    counting style
    0  binary counter 16 bits
    1  BCD counter (4 decades)
---if read back---
 5-4    what to read
    00 reserved
    01 counter status
    10 counter value
    11 counter status and value
 3    select counter 2
 2    select counter 1
 1    select counter 0
 0    reserved (0)
Note:    after issuing a read back 'get status' command, any new read back
      command is ignored until the status is read from all selected
      counters.
----------P00430047--------------------------
PORT 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2
SeeAlso: PORT 0040h,PORT 0048h

0044  RW  PIT  counter 3 (PS/2)
        used as fail-safe timer. generates an NMI on time out.
        for user generated NMI see at 0462.
0047  -W  PIT  control word register counter 3 (PS/2, EISA)
    bit 7-6 = 00  counter 3 select
        = 01  reserved
        = 10  reserved
        = 11  reserved
    bit 5-4 = 00  counter latch command counter 3
        = 01  read/write counter bits 0-7 only
        = 1x  reserved
    bit 3-0 = 00
---------------------------------------------
PORT 0048-004B - EISA - PROGRAMMABLE INTERVAL TIMER 2
SeeAlso: PORT 0040h,PORT 0044h

0048  RW  EISA PIT2 counter 3 (Watchdog Timer)
0049  ??  EISA 8254 timer 2, not used (counter 4)
004A  RW  EISA PIT2 counter 5 (CPU speed control)
004B  -W  EISA PIT2 control word
----------P0060006F--------------------------
PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)
Note:    XT uses ports 60h-63h, AT uses ports 60h-64h

0060  RW  KB controller data port or keyboard input buffer (ISA, EISA)
        should only be read from after status port bit0 = 1
        should only be written to if status port bit1 = 0
0060  R-  KeyBoard or KB controller data output buffer (via PPI on XT)
        PC: input from port A of 8255, if bit7 in 61h set (see #P063)
        get scancodes, special codes (in PC: with bit7 in 61h cleared)
          (see #P057)

0061  R-  KB controller port B control register (ISA, EISA)
        system control port for compatibility with 8255 (see #P060)
0061  -W  KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
        system control port for compatibility with 8255 (see #P059)
0061  -W  PPI Programmable Peripheral Interface 8255 (XT only)
        system control port (see #P061)
0062  RW  PPI (XT only) data port C (see #P062)
0063  RW  PPI (XT only) command mode register (see #P064)

0064  R-  keyboard controller read status (see #P065,#P066,#P067)
0064  -W  keyboard controller input buffer (ISA, EISA) (see #P068)

0064  -W  (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
      stored in CMOS RAM that PPI should report for compatibility
0065  -W  (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
      stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
      compatibility

0065  R-  communications port (Olivetti M24)

0068  -W  (HP-Vectra) control buffer (HP commands) (see #P069)
0069  R-  (HP-Vectra) SVC (keyboard request SerViCe port)
006A  -W  (HP-Vectra) Acknowledge (clear processing, done)
006C-006F    HP-HIL    (Human Interface Link = async. serial inputs 0-7)

Bitfields for AT keyboard controller input port:
Bit(s)    Description    (Table P048)
 7    keyboard enabled
 6    =0  CGA, else MDA
 5    =0  manufacturing jumper installed
 4    =0  system RAM 512K, else 640K
 3-0    reserved
SeeAlso: #P049,#P051

Bitfields for AT keyboard controller input port (Compaq):
Bit(s)    Description    (Table P049)
 7    security lock is unlocked
 6    =0  Compaq dual-scan display, 1=non-Compaq display
 5    system board dip switch 5 is OFF
 4    =0  auto speed selected, 1=high speed selected
 3    =0  slow (4MHz), 1 = fast (8MHz)
 2    no math coprocessor installed
 1-0    reserved
SeeAlso: #P050

Bitfields for AT keyboard controller output port:
Bit(s)    Description    (Table P050)
 7    keyboard data output
 6    keyboard clock output
 5    input buffer NOT full
 4    output buffer NOT empty
 3    reserved (see note)
 2    reserved (see note)
 1    gate A20
 0    system reset
Note:    bits 2 and 3 are the turbo speed switch or password lock on
      Award/AMI/Phoenix BIOSes.  These bits make use of nonstandard
      keyboard controller BIOS functionality to manipulate
        pin 23 (8041 port 22) as turbo switch for AWARD
        pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P048,#P051

Bitfields for HP Vectra keyboard controller output port:
Bit(s)    Description    (Table P051)
 7-5    reserved
 4    output buffer full (OBF) interrupt
 3    HP SVC interrupt
 2    HP-HIL controller AutoPoll
 1    A20 gate
 0    system reset
SeeAlso: #P050,#P052

Bitfields for HP Vectra command byte:
Bit(s)    Description    (Table P052)
 7    reserved (0)
 6    scancode conversion mode (1 = PC/XT, 0 = PC/AT)
 5    unused
 4    disable keyboard (unless bit 3 set)
 3    override keyboard disable
 2    System Flag (may be read from PORT 0060h)
 1    reserved
 0    OBF interrupt enable
SeeAlso: #P051

(Table P053)
Values for keyboard commands (data also goes to PORT 0060h):
Value    Count    Description
 EDh    double    set/reset mode indicators Caps Num Scrl
        bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
        all other bits must be zero.
 EEh    sngl    diagnostic echo. returns EEh.
 EFh    sngl    NOP (No OPeration). reserved for future use
 EF+26h    double    [Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
        keyboard must be disabled before this and has to
        be enabled after finished.
 F0h    double    get/set scan code set
        00h get current set
        01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
        02h scancode set 2 (ATs, PS/2, default)
        03h scancode set 3
 F2h    sngl    read keyboard ID (read two ID bytes)
        AT keyboards returns FA (ACK)
        MF2 returns AB 41 (translation) or
                AB 83 (pass through)
 F3h    double    set typematic rate/delay
        format of the second byte:
        bit7=0 : reserved
        bit6-5 : typemativ delay
             00b=250ms     10b= 750ms
             01b=500ms     11b=1000ms
        bit4-0 : typematic rate (see #P058)
 F4h    sngl    enable keyboard
 F5h    sngl    disable keyboard. set default parameters (no keyboard scanning)
 F6h    sngl    set default parameters
 F7h    sngl    [MCA] set all keys to typematic (scancode set 3)
 F8h    sngl    [MCA] set all keys to make/release
 F9h    sngl    [MCA] set all keys to make only
 FAh    sngl    [MCA] set all keys to typematic/make/release
 FBh    sngl    [MCA] set al keys to typematic
 FCh    double    [MCA] set specific key to make/release
 FDh    double    [MCA] set specific key to make only
 FEh    sngl    resend last scancode
 FFh    sngl    perform internal power-on reset function
Note:    each command is acknowledged by FAh (ACK), if not mentioned otherwise.
      See PORT 0060h-R for details.
SeeAlso: #P054

(Table P054)
Values for Mouse functions (for PS/2-like pointing devices):
Value    Count    Description
 E6h    sngl    set mouse scaling to 1:1
 E7h    sngl    set mouse scaling to 2:1
 E8h    double    set mouse resolution
        (00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
 E9h    sngl    get mouse information
        read two status bytes:
          byte 0: flags (see #P055)
          byte 1: resolution
 EAh    sngl    set mouse to stream mode (mouse sends data on any changes)
 EBh    sngl    get mouse data (from mouse to controller) (see #P056)
        on reading, each data packet consists of 8 bytes:
 ECh    sngl    reset mouse wrap mode (to normal mode)
 EEh    sngl    set wrap mode
 F0h    sngl    set remote mode (instead of stream mode), mouse sends data
          only on issueing command EBh.
 F2h    sngl    read mouse ID (read one, two?? ID bytes)
        00h=mouse
 F3h    double    set mouse sample rate in reports per second
        0Ah=10/s       50h= 80/s
        14h=20/s       64h=100/s
        28h=40/s       C8h=200/s
        3Ch=60/s
 F4h    sngl    enable mouse (in stream mode)
 F5h    sngl    disable mouse (in steam mode), set default parameters
 F6h    sngl    reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
          disabled
 FEh    sngl    resend last mouse data (8 bytes, see EBh)
 FFh    sngl    reset mouse
Notes:     must issue command D4h to PORT 0064h first to access mouse functions
     all commands except ECh and FFh are acknowledged by FAh (ACK) or
       FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P053

Bitfields for mouse status byte 0:
Bit(s)    Description    (Table P055)
 7    unused
 6    remote rather than stream mode
 5    mouse enabled
 4    scaling set to 2:1
 3    unused
 2    left button pressed
 1    unused
 0    right button pressed
SeeAlso: #P054,#P056

Format of mouse data packet:
Offset    Size    Description    (Table P056)
 00h    BYTE    status
        bit7    : y-data overrun
        bit6    : x-data overrun
        bit5    : y-data negative
        bit4    : x-data negative
        bit3-2=0: reserved
        bit1    : right button pressed
        bit0    : left button pressed
 01h    BYTE    reserved
 02h    BYTE    x-data
 03h    BYTE    reserved
 04h    BYTE    y-data
 05h    BYTE    reserved
 06h    BYTE    z-data (0)
 07h    BYTE    reserved
SeeAlso: #P054,#P055

(Table P057)
Values for keyboard special codes:
 00h    (MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
 00h    (mouse) ID
 AAh    BAT completion code (sent after errorfree Basic Assurance Test)
 ABh    first byte of general MF2 keyboard ID
 EEh    Echo command return
 FAh    Acknowledge (all general commands except Resend and Echo)
 FAh    (mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
 FCh    (MF2) BAT Failure Code (error in second half of the power on self test)
 FDh    (AT-keyboard) BAT Failure Code (error in the second half of the
      power-on self test)
 FEh    Resend: CPU to controller should resend last keyboard-command
 FEh    (mouse) CPU to controller should resend last mouse-command
 FFh    (MF2 in codeset1) keydetection/overrun error
Note:    keyboard stops scanning and waits for next command after returning
      code FCh or FDh
SeeAlso: PORT 0060h-R

(Table P058)
Values for keyboard typematic rate:
 00000b=30.0   10000b=7.5
 00001b=26.7   10001b=6.7
 00010b=24.0   10010b=6.0
 00011b=21.8   10011b=5.5
 00100b=20.0   10100b=5.0
 00101b=18.5   10101b=4.6
 00110b=17.1   10110b=4.3
 00111b=16.0   10111b=4.0
 01000b=15.0   11000b=3.7
 01001b=13.3   11001b=3.3
 01010b=12.0   11010b=3.0
 01011b=10.9   11011b=2.7
 01100b=10.0   11100b=2.5
 01101b= 9.2   11101b=2.3
 01110b= 8.5   11110b=2.1
 01111b= 8.0   11111b=2.0
SeeAlso: #P053

Bitfields for KB controller port B (system control port) [output]:
Bit(s)    Description    (Table P059)
 7    pulse to 1 for IRQ1 reset (PC,XT)
 6-4    reserved
 3    I/O channel parity check disable
 2    RAM parity check disable
 1    speaker data enable
 0    timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P060

Bitfields for KB controller port B control register (system control port) [input]:
Bit(s)    Description    (Table P060)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    mirrors timer 2 output condition
 4    toggles with each refresh request
 3    NMI I/O channel check status
 2    NMI parity check status
 1    speaker data status
 0    timer 2 clock gate to speaker status
SeeAlso: PORT 0061h-R,#P059

Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s)    Description    (Table P061)
 7    clear keyboard (only pulse, normally kept at 0)
 6    =0  hold keyboard clock low
 5    NMI I/O parity check disable
 4    NMI RAM parity check disable
 3    =0 read low nybble of switches S2
    =1 read high nybble of switches S2
 2    reserved, often used as turbo switch
    original PC: cassette motor off
 1    speaker data enable
 0    timer 2 gate to speaker enable
Note:    bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P0051,#P062,#P063,#P064

Bitfields for PPI (XT only) data port C:
Bit(s)    Description    (Table P062)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    timer 2 channel out
 4    reserved
    original PC: cassette data input
---
 3    system board RAM size type 1
 2    system board RAM size type 2
 1    coprocessor installed
 0    loop in POST
---
 3-0    DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P061,#P063,#P064

Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s)    Description    (Table P063)
 7-6    number of disk drives
    00  1 diskette drive
    01  2 diskette drives
    10  3 diskette drives
    11  4 diskette drives
 5-4    initial video
    00  reserved (video adapter has on-board BIOS)
    01  40*25 color (mono mode)
    10  80*25 color (mono mode)
    11  MDA 80*25
 3-2    memory size (using 256K chips)
    00  256K
    01  512K
    10  576K
    11  640K
 3-2    memory size (using 64K chips)
    00  64K
    01  128K
    10  192K
    11  256K
 3-2    memory size (original PC)
    00  16K
    01  32K
    10  48K
    11  64K
 1-0    reserved
 1    NPU (math coprocessor) present
 0    boot from floppy
SeeAlso: #P062,#P064,PORT 0060h-R

Bitfields for PPI (8255) command mode register:
Bit(s)    Description    (Table P064)
 7    activation function (0 = bit set/reset, 1 = mode set function)
 6,5    port A mode: 00 = mode0, 01 = mode1, 1x = mode2
 4    port A direction: 0 = output, 1 = input
 3    port C bits 7-4 direction: 0 = output, 1 = input
 2    port B mode: 0 = mode0, 1 = mode1
 1    port B direction: 0 = output, 1 = input
 0    port C bits 3-0 direction: 0 = output, 1 = input
Note:    Attention: Never write anything other than 99h to this port
      (better: never write anything to this port, only during BIOS
      init), as other values may connect multiple output drivers
      and will cause hardware damage in PC/XTs!  By setting command
      word to 99h, PPI will be set in input/output modes as it is
      necessary to support the commonly known IO-ports 60, 61, 62
      as desired.
SeeAlso: #P061,#P062,#P063

Bitfields for keyboard controller read status (ISA, EISA):
Bit(s)    Description    (Table P065)
 7    parity error on transmission from keyboard
 6    receive timeout
 5    transmit timeout
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (input 60/64 has data for 8042)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: PORT 0064h-R,#P066,#P067,#P068

Bitfields for keyboard controller read status (MCA):
Bit(s)    Description    (Table P066)
 7    parity error on transmission from keyboard
 6    general timeout
 5    mouse output buffer full
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: #P065,#P067,#P068

Bitfields for keyboard controller read status (Compaq):
Bit(s)    Description    (Table P067)
 7    parity error detected (11-bit format only). If an
      error is detected, a Resend command is sent to the
      keyboard once only, as an attempt to recover.
 6    receive timeout. transmission didn't finish in 2mS.
 5    transmission timeout error
    bit 5,6,7  cause
        1 0 0  No clock
        1 1 0  Clock OK, no response
        1 0 1  Clock OK, parity error
 4    =0 security lock engaged
 3    =1 data in OUTPUT register is command
    =0 data in OUTPUT register is data
 2    system flag status: 0=power up or reset     1=soft reset
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (PORT 0060h has data for system)
    bit is cleared after read access
SeeAlso: #P065,#P066,#P068

(Table P068)
Values for keyboard controller commands (data goes to PORT 0060h):
Value        Description
 20h    read    read byte zero of internal RAM, this is the last KB command
          sent to the 8041/8042
    Compaq    put current command byte on PORT 0060h (see #P070,#P071)
 21-3F    read    reads the byte specified in the lower 5 bits of the command
          in the 804x's internal RAM
 60-7F    double    writes the data byte to the address specified in the 5 lower
          bits of the command
 60h    Compaq    Load new command (60 to [64], command to [60]) (see #P071)
        (also general AT-class machines)
 A0h    AMI    get ASCIZ copyright message on PORT 0060h
 A1h    AMI    get controller version byte on PORT 0060h
 A1h    Compaq    unknown speedfunction ??
 A2h    Compaq    unknown speedfunction ??
 A2h    AMI    set keyboard controller pins 22 and 23 low
 A3h    Compaq    Enable system speed control
 A3h    AMI    set keyboard controller pins 22 and 23 high
 A4h    MCA    check if password installed
 A4h    Compaq    Toggle speed
 A4h    AMI    set internal system speed flag to low
 A5h    MCA    load password
 A5h    AMI    set internal system speed flag to high
 A5h    Compaq    Special read. the 8042 places the real values of port 2
          except for bits 4 and 5 wich are given a new definition in
          the output buffer. No output buffer full is generated.
            if bit 5 = 0, a 9-bit keyboard is in use
            if bit 5 = 1, an 11-bit keyboard is in use
            if bit 4 = 0, output-buff-full interrupt disabled
            if bit 4 = 1, output-buffer-full interrupt enabled
 A6h    MCA    check password
 A6h    AMI    get internal system speed flag on PORT 0060h
 A6h    Compaq    unknown speedfunction ??
 A7h    MCA    disable mouse port
 A7h    AMI    set internal flag indicating bad write cache
 A8h    MCA    enable mouse port
 A8h    AMI    set internal flag indicating good write cache
 A9h    MCA    test mouse port
 A9h    AMI    get internal flag indicating cache OK to 0060
 AAh    sngl    initiate self-test. will return 55h to data port if self-test
          successful, FCh if failed
 AAh    Compaq    initializes ports 1 and 2, disables the keyboard and clears
          the buffer pointers. It then places 55h in the output buffer.
 ABh    sngl    initiate interface test. result values:
        00h no error
        01h keyboard clock line stuck low
        02h keyboard clock line stuck high
        03h keyboard data line is stuck low
        04h keyboard data line stuck high
        05h (Compaq only) diagnostic feature
 ACh    read    diagnostic dump. the contents of the 804x RAM, output port,
          input port, status word are sent.
 ADh    sngl    disable keyboard (sets bit 4 of commmand byte)
 ADh    Vectra    HP Vectra diagnostic dump
 AEh    sngl    enable keyboard     (resets bit 4 of commmand byte)
 AFh    AWARD    Enhanced Command: read keyboard version
 B1h    AMI    set keyboard controller P11 line low
 B2h    AMI    set keyboard controller P12 line low
 B3h    AMI    set keyboard controller P13 line low
 B4h    AMI    set keyboard controller P22 line low
 B5h    AMI    set keyboard controller P23 line low
 B8h    AMI    set keyboard controller P10 line high
 B9h    AMI    set keyboard controller P11 line high
 BAh    AMI    set keyboard controller P12 line high
 BBh    AMI    set keyboard controller P13 line high
 BCh    AMI    set keyboard controller P22 line high
 BDh    AMI    set keyboard controller P23 line high
 C0h    read    read input port and place on PORT 0060h
        bit 7    keyboard NOT locked
        bit 6    =0 first video is CGA
            =1 first video is MDA
        bit 5    =0 factory testmode
            =1 normal
        bit 4    =0 256KB RAM, 1=512KB
        bit 5,3-0 are used in Intel chipset 386sx machines with
            AMI/Phoenix BIOSes for BIOS specific hardware settings
 C0h    Compaq    places status of input port in output buffer.  Use this
          command only when the output buffer is empty
 C1h    MCA    Enhanced Command: poll input port Low nibble
 C2h    MCA    Enhanced Command: poll input port High nibble
 C8h    AMI    unblock keyboard controller lines P22 and P23
 C9h    AMI    block keyboard controller lines P22 and P23
 CAh    AMI    read keyboard mode, return in 0060 bit 0
          (bit clear if ISA mode, set if PS/2 mode)
 CBh    AMI    set keyboard mode (write back mode byte returned by CAh,
          modifying only bit 0)
 D0h    read    read output port and place on PORT 0060h (see #P072)
 D0h    Compaq    places byte in output port in output buffer. Use this command
          only when the output buffer is empty
 D1h    double    write output port.  The next byte written to PORT 0060h will
          be written to the 804x output port; the original IBM AT and
          many compatibles use bit 1 of the output port to control
          the A20 gate.
        Important: bit 0 (system reset) should always be set here, as
              the system may hang constantly, use pulse output port
              (FEh) instead.
 D1h    Compaq    the system speed bits are not set by this command use
          commands A1-A6 (!) for speed functions.
 D2h    MCA    Enhanced Command: write keyboard output buffer
 D3h    MCA    Enhanced Command: write pointing device out.buf.
 D4h    MCA    write to mouse/pointing device instead of to keyboard; this
          controller command must precede every PORT 0060h command
          directed to the mouse, otherwise it will be sent to the
          keyboard
 D4h    AWARD    Enhanced Command: write to auxiliary device
 DDh    sngl    disable address line A20 (HP Vectra only???)
        default in Real Mode
 DFh    sngl    enable address line A20 (HP Vectra only???)
 E0h    read    read test inputs.
        bit0 = kbd clock, bit1 = kbd data
 Exxx    AWARD    Enhanced Command: active output port
 EDh    double    this is a two part command to control the state of the
          NumLock, CpasLock and ScrollLock LEDs
        The second byte contains the state to set LEDs.
            bit 7-3    reserved. should be set to 0.
            bit 2 = 0    Caps Lock LED off
            bit 1 = 0    Num Lock LED off
            bit 0 = 0    Scroll Lock LED off
 F0-FF    sngl    pulse output port low for 6 microseconds.
        bits 0-3 contain the mask for the bits to be pulsed.  A bit is
          pulsed if its mask bit is zero
        bit0=system reset. Don't set to zero. Pulse only!
Note:     keyboard controllers are widely different from each other.  You
       cannot generally exchange them between different machines.
     (Award) Derived from Award's Enhanced KB controller advertising sheet.
     (Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.

(Table P069)
Values for HP Vectra control buffer command code:
 00h-54h insert standard key make code into 8041 scancode buf
 55h-77h insert HP key make code into 8041 scancode buffer
 7Ah    pass through next data byte
 7Bh    set RAM Switch to 0
 7Ch    set RAM Switch to 1 (default)
 7Dh    set CRT Switch to 0
 7Eh    set CRT Switch to 1 (default)
 7Fh    reserved
 80h-D4h insert standard key break code into scancode buffer
 D5h-F7h insert HP key break code into scancode buffer
 F8h    enable AutoPoll
 F9h    disable AutoPoll
 FAh-FEh reserved
 FFh    keyboard overrun
SeeAlso: PORT 0068h-W

Bitfields for Compaq keyboard command byte:
Bit(s)    Description    (Table P070)
 7    reserved
 6    =1 convert KB codes to 8086 scan codes
 5    =0 use 11-bit codes, 1=use 8086 codes
 4    =0 enable keyboard, 1=disable keyboard
 3    ignore security lock state
 2    this bit goes into bit2 status reg.
 1    reserved (0)
 0    generate interrupt when output buffer full
SeeAlso: #P071

Bitfields for keyboard command byte (alternate description):
Bit(s)    Description    (Table P071)
 7    reserved (0)
 6    IBM PC compatibility mode
 5    IBM PC mode
    no parity, no stop bits, no translation
    (PS/2) force mouse clock low
 4    disable keyboard (clock)
 3    inhibit override
    (PS/2) reserved
 2    system flag
 1    reserved (0)
    (PS/2) enable mouse output buffer full interrupt
 0    enable output buffer full interrupt
SeeAlso: #P070,#P072

Bitfields for keyboard controller output port:
Bit(s)    Description    (Table P072)
 7    keyboard data (output)
 6    keyboard clock (output)
 5    input buffer empty
 4    output buffer empty
 3    undefined
 2    undefined
    used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
      configuration of turbo switch
 1    gate address A20
 0    system reset
Note:    bit 0 (system reset) should always be set when writing the output
      port, as the system may hang constantly; use pulse output port
      (command FEh) instead.
SeeAlso: #P071
----------P0065------------------------------
PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT
----------P0065------------------------------
PORT 0065 - ???

0065  RW  ???
        bit 2: A20 gate control (set = A20 enabled, clear = disabled)
----------P00660067--------------------------
PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES
----------P0066------------------------------
PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"
----------P0068------------------------------
PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL

Note:      on Micronics 386-25/386-33/486-25 motherboards, setting this port to
        00h enables full speed; setting it to C0h slows the system down by
        a factor corresponding to the value programmed into the EISA
        interval timer 2 at ports 004Ah and 004Bh
----------P0069------------------------------
PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"
----------P006B006F--------------------------
PORT 006B-006F - SSGA CONTROL REGISTERS

006B  ??  RAM enable/remap
006C  ??  undocumented
006D  ??  undocumented
006E  ??  undocumented
006F  ??  undocumented
----------P0070007F--------------------------
PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)
Note:    the real-time clock may be either a discrete MC146814, MC146818, or
      an emulation thereof built into the motherboard chipset

0070  -W  CMOS RAM index register port (ISA, EISA)
         bit 7    = 1  NMI disabled
            = 0  NMI enabled
         bit 6-0     CMOS RAM index (64 bytes, sometimes 128 bytes)

        any write to 0070 should be followed by an action to 0071
        or the RTC wil be left in an unknown state.

0071  RW  CMOS RAM data port (ISA, EISA) (see #P073)

(Table P073)
Values for Real-Time Clock register number (see also CMOS.LST):
 00h-0Dh clock registers
 0Eh    diagnostics status byte
 0Fh    shutdown status byte
 10h    diskette drive type for A: and B:
 11h    reserved / IBM fixed disk / setup options
 12h    fixed disk drive type for drive 0 and drive 1
 13h    reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
 14h    equipment byte
 15h    LSB of system base memory in Kb
 16h    MSB of system base memory in Kb
 17h    LSB of total extended memory in Kb
 18h    MSB of total extended memory in Kb
 19h    drive C extension byte
 1Ah    drive D extension byte
 1Bh-2Dh reserved
 20h-27h commonly used for first user-configurable drive type
 2Eh    CMOS MSB checksum over 10-2D
 2Fh    CMOS LSB checksum over 10-2D
 30h    LSB of extended memory found above 1Mb at POST
 31h    MSB of extended memory found above 1Mb at POST
 32h    date century in BCD
 33h    information flags
 34h-3Fh    reserved
 35h-3Ch commonly used for second user-configurable drive type
 3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
 42h-4Ch AMI 1990 Hyundai super-NB368S notebook
    ???
 54h-57h AMI 1990 Hyundai super-NB368S notebook
    ???
 5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
    ???
 60h-61h AMI 1990 Hyundai super-NB368S notebook
    ???
----------P0073------------------------------
PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0075h

0073  RW  ???
    bit 7: ???
    bit 6: disable ROM shadowing
    bit 5: ??? (related to IDE controller)
    bit 4: ???
    bit 3: ???
----------P00740076--------------------------
PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS
Note:    NVRAM may be 2K, 8K, or 16K
SeeAlso: PORT 0070h-007Fh,CMOS.LST

0074  -W  secondary CMOS RAM (IBM NVRAM) index, low byte
0075  -W  secondary CMOS RAM (IBM NVRAM) index, high (in bits 2-0)
0076  RW  secondary CMOS RAM (IBM NVRAM) data byte
----------P0075------------------------------
PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0073h,PORT 0078h"82378IB"

0075  R-  ???
      bits 3-2: external bus speed???
           00  50 MHz
           01  66 MHz
           10  60 MHz
           11  40 MHz
----------P0078------------------------------
PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE

0078  ?W  NMI enable/disable
        bit 7 = 0  disable & clear hard reset from HP-HIL controller
              = 1  enable hard reset from HP-HIL controller chip
        bit 6-0       reserved
----------P0078------------------------------
PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER
Notes:    the BIOS uses this port for certain fine timings; presumably it is
      independent of processor speed (it appears to decrement at 1 MHz)
    the address at which this port appears may be set via the 82378's
      PCI configuration space word at offset 0080h (see #0642), or the
      timer may be disabled entirely
SeeAlso: PORT 0075h

0078w -W  set count-down timer
0078w R-  get current count (timer stops when it reaches 0000h)
----------P0078007F--------------------------
PORT 0078-007F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Note:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show FBh, whatever might happen.
----------P007C007D--------------------------
PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)
Notes:    cascaded to first controller.
    used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h,INT 68"Vectra",INT 6E"Vectra"

007C  RW  HP-Vectra  PIC 3  see at 0020     PIC 1
007D  RW  HP-Vectra  PIC 3  see at 0021     PIC 1
----------P0080------------------------------
PORT 0080 - MANUFACTURING DIAGNOSTICS PORT
Note:    sometimes used for a POST hex display

0080  -W  Manufacturing Diagnostics port
0080  R-  ???

(Table P074)
Values for AMI BIOS diagnostics codes:
 00h    system boot completed, control passed to INT 19 bootstrap loader
 01h    register test
 02h    video initialization; NMIs disabled
 03h    power-on delay complete
 04h    pre-keyboard-test initializations complete
 05h    soft-reset/power-on setting determined
 06h    ROM enabled
 07h    ROM BIOS checksum test passed
 08h    keyboard BAT command issued
 09h    keyboard controller BAT result verified
 0Ah    keyboard controller command code issued
 0Bh    keyboard controller command byte written
 0Ch    keyboard controller pins 23/24 blocked and unblocked
 0Dh    keyboard controller NOP processing in progress
 0Eh    CMOS RAM shutdown register read/write test passed
 0Fh    CMOS RAM checksum calculation complete
 10h    CMOS RAM initialization complete
 11h    CMOS RAM status register initialized
 12h    DMA controllers 1/2 and interrupt controllers 1/2 disabled
 13h    video display disabled, port B initialized
 14h    chipset initialization, auto memory detection
 15h    8254 channel 2 test half complete
 16h    8254 channel 2 test completed
 17h    8254 channel 1 test completed
 18h    8254 channel 0 test completed
 19h    memory refresh started
 1Ah    memory refresh line is toggling
 1Bh    memory refresh test completed
 20h    base 64K memory test started
 21h    address line test passed
 22h    parity toggle complete
 23h    base 64K sequential read/write test passed
 24h    pre-interrupt-vector-initialization configuration complete
 25h    interrupt vectors initialized
 26h    8042 input port read
 27h    global data initialization complete
 28h    post-interrupt-vector-initialization initialization complete
 29h    monochrome mode set
 2Ah    color mode set
 2Bh    parity toggle on option video ROM test complete
 2Ch    initialization before video ROM control complete
 2Dh    video ROM check complete
 2Eh    !!!
 A9h    returned from E0000h adapter ROM
 AAh    final initializations after adapter ROM initializations complete
----------P0080008F--------------------------
PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
008A  RW  DMA channel 7 address byte 2
008B  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register
----------P0080009F--------------------------
PORT 0080-009F - Intel386sx CHIPSET 82231
Note:    includes the DMA controller functionality on PORT 0080h to PORT 008Fh
----------P0084------------------------------
PORT 0084 - Compaq POST Diagnostic
--------X-P0084------------------------------
PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE
----------P00850086--------------------------
PORT 0085-0086 - Intel "Triton" chipset - ???
SeeAlso: PORT 00EBh"Triton"

0085  ?W  ???
0086  ?W  ???
----------P0090009F--------------------------
PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)

0090  ??  Central arbitration control port
0091  R-  Card selection feedback
0092  RW  PS/2 system control port A  (port B is at 0061) (see #P075)
0094  -W  system board enable/setup register (see #P076)
0095  --  reserved
0096  -W  adapter enable / setup register
         bit 3 = 1  setup adapters
               = 0  enable registers
0097  --  reserved

Bitfields for PS/2 system control port A:
Bit(s)    Description    (Table P075)
 7-6    any bit set to 1 turns activity light on
 5    reserved
 4    watchdog timout occurred
 3    =0 RTC/CMOS security lock (on password area) unlocked
    =1 CMOS locked (done by POST)
 2    reserved
 1    A20 is active
 0    =0 system reset or write
    =1 pulse alternate reset pin (alternate CPU reset)
SeeAlso: #P076,MSR 00001000h

Bitfields for PS/2 system board enable/setup register:
Bit(s)    Description    (Table P076)
 7    =1  enable functions
    =0  setup functions
 5    =1  enables VGA
    =0  setup VGA
 2    =1  enable integrated SCSI (PS/2 M77)
    =0  setup integrated SCSI
SeeAlso: #P075
----------P00A000AF--------------------------
PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"

00A0  RW  NMI mask register (XT)
         bit 7 = 0 disabled
               = 1 enabled
00A0  RW  PIC 2     same as 0020 for PIC 1
00A1  RW  PIC 2     same as 0021 for PIC 1 except for OCW1 (see #P077)

Bitfields for PIC2 output control word OCW2:
Bit(s)    Description    (Table P077)
 7    disable IRQ15 (reserved)
 6    disable IRQ14 (fixed disk interrupt)
 5    disable IRQ13 (coprocessor exception interrupt)
 4    disable IRQ12 (mouse interrupt)
 3    disable IRQ11 (reserved)
 2    disable IRQ10 (reserved)
 1    disable IRQ9  (redirect cascade)
 0    disable IRQ8  (real-time clock interrupt)
SeeAlso: #P010
----------P00B000BF--------------------------
PORT 00B0-00BF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P00B2------------------------------
PORT 00B2 - Intel chipsets - Advanced Power Management Control
Notes:    used to pass data between the operating system and the System
      Management Interrupt (SMI) handler
    writes to this port can cause an SMI; reads can cause STPCLK# to be
      asserted (putting the CPU in sleep mode)
    supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B3h,#3345

00B2  RW  control
----------P00B3------------------------------
PORT 00B3 - Intel chipsets - Advanced Power Management Status
Notes:    used to pass data between the operating system and the System
      Management Interrupt (SMI) handler
    supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B2h

00B3  RW  status
----------P00C0------------------------------
PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)
----------P00C000DF--------------------------
PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R-  DMA channel 4-7 status register (ISA, EISA) (see #P078)
00D0  -W  DMA channel 4-7 command register (ISA, EISA) (see #P079)
00D2  -W  DMA channel 4-7 write request register (ISA, EISA)
00D4  -W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P080)
00D6  -W  DMA channel 4-7 mode register (ISA, EISA) (see #P081)
00D8  -W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R-  DMA channel 4-7 read temporary register (ISA, EISA)
00DA  -W  DMA channel 4-7 master clear (ISA, EISA)
00DC  -W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE  -W  DMA channel 4-7 write mask register (ISA, EISA)

Bitfields for DMA channel 4-7 status register:
Bit(s)    Description    (Table P078)
 7 = 1    channel 7 request
 6 = 1    channel 6 request
 5 = 1    channel 5 request
 4 = 1    channel 4 request
 3 = 1    terminal count on channel 7
 2 = 1    terminal count on channel 6
 1 = 1    terminal count on channel 5
 0 = 1    terminal count on channel 4
SeeAlso: #P001,#P079

Bitfields for DMA channel 4-7 command register:
Bit(s)    Description    (Table P079)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1  extended write selection
    =0  late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing
 2    =1  enable controller
    =0  enable memory-to-memory transfer
 1-0    channel number (00 = 4 to 11 = 7)
SeeAlso: #P002,#P078,#P080

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)    Description    (Table P080)
 7-3    reserved
 2    =0  clear mask bit
    =1  set mask bit
 1-0    channel select
    00 channel 4 select
    01 channel 5 select
    10 channel 6 select
    11 channel 7 select
SeeAlso: #P004,#P079

Bitfields for DMA channel 4-7 mode register:
Bit(s)    Description    (Table P081)
 7-6    transfer mode
    00  demand mode
    01  single mode
    10  block mode
    11  cascade mode
 5    direction
    0  address increment select
    1  address decrement select
 4    autoinitialisation enabled
 3-2    operation
    00  verify operation
    01  write to memory
    10  read from memory
    11  reserved
 1-0    channel number
    00  channel 4 select
    01  channel 5 select
    10  channel 6 select
    11  channel 7 select
SeeAlso: #P005,#P080
----------P00E000E1--------------------------
PORT 00E0-00E1 - CHIPSET FROM ACT

00E0  ?W  index for accesses to data port
00E1  R?  chip set data
----------P00E000E7--------------------------
PORT 00E0-00E7 - MICROCHANNEL

00E0  RW  split address register, memory encoding registers PS/2m80 only
00E1  RW  memory register
00E3  RW  error trace
00E4  RW  error trace
00E5  RW  error trace
00E7  RW  error trace
----------P00E000EF--------------------------
PORT 00E0-00EF - IBM PS/1 CLOCK
----------P00E1------------------------------
PORT 00E1 - STB PowerMEG - ???
Desc:    the STB PowerMEG is a memory expansion card capable of providing EMS

00E1  RW  ???
      bit 0: ???
----------P00EB------------------------------
PORT 00EB - Intel "Triton" chipset - ???
SeeAlso: PORT 0085h"Triton"

00EB  ?W  ???
----------P00EC00ED--------------------------
PORT 00EC-00ED - Compaq LTE Elite
----------P00ED------------------------------
PORT 00ED - ???
Note:    on a number of machines, the BIOS appears to write a copy of any
      data sent to numerous other ports to this port as well

00EDw  ?W  ???
----------P00EF------------------------------
PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!
----------P00F000F5--------------------------
PORT 00F0-00F5 - PCjr Disk Controller

00F0  ??  disk controller
00F2  ??  disk controller control port
00F4  ??  disk controller status register
00F5  ??  disk controller data port
----------P00F000FF--------------------------
PORT 00F0-00FF - MATH COPROCESSOR (8087..80387)

00F0  -W  math coprocessor clear busy latch
00F1  -W  math coprocessor reset
00F8  RW  opcode transfer
00FA  RW  opcode transfer
00FC  RW  opcode transfer
----------P00F9------------------------------
PORT 00F9 - Compaq LTE Elite
----------P00FB------------------------------
PORT 00FB - Compaq LTE Elite
----------P00F900FF--------------------------
PORT 00F9-00FF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P0100------------------------------
PORT 0100 - 3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0110h,PORT 0120h
----------P01000107--------------------------
PORT 0100-0107 - PS/2 POS (Programmable Option Select)
Note:    the default value for PORT 0102h is stored in CMOS 31h

0100  R      POS register 0    Low adapter ID byte
0101  R      POS register 1    High adapter ID byte
0102  RW  POS register 2    option select data byte 1 (see #P082)
0103  RW  POS register 3    option select data byte 2
0104  RW  POS register 4    option select data byte 3
0105  RW  POS register 5    option select data byte 4
         bit 7    channel active (-CHCK)
         bit 6    channel status
0106  RW  POS register 6    Low subaddress extension
0107  RW  POS register 7    High subaddress extension

Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s)    Description    (Table P082)
 7      0  = unidirectional LPT port
      1  = bidirectional LPT port
 6-5    PS/2 Model 50 and higher
     00b = default LPT port at 3BCh
     01b = ""           378h
     10b = ""           278h
     11b = reserved
 4    reserved
 0    card enable (CDEN)
 0    =1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
      without monitor)
---ET4000---
 7-4    reserved???
 3    video RAM wait enable
 2    ET4000: ROM BIOS wait enable
 1    ET4000: I/O wait enable
Note:    access to this port is only possible when PORT 0094h bit 7 is low.
----------P0100010F--------------------------
PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300
----------P0108010F--------------------------
PORT 0108-010F - IBM PS/2 - 8 digit LED info panel

010F  -W  leftmost character on display
010E  -W  second character
 ...
0108  -W  eighth character
----------P0110------------------------------
PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0120h"3COM"
----------P0120------------------------------
PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0110h"3COM"
----------P0130013F--------------------------
PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330
----------P01300133--------------------------
PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0134, 0230, 0234, 0330 and 0334
----------P01340137--------------------------
PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0130, 0230, 0234, 0330 and 0334
----------P0138013F--------------------------
PORT 0138-013F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P0140014F--------------------------
PORT 0140-014F - SCSI (alternate Small Computer System Interface) adapter
Note:    first adapter is at 0340-034F
----------P01400157--------------------------
PORT 0140-0157 - RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
----------P015C015D--------------------------
PORT 015C-015D - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 026Eh,PORT 0398h

015C  -W  index for data port
015D  RW  EPP command data
----------P015F------------------------------
PORT 015F - ARTEC Handyscanner A400Z.  alternate address at 35F.
----------P0168016F--------------------------
PORT 0168-016F - 4th (Quaternary) EIDE Controller
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01700177--------------------------
PORT 0170-0177 - HDC 2    (2nd Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01780179--------------------------
PORT 0178-0179 - Power Management
SeeAlso: PORT 0026h,#P279

0178  -W  index selection for data port
0179  RW  power management data
----------P0178017F--------------------------
PORT 0178-017F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P01CE01CF--------------------------
PORT 01CE-01CF - ATI Mach32 video chipset - ???

01CE  -W  index register
01CF  RW  data register
----------P01E801EF--------------------------
PORT 01E8-01EF - Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL

01ED  RW  select internal register. Data to/from 01EF
01EE  R-  ???
01EF  RW  register value
    05h  = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac)
         = 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac)
    10h memory size
       bits 2-0 = size
           (undefined,512K,640K,1024K,2560K,2048K,4096K,undef.)
    14h ???
       bit 2: 384K RAM of first 1024K relocated to top of memory
----------P01E801EF--------------------------
PORT 01E8-01EF - 3rd (Tertiary) EIDE Controller
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 0170h-0177h,PORT 01F0h-01F7h
----------P01F001F7--------------------------
PORT 01F0-01F7 - HDC 1    (1st Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 3510h-3513h

01F0  RW  data register
01F1  R-  error register (see #P083)
01F1  -W  WPC/4     (Write Precompensation Cylinder divided by 4)
01F2  RW  sector count
01F3  RW  sector number (CHS mode)
      logical block address, bits 0-7 (LBA mode)
01F4  RW  cylinder low (CHS mode)
      logical block address, bits 15-8 (LBA mode)
01F5  RW  cylinder high (CHS mode)
      logical block address, bits 23-16 (LBA mode)
01F6  RW  drive/head (see #P084)
01F7  R-  status register (see #P085)
01F7  -W  command register (see #P086)

Bitfields for Hard Disk Controller error register:
Bit(s)    Description    (Table P083)
---diagnostic mode errors---
 7    which drive failed (0 = master, 1 = slave)
 6-3    reserved
 2-0    error code
    001    no error detected
    010    formatter device error
    011    sector buffer error
    100    ECC circuitry error
    101    controlling microprocessor error
---operation mode---
 7    bad block detected
 6    uncorrectable ECC error
 5    reserved
 4    ID found
 3    reserved
 2    command aborted prematurely
 1    track 000 not found
 0    DAM not found (always 0 for CP-3022)
SeeAlso: #P084,#P085

Bitfields for hard disk controller drive/head specifier:
Bit(s)    Description    (Table P084)
 7    =1
 6    LBA mode enabled, rather than default CHS mode
 5    =1
 4    drive select (0 = drive 0, 1 = drive 1)
 3-0    head select bits (CHS mode)
    logical block address, bits 27-24 (LBA mode)
SeeAlso: #P083,#P085

Bitfields for hard disk controller status register:
Bit(s)    Description    (Table P085)
 7    controller is executing a command
 6    drive is ready
 5    write fault
 4    seek complete
 3    sector buffer requires servicing
 2    disk data read successfully corrected
 1    index - set to 1 each disk revolution
 0    previous command ended in an error
SeeAlso: #P083,#P086

(Table P086)
Values for hard disk controller command codes:
Command     Spec    Type    Proto    Description            class:
 00h        opt    nondata    NOP
 1xh        opt    nondata    recalibrate              1
 20h        req    PIOin    read sectors with retry          1
 21h        req    PIOin    read sectors without retry      1
 22h        req    PIOin    read long with retry          1
 23h        req    PIOin    read long without retry          1
 30h        req    PIOout    write sectors with retry      2
 31h        req    PIOout    write sectors without retry      2
 32h        req    PIOout    write long with retry          2
 33h        req    PIOout    write long without retry      2
 3Ch     IDE    opt    PIOout    write verify              3
 40h        req    nondata    read verify sectors with retry      1
 41h        req    nondata    read verify sectors without retry 1
 50h        req    vend    format track              2
 7xh        req    nondata    seek                  1
 8xh     IDE    vendor    vend    vendor unique 3
 90h        req    nondata    execute drive diagnostics      1
 91h        req    nondata    initialize drive parameters      1
 92h        opt    PIOout    download microcode
 94h E0h IDE    opt    nondata    standby immediate          1
 95h E1h IDE    opt    nondata    idle immediate              1
 96h E2h IDE    opt    nondata    standby                  1
 97h E3h IDE    opt    nondata    idle                  1
 98h E5h IDE    opt    nondata    check power mode          1
 99h E6h IDE    opt    nondata    set sleep mode              1
 9Ah     IDE    vendor    vend    vendor unique 1
 A1h     ATAPI    opt    PIOin    ATAPI Identify            (see #P089)
 B0h     SMART  opt        Self Mon., Analysis, Rept. Tech. (see #P280)
 C0h-C3h IDE    vendor    vend    vendor unique 2
 C4h     IDE    opt    PIOin    read multiple              1
 C5h     IDE    opt    PIOout    write multiple              3
 C6h     IDE    opt    nondata    set multiple mode          1
 C8h     IDE    opt    DMA    read DMA with retry          1
 C9h     IDE    opt    DMA    read DMA without retry          1
 CAh     IDE    opt    DMA    write DMA with retry          3
 CBh     IDE    opt    DMA    write DMA w/out retry          3
 DBh     ATA-2    opt    vend    acknowledge media chng        [Removable]
 DCh     ATA-2    opt    vend    Boot / Post-Boot        [Removable]
 DDh     ATA-2    opt    vend    Boot / Pre-Boot    (ATA-2)        [Removable]
 DEh     ATA-2    opt    vend    door lock            [Removable]
 DFh     ATA-2    opt    vend    door unlock            [Removable]
 E0h-E3h            (second half of commands 94h-96h)
 E4h     IDE    opt    PIOin    read buffer              1
 E5h-E6h            (second half of commands 98h-99h)
 E8h     IDE    opt    PIOout    write buffer              2
 E9h     IDE    opt    PIOout    write same              3
 EAh     ATA-3    opt        Secure Disable            [Security Mode]
 EAh     ATA-3    opt        Secure Lock            [Security Mode]
 EAh     ATA-3    opt        Secure State            [Security Mode]
 EAh     ATA-3    opt        Secure Enable WriteProt        [Security Mode]
 EBh     ATA-3    opt        Secure Enable            [Security Mode]
 EBh     ATA-3    opt        Secure Unlock            [Security Mode]
 ECh     IDE    req    PIOin    identify drive              1 (see #P087)
 EDh     ATA-2    opt    nondata    media eject            [Removable]
 EEh     ATA-3    opt        identify device DMA            (see #P087)
 EFh     IDE    opt    nondata    set features              1 (see #P281)
 F0h-F4h IDE        vend    EATA standard
 F1h                Security Set Password
 F2h                Security Unlock
 F3h                Security Erase Prepare
 F4h                Security Erase Unit
 F5h-FFh IDE    vendor    vend    vendor unique 4
 F5h                Security Freeze Lock
 F6h                Security Disable Password
SeeAlso: #P083,#P085

Format of IDE Identify Drive information:
Offset    Size    Description    (Table P087)
 00h    WORD    general configuration (see #P282)
 02h    WORD    number of logical cylinders
 04h    WORD    reserved
 06h    WORD    number of logical heads
 08h    WORD    vendor-specific (obsolete: unformatted bytes per track)
 0Ah    WORD    vendor-specific (obsolete: unformatted bytes per sector)
 0Ch    WORD    number of logical sectors
 0Eh    WORD    vendor-specific
 10h    WORD    vendor-specific
 12h    WORD    vendor-specific
 14h 10 WORDs    serial number
        no serial number if first word is 0000h
        else blank-padded ASCII serial number
 28h    WORD    vendor-specific
        [buffer type: 01h single-sector, 02h multisector,
          03h multisector with read cache]
 2Ah    WORD    controller buffer size in 512-byte sectors
        0000h = unspecified
 2Ch    WORD    number of vendor-specific (usually ECC) bytes on
          Read/Write Long; 0000h = unspecified
 2Eh  4    WORDs    firmware revision
        no revision number if first word is 0000h
        else blank-padded ASCII revision number
 36h 20    WORDs    model number
        no model number if first word is 0000h
        else blank-padded ASCII model string
 5Eh    WORD    read/write multiple support
        bits 7-0: maximum number of sectors per block supported
            00h if read/write multiple not supported
        bits 15-8: vendor-specified
 60h    WORD    able to do doubleword transfers if nonzero
 62h    WORD    capabilities (see #P088)
 64h    WORD    security mode
        bit 15: security-mode feature set supported
        bits 14-8: maximum number of passwords supported
 66h    WORD    PIO data transfer cycle timing
 68h    WORD    single-word DMA data transfer cycle timing
 6Ah    WORD    field validity
        bit 0: offsets 6Ch-75h valid
        bit 1: offsets 80h-8Dh valid
 6Ch    WORD    logical cylinders in current translation mode
 6Eh    WORD    logical heads in current translation mode
 70h    WORD    logical sectors per track in current translation mode
 72h    DWORD    current capacity in sectors (excluding device-specific uses)
 76h    WORD    multiple-sector support
        bits 7-0: count for read/write multiple command
        bit 8:    multiple-sector setting is valid
 78h    DWORD    total number of user-addressable sectors (LBA mode)
        00000000h if LBA mode not supported
 7Ch    WORD    single-word DMA transfer modes
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh    WORD    multiword DMA transfer
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high byte is bitmap of active mode (bit 8 = mode 0, etc.)
 80h    WORD    supported flow control PIO transfer modes
 82h    WORD    minimum multiword DMA transfer cycle time in ns
 84h    WORD    recommended multiword DMA cycle time in ns
 86h    WORD    minimum non-flow-control PIO transfer cycle time in ns
 88h    WORD    minimum PIO transfer cycle time with IORDY in ns
 8Ah  2 WORDs    reserved for future PIO modes (0)
 8Eh  9 WORDs    reserved (0)
 A0h    WORD    major revision number of specification to which device conforms
        01h = ATA-1, 02h = ATA-2, etc.  0000h/FFFFh = not reported
 A2h    WORD    minor revision number of specification to which device conforms
        0000h/FFFFh = not reported
 A4h    WORD    feature set support
        (only valid if revision reported in A0h/A2h)
 A6h    WORD    feature set support
        (only valid if revision reported in A0h/A2h)
 A8h 45 WORDs    reserved (0)
100h 32 WORDs    vendor-specific
100h    WORD    security status
140h 96 WORDs    reserved (0)
SeeAlso: #P089,#0177

Bitfields for IDE general configuration:
Bit(s)    Description    (Table P282)
 15    device class
    =0 ATA device
    =1 ATAPI device
 14    requires format speed tolerance gap
 13    supports track offset option
 12    supports data strobe offset
 11    disk rotational sped tolerance > 0.5%
 10-8    disk transfer rate
    001 <= 5Mbit/sec
    010 5-10 Mbit/sec
    100 > 10Mbit/sec
 7-6    drive type
    01 fixed media
    10 removable media
 5    synchronized drive motor option enabled
 4    head-switching time > 15 microseconds
 3    encoding
    =0 MFM
 2-1    sector type
    01 hard-sectored
    10 soft-sectored
 0    unused (0)
SeeAlso: #P087

Bitfields for IDE capabilities:
Bit(s)    Description    (Table P088)
 13    Standby Timer values used according to ATA standard
 11    IORDY supported
 10    device can disable use of IORDY
 9    LBA mode supported
 8    DMA supported
SeeAlso: #P087

Format of ATAPI Identify Information:
Offset    Size    Description    (Table P089)
 00h    WORD    general configuration (see #P090)
 14h 10 WORDs    serial number
        no serial number if first word is 0000h
        else blank-padded ASCII serial number
 28h  3 WORDs    vendor-specific
 2Eh  4    WORDs    firmware revision
        no revision number if first word is 0000h
        else blank-padded ASCII revision number
 36h 20    WORDs    model number
        no model number if first word is 0000h
        else blank-padded ASCII model string
 5Eh    WORD    vendor-specific
 60h    WORD    reserved (0)
 62h    WORD    capabilities (see #P088)
 64h    WORD    security mode???
 66h    WORD    PIO data transfer cycle timing
 68h    WORD    single-word DMA data transfer cycle timing
 6Ah    WORD    field validity
        bit 0: offsets 6Ch-73h valid
        bit 1: offsets 80h-8Dh valid
 6Ch    WORD    ??? logical cylinders in current translation mode
 6Eh    WORD    ??? logical heads in current translation mode
 70h    WORD    ??? logical sectors per track in current translation mode
 72h  2    WORDs    ??? current capacity in sectors
 76h    WORD    ??? multiple-sector count for read/write multiple command
 78h  2    WORDs    ??? total number of user-addressable sectors (LBA mode)
 7Ch    WORD    single-word DMA transfer modes
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh    WORD    multiword DMA transfer
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 80h    WORD    supported flow control PIO transfer modes
 82h    WORD    minimum multiword DMA transfer cycle time
 84h    WORD    recommended multiword DMA cycle time
 86h    WORD    minimum non-flow-control PIO transfer cycle time
 88h    WORD    minimum PIO transfer cycle time with IORDY
 8Ah  2 WORDs    reserved for future PIO modes (0)
 8Eh    WORD    typical time for release when processing overlapped CMD in
          microseconds
 90h    WORD    ???
 92h    WORD    major ATAPI version number
 94h    WORD    minor ATAPI version number
 96h 54 WORDs    reserved (0)
100h 32 WORDs    vendor-specific
140h 96 WORDs    reserved (0)
SeeAlso: #P087

Bitfields for ATAPI General Configuration:
Bit(s)    Description    (Table P090)
 15-14    device type
 13    reserved
 12    device present
 7    device is removable
 6-5    CMD DMA Request type
    00 microprocessor DRQ
    01 interrupt DRQ
    10 accelerated DRQ
    11 reserved
 4-2    reserved
 1-0    CMD packet size (00 = 12 bytes, 01 = 16 bytes)
SeeAlso: #P089

(Table P280)
Values for Self-Monitoring, Analysis, Reporting Technology (SMART) command:
 D0h    Read Attribute Values (optional)
 D1h    Read Attribute Thresholds (optional)
 D2h    Disable Attribute Autosave (optional)
    sector-count register set to 0000h
 D2h    Enable Attribute Autosave
    sector-count register set to 00F1h
 D3h    Save Attribute Values (optional)
 D8h    Enable Operations
 D9h    Disable Operations
 DAh    Return Status
Note:    to access SMART commands, the Cylinder Low register must be set to
      004Fh and the Cylinder High register must be set to 00C2h before
      invoking the SMART command with the SMART command number in the
      Features register
SeeAlso: #P086

(Table P281)
Values for Feature Code:
 01h    [opt] 8-bit instead of 16-bit data transfers
 02h    [opt] enable write cache
 03h          set transfer mode as specified by Sector Count register
 04h    [opt] enable all automatic defect reassignment
 22h    [opt] Write Same, user-specified area
 33h    [opt] disable retries
 44h          specify length of ECC bytes used by Read Long and Write Long
 54h    [opt] set cache segments (value in Sector Count register)
 55h          disable look-ahead
 66h          disable reverting to power-on defaults
 77h    [opt] disable ECC
 81h    [opt] 16-bit instead of 8-bit data transfers
 82h    [opt] disable write cache
 84h    [opt] disable all automatic defect reassignment
 88h    [opt] enable ECC
 99h    [opt] enable retries
 9Ah    [opt] set device maximum average current
 AAh          enable look-ahead
 ABh    [opt] set maximum prefecth (value in Sector Count register)
 BBh          use four bytes of ECC on Read Long and Write Long (for compat.)
 CCh          enable reverting to power-on defaults
 DDh    [opt] Write Same, entire disk
SeeAlso: #0176
----------P01F8------------------------------
PORT 01F8 - ???

01F8  RW  ???
        bit 0: A20 gate control (set = A20 enabled, clear = disabled)
----------P01F901FF--------------------------
PORT 01F9-01FF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
--------d-P0200------------------------------
PORT 0200 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0300h"Digidesign"
----------P0200020F--------------------------
PORT 0200-020F - Game port reserved I/O address space
0200-0207 - Game port, eight identical addresses on some boards

0201  R-  read joystick position and status (see #P091)
0201  -W  fire joystick's four one-shots
0201  RW  gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible,
        Covox 'voice master' & 'speech thing' compatible soundcard.
        (enabled if bit1=1 in PORT 038Fh. Because it is disabled on
        power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh)

Bitfields for joystick position and status:
Bit(s)    Description    (Table P091)
 7    status B joystick button 2 / D paddle button
 6    status B joystick button 1 / C paddle button
 5    status A joystick button 2 / B paddle button
 4    status A joystick button 1 / A paddle button
 3    B joystick Y coordinate       / D paddle coordinate
 2    B joystick X coordinate       / C paddle coordinate
 1    A joystick Y coordinate       / B paddle coordinate
 0    A joystick X coordinate       / A paddle coordinate
----------P020002FF--------------------------
PORT 0200-02FF - Sunshine uPW48, programmer for EPROM version CPU's 8748/8749
Range:    4 bit DIP switch installable in the range 20x-2Fx

0200-0203    adresses of the 8255 on the uPW48
0208-020B    adresses of ??? on the uPW48 (all showing zeros)
----------P02080209--------------------------
PORT 0208-0209 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8
----------P020C020F--------------------------
PORT 020C-020F - AIMS LAB PC Radio
Range:    configurable to 020C or 030C
----------P02100217--------------------------
PORT 0210-0217 - Expansion unit (XT)

0210  -W  latch expansion bus data
0210  R-  verify expansion bus data
0211  -W  clear wait, test latch
0211  R-  High byte data address
0212  R-  Low byte data address
0213  -W  0=enable,  1=disable expansion unit
0214  -W  latch data  (receiver card port)
0214  R-  read data   (receiver card port)
0215  R-  High byte of address, then Low byte    (receiver card port)
----------P02100211--------------------------
PORT 0210-0211 - Game Blaster
Range:    PORT 02x0h-02x1h, x=1,2,...

0210  -W  register index
0211  ?W  register data
----------P02180219--------------------------
PORT 0218-0219 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02200223--------------------------
PORT 0220-0223 - Sound Blaster / Adlib port (Stereo)
SeeAlso: PORT 0388h-0389h

0220  R-  Left speaker -- Status port
0220  -W  Left speaker -- Address port
0221  -W  Left speaker -- Data port
0222  R-  Right speaker -- Status port
0222  -W  Right speaker -- Address port
0223  -W  Right speaker -- Data port
----------P02200227--------------------------
PORT 0220-0227 - Soundblaster PRO and SSB 16 ASP
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 2.0
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 4.0
Note:    the FM music is accessible on 0388/0389 for compatibility.

0220  R-  left FM status port
0220  -W  left FM music register address port (index)
0221  RW  left FM music data port
0222  R-  right FM status port
0222  -W  right FM music register address port (index)
0223  RW  right FM music data port
0224  -W  mixer register address port (index)
0225  RW  mixer data port
0226  -W  DSP reset
0228  R-  FM music status port
0228  -W  FM music register address port (index)
0229  -W  FM music data port
022A  R-  DSP read data (voice I/O and Midi)
022C  -W  DSP write data / write command
022C  R-  DSP write buffer status (bit 7)
022E  R-  DSP data available status (bit 7)
----------P022B------------------------------
PORT 022B - GI1904 Scanner Interface Adapter
Range:    PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
----------P022C------------------------------
PORT 022C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P022F------------------------------
PORT 022F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    An Adlib-compatible Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine"

022F  RW  Covox compatible speech I/O  (via internal A/D converter,
        each read access starts a new conversion cycle)
        register enabled if bit7=1 in PORT 038Fh
----------P02300233--------------------------
PORT 0230-0233 - Adaptec 154xB/154xC SCSI adapter.
        alternate address at 0130, 0134, 0230, 0330 and 0334
----------P02340237--------------------------
PORT 0234-0237 - Adaptec 154xB/154xC SCSI adapter.
        alternate address at 0130, 0134, 0230, 0330 and 0334
----------P0238023F--------------------------
PORT 0238-023F - COM port addresses on UniRAM card by German magazine c't
        selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
----------P0238023x--------------------------
PORT 0238-023x - Bus Mouse Port (secondary address)
Note:    secondary address for bus mice from MS and Logitech, and the ATI
      video adapter mouse
SeeAlso: PORT 023Ch"Mouse"
----------P023C023x--------------------------
PORT 023C-023x - Bus Mouse Port (primary address)
Note:    primary address for bus mice from MS and Logitech, the ATI video
      adapter mouse, and the Commodore PC30III bus mouse
SeeAlso: PORT 0238h"Mouse"
----------P0240024F--------------------------
PORT 0240-024F - Gravis Ultra Sound by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
SeeAlso: PORT 0340h-034Fh,PORT 0746h

0240  -W  Mix Control register (see #P092)
0241  R-  Read Data
0241  -W  Trigger Timer
0246  R-  IRQ Status Register (see #P093)
0248  RW  Timer Control Reg
      Same as ADLIB Board (see PORT 0200h)
0249  -W  Timer Data (see #P094)
024B  -W  IRQ Control Register (0240 bit 6 = 1) (see #P095)
024B  -W  DMA Control Register (0240 bit 6 = 0) (see #P096)
024F  RW  Register Controls (rev 3.4+)

Bitfields for Gravis Ultra Sound mix control register:
Bit(s)    Description    (Table P092)
 6       Control Register Select (see 024B)
 5       Enable MIDI Loopback
 4       Combine GF1 IRQ with MIDI IRQ
 3       Enable Latches
 2       Enable MIC IN
 1       Disable LINE OUT
 0       Disable LINE IN
SeeAlso: #P093

Bitfields for Gravis Ultra Sound IRQ status register:
Bit(s)    Description    (Table P093)
 7       DMA TC IRQ
 6       Volume Ramp IRQ
 5       WaveTable IRQ
 3       Timer 2 IRQ
 2       Timer 1 IRQ
 1       MIDI Receive IRQ
 0       MIDI Transmit IRQ
SeeAlso: #P092,#P095,#P096

Bitfields for Gravis Ultra Sound timer data:
Bit(s)    Description    (Table P094)
 7       Reset Timr IRQ
 6       Mask Timer 1
 5       Mask Timer 2
 1       Timer 2 Start
 0       Timer 1 Start
SeeAlso: #P093,#P095

Bitfields for Gravis Ultra Sound IRQ control register:
Bit(s)    Description    (Table P095)
 6    Combine Both IRQ
 5-3    MIDI IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
 2-0    GF1 IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
SeeAlso: #P093,#P096

Bitfields for Gravis Ultra Sound DMA Control Register:
Bit(s)    Description    (Table P096)
 6    Combine Both DMA
 5-3    DMA Select Register 2
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
 2-0    DMA Select Register 1
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
SeeAlso: #P093,#P095,#P100
----------P02400257--------------------------
PORT 0240-0257 - RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
----------P02580259--------------------------
PORT 0258-0259 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02580259--------------------------
PORT 0258-0259 - AT RAMBANK Memory Expansion Board - EXT MEMORY AND EMS-SUPPORT
Range:    base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h,
      or 02A8h
----------P0258025F--------------------------
PORT 0258-025F - Intel Above Board
----------P02600268--------------------------
PORT 0260-0268    -  LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02680269--------------------------
PORT 0268-0269 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P026B------------------------------
PORT 026B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
----------P026C------------------------------
PORT 026C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P026E026F--------------------------
PORT 026E-026F - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 0398h

026E  -W  index for data port
026F  RW  EPP command data
----------P0278------------------------------
PORT 0278 - Covox 'Speech Thing' COMPATIBLES
SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine"

0278  -W  speech data output via printer data port
        (with mc-soundmachine, enabled if bit5=1 in 38F)
----------P0278027E--------------------------
PORT 0278-027E - parallel printer port, same as 0378 and 03BC

0278  -W  data port
0279  Rw  status port
027A  RW  control port
----------P0279------------------------------
PORT 0279 - Plug-and-Play - CONFIGURATION REGISTER
SeeAlso: PORT 0A79h

0279  -W  index into Plug-and-Play register set for Read Data Port and
      Write Data Port I/O (see #P097,#P098)

(Table P097)
Values for Plug-and-Play Card-Level Registers:
 00h    set Read Port address
    bits 9-2 of Read Data port address (bits 15-10 are always 0, bits 1-0
      are always 11); valid Read Port addresses are 0203h-03FFh
 01h    serial isolation
 02h    configuration control
 03h    Wake command
    (specifies which card is accessed through configuration registers)
 04h    resource data
 05h    status
 06h    Card Select Number (CSN)
 07h    logical device number
    (selects which logical device on card is accessed at locations 30h-FFh)
    (see #P098)
 08h-1Fh reserved
 20h-2Fh vendor-specific
Note:    there is one set of these registers per installed card
SeeAlso: #P098

(Table P098)
Values for Plug-and-Play Logical Device Registers:
 30h    activate
    bit 0: device is active on ISA bus
    bits 7-1: reserved (0)
 31h    I/O range check
    bit 0: I/O Read Pattern select (if bit 1 set, then I/O reads return
        55h if this bit is set, AAh if this bit is clear)
    bit 1: I/O Range Check Enable: if set, all reads from device I/O
          registers return 55h or AAh, depending on bit 0
    bits 7-2: reserved (0)
 32h-37h reserved
 38h-3Fh vendor-specific
 40h-44h 24-bit ISA memory descriptor 0
 45h-47h reserved
 48h-4Ch 24-bit ISA memory descriptor 1
 4Dh-4Fh reserved
 50h-54h 24-bit ISA memory descriptor 2
 55h-57h reserved
 58h-5Ch 24-bit ISA memory descriptor 3
 5Dh-5Fh reserved
 60h-6Fh I/O configuration registers 0-7
 70h-71h IRQ channel select 0
 72h-73h IRQ channel select 1
 74h-75h DMA configuration registers 0-1
 76h-7Eh 32-bit memory range configuration register 0
 7Fh     reserved
 80h-88h 32-bit memory range configuration register 1
 89h-8Fh reserved
 90h-98h 32-bit memory range configuration register 2
 99h-9Fh reserved
 A0h-A8h 32-bit memory range configuration register 3
 A9h-EFh reserved for logical device configuration
 F0h-FEh vendor-specific
 FFh    reserved
Note:    there is one set of these registers per logical device
SeeAlso: #P097
----------P0280------------------------------
PORT 0280 - LCD display on Wyse 2108 PC
----------P02800288--------------------------
PORT 0280-0288    - non-standard COM port addresses (V20-XT by German magazine c't)
        selectable from 0280, 0288, 0290, 0298, 6A0, 6A8
----------P0288028F--------------------------
PORT 0288-028F    - non-standard COM port addresses (V20-XT by German magazine c't)
0280-0288    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
0290-0298
0298-029F
----------P02A002A7--------------------------
PORT 02A0-02A7 - Sunshine EW-901BN, EW-904BN
        EPROM writer card (release 1986) for EPROMs up to 27512
02A0-02A3    adresses of the 8255 on the EW-90xBN
----------P02A202A3--------------------------
PORT 02A2-02A3 - MSM58321RS clock
----------P02A802A9--------------------------
PORT 02A8-02A9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02AB------------------------------
PORT 02AB - GI1904 Scanner Interface Adapter (default)
Range:    PORT 022Bh, PORT 026Bh, PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
Note:    the GI1904 is used by many SPI 400/800dpi gray/halftone/color handy
      scanners by Marstek, Mustek, Conrad, Völkner and others
----------P02AC------------------------------
PORT 02AC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P02B002BF--------------------------
PORT 02B0-02BF - Trantor SCSI adapter
----------P02B002DF--------------------------
PORT 02B0-02DF - alternate EGA,    primary EGA at 03C0
----------P02B802B9--------------------------
PORT 02B8-02B9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02C002Cx--------------------------
PORT 02C0-02Cx - AST-clock
----------P02C002DF--------------------------
PORT 02C0-02DF - XT-Real Time Clock 2 (default jumpered address)
----------P02E002E8--------------------------
PORT 02E0-02E8 - LPT port address on the UniRAM card by German magazine c't
Range:    base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8.
----------P02E002EF--------------------------
PORT 02E0-02EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)
        (GAB 0 on XT)
02E1  ??  GPIB (adapter 0)
02E2
02E3
----------P02E002EF--------------------------
PORT 02E0-02EF - data aquisition     (AT)

02E2  ??  data aquisition (adapter 0)
02E3  ??  data aquisition (adapter 0)
----------P02E8------------------------------
PORT 02E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P02E802E9--------------------------
PORT 02E8-02E9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02E802EF--------------------------
PORT 02E8-02EF - serial port, same as 02F8, 03E8 and 03F8 (COM4)
----------P02E802EF--------------------------
PORT 02E8-02EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

02E8  R-  display status
02E8  -W  horizontal total
02EA  RW  Lookup: DAC mask
02EB  -W  Lookup: DAC read index
02EC  -W  Lookup: DAC write index
02ED  RW  Lookup: DAC data
----------P02EA------------------------------
PORT 02EA - S3 86C928 video controller (ELSA Winner 1000)
----------P02EB------------------------------
PORT 02EB - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 032Bh, PORT 036Bh,
      PORT 03ABh, PORT 03EBh
----------P02EC------------------------------
PORT 02EC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P02F002F8--------------------------
PORT 02F0-02F8 - LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02F802FF--------------------------
PORT 02F8-02FF - serial port, same as 02E8, 03E8 and 03F8 (COM2)

02F8  -W  transmitter holding register
02F8  R-  receiver buffer register
02F8  RW  divisor latch, low byte    when DLAB=1
02F9  RW  divisor latch, high byte    when DLAB=1
02F9  RW  interrupt enable register when DLAB=0
02FA  R-  interrupt identification register
02FB  RW  line control register
02FC  RW  modem control register
02FD  R-  line status register
02FF  RW  scratch register
----------P0300------------------------------
PORT 0300 - Award POST Diagnostic
--------d-P0300------------------------------
PORT 0300 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0200h"Digidesign"
----------P03000301--------------------------
PORT 0300-0301 - Soundblaster 16 ASP MPU-Midi
----------P0300????--------------------------
PORT 0300-???? - HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142)
----------P03000303--------------------------
PORT 0300-0303 - Panasonic 52x CD-ROM SCSI Miniport
Range:    PORT 0300h-0303h,PORT 0320h-0323h,PORT 0340h-0343h,PORT 0360h-0363h,
      and PORT 0380h-0383h
----------P0300030F--------------------------
PORT 0300-030F - Philips CD-ROM player CM50
----------P0300030F--------------------------
PORT 0300-030F - CompaQ Tape drive adapter. alternate address at 0100
--------N-P0300031F--------------------------
PORT 0300-031F - 3com Ethernet adapters (default address)
--------N-P0300031F--------------------------
PORT 0300-031F - NE2000 compatible Ethernet adapters
Range:    may be placed at 0300h, 0320h, 0340h, or 0360h
SeeAlso: PORT 0300h"PCnet"
--------N-P0300031F--------------------------
PORT 0300-031F - AMD PCnet - NE2100-compatible Ethernet adapters
Range:    may be placed at 0300h, 0320h, 0340h, or 0360h, with the card's ROM
      appearing at segment C800h, CC00h, D000h, or D400h, respectively
Note:    for the PCnet-FAST chip, the I/O address may be read from the PCI
      configuration space at offset 10h (see #0628 at INT 1A/AX=B10Ah)
SeeAlso: PORT 0300h"NE2000",#0628

0300-030F  R-  address PROM (used to store Ethernet address, etc.)
0310w RW  Register Data Port (RDP) (see #P241,#P250)
0312w ?W  Register Access Port (RAP) (selects register index for RDP and IDP)
      (see #P247)
0314w ?W  Reset
0316w RW  ISA Bus Data Port (IDP)
0318w     reserved for vendor-specific use
031A-031F      reserved

(Table P241)
Values for AMD PCnet-ISA Register Data Port index:
 00h    "CSR0" status and control flags (see #P242)
 01h    "CSR1" low half of IADR (appears at PORT 0316h)
 02h    "CSR2" high half of IADR (appears at PORT 0317h)
 03h    "CSR3" interrupt masks (see #P243)
 04h    "CSR4" interrupt masks and status bits (see #P244)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh    "CSR15" mode (see #P245)
 4Ch    "CSR76" receive descriptor ring length
 4Eh    "CSR78" transmit descriptor ring length
 50h    "CSR80" FIFO threshold / DMA burst control (see #P246)
 52h    "CSR82" DMA bus timer
 58h    "CSR88" chip ID
 70h    "CSR112" number of missed packets
 72h    "CSR114" number of receive collisions
 7Ch    "CSR124" BMU test register
        bit 4: accept runt packets
SeeAlso: #P247,#P250

(Table P250)
Values for AMD PCnet-SCSI/PCnet-FAST Register Data Port index:
 00h    "CSR0" status and control flags (see #P242)
 01h    "CSR1" low half of IADR (appears at PORT 0316h)
 02h    "CSR2" high half of IADR (appears at PORT 0317h)
 03h    "CSR3" interrupt masks (see #P243)
 04h    "CSR4" interrupt masks and status bits (see #P244)
 05h    "CSR5" (PCnet-FAST) extended control and interrupt 1 (see #P261)
 06h    "CSR6" receive/transmit descriptor table lengths (see #P262)
 07h    "CSR7" (PCnet-FAST) extended control and interrupt 2 (see #P263)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh    "CSR15" mode (see #P245)
 10h    "CSR16"    alias of CSR1
 11h    "CSR17"    alias of CSR2
 12h    "CSR18" low half of current receive buffer address
 13h    "CSR19" high half of current receive buffer address
 14h    "CSR20" low half of current transmit buffer address
 15h    "CSR21" high half of current transmit buffer address
 16h    "CSR22" low half of next receive buffer address
 17h    "CSR23" high half of next receive buffer address
 18h    "CSR24" low half of receive-ring base address
 19h    "CSR25" high half of receive-ring base address
 1Ah    "CSR26" low half of next receive descriptor address
 1Bh    "CSR27" high half of next receive descriptor address
 1Ch    "CSR28" low half of current receive descriptor address
 1Dh    "CSR29" high half of current receive descriptor address
 1Eh    "CSR30" low half of transmit ring base address
 1Fh    "CSR31" high half of transmit ring base address
 20h    "CSR32" low half of next transmit descriptor address
 21h    "CSR33" high half of next transmit descriptor address
 22h    "CSR34" low half of current transmit descriptor address
 23h    "CSR35" high half of current transmit descriptor address
 24h    "CSR36" low half of next next receive descriptor address
 25h    "CSR37" high half of next next receive descriptor address
 26h    "CSR38" low half of next next transmit descriptor address
 27h    "CSR39" high half of next next transmit descriptor address
 28h    "CSR40" current receive byte count (see #P264)
 29h    "CSR41" current receive status
 2Ah    "CSR42" current transmit byte count (see #P265)
 2Bh    "CSR43" current transmit status
 2Ch    "CSR44" next receive byte count (bits 11-0; bits 15-12=0)
 2Dh    "CSR45" next receive status
 2Eh    "CSR46" transmit poll time counter
 2Fh    "CSR47" transmit polling interval
 30h    "CSR48" receive poll time counter
 31h    "CSR49" receive polling interval
 32h-39h reserved
 3Ah    "CSR58" software style (see #P266)
 3Bh    reserved
 3Ch    "CSR60" previous transmit descriptor address (low)
 3Dh    "CSR61" previous transmit descriptor address (high)
 3Eh    "CSR62" previous transmit byte count (bits 11-0; bits 15-12=0)
 3Fh    "CSR63" previous transmit status
 40h    "CSR64" next transmit buffer address (low)
 41h    "CSR65" next transmit buffer address (high)
 42h    "CSR66" next transmit byte count (bits 11-0; bits 15-12=0)
 43h    "CSR67" next transmit status
 44h-47h reserved
 48h    "CSR72" receive ring counter
 49h    reserved
 4Ah    "CSR74" transmit ring counter
 4Bh    reserved
 4Ch    "CSR76" receive descriptor ring length
 4Dh    reserved
 4Eh    "CSR78" transmit descriptor ring length
 4Fh    reserved
 50h    "CSR80" FIFO threshold / DMA burst control (see #P246)
 51h    reserved
 52h    "CSR82" (PCnet-SCSI) DMA bus timer
        (PCnet-FAST) transmit descriptor address (low)
 53h    reserved
 54h    "CSR84" DMA address register (low)
 55h    "CSR85" DMA address register (high)
 56h    "CSR86" buffer byte counter (bits 11-0; bits 15-12=0)
 57h    reserved
 58h    "CSR88" chip ID (low 16 bits) (see #P267)
 59h    "CSR89" chip ID (high 16 bits) (see #P267)
 5Ah    "CSR90" (PCnet-SCSI)
 5Bh    reserved
 5Ch    "CSR92" ring length conversion
 5Dh    reserved
 5Eh    "CSR94" (PCnet-SCSI)
 5Fh-63h reserved
 64h    "CSR100" bus timeout
 65h-6Fh reserved
 70h    "CSR112" number of missed packets
 71h    reserved
 72h    "CSR114" number of receive collisions
 73h-79h reserved
 7Ah    "CSR122" advanced feature control (see #P268)
 7Bh    reserved
 7Ch    "CSR124" BMU test register (see #P269)
 7Dh    "CSR125" (PCnet-FAST) MAC Enhanced Configuration Control (see #P270)
 7Eh-7Fh reserved
SeeAlso: #P241,#P251

Bitfields for AMD PCnet CSR0 status and control flags:
Bit(s)    Description    (Table P242)
 15    "ERR"    error; set if BABL, CERR, MISS, or MESS set
 14    "BABL"  network babbling control
 13    "CERR"    collision error
 12    "MISS"    missed frame
 11    "MERR"    memory error
 10    "RINT"    receive interrupt
 9    "TINT"    transmit interrupt
 8    "IDON"    initialization done
 7    "INTR"    interrupt flag
 6    "IENA"    interrupt enable
 5    "RXON"    recieve ON
 4    "TXON"    transmit ON
 3    "TDMD"    transmit demand
 2    "STOP"    stop -- disable all external activity
 1    "STRT"    start -- enable extrnal activity
 0    "INIT"    begin initialization procedure
SeeAlso: #P241,#P243

Bitfields for AMD PCnet CSR3 interrupt masks:
Bit(s)    Description    (Table P243)
 15    reserved
 14    "BABLM"    disable babble interrupt
 13    reserved
 12    "MISSM" disable missed-frame interrupt
 11    "MERM"    disable memory-error interrupt
 10    "RINTM"    disable receive interrupt
 9    "TINTM" disable transmit interrupt
 8    "IDONM" disable initialization-done interrupt
 7-5    reserved
 4    "DXMT2PD" disable Transmit Two Part Deferral
 3    "EMBA"    enable modified back-off algorithm
 2-0    reserved
Note:    other bits are reserved
SeeAlso: #P241,#P242,#P244

Bitfields for AMD PCnet CSR4 interrupt masks and status bits:
Bit(s)    Description    (Table P244)
 15    "ENTST"       enable Test Mode / CSR124 access
 14    "DMAPLUS"  disable CSR80 burst transaction counter
 13    "TIMER"       enable Bus Timer register
 12    "DPOLL"       disable transmit polling
 11    "APADXMT"  Auto-Pad Transmit
 10    "ASTRPRCV" enable automatic pad stripping
 9    "MFCO"       missed frame counter has overflowed
 8    "MFCOM"       disable interrupt on MFCO
 7    "UINTCMD"  (PCnet-FAST) user interrupt command
 6    "UINT"       (PCnet-FAST) user interrupt pending
            write 1 to clear
 5    "RCVCCO"   receive collision counter has overflowed
 4    "RCVCCOM"  disable interrupt on RCVCCO
 3    "TXSTRT"   Transmit Start
 2    "TXSTRTM"  disable interrupt on TXSTRT
 1    "JAB"       Jabber error
 0    "JABM"       disable interrupt on JAB
SeeAlso: #P241,#P243,#P250

Bitfields for AMD PCnet-FAST CSR5 extended control and interrupt 1:
Bit(s)    Description    (Table P261)
 31-16    reserved
 15    "TOKINTD"  disable Transmit OK interrupt
 14    "LTINTEN"  enable Last Transmit interrupt
 13-12    reserved
 11    "SINT"       System Interrupt (write 1 to clear)
 10    "SINTE"       enable System Interrupt
 9    "SLPINT"   Sleep Interrupt (write 1 to clear)
 8    "SLPINTE"  enable Sleep Interrupt
 7    "EXDINT"   Excessive Deferral Interrupt (write 1 to clear)
 6    "EXDINTE"  enable Excessive Deferral Interrupt
 5    "MPPLBA"   Magic Packet Physical Logical Broadcast Accept
 4    "MPINT"       Magic Packet Interrupt (write 1 to clear)
 3    "MPINTE"   enable Magic Packet Interrupt
 2    "MPEN"       enable Magic Packet mode
 1    "MPMODE"   Magic Packet mode active
 0    "SPND"       Suspend
SeeAlso: #P250,#P244,#P263

Bitfields for AMD PCnet CSR6 Descriptor Table Length register:
Bit(s)    Description    (Table P262)
 15-12    transmit encoded ring length
 11-8    receive encoded ring length
 7-0    reserved
SeeAlso: #P250,#P261

Bitfields for AMD PCnet CSR7 Extended Control and Interrupt 2:
Bit(s)    Description    (Table P263)
 15    "FASTSPNDE"  enable Fast Suspend
 14    "RXFRTG"     Receive Frame Tag
 13    "RDMD"         Receive Demand
 12    "RXDPOL"     disable receive polling
 11    "STINT"         Software Timer Interrupt (write 1 to clear)
 10    "STINTE"     enable Software Timer Interrupt
 9    "MREINT"     MII Management Read Error Interrupt (write 1 to clear)
 8    "MREINTE"    enable MII Management Read Error Interrupt
 7    "MAPINT"     MII Management Auto-Poll Interrupt (write 1 to clear)
 6    "MAPINTE"    enable MII Management Auto-Poll Interrupt
 5    "MCCINT"     MII Management Command Complete Interrupt (write 1 to clr)
 4    "MCCINTE"    enable MII Management Command Complete Interrupt
 3    "MCCIINT"    MII Management Command Complete Internal Interrupt
            (write 1 to clear)
 2    "MCCIINTE"   enable MII Manamagement Command Complete Internal Int.
 1    "MIIPDTINT"  MII PHY Detect Transition Interrupt (write 1 to clear)
 0    "MIIPDTINTE" enable MII PHY Detect Transition Interrupt
SeeAlso: #P250,#P261

Bitfields for AMD PCnet CSR15 mode flags:
Bit(s)    Description    (Table P245)
 15    "PROM"       promiscuous mode
 14    "DRCVBC"   disable Receive Broadcast
 13    "DRCVPA"   disable Receive Physical Address
 12    "DLNKTST"  disable Link Status
 11    "DAPC"       disable Automatic Polarity Correction
 10    "MENDECL"  MENDEC loopback mode
 9    "LRT/TSEL" Low Receive Threshold
 8-7    "PORTSEL"  Port Select
        00  AUI
        01  10Base-T
        10  GPSI
        11  reserved
 6    "INTL"       internal loopback
 5    "DRTY"       disable retry
 4    "FCOLL"       force collision
 3    "DXMTFCS"  disable Transmit CRC
 2    "LOOP"       enable Loopback
 1    "DTX"       disable transmitter
 0    "DRX"       disable receiver
SeeAlso: #P241,#P244,#P246

Bitfields for AMD PCnet CSR40 Current Receive Byte Count register:
Bit(s)    Description    (Table P264)
 15-12    reserved (0)
 11-0    current receive byte count (copy of BCNT field of current receive
      descriptor's RMD1)
SeeAlso: #P250,#P265

Bitfields for AMD PCnet CSR42 Current Transmit Byte Count register:
Bit(s)    Description    (Table P265)
 15-12    reserved (0)
 11-0    current transmit byte count (copy of BCNT field of current receive
      descriptor's TMD1)
SeeAlso: #P250,#P264

Bitfields for AMD PCnet CSR58 Software Style register:
Bit(s)    Description    (Table P266)
 15-11    reserved (undefined)
 10    "APERREN"    enabled advanced parity error handling
 9    "CSRPCNET"    PCnet-ISA compatibility (read-only)
 8    "SSIZE32"    32-bit software structures for data blocks
 7-0    "SWSTYLE"    software style
        00h LANCE/PCnet-ISA (16-bit software structures)
        01h reserved
        02h PCnet-PCI (32-bit software)
        03h PCnet-PCI (32-bit software)
SeeAlso: #P250

Bitfields for AMD PCnet CSR80 FIFO threshold and DMA burst control:
Bit(s)    Description    (Table P246)
 15-14    reserved
 13-12    receive FIFO high-water mark; request DMA when N byte available
    00 = 16 bytes
    01 = 32 bytes
    10 = 64 bytes
 11-10    transmit starting point; start transmission after N bytes written
    00 = 4 bytes
    01 = 16 bytes
    10 = 64 bytes
    11 = 112 bytes
 9-8    transmit FIFO low-water mark; start DMA when room for N bytes
    00 = 8 bytes
    01 = 16 bytes
    10 = 32 bytes
 7-0    DMA burst register
SeeAlso: #P241,#P245

Bitfields for AMD PCnet Chip ID register (read-only):
Bit(s)    Description    (Table P267)
 31-28    hardware version
 27-12    part number
    2623h = Am79C971
 11-1    manufacturer ID (0001h = AMD)
 0    reserved (1)
SeeAlso: #P250

Bitfields for AMD PCnet CSR122 Advanced Feature Control register:
Bit(s)    Description    (Table P268)
 15-1    reserved
 0    "RCVALGN"    DWORD-align received packets
SeeAlso: #P250,#P269

Bitfields for AMD PCnet CSR124 Test Register 1:
Bit(s)    Description    (Table P269)
 15-5    reserved
 4    (PCnet-SCSI) accept runt packets
 3    (PCnet-FAST) accept runt packets
 2-0    reserved
SeeAlso: #P250,#P268

Bitfields for AMD PCnet-FAST CSR125 MAC Enhanced Configuration Control reg:
Bit(s)    Description    (Table P270)
 15-8    inter-packet gap (reducing from default 96 can disrupt network)
 7-0    inter-frame spacing, part 1
SeeAlso: #P250

(Table P272)
Values for AMD PCnet-ISA ISA Bus Configuration Register index:
 00h    "MSRDA" width of DMA read signal
 01h    "MSWRA" width of DMA write signal
 02h    "MC"    ISA bus configuration (see #P248)
 05h    "LED1"    LED1 signal control (see #P249)
 06h    "LED2"    LED2 signal control (see #P249)
 07h    "LED3"    LED3 signal control (see #P249)
SeeAlso: #P241,#P251,#P247

(Table P247)
Values for AMD PCnet-SCSI Bus Configuration Register index:
 00h    "MSRDA" width of DMA read signal (reserved)
 01h    "MSWRA" width of DMA write signal (reserved)
 02h    "MC"    miscellaneous configuration (see #P248)
 03h    reserved
 04h    "LINKST" link status
 05h    "LED1"    LED1 signal control (see #P249) -- receive status
 06h    "LED2"    LED2 signal control (see #P249)
 07h    "LED3"    LED3 signal control (see #P249) -- transmit status
 08h-0Fh reserved
 10h    "IOBASEL"
 11h    "IOBASEU"
 12h    "BSBC"    burst size and bus control
 13h    "EECAS" EEPROM Control and Status
 14h    "SWS"    software style
 15h    "INTCON" reserved
SeeAlso: #P250,#P272,#P271

(Table P271)
Values for AMD PCnet-FAST Bus Configuration Register index:
 00h    "MSRDA"        width of DMA read signal (reserved)
 01h    "MSWRA"        width of DMA write signal (reserved)
 02h    "MC"        miscellaneous configuration (see #P248)
 03h    reserved    !!!p.154
 04h    "LED0"  LED0 status
 05h    "LED1"    LED1 signal control (see #P249) -- receive status
 06h    "LED2"    LED2 signal control (see #P249)
 07h    "LED3"    LED3 signal control (see #P249) -- transmit status
 08h    reserved
 09h    "FDC"        full-duplex control
 0Ah-0Fh reserved
 10h    "IOBASEL"    I/O base select (lo) -- reserved
 11h    "IOBASEU"    I/O base select (hi) -- reserved
 12h    "BSBC"        burst size and bus control
 13h    "EECAS"        EEPROM Control and Status
 14h    "SWS"        software style
 15h    "INTCON"    reserved
 16h    "PCILAT"    PCI-bus latency
 17h    "PCISID"    PCI subsystem ID
 18h    "PCISVID"    PCI subsystem vendor ID
 19h    "SRAMSIZ"    SRAM size
 1Ah    "SRAMB"        SRAM boundary
 1Bh    "SRAMIC"    SRAM interface control
 1Ch    "EBADDRL"    expansion bus address (low)
 1Dh    "EBADDRU"    expansion bus address (high)
 1Eh    "EBD"        expansion bus data port
 1Fh    "STVAL"        software timer value
 20h    "MIICAS"    MII control and status
 21h    "MIIADDR"    MII address
 22h    "MIIMDR"    MII management data
 23h    "PCIVID"    PCI vendor ID
SeeAlso: #P250,#P272,#P247

Bitfields for AMD PCnet ISA bus configuration:
Bit(s)    Description    (Table P248)
 3    EADISEL
 2    AWAKE
 1    ASEL
 0    XMAUSEL
SeeAlso: #P247,#P249

Bitfields for AMD PCnet LEDn signal control:
Bit(s)    Description    (Table P249)
 15    LEDOUT
 14-8    reserved
 7    PSE
 6-5    reserved
 4    XMTE
 3    RVPE
 2    RCVE
 1    JABE
 0    COLE
SeeAlso: #P247
----------P0300031F--------------------------
PORT 0300-031F - prototype cards
        Periscope hardware debugger
----------P030C030F--------------------------
PORT 030C-030F - AIMS LAB PC Radio

    configurable to 020C or 030C
----------P0310031F--------------------------
PORT 0310-031F - Philips CD-ROM player CM50
----------P03200323--------------------------
PORT 0320-0323 - XT HDC 1   (Hard Disk Controller)
SeeAlso: PORT 01F0h-01F7h

0320  RW  data register
0321  -W  reset controller
0321  R-  read controller hardware status (see #P099)
0322  R-  read DIPswitch setting on XT controller card
0322  -W  generate controller-select pulse
0323  -W  write pattern to DMA and INT mask register

Bitfields for XT hard disk controller hardware status:
Bit(s)    Description    (Table P099)
 7-6    always 0
 5    logical unit number
 4-2    always 0
 1    error occurred
 0    always 0
----------P03240327--------------------------
PORT 0324-0327 - XT HDC 2   (Hard Disk Controller)
----------P0328032B--------------------------
PORT 0328-032B - XT HDC 3   (Hard Disk Controller)
----------P032B------------------------------
PORT 032B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 036Bh,
      PORT 03ABh, PORT 03EBh
----------P032C------------------------------
PORT 032C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P032C032F--------------------------
PORT 032C-032F - XT HDC 4   (Hard Disk Controller)
----------P03300331--------------------------
PORT 0330-0331 - MIDI interface
----------P03300333--------------------------
PORT 0330-0333 - Adaptec 154xB/154xC SCSI adapter. default address.
Range:    alternate address at 0130, 0134, 0230, 0234 and 0334
----------P0330033F--------------------------
PORT 0330-033F - CompaQ SCSI adapter. alternate address at 0130
----------P0330033F--------------------------
PORT 0330-033F - Philips CD-ROM player CM50
----------P03340337--------------------------
PORT 0334-0337 - Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0130, 0134, 0230, 0234 and 0330
----------P0338------------------------------
PORT 0338 - AdLib soundblaster card
----------P0338033F--------------------------
PORT 0338-033F - COM port addresses on UniRAM card by German magazine c't
Range:    selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8
----------P0340034F--------------------------
PORT 0340-034F - Philips CD-ROM player CM50
----------P0340034F--------------------------
PORT 0340-034F - SCSI (1st Small Computer System Interface) adapter
Range:    alternate address at 0140-014F
----------P0340034F--------------------------
PORT 0340-034F - Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
Note:    the AMD InterWave chip provides a superset of the UltraSound's
      functionality, including these ports
SeeAlso: PORT 0240h-024Fh,PORT 0746h

0340  -W  MIDI Control (see #P100)
0340  R-  MIDI Status (see #P101)
0341  -W  MIDI Transmit Data
0341  R-  MIDI Receive Data
0342  RW  GF1 Page Register / Voice Select
0343  RW  GF1/Global Register Select (see #P102)
0344  RW  GF1/Global Data Low Byte (16 bits)
0345  RW  GF1/Global Data High Byte (8 bits)
0346  -W  Mixer Data Port
0347  RW  GF1 DRAM
         Direct Read Write at Loction pointed with regs 43 and 44

Bitfields for Gravis Ultra Sound MIDI control register:
Bit(s)    Description    (Table P100)
 7       Receive IRQ (1 = enabled)
 5-6   Xmit IRQ
 0-1   Master Reset (1 = enabled)
SeeAlso: #P093,#P095,#P101

Bitfields for Gravis Ultra Sound MIDI status register:
Bit(s)    Description    (Table P101)
 7    Interrupt pending
 5    Overrun Error
 4    Framing Error
 1    Transmit Register Empty
 0    Receive Register Empty
SeeAlso: #P100,#P102

(Table P102)
Values for Gravis Ultra Sound GF1/Global Registers:
---Voice specific registers---
 00h  w        Voice Control (see #P103)
 01h  w        Frequency Control
         bit 15-10     Integer Portion
         bit 9-1     Fractional Portion
 02h  w        Start Address HIGH
         bit 12-0     Address Lines 19-7
 03h  w        Start Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of Start Address
 04h  w        End Address HIGH
         bit 12-0     Address Lines 19-7
 05h  w        End Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of End Address
 06h  w        Volume Ramp Rate
         bit 5-0     Amount added
         bit 7-6     Rate
 07h  w        Volume Ramp Start
         bit 7-4     Exponent
         bit 3-0     Mantissa
 08h  w        Volume Ramp End
         bit 7-4     Exponent
         bit 3-0     Mantissa
 09h  w        Current Volume
         bit 15-12     Exponent
         bit 11-4     Mantissa
 0Ah  w        Current Address HIGH
         bit 12-0     Address Lines 19-7
 0Bh  w        Current Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-0     Fractional Position
 0Ch  w        Pan Position
         bit 3-0     Pan Postion
 0Dh  w        Volume Control (see #P104)
 0Eh  w        Active Voices
         bit 5-0     #Voices -1  (allowed 13 - 31)
 0Fh  w        IRQ Source Register (see #P105)
---NOT voice specific---
 41h  r/w   DRAM DMA Control (see #P106)
 42h  w        DMA Start Address
         bits 15-0     DMA Address Lines 19-4
 43h  w        DRAM I/O Address LOW
 44h  w        DRAM I/O Address HIGH
         bits 0-3     Upper 4 Address Lines
 45h  r/w   Timer Control
         bit 3     Enable Timer 2
         bit 2     Enable Timer 1
 46h  w        Timer 1 Count (granularity of 80 micro sec)
 47h  w        Timer 2 Count (granulatity of 320 micro sec)
 48h  w        Sampling Frequency
         rate = 9878400 / (16 * (FREQ + 2))
 49h  r/w   Sampling Control (see #P107)
 4Bh  w        Joystick Trim DAC
 4Ch  r/w   RESET
         bit 2     GF1 Master IRQ Enable
         bit 1     DAC Enable
         bit 0     Master Reset
---Voice specific registers---
 80h  r        Voice Control (see 00h)
 81h  r        Frequency Control (see 01h)
 82h  r        Start Address HIGH (see 02h)
 83h  r        Start Address LOW (see 03h)
 84h  r        End Address HIGH (see 04h)
 85h  r        End Address LOW (see 05h)
 86h  r        Volume Ramp Rate (see 06h)
 87h  r        Volume Ramp Start (see 07h)
 88h  r        Volume Ramp End (see 08h)
 89h  r        Current Volume (see 09h)
 8Ah  r        Current Address HIGH (see 0Ah)
 8Bh  r        Current Address LOW (see 0Bh)
 8Ch  r        Pan Position (see 0Ch)
 8Dh  r        Volume Control (see 0Dh)
 8Eh  r        Active Voices (see 0Eh)
 8Fh  r        IRQ Status (see 0Fh)
SeeAlso: #P101,#P251

(Table P251)
Values for InterWave synthesizer registers:
---voice-specific registers---
 10h  w     synthesizer  upper address
 11h  w        synthesizer effects address high (16 bits)
 12h  w        synthesizer effects address low (16 bits)
 13h  w        synthesizer left offset (16 bits)
 14h  w        synthesizer effects output accumulator select
 15h  w     synthesizer mode select
 16h  w     synthesizer effects volume (16 bits)
 17h  w     synthesizer frequency LFO
 18h  w     synthesizer volume LFO
---NOT voice-specific---
 19h  w     synthesizer global mode
 1Ah  w     synthesizer LFO base address (16 bits)
---voice-specific registers---
 1Bh  w     synthesizer right offset (16 bits)
 1Ch  w        synthesizer left offset (16 bits)
 1Dh  w     synthesizer effect volume final (16 bits)
---NOT voice-specific---
 41h  r/w   local memory control: DMA control
 42h  r/w   local memory control: DMA start address bits 19-4 (16 bits)
 43h  w     local memory control: I/O address low (16 bits)
 44h  w     local memory control: I/O address high (16 bits)
 45h  r/w   AdLib/SoundBlaster control
 46h  r/w   AdLib timer 1
 47h  r/w   AdLib timer 2
 49h  r/w   ADC sample control
 4Bh  r/w   joystick trim
 4Ch  w        GUS reset
 50h  r/w   local memory control: DMA start address bits 23-20/3-0 (16 bits)
 51h  r/w   local memory control: 16-bit access
 52h  r/w   local memory control: configuration
 53h  r/w   local memory control: control
 54h  r/w   local memory control: record FIFO base address bits 23-8 (16-bit)
 55h  r/w   local memory control: playback FIFO base address bits 23-8 (16-bit)
 56h  r/w   local memory control: FIFO size (16-bit)
 57h  r/w   local memory control: DMA interleave control (16-bit)
 58h  r/w   local memory control: DMA interleaev base address bits 23-8
 59h  r/w   compatibility control
 5Ah  r/w   decode control
 5Bh  r/w   version number
 5Ch  r/w   MPU-401 emulation control A
 5Dh  r/w   MPU-401 emulation control B
 5Eh  w     MIDI receive FIFO access
 5Fh  -        reserved
 60h  r/w   emulation IRQ
---voice-specific registers---
 90h  r     synthesizer  upper address
 91h  r        synthesizer effects address high (16 bits)
 92h  r        synthesizer effects address low (16 bits)
 93h  r        synthesizer left offset (16 bits)
 94h  r        synthesizer effects output accumulator select
 95h  r     synthesizer mode select
 96h  r     synthesizer effects volume (16 bits)
 97h  r     synthesizer frequency LFO
 98h  r     synthesizer volume LFO
---NOT voice-specific---
 99h  r     synthesizer global mode
 9Ah  r     synthesizer LFO base address (16 bits)
---voice-specific registers---
 9Bh  r     synthesizer right offset (16 bits)
 9Ch  r        synthesizer left offset (16 bits)
 9Dh  r     synthesizer effect volume final (16 bits)
---NOT voice-specific---
 9Fh  r        synthesizer voices IRQ
Note:    these registers are *in*addition* to the Gravis UltraSound registers
SeeAlso: #P102

Bitfields for Gravis Ultra Sound voice control global register:
Bit(s)    Description    (Table P103)
 7     IRQ pending
 6     Direction
 5     Enable WAVE IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Size data (8/16 bits)
 1     Stop Voice
 0     Voice Stopped
SeeAlso: #P102,#P104

Bitfields for Gravis Ultra Sound volume control global register:
Bit(s)    Description    (Table P104)
 7     IRQ Pending
 6     Direction
 5     Enable Volume Ramp IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Rollover Condition
 1     Stop Ramp
 0     Ramp Stopped
SeeAlso: #P102,#P103

Bitfields for Gravis Ultra Sound IRQ source register:
Bit(s)    Description    (Table P105)
 7     WaveTable IRQ pending
 6     Volume Ramp IRQ pending
 4-0     Voice Number
SeeAlso: #P102,#P103,#P106

Bitfields for Gravis Ultra Sound DRAM DMA control register:
Bit(s)    Description    (Table P106)
 7     Invert MSB
 6     Data Size (8/16 bits)
 5     DMA Pending
 3-4     DMA Rate Divider
 2     DMA Channel Width (8/16 bits)
 1     DMA Direction (1 = read)
 0     DMA Enable
SeeAlso: #P102,#P105

Bitfields for Gravis Ultra Sound sampling control register:
Bit(s)    Description    (Table P107)
 7     Invert MSB
 6     DMA IRQ pending
 5     DMA IRQ enable
 2     DMA width (8/16 bits)
 1     Mode (mone/stereo)
 0     Start Sampling
SeeAlso: #P102
----------P03400357--------------------------
PORT 0340-0357 - RTC (1st Real Time Clock for XT)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
Range:    alternate at 0240-0257
SeeAlso:  PORT 0240h-0257h

0340  RW  0.001 seconds        0-99
0341  RW  0.1 and 0.01 seconds    0-99
0342  RW  seconds        0-59
0343  RW  minutes        0-59
0343  RW  hours            0-23
0345  RW  day of week        1-7
0346  RW  day of month        1-31
0347  RW  month            1-12
0348  RW  RAM (upper nybble only)
0349  RW  year            0-99
034A  RW  RAM last month storage
034B  RW  RAM year storage (-80)
034C  RW  RAM reserved
034D  RW  RAM not used
034E  RW  RAM not used
034F  RW  RAM not used
0350  R-  interrupt status register
0351  -W  interrupt control register
0352  -W  counter reset
0353  -W  RAM reset
0354  R-  status bit
0355  -W  GO command
0356  ??  standby interrupt
0357  ??  test mode
----------P03480357--------------------------
PORT 0348-0357 - DCA 3278
----------P034C034F--------------------------
PORT 034C-034F - Gravis UltraMax by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
----------P035A035B--------------------------
PORT 035A-035B - Adaptec AH1520 jumper settings

035A  R      I/O channel setup (see #P108)
035B  R      transfer mode setup (see #P109)

Bitfields for Adaptec AH1520 channel setup jumper settings:
Bit(s)    Description    (Table P108)
 7    SCSI parity disabled
 6-5    DMA channel (00 = channel 0, 01 = 5, 10 = 6, 11 = 7)
 4-3    IRQ number (00 = IRQ9, 01 = IRQ10, 10 = IRQ11, 11 = IRQ12)
 2-0    SCSI ID
SeeAlso: #P109

Bitfields for Adaptec AH1520 transfer mode setup jumper settings:
Bit(s)    Description    (Table P109)
 7    DMA transfer mode (clear for PIO)
 6    boot enabled
 5-4    boot type
    00 ???
    01 boot from floppy
    10 print configured options
    11 boot from hard disk
 3    enable sync negotiation
 2    enable target disconnection
 1-0    unused???
SeeAlso: #P108
----------P035F------------------------------
PORT 035F - ARTEC Handyscanner A400Z.  alternate address at 15F.
----------P03600367--------------------------
PORT 0360-0367 - PC network (XT only)
----------P0360036F--------------------------
PORT 0360-036F - PC network (AT)
----------P0360036F--------------------------
PORT 0360-036F - National Semiconductor DP8390(1)C/NS3249C network chipset
Note:    cards based on this IEEE 802.3 networking chipset can use any range
      of 16 consecutive addresses, and provide a total of four pages of
      sixteen registers (see #P110,#P111,#P112,#P143)

(Table P110)
Values for NS DP8390C/NS3249C network chipset Page 0 registers:
Number    Read Register                Write Register
 00h    Command reg. (see #P114)    CR    Command reg.        CR
 01h    current local DMA address 0    CLDA0    page start reg.        PSTART
 02h    current local DMA address 1    CLDA1    page stop reg.        PSTOP
 03h    boundary pointer        BNRY    boundary pointer    BNRY
 04h    transmit status reg.        TSR    Tx page start address    TPSR
 05h    number of collisions reg.    NCR    Tx byte count reg.0    TBCR0
 06h    FIFO                    Tx byte count reg.1    TBCR1
 07h    interrupt status reg.        ISR    interrupt status reg.    ISR
 08h    current remote DMA address 0    CRDA0    remote start addr.reg.0 RSAR0
 09h    current remote DMA address 1    CRDA1    remote start addr.reg.1 RSAR1
 0Ah    reserved                remote byte count reg.0 RBCR0
 0Bh    reserved                remote byte count reg.1 RBCR1
 0Ch    receive status reg.        RSR    Rx configuration reg.    RCR
 0Dh    tally counter 0 (frame errors)    CNTR0    Tx configuration reg.    TCR
 0Eh    tally counter 1 (CRC errors)    CNTR1    data configuration reg. DCR
 0Fh    tally counter 2 (missed pkt)    CNTR2    interrupt mask reg.    IMR
SeeAlso: #P111,#P112,#P113

(Table P111)
Values for NS DP8390C/NS3249C network chipset Page 1 registers:
Number    Read/Write
 00h    Command            CR (see #P114)
 01h    physical address reg.0    PAR0
 02h    physical address reg.1    PAR1
 03h    physical address reg.2    PAR2
 04h    physical address reg.3    PAR3
 05h    physical address reg.4    PAR4
 06h    physical address reg.5    PAR5
 07h    current page reg.    CURR
 08h    multicast address reg.0 MAR0
 09h    multicast address reg.1 MAR1
 0Ah    multicast address reg.2 MAR2
 0Bh    multicast address reg.3 MAR3
 0Ch    multicast address reg.4 MAR4
 0Dh    multicast address reg.5 MAR5
 0Eh    multicast address reg.6 MAR6
 0Fh    multicast address reg.7 MAR7
SeeAlso: #P110,#P112,#P113

(Table P112)
Values for NS DP8390C/NS3249C network chipset Page 2 registers:
Number    Read Register                Write Register
 00h    Command                CR    Command             CR
 01h    page start reg.            PSTART    current local DMA addr.0 CLDA0
 02h    page stop reg.            BPSTOP    current local DMA addr.1 CLDA1
 03h    remote next packet pointer        remote next packet pointer
 04h    Tx page start address        TPSR    reserved
 05h    local next packet pointer        local next packet pointer
 06h    address counter (upper)            address counter (upper)
 07h    address counter (lower)            address counter (lower)
 08h    reserved                reserved
 09h    reserved                reserved
 0Ah    reserved                reserved
 0Bh    reserved                reserved
 0Ch    Rx configuration reg.        RCR    reserved
 0Dh    Tx configuration reg.        TCR    reserved
 0Eh    data configuration reg.        DCR    reserved
 0Fh    interrupt mask reg.        IMR    reserved
Note:    this is a diagnostics page, and should never be modfied under normal
      operation.
SeeAlso: #P110,#P111,#P113

(Table P113)
Values for NS DP8390C/NS3249C network chipset Page 3 registers:
Number    Read Register                Write Register
 00h    Command CR (see #P114)            Command CR
Note:    Test Page - should never be modified!
SeeAlso: #P110,#P111,#P112

Bitfields for NS DP8390C/NS3249C network chipset command register (00h):
Bit(s)    Description    (Table P114)
 0    software reset command (1=offline, 0=online)
 1    do not activate NIC after reset command
 2    start transmision of a packet
 3-5    remote DMA command
    000 not allowed
    001 remote read
    010 remote write
    011 send packet
    1xx abort/complete rmote DMA
 6-7    page select
    00 register page 0
    01 register page 1
    10 register page 2
    11 register page 3
SeeAlso: #P113
----------P036B------------------------------
PORT 036B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
      PORT 03ABh, PORT 03EBh
----------P036C------------------------------
PORT 036C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P03700377--------------------------
PORT 0370-0377 - FDC 2    (2nd Floppy Disk Controller)    first FDC at 03F0
Note:    floppy disk controller is usually an 8272, 8272A, NEC765 (or
      compatible), or an 82072 or 82077AA for perpendicular recording at
      2.88M
SeeAlso: PORT 03F0h-03F7h

0370  R-  diskette Extra High Density controller board jumpers (AT)
0370  R-  diskette controller status A (PS/2, PS/2 model 30)
0371  R-  diskette controller status B (PS/2, PS/2 model 30)
0372  -W  diskette controller DOR (Digital Output Register)
0374  R-  diskette controller main status register
0374  -W  diskette controller datarate select register
0375  RW  diskette controller command/data register
0376  RW  (2nd FIXED disk controller status/data register)
0377  RW  (2nd FIXED disk controller drive address register)
0377  R-  diskette controller DIR (Digital Input Register)
0377  -W  select register for diskette data transfer rate
----------P0378------------------------------
PORT 0378 - Covox 'Speech Thing' COMPATIBLE SPEECH OUTPUT
SeeAlso: PORT 022Fh"mc-soundmachine",PORT 0388h-038Fh"soundmachine"

0378  -W  speech output via printer port
      (with mc-soundmachine, enabled if bit4=1 in 38F)
----------P0378037A--------------------------
PORT 0378-037A - parallel printer port, same as 0278 and 03BC

0378  -W  data port
0379  RW  status port
037A  RW  control port

037B  ??  bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
----------P0380038F--------------------------
PORT 0380-038F - 2nd BSC (Binary Synchronous Communication) adapter
SeeAlso:  PORT 03A0h"BSC"
----------P0380038C--------------------------
PORT 0380-038C - 2nd SDLC (Synchronous Data Link Control) adapter
Notes:    Initialization of the SDLC adapter is performed in a typical
      sequence like this: Setup 8255 port A-C configuration by writing
      98h to 383h, followed by initializing 8255 port C by writing 0Dh
      to 382h. Reset 8273 internal registers by pulsing 8255 port B4.
      After this the 8253 has to be programmed to the desired values
      (counter 0 in mode 3). Now the 8273 is ready to be configured for
      the operating mode that defines the communication environment in
      which it will be used.
    Note on 8273: Each 8273 protocol controllers internal register is
      programmed by individual set/reset commands (via 388h) in
      conjunction with a parameter (via 389h) that give an OR/AND mask
      to the internal register value.
      Although the 8273 is a full duplex device, there is only one
      command register. Thus, the command register must be used for
      only one command sequence at a time and the transmitter and
      receiver may never be simultaneously in a command phase.
      The system software starts the command phase by writing a command
      byte into the command register. If further information is required
      by the 8273 prior to execution of the command, the system software
      must write the list of parameters into the parameter register.
SeeAlso: PORT 03A0h"SDLC"

0380  R-   on adapter 8255(A5) port A: internal/external sensing (see #P115)
0381  -W   on adapter 8255(A5) port B: external modem interface (see #P116)
0382  RW   on adapter 8255(A5) port C: internal control (see #P117)
0383  ?W   on adapter 8255(A5) mode initialization
0384  RW   on adapter 8253 (programmable counter) counter 0:
        LSB / MSB square wave generator (input for timer 2, connected
          to 8255 bitC5)
0385  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
        (connected to 8255 bitA7, IRQ4 level)
0386  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
        (connected to 8255 bitA6, IRQ4 level)
0387  ?W   on adapter 8253 mode register (see #P118)
0388  R-   on adapter 8273 status register (see #P119)
0388  -W   on adapter 8273 command register (see #P120)
0389  R-   on adapter 8273 (immediate) result register (see #P127)
0389  -W   on adapter 8273 parameter register
        Commands issued via PORT 0388h may need additional parameters,
          which have to be passed through this port (see table).
038A  R-   on adapter 8273 transmit INT status (DMA/INT)
038A  -W   on adapter 8274 reset
038B  R-   on adapter 8273 receive INT status (DMA/INT)
038C  -W   on adapter 8273 data: direct program control (DPC)
      scratch-pad

Bitfields for SDLC 8255 port A:
Bit(s)    Description    (Table P115)
 7    =1 timer 1 output active
 6    =1 timer 2 output active
 5    =1 modem status changed
 4    receive clock active (if pulsing)
 3    =0 clear to send is on from interface
 2    transmit clock active (if pulsing)
 1    =0 data carrier detect is on from interface
 0    =0 ring indicator is on from interface
SeeAlso: #P116,#P117

Bitfields for SDLC 8255 port B:
Bit(s)    Description    (Table P116)
 7    enable IRQ 4 level interrupt
 6    =1 gate timer 1
 5    =1 gate timer 2
 4    =1 reset 8273
 3    =1 reset modem status changed logic
 2    =0 turn on test
 1    =0 turn on select standby at modem interface
 0    =0 turn on data signal rate select at modem interface
SeeAlso: #P115,#P117

Bitfields for SDLC 8255 port C:
Bit(s)    Description    (Table P117)
 7 R-    =? not used (detection: =1 SDLC, =0 may be SDLC or BSC??)
 6 R-    =0 test indicate active
 5 R-    timer 0 output (if pulsing)
 4 R-    receive data (if pulsing)
 3 -W    =0 gate interrupts 3 and 4
 2 -W    =1 electronic wrap
 1 -W    =1 gate external clock
 0 -W    =1 gate internal clock
SeeAlso: #P115,#P116

Bitfields for SDLC 8253 mode register:
Bit(s)    Description    (Table P118)
 7-6    SC1-SC0     00, 01, 10= select counter 0,1,2; 11=illegal
 5-4    RL1-RL0     00= couner latching operation
         01= read/load most significant byte (MSB)
         10= read/load least significant byte (LSB)
         11= read/load LSB first, then MSB
 3-1    M2-M0     000= mode 0
         001= mode 1
         x10= mode 2
         x11= mode 3
         100= mode 4
         101= mode 5
 0    BCD     0= binary counter 16bits
         1= BCD counter 4 decades

Bitfields for SDLC 8273 status register:
Bit(s)    Description    (Table P119)
 7    =1 command busy (CBSY)
 6    =1 command buffer full (CBF)
 5    =1 command parameter buffer full (CPBF)
 4    =1 command result buffer full (CRBF)
 3    =1 Rx interupt (RxINT)
 2    =1 Tx interupt (TxINT)
 1    =1 RxINT result available (RxIRA)
 0    =1 TxINT result available (TxIRA)
SeeAlso: #P120

(Table P120)
Values for SDCL 8273 command register:
 commands:           parameters:    results:   result port: int:
  A4: set one-bit delay        set mask     -           -    no
  64: reset one-bit delay   reset mask     -           -    no
  97: set data transfer        set mask     -           -    no
  57: reset data transfer   reset mask     -           -    no
  91: set operating mode    set mask     -           -    no
  51: reset operating mode  reset mask     -           -    no
  A0: set serial I/O mode   set mask     -           -    no
  60: reset serial I/O mode reset mask     -           -    no
  C0: general receive        B0,B1     RIC,R0,R1,A,C RXI/R   yes
  C1: selective receive        B0,B1,A1,A2     RIC,RD,R1,A,C RXI/R   yes
  C5: receive disable        -         -           -    no
  C8: transmit frame        L0, L1, A, C TIC           TXI/R   yes
  C9: transmit transparent  L0, L1     TIC           TXI/R   yes
  CC: abort transmit frame  -         TIC           TXI/R   yes
  CD: abort transmit        -         TIC           TXI/R   yes
  22: read 8273 port A        -         port value    result    no
  23: read 8273 port B        -         port value    result    no
  A3: set 8273 port A bit   set mask     -           -    no
  63: set 8273 port B bit   reset mask     -           -    no
Notes:    B0/B1 LSB/MSB of the receiver buffer length
    L0/L1 LSB/MSB of the Tx buffer length
    A1/A2 receive frame address match field one/two
    A     address fieldof received frame. In non-buffered mode, this
          result is not provided.
    C     control field of received frame. In non-buffered mode, this
          result is not provided.
    RXI/R TXI/R receive/transmit interrupt result register
    R0/R1 LBS/MSB of the length of the frame received
    RIC/TIC receiver/transmitter interrupt result code
SeeAlso: #P121,#P122,#P123,#P124,#P125,#P126

Bitfields for SDLC 8273 interal port A: Modem Control Input Port:
Bit(s)    Description    (Table P121)
 7-5    not used
 4    DSR change (PA4)
 3    CTS change (PA3)
 2    Data Set Ready (PA2)
 1    Carrier Detect (PA1)
 0    Clear to Send (PA0)
SeeAlso: #P120

Bitfields for SDLC 8273 interal port B: Modem Control Output Port:
Bit(s)    Description    (Table P122)
 7-6    not used
 5    Flag Detect (PB5)
 4-3    reserved
 2    Data Terminal Ready (PB2)
 1    reserved (PB1)
 0    Request to Send (PB0)
SeeAlso: #P120

Bitfields for SDLC 8273 internal: Operating Mode Register:
Bit(s)    Description    (Table P123)
 7-6    not used
 5    =1 HDLC abort enable
 4    =1 EOP interrupt enable
 3    =1 enable early Tx interrupt
 2    =1 Buffered Mode
 1    =1 Two Preframe Sync Characters
 0    =1 Flag Stream Mode
SeeAlso: #P120

Bitfields for SDLC 8273 internal: Serial I/O Register:
Bit(s)    Description    (Table P124)
 7-3    not used
 2    =1 Data Loopback
 1    =1 Clock Loopback
 0    =1 NRZI Mode
SeeAlso: #P120

Bitfields for SDLC 8273 internal: Data Transfer Mode Register:
Bit(s)    Description    (Table P125)
 7-1    not used
 0    =1 Interrupt Data Transfers
SeeAlso: #P120

Bitfields for SDLC 8273 internal: One-Bit Delay Mode Register:
Bit(s)    Description    (Table P126)
 7 =1    One-Bit Delay Enable
 6-0    not used
SeeAlso: #P120

(Table P127)
Values for SDLC 8273 result register:
 transmit result codes:         status after interrupt:
  0C: early transmit interrupt      transmitter active
  0D: frame transmit complete      idle or flags
  0E: DMA underrun          abort
  0F: clear to send error      abort
  10: abort complete          idle or flags
 receive result codes:
  X0: A1 match / general receive  active
  X1: A2 match              active
  03: CRC error              active
  04: abort detected          active
  05: idle detected          disabled
  06: EOP detected          disabled
  07: frame less than 32 bits      active
  08: DMA overrun          disabled
  09: memory buffer overflow      disabled
  0A: carrier detect failure      disabled
  0B: receiver interrupt overrun  disabled
 X bits received inlast byte:
   E: all eight bits of last byte (bit7-0)
   0: bit0 only
   8: bit1-0
   4: bit2-0
   C: bit3-0
   2: bit4-0
   A: bit5-0
   6: bit6-0
----------P03880389--------------------------
PORT 0388-0389 - AdLib - MONO SOUND OUTPUT
Note:    also supported by SoundBlaster and compatibles
SeeAlso: PORT 0220h-0223h,PORT 0388h-038Fh"soundmachine"

0388  R-  both speakers -- Status
        bit7  : interrupt request (IRQ)
        bit6  : timer 1 overflow
        bit5  : timer 2 overflow
        bit4-0: reserved
0388  -W  both speakers -- Address port (see #P128)
    index in OPL2 (YMF3812), OPL3 (YMF262), OPL4 (YF278-F)
0389  -W  data port
Note:    the AdLib requires a delay of 3.3 microseconds between writing to
      PORT 0388h and writing to PORT 0389h, and a delay of 23 microseconds
      after a write to PORT 0389h before any other operation is allowed

(Table P128)
Values for AdLib address port index:
 01h    Enable waveform control
    bit 7-6: (OPL4, OPL3 in OPL2 mode only) lsi test
    bit 5: (OPL2 only) wave select enable (WS)
           (OPL4, OPL3) lsi test
    bit 4-0: lsi test
 02h    Timer #1 data (OPL2 and OPL3 in OPL2 mode only)
 03h    Timer #2 data (OPL2 and OPL3 in OPL2 mode only)
 04h    Timer control flags (OPL2 and OPL3 in OPL2 mode only)
    bit 7  : reset interrupt (RST)
    bit 6  : timer 1 mask (MASK1)
    bit 5  : timer 2 mask (MASK2)
    bit 4-2: reserved
    bit 1  : start timer 2 (ST2)
    bit 0  : start timer 1 (ST1)
 04h    (OPL3 in OPL3 mode only) connection select
    bit 7-6: reserved
    bit 5-0: connection selection
 05h    (OPL3) compatibility register
    bit 7-1: reserved
    bit 0: enable OPL3 mode (NEW), default disabled
 08h    Speech synthesis mode
    bit 7: (OPL2 only) speech synthesis or FM music mode (CSM)
    bit 6: select keyboard split point (SEL/NTS)
    bit 5-0: reserved
 20h-35h Amplitude Modulation / Vibrato
    bit 7: AM modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: sustain (EG)
    bit 4: keyboard scaling rate (KSR)
    bit 3-0: multi (MF)
 40h-55h Level key scaling / Total level
    bit 7-6: key scale level (KSL)
    bit 5-0: total level (TL)
 60h-75h Attack / Decay rate
    bit 7-4: attack rate
    bit 3-0: decay rate
 80h-95h Sustain / Release rate
    bit 7-4: sustain level
    bit 3-0: release rate
 A0h-A8h Octave / Frequency (LSB)
 A9h-AFh ???
 B0h-B8h Octave / Frequency Number
    bit 7-6: reserved
    bit 5  : key on, mute
    bit 4-2: block, octave
    bit 1-0: f-number (MSB)
 BDh    percussion, vibrato, AM    (OPL2, OPL3 in OPL2 mode only)
    bit 7: amplitude modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: ryhthm, percussion on/off (R)
    bit 4: bass drum on/off (BD)
    bit 3: snare drum on/off (SD)
    bit 2: tom-tom on/off (TOM)
    bit 1: top cymbal on/off (TC)
    bit 0: hi hat on/off (HH)
 C0h-C8h Feedback / Algorithm
    bit 7-4: OPL3: channel D-A
    bit 3-1: feedback
    bit 0: connection
 E0h-F5h Waveform Selection
    bit 7-3: reserved
    bit 2  : (OPL3) waveform bit2
    bit 1-0: waveform
SeeAlso: #P129

(Table P129)
Values for Sound Blaster registers inside groups:
Offset
 +00..+02: operators 1-3    modulator channel 1-3
 +03..+05: operators 4-6    carrier channel 1-3
 +08..+0A: operators 7-9    modulator channel 4-6
 +0B..+0D: operators 10-12  carrier channel 4-6
 +10..+12: operators 13-15  modulator channel 7-9
 +13..+15: operators 16-18  carrier channel 7-9
 +06, +07, +0E, +0F: reserved
SeeAlso: #P128
----------P03880389--------------------------
PORT 0388-0389 - Soundblaster PRO FM-Chip
----------P0388038B--------------------------
PORT 0388-038B - Soundblaster 16 ASP FM-Chip
----------P0388038F--------------------------
PORT 0388-038F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    Adlib-compatible, Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 022Fh"soundmachine",PORT 0278h"Covox"

0388  -W  Covox 'speech thing' compatible speech output via printer port?
        enabled if bit 6 set in PORT 038Fh
0388  RW  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster")
0389  -W  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster")
038A  -W  I²C control for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA out (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL out (clock), enabled if bit2=1 in PORT 038Fh
038B  R-  I²C status for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA in (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL in (clock), enabled if bit2=1 in PORT 038Fh
038F  RW  configuration port (power on default=0, all features disabled)
    (see #P130)

Bitfields for mc-soundmachine configuration port:
Bit(s)    Description    (Table P130)
 7    Covox 'voice master' enabled at PORT 022Fh
 6     ""   'speech thing' enabled at PORT 03BCh
 5     ""             enabled at PORT 0278h
 4     ""             enabled at PORT 0378h
 3    not used (0388???)
 2    I²C bus enabled (see PORT 038Ah,PORT 038Bh)
 1    gameport enabled (see PORT 0201h)
 0    AdLib registers (see PORT 0388h,PORT 0389h) enabled
----------P03900397--------------------------
PORT 0390-0397 - Sunshine EW-901B, EW-904B
        EPROM writer card for EPROMs up to 27512
0390-0393  ??  adresses of the 8255 on the EW-90xB
----------P0390039F--------------------------
PORT 0390-039F - Cluster adapter (AT)

0390  ??  (adapter 0)    (XT)
0391  ??  (adapter 0)    (XT)
0392  ??  (adapter 0)    (XT)
0393  ??  (adapter 0)    (XT)
----------P03980399--------------------------
PORT 0398-0399 - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 026Eh

0398  -W  index for data port
0399  RW  EPP command data
----------P03A003AC--------------------------
PORT 03A0-03AC - 1st SDLC (Binary Synchronous Data Link Control adapter)
SeeAlso: PORT 0380h"SDLC"
----------P03A003AF--------------------------
PORT 03A0-03AF - 1st BSC (Binary Synchronous Communication) adapter
Notes:    Initialization of the BSC adapter is performed in a typical
      sequence like this: Setup 8255 port A-C configuration by writing
      98h to 383h, followed by initializing 8255 port C by writing 0Dh
      to 382h. Reset 8251A internal registers by pulsing 8255 port B4.
      After this the 8253 has to be programmed to the desired values
      (counter 0 not used, counters 1 and 2 to mode 0). Now, the 8251A
      is ready to be loaded with a set of control words that define the
      communication environment.
    8251A: The control words are split into two formats, mode
      instruction and command instruction. The mode instruction must
      be inserted immediately after a reset operation (via 8255 port B4
      or setting command instruction bit6 to 'internal reset').
      The required synchronization characters are next loaded into the
      8251A (usually 32h for BSC). All control words written to the
      8251A after this will load the command instruction.
         reset -> mode instruction
              SYNC character 1
              SYNC character 2
              command instruction
              data ...
              command instruction
              data ...
              command instruction
              ...
SeeAlso: PORT 0380h"BSC"

03A0  R-   on adapter 8255(A5) port A: internal/external sensing (see #P131)
03A1  -W   on adapter 8255(A5) port B: external modem interface (see #P132)
03A2  RW   on adapter 8255(A5) port C: internal control (see #P133)
03A3  ?W   on adapter 8255(A5) mode initialization
03A4  RW   on adapter 8253 (programmable counter) counter 0:
        LSB / MSB square wave generator (unused in sync mode)
03A5  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
        (connected to 8255 bitA7, IRQ4 level)
03A6  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
        (connected to 8255 bitA6, IRQ4 level)
03A7  ?W   on adapter 8253 mode register (see #P134)
03A8  RW   on adapter 8251: data (see #P135)
03A9  R-   on adapter 8251: command/mode/USART status register (see #P136)

Bitfields for BSC 8255 port A:
Bit(s)    Description    (Table P131)
 7    =1 timer 1 output active
 6    =1 timer 2 output active
 5    =1 TxRDY active
 4    receive clock active (if pulsing)
 3    =0 clear to send is on from interface
 2    transmit clock active (if pulsing)
 1    =0 data carrier detect is on from interface
 0    =0 ring indicator is on from interface
SeeAlso: #P132

Bitfields for BSC 8255 port B:
Bit(s)    Description    (Table P132)
 7    =1 enable IRQ 4 level interrupt (timer 1 and 2)
 6    =1 gate timer 1
 5    =1 gate timer 2
 4    =1 reset 8251A
 3    =1 not used
 2    =0 turn on test
 1    =0 turn on select standby
 0    =0 turn on data signal rate select
SeeAlso: #P131,#P133

Bitfields for BSC 8255 port C:
Bit(s)    Description    (Table P133)
 7 R-    =0 BSC adapter (=1 may be used to detect SDLC??)
 6 R-    =0 test indicate active
 5 R-    timer 0 output (if pulsing)
 4 R-    receive data (if pulsing)
 3 -W    =0 enable timer 1 and 2 IRQ4 and receive IRQ 4
 2 -W    =1 electronic wrap
 1 -W    =1 gate external clock
 0 -W    =1 gate internal clock
SeeAlso: #P131,#P132

Bitfields for BSC 8253 mode register:
Bit(s)    Description    (Table P134)
 7-6    SC1-SC0     00, 01, 10= select counter 0,1,2; 11=illegal
 5-4    RL1-RL0     00= couner latching operation
         01= read/load most significant byte (MSB)
         10= read/load least significant byte (LSB)
         11= read/load LSB first, then MSB
 3-1    M2-M0     000= mode 0 (for counter 1 and 2)
         001= mode 1 (not used for BSC)
         x10= mode 2 (not used for BSC)
         x11= mode 3 (not used for BSC)
         100= mode 4 (not used for BSC)
         101= mode 5 (not used for BSC)
 0    BCD       0= binary counter 16bits
           1= BCD counter 4 decades

Bitfields for BSC 8251 data:
Bit(s)    Description    (Table P135)
---mode instruction (W)---
 7    =0 Double SYNC Character
 6    =1 SYNDET is an Input
 5    =1 Even Parity
 4    =1 Parity Enable
 3-2    Character Length 00=5bits, 01=6bits, 10=7bits, 11=8bits
 1-0    not used (always 0)
---SYNC character 1/2 (W)---
 string of two characters to be sync'ed at (in hunt mode).
---command instruction (W)---
 7    Enter Hunt Mode
 6    Internal Reset
 5    Request to Send
 4    Error Reset
 3    Send Break Character
 2    Receive Enable
 1    Data Terminal Ready
 0    Transmit Enable
---data (RW)---
    any data
SeeAlso: #P134,#P136

Bitfields for BSC 8251 command/mode/USART status:
Bit(s)    Description    (Table P136)
 7    Data Set Ready (indicated that DSR is at 0 level)
 6    SYNDET
 5    Framing Error (not used for synchronous communications)
 4    Overrun Error (OE flag on when Overrun Error occurs)
 3    Parity Error (PE flag on when a parity error occurs)
 2    TxEmpty
 1    RxRDY (causing IRQ 3 level)
 0    TxRDY (has not the same meaning as 8251A TxRDY output pin).
      THIS one is NOT conditioned by CTS and TxEnable (causing IRQ 4 level)
SeeAlso: #P135
----------P03AB------------------------------
PORT 03AB - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
      PORT 036Bh, PORT 03ABh, PORT 03EBh
----------P03AC------------------------------
PORT 03AC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P03B003BF--------------------------
PORT 03B0-03BF - MDA  (Monochrome Display Adapter based on 6845)

03B0  -W  same as 03B4
03B1  RW  same as 03B5
03B2  -W  same as 03B4
03B3  RW  same as 03B5
03B4  -W  MDA CRT index register     (MDA/mono EGA/mono VGA)
        selects which register (0-11h) is to be accessed through 03B5h
        Note: this port is read/write on some VGAs
        bit7-6: (VGA) reserved (0)
        bit5  : (VGA) reserved for testing (0)
        bit4-0: selects which register is to be accessed through 03B5h
03B5  RW  MDA CRT data register     (MDA/mono EGA/mono VGA) (see #P137)
        selected by PORT 03B4h. registers 0C-0F may be read
        Color adapters are at 3D4/3D5, but are mentioned here for
          better overview.
        There are differences in names and some bits functionality
          on EGA, VGA in their native modes, but clones in their
          emulation modes emulate the original 6845 at bit level. The
          default values are for MDA, HGC, CGA only, if not otherwise
          mentioned.
03B6  -W  same as 03B4h
03B7  RW  same as 03B5h
03B8  rW  MDA mode control register (see #P138)
03B9  ?W  reserved for color select register on color adapter
03B9  -W  MDA/HGC: set lightpen flipflop (value written is ignored)
        cannot be found on native mono EGA, mono VGA (without
          translation ROM)
03BA  R-  CRT status register (see #P139)
        (EGA/VGA) input status 1 register
03BA  -W  (mono EGA/mono VGA) feature control register
        (see PORT 03DAh-W for details; VGA, see PORT 03CAh-R)
03BB  -W  light pen strobe reset (on any value)

(Table P137)
Values for mono video adapter CRT data register index:
                  defaults:    MDA/HGC    HGC   CGA   CGA      CGA
                         text  graph text1 text2 graph
                           7  720x348  1     3      5,6
 00h    horizontal total              61h    35h   38h   71h      38h
          ET4000: in VGA mode scanlines-5
              in EGA mode scanlines-2
 01h    horizontal displayed              50h    2Dh   28h   50h      28h
          horizontal display end-1 (EGA,VGA)
 02h    horizontal sync position          52h    2Eh   2Dh 5Ah/5Ch 2Dh
 03h    sync pulse width              0Fh 07h/0Fh 0Ah   0Ah      0Ah
           bit7-4 vsync, bit3-0 hsync
          end horizontal blanking (EGA,VGA)
           VGA    : bit7=1      : enable read access to regs
                    10h, 11h (otherwise VGA clones
                    may show lightpen values)
           EGA,VGA: bit6-5=0-3: display enable skew control
            bit4-0      : end blanking
 04h    vertical total (vcycle-1)          19h    5Bh   1Fh   1Fh      7Fh
           bit7 only used on MCGA
          start horizontal retrace (EGA, VGA)
          Genoa SuperEGA only???:
           bit7  : start at odd memory address
           bit6-5: horizontal sync skew
           bit4-0: start retrace+ retrace width
 05h    vertical total adjust              06h    02h   06h   06h      06h
           bit7-5 only used on MCGA
          end horizontal retrace (EGA, VGA)
           bit7  : (EGA) start at odd memory address
               (VGA) bit5 of end horizontal retrace
           bit6-5: horizontal sync skew
           bit4-0: end horizontal retrace
 06h    vertical displayed              19h    57h   19h   19h      64h
           bit7 only used on MCGA
          (EGA) vertical total-1
          (VGA) vertical total-2
 07h    vertical sync pulse width-1          19h    57h   1Ch   1Ch 70h/66h
           bit7  only used on MCGA
          controller overflow (EGA,VGA)
           bit7: (VGA) bit9 of start vertical retrace (10h)
           bit6: (VGA) bit9 of vertical display end (12h)
           bit5: (VGA) bit9 of vertical total (06h)
             (EGA) bit5 of cursor-position (0Ah)
           bit4: bit8 of line compare (18h)
           bit3: bit8 of start vertical blanking (15h)
           bit2: bit8 of vertical retrace start (10h)
           bit1: bit8 of vertical display end (12h)
           bit0: bit8 of vertical total (06h)
 08h    interlace mode (not MCGA)          02h    02h   02h   02h      02h
           bit7-2: reserved
           bit1  : delay
           bit0=1: interlace on
          preset row scan (EGA, VGA)
           bit7  : reserved
           bit6-5: (VGA) byte panning
           bit4-0: start row scan after retrace
 09h    maximum scan lines              0Dh    03h   07h   07h      01h
           bit7  : (VGA) double scan active
           bit6  : (VGA) bit9 of line compare (18h)
           bit5  : (VGA) bit9 of start vertical blanking (15h)
           bit4-0: maximum scan line 00..31 (height-1)
 0Ah    cursor start                  0Bh    00h   06h   06h 06h/00h
           bit7  : reserved
           bit6-5: original 6845: cursor on/off, blink interval
               (not on all adapters, as original MDA, CGA have
               extra circuitrity to avoid this!!)
           bit6-5: native EGA: not used
           bit6  : (VGA) not used
           bit5=0: (VGA) cursor on
           bit4-0: first cursor scanline
 0Bh    cursor end                  0Ch    00h   07h   07h 07h/00h
           bit7  : reserved
           bit6-5: EGA, VGA: cursor skew control
           bit4-0: end cursor row
 0Ch RW    start address high              00h    00h   00h   00h      00h
           bit7-6 not used by original 6845 (MDA,HGC,CGA)
 0Dh RW    start address low              00h    00h   00h   00h      00h
 0Eh RW    cursor location high              00h    00h   00h   00h      00h
           bit7-4 not used by original 6845 (MDA,HGC,CGA)
           bit5-4 reserved on MCGA
 0Fh RW cursor location low              00h    00h   00h   00h      00h
---for 10h-14h MCGA registers see at 3D4h/3D5h---
 10h R-    light pen high (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 10h R-    native VGA with bit7=1 in end horizontal blanking (03h) and ET4000:
           start vertical retrace
 10h R- MCGA at 3D5h only: mode control status register (see #P174)
 10h -W EGA, VGA: start vertical retrace
 10h -W MCGA at 3D5h only: mode control register (see #P175)
 11h R- light pen low (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 11h R- native VGA with bit7=1 in end horizontal blanking (03h):
           end vertical retrace
 11h -W EGA, VGA: end vertical retrace
           bit7  : VGA: protection bit
                =0 enable write access to 00h-07h
                =1 read only regs 00h-07h with the exception
                   of bit4 in 07h. ET4000: protect 35h also.
           bit6  : VGA: =0 three, =1 five refreshcycles/line
               ET4000: reserved
           bit5=0: (MCGA also) enable vertical interrupt
           bit4=0: (MCGA also) clear vertical interrupt
           =1:           no effect
           bit3-0: (MCGA also) vertical retrace end
 11h RW MCGA at 3D5h only: interrupt control register (see #P176)
 12h    EGA, VGA: vertical display end register
 12h RW MCGA at 3D5h only: character generator/sync polarity register
          (see #P177)
 12h R- MCGA at 3D5h only: display sense register (see #P173)
        (with bit7=1 in 11h only)
 13h    EGA, VGA: row offset register
           logical screen line width in
        byte mode : bytes/(line/2)
        word mode : bytes/(line/4)
        dword mode: bytes/(line/8)
 13h -W MCGA at 3D5h only: character font pointer register (see #P173)
 14h    EGA, VGA: underline location register
           bit7=0: reserved
           bit6  : VGA: 0=word-mode, 1=dword-mode (see 17h, bit6)
           bit5  : VGA: 0=standard address counter clock
                1=address counter clock/4 (see 17h, bit3)
           bit4-0: horizontal underline row scan
 14h -W MCGA at 3D5h only: number of characters to load during
           vretrace period (see #P173)
 14h -W HGC+,InColor: xMode register
 15h    EGA, VGA: start vertical blanking-1
 15h -W HGC+,InColor: underscore register
 16h    EGA, VGA: end vertical blanking register
           bit7-5 : EGA: reserved, but used on original EGA???
           bit4-0 : end vertical blanking
 16h -W HGC+,InColor: overstrike register
 17h    EGA, VGA: mode control register (see #P140)
 17h -W    InColor: exception register
 18h    EGA, VGA: line compare register
 18h -W    InColor: plane mask register
 19h    Genoa SuperEGA only: double scan control
           at 3B5h only in MDA, HGC emulation, but at 3D5h even in
           mono EGA modes.
           bit7-5 : reserved
           bit4   : HR/VR width adjust flag for double scan mode
           bit3-1 : 1=test, 0=normal
           bit0   : double scan enable
 19h -W    InColor: read/write control register
 1Ah -W    InColor: read/write color register
 1Bh -W    InColor: Latch Protect register
 1Bh    ET3000 only: x-zoom start register
          The existence of this register is often used to decide
           between ET3000 and ET4000, as the ET4000 does not offer
           hardware-zoom features.
 1Ch RW    InColor: palette register
 1Ch    ET3000 only: x-zoom end register
 1Dh    ET3000 only: y-zoom start register low
 1Eh    ET3000 only: y-zoom end register low
 1Fh    ET3000 only: y-zoom start & end high register
 20h    ET3000 only: zoom start address register low
 21h    ET3000 only: zoom start address register medium
 23h    ET3000 only: extended start address (see register 33h)
 24h    ET3000 only: compatibility register (see register 34h)
 25h    ET3000 only: overflow high register (see registers 35h, 07h)
 2Dh R- S3: extended Chip ID (always 88h???)
 2Eh R- S3 7xx/866/x68: new chip ID
 2Fh R- S3 7xx/866/x68: chipset revision
 30h RW    S3: chip ID/revision (see #P146)
 31h RW    S3: memory configuration (see #P147)
 32h    ET4000: RAS/CAS configuration ('key' protected) (see #P141)
 32h RW S3: backward compatibility 1 (see #P148)
 33h    ET4000: extended start address
          This register is often used to decide between ET4000
          and ET3000, when bit3-0 can be reread after write.
           bit7-4 : reserved
           bit3-2 : cursor address bit 17-16
           bit1-0 : linear start address bits 17-16
 33h RW S3: backward compatibility 2 (see #P149)
 34h    ET4000: 6845 compatibility control register ('key' protected)
      (see #P142)
 34h RW S3: backward compatibility 3
 35h    ET4000: overflow high register (protected by 11h, bit7) (see #P143)
 35h RW S3: CRT register lock
 36h    ET4000: video system configuration 1 ('key' protected) (see #P144)
 36h R    S3: Reset State read 1
 37h    ET4000: video system configuration 2 ('key' protected) (see #P145)
 37h R    S3: Reset State read 2
 38h RW    S3: S3 Register lock 1
    set reg 38h to 48h and reg 39h to A5h to unlock other S3 registers
 39h RW    S3: S3 Register lock 2
 3Ah RW S3: S3 Miscellaneous
    bit 4: ???
 3Bh RW S3: Data Transfer Execute position
 3Ch RW S3: Interlace Retrace start
 40h RW S3: System Configuration
    bit 0: enable access to 8514/A-compatible registers at PORT x2E8h
 41h    S3: BIOS Flag register
 42h RW S3: mode control
 43h RW S3: extended mode
 45h RW S3: hardware graphics cursor mode
 46h-47h RW S3: hardware cursor origin X
 48h-49h RW S3: hardware cursor origin Y
 4Ah RW S3: hardware graphics cursor foreground stack
 4Bh RW S3: hardware graphics cursor background stack
 4Ch-4Dh RW S3: hardware graphics cursor map start address
 4Eh RW S3: hardware cursor pattern start X
 4Fh RW S3: hardware cursor pattern start Y
 50h RW S3 801+: Extended System Control 1
 51h RW S3 801+: Extended System Control 2
 52h RW S3 801+: Extended BIOS Flag 1
        bits 7-6 are sync polarities (see #P165) for Diamond cards
 53h RW S3 801+: Extended Memory Control 1
 54h RW S3 801+: Extended Memory Control 2
 55h RW S3 801+: Extended Video DAC Control
 56h RW S3 801+: External Sync Control 1
 57h RW S3 801+: External Sync Control 2
 58h RW S3 801+: Linear Address Window Control
 59h RW S3 801+: Linear Address Window Position (high)
 5Ah RW S3 801+: Linear Address Window Position (low)
 5Bh RW S3 801+: Extended BIOS Flag 2
 5Ch RW S3 801+: General Output Port
    bit 0: ???
    bit 1: ???
 5Dh RW S3 801+: Extended Horizontal Overlow
 5Eh RW S3 801+: Extended Vertical Overflow
 5Fh RW S3 928/964: Bus Grant Termination Position
 60h RW S3 864/964: extended memory control 3
 61h RW S3 864/964: extended memory control 4
 62h RW S3 864/964: extended memory control 5
 63h RW S3 864/964: external sync delay adjustment (high)
 64h RW S3 864/964: genlocking adjustment
 65h RW S3 864/964: extended miscellaneous control
 66h RW S3 864/964: extended miscellaneous control 1
 67h RW S3 864/964: extended miscellaneous control 2
 68h RW S3 864/964: configuration 3
 69h RW S3 864/964: extended system control 3
 6Ah RW S3 864/964: extended system control 4
 6Bh RW S3 864/964: extended BIOS flag 3
 6Ch RW S3 864/964: extended BIOS flag 4
 6Dh RW S3 864/964: extended miscellaneous control
Notes:    MDA, HGC, CGA: 6845 registers 00h-0Dh are write only, 0Eh, 0Fh
           are r/w, and 10h-11h are read only.
           The alternative initial defaults may be used
           sometimes on modern adapters.
    HGC+(RamFont): as with HGC, but 3 (unknown) registers more for
           font control
    emulations   : more registers may be r/w, but most often it's
           the same as with native 6845.
    MCGA (CGA+)  : Though this is a mixture of CGA and VGA, most
           registers are same as with CGA, but with some
           enhancements and incompatibilities to EGA, VGA.
    native EGA   : registers 00h-0Bh are write only, 0Ch-0Fh are
           r/w, 10h-11h are read/write, 12h-18h are write
           only. More regs may be r/w on enhanced clones.
    GenoaSuperEGA: adapter with chips SEQCRT GN006001 and GRAT
           GN006002, e.g. c't Super-EGA adapter. Is EGA
           clone with up to 800x600 and full 6845 emulation.
    native VGA   : all registers 00-18h are r/w, but 00h-07h are
           write-locked if bit7 in 11h is set.
    ET4000         : same as VGA, but with additional r/w registers
           32h-37h, protected by 'key' except 33h, 35h
           (see 3BFh for details). 35h is protected by
           bit7 in 11h. The 'key' must be issued at least
           after each power on or synchronous reset.
SeeAlso: #P138,#P139,#P173

Bitfields for mono video adapter mode control register:
Bit(s)    Description    (Table P138)
 7 not used by MDA, page number on HGC
 6    not used
 6  R-O    (mono ET4000 only) report status of bit 1 (enable 2nd page) of
      Hercules compatibility register (PORT 03BFh)
 5    enable blink (0 = intense background, 1 = blink)
 4    not used
 3    video enable
 2    not used
 1    (MDA) not used
    (HGC) graphics enable
    the 6845 has to be reprogrammed completely, if this bit is
      changed, otherwise the TTL-monitor may be damaged by wrong
      sync impulses!
 0    high resolution mode (always set on MDA)
---mono ET4000 only, W-O ---
 7-0    =A0h: second part of 'key', see Hercules compatibility register
      (PORT 03BFh) for details
Note:    this port might be completely or partially readable on very few MDA,
      HGC clones or emulations (e.g. Genoa SuperEGA), but not with the
      majority of original and clone chips.     It cannot be found on
      native mono EGA, mono VGA, but on most clones, where it is usually
      R/W.
SeeAlso: #P137,#P139

Bitfields for mono video adapter CRT status register:
Bit(s)    Description    (Table P139)
 7    HGC: vertical sync pulse in progress
 6-4    adapter identification
    (MSD says) if bit 7 changes within 8000h reads then
        =000 adapter is Hercules or compatible
        =001 adapter is Hercules+
        =101 adapter is Hercules InColor
        else: adapter is unknown
 6-4    =111 on MDA and some HGC clones
 5-4    (mono EGA, mono ET4000) diagnose video display feedback
    select from color plane enable
 3    (MDA,HGC) pixel stream (0=currently black, 1=currently white)
    (mono EGA, mono VGA) vertical retrace in progress
 2-1    (MDA) reserved
 2    (HGC, mono EGA) lightpen flipflop set
    (mono ET4000) reserved (0)
 1    (HGC) lightpen input stream (if set, current value to get from
      PORT 03B5h registers 10h-11h)
    (mono ET4000) reserved (0)
 0    horizontal drive enabled
SeeAlso: #P137,#P138

Bitfields for EGA,VGA mode control register:
Bit(s)    Description    (Table P140)
 7    0=CRTC reset and stop, 1=resume reset
 6    0=word-mode, 1=byte-mode (VGA: see 14h, bit6)
 5    0=14bit, 1=16bit address wrap
 4    (native VGA only) reserved (0)
 4    (EGA and most VGA clones) output control
    0: video driver active
    1: video driver not active
 3    linear address counter clock (0 = standard, 1 = clock/2)
    (VGA: see register 14h, bit 5)
 2    horizontal retrace clock (0 = standard, 1 = clock/2)
 1    row scan counter
    0: address bit 14 = scan bit 1
    1: address bit 14 not altered
 0    6845 compatibility mode
    0: address bit 13 = scan bit 0 (as with 6845)
    1: address bit 13 not altered
SeeAlso: #P137

Bitfields for ET4000 RAS/CAS configuration register:
Bit(s)    Description    (Table P141)
 7    static column memory
    ET4000/W32i: interleave mode
 6    RAL RAS&CAS column setup time
 5    RCD RAS & CAS time
 4-3    RSP, RAS pre-charge time
 2    CPS, CAS pre-charge time
 1-0    CSW, CAS low pulse width
SeeAlso: #P137,#P142

Bitfields for ET4000 compatibility control register:
Bit(s)    Description    (Table P142)
 7    6845 compatibility enabled
 6    ENBA enable double scan/underline in AT&T mode
 5    ENXL enable translation ROM on writing
 4    ENXR enable translation ROM on reading
 3    ENVS VSE register port address
 2    TRIS tristate ET4000 output pins
 1    CS2 MCLCK clock select 2
 0    EMCK enable translation of CS0 bit
SeeAlso: #P137,#P141,#P143

Bitfields for ET4000 overflow high register:
Bit(s)    Description    (Table P143)
 7    vertical interlace mode
 6    alternate RMW control
 5    external sync reset (gen-lock) the line/chr counter
 4    line compare bit10
 3    vertical sync start bit10
 2    vertical display end bit10
 1    vertical total bit10
 0    vertical blank start bit10
SeeAlso: #P137,#P142,#P144

Bitfields for ET4000 video system configuration 1 register:
Bit(s)    Description    (Table P144)
 7    enable 16bit I/O read/write
 6    enable 16bit display memory read/write
 5    addressing mode (0=IBM, 1=TLI)
 4    0=segment / 1=linear system configuration
 3    font width control (1=up to 16bit, 0=8bit)
 2-0    refresh count per line-1
SeeAlso: #P137,#P143,#P145

Bitfields for ET4000 video system configuration 2 register:
Bit(s)    Description    (Table P145)
 7    DRAM display memory type (1=VRAM, 0=DRAM)
 6    test (1=TLI interal test mode)
 5    priority threshold control (0=more mem BW)
 4    disable block read-ahead
 3    display memory data depth
 2    bus read data latch control
 1-0    display memory data bus width
SeeAlso: #P137,#P144

(Table P146)
Values for S3 chip ID/Revision register "CR30":
 81h    86c911
 82h    86c911A/924
 90h    86c928 (original)
 ...
 A0h    86c801/805 A-step or B-step
 ...
 B0h    86c928 PCI
 C0h    Vision864
 C1h    Vision864P
 D0h    Vision964
 D1h    Vision964P
 E0h    Trio32/64, 86c866, 86c868, 86c968; actual ID and revision stored in
      PORT 03B5h registers 2Eh and 2Fh
 E1h    Trio32/64, 86c866, 86c868, 86c968; actual ID and revision stored in
      PORT 03B5h registers 2Eh and 2Fh
SeeAlso: #P147

Bitfields for S3 "CR31" memory configuration register:
Bit(s)    Description    (Table P147)
 0    enable base-address offset (turn on bank-switched operation)
 1    two-page screen image (enables 2048-pixel wide screen)
 2    VGA 16-bit memory bus (clear for 8-bit memory bus)
 3    video memory above 256K accessible
 5-4    display start address, bits 17&16.  See also registers 51h and 69h
 6    enable page-mode memory access for text-mode font access
 7    (except 864/964) enable BIOS ROM address space C6800h-C7FFFh
SeeAlso: #P146,#P148

Bitfields for S3 "CR32" Backwards Compatibility 1 register:
Bit(s)    Description    (Table P148)
 1-0    character clock period
    00 IBM-compatible, 8 or 9 dots
    01 7 dots
    10 9 dits
 2    force full character clock for horizontal timing (CGA/HGC emulation),
      rather than 1/2 dot clock rate
 3    backward-compatible modes (set for MDA/CGA/EGA/HGC)
 6    fix VGA screen page using display start address bits 16&17 (see #P147)
 7    (928,964) tri-state serial output pins SC, SOE0, and SXNR
SeeAlso: #P147,#P149

Bitfields for S3 "CR33" Backwards Compatibility 2 register:
Bit(s)    Description    (Table P149)
 1    disable VDE protection (PORT 03D4h register 11h bit 7 will not act
      on PORT 03D4h register 7h bits 1 and 6)
 3    VCLK is inverted DCLK rather than inverted DCLK/2
 4    disable writes to RamDAC
 5    blank signal does not include border area, is same as display enable
 6    lock palette/overscan registers
 7    override CGA "enable video" at PORT 03D8h bit 3
SeeAlso: #P148
----------P03BC03BF--------------------------
PORT 03BC-03BF - PARALLEL PRINTER PORT (MDA's LPT1)
Range:    PORT 0278h, PORT 0378h, or PORT 03BCh

03BC  -W  data port
03BC  R-  bidirectional port: input from connector
      unidirectional port: last value written to port
03BD  RW  status port (see #P150)
03BE  RW  control port (see #P151)

Bitfields for parallel interface status port:
Bit(s)    Description    (Table P150)
 7    busy
 6    NOT acknowledge (approx. 5us low pulse)
 5    out of paper
 4    printer is selected
 3    *no* error
 2    IRQ has *not* occurred
    (PS/2) printer returned -ACK
 1-0    reserved
SeeAlso: #P151

Bitfields for parallel interface control port:
Bit(s)    Description    (Table P151)
 7-5    reserved
 7    (see PORT 037Bh bit 7)
 5    enable bidirectional port
    (PS/2 also requires enabling via PORT 0102h)
 4    enable IRQ (via -ACK)
 3    select printer (SLCT IN line)
 2    =0 initialize printer (-RESET line)
 1    automatic line feed
 0    strobe (must be set for minimum of 5 microseconds)
SeeAlso: #P150
----------P03BF------------------------------
PORT 03BF - Hercules configuration switch register
Note:    can also be found on EGA and VGA clones in Hercules emulation

03BF  -W  configuration switch register (see #P152)
03BF  -W  (ET4000) Hercules compatibility register (see #P153)
03BF  RW  (Genoa SuperEGA) miscellaneous register
    Note: only available in MDA, HGC, and CGA emulation; should be
      compatible with Hercules configuration register, but may contain
      additional features

Bitfields for Hercules configuration switch register:
Bit(s)    Description    (Table P152)
 7-2    reserved
 1    =0  disables upper 32K of graphics mode buffer
    =1  enables upper 32K of graphics mode buffer
 0    =0  prevents graphics mode
    =1  allows graphics mode
SeeAlso: #P153

Bitfields for ET4000 compatibility register:
Bit(s)    Description    (Table P153)
 1    =0 disables upper 32K of graphics mode buffer
    =1 enables upper 32K of graphics mode buffer
 0    reserved (not needed for HGC graphics)
 7-0    =03h: first part of 'key' for access to some extra
         ET4000 regs. To issue the 'key', the following
         code must be executed:
          MOV DX, 3BFh
          MOV AL, 3
          OUT DX, AL
          MOV DX, 3D8h  (3B8h in mono mode)
          MOV AL, 0A0h
          OUT DX, AL
SeeAlso: #P152
----------P03C003C7--------------------------
PORT 03C0-03C7 - Sunshine EW-901, EW-901A, EW-904, EW-904A
        EPROM writer card for EPROMs up to 27512
03C0-03C3    adresses of the 8255 on the EW-90x
----------P03C003CF--------------------------
PORT 03C0-03CF - EGA  (1st Enhanced Graphics Adapter)    alternate at 02C0

03C0  rW  EGA VGA ATC index/data register
         Every write access to this register will toggle an internal
         index/data selection flipflop, so that consecutive writes to
         index & data is possible through this port. To get a defined
         start condition, each read access to the input status register
         #1 (3BAh in mono / 3DAh in color) resets the flipflop to load
         index. If values are changed during the vertical retrace
         period only no flicker will occur.

        index register (flipflop reset to 'index'): (default 20h)
         bit7-6: reserved
         bit5  : 0=CPU access (screen dark),
             1=video access to registers
         bit4-0: index in ATC (0..31)

        indexed registers in ATC (flipflop set to 'data'): (see #P154)
03C1  R-  VGA    ATC index/data read register
03C2  R-  EGA VGA input status 0 register
             (Genoa SuperEGA in all emulation modes)
             bit6-5 are 'key' protected on ET4000.
             bit7  : CRT interrupt occured
                 EGA: 0=vertical retrace in progress, 1=display
             bit6  : EGA and ET4000: feature control 1 (pin17)
             bit5  : EGA and ET4000: feature control 0 (pin19)
             bit4  : DIP switch sense
                (0=closed, 1=open/switches readable)
             bit3-0: reserved
03C2  -W  EGA VGA miscellaneous output register (see #P165)
03C3  RW  VGA    video subsystem enable (see also PORT 46E8h)
        for IBM, motherboard VGA only
             bit7-4=0: reserved
             bit3     : select video subsystem (address 46E8h)
             bit2-1     : reserved
             bit0     : select video subsystem (address 03C3)
03C4  -W  EGA    TS index register
03C4  RW  VGA    sequencer index register (see also #P160)
             bit7-3     : reserved (VGA only)
             bit2-0     : current TS index
03C5  -W  EGA    TS data register
03C5  RW  VGA    sequencer data register (see #P160)
03C6  RW  (VGA, MCGA) PEL mask register (default FFh)
         VGA:    AND mask for color-register address.
         MCGA:    Never change from the default FFh.
03C6  RW  HiColor ET4000 (Sierra RAMDACs e.g. SC11486, SC11481, SC11488):
         Enable HiColor feature: beside other assignments,
         consequtive read 3C6h 4 times and write magic value 80h to it.
03C7  -W  (VGA,MCGA,CEG-VGA) PEL address register (read mode)
         Sets DAC in read mode and assign start of color register
         index (0..255) for following read accesses to 3C9h.
         Don't write to 3C9h while in read mode. Next access to
         03C8h will stop pending mode immediatly.
03C7  -W  (CEG-Color VGA w/ Edsun Labs RAMDACs)
         Enable and set Countinous Edge Graphics Mode:
         Consecutive write the following three key sequences in read
         mode (!) to 3C9h register DEh : 'CEG', 'EDS', 'UNx' (x see
         below). Current CEG mode can be read from palette register
         BFh 'blue', write access to that register will disable CEG
         features.
         In CEG modes by combining old with new colors and dynamically
         changing palette values, the effective colors displayable
         are enhanced dramatically (in EDP modes up to virtually 32bit
         truecolor) on standard 16/256 color VGA. Also, effective
         resolution enhancement takes effect by anti-aliasing.
         Neccessary EDP escape sequences should be moved to image
         border or single colored areas, if possible.

         REP-mode: if pixel are doubled in current video mode
         EDP-mode: pseudo-truecolor with Edsun dynamic palette
         (see #P170,#P171)

         Palette-color-register single-byte-format (each 3 times):
          Mode A:          Mode C:
           bit7-4: mix code       bit3     : 0=color, 1=code
           bit3-0: color code       bit2-0: color / mix code
          Mode B:          Mode D:
           bit7-5: mix code       bit7-0: see mix code table
           bit4     : 0=new, 1=old      Non-CEG modes:
           bit3-0: color code       bit7-0: as usual

         In EDP modes, video-memory-palette-changing escape-sequences:
          Mode A:     Mode B:      Mode C:     Mode D:
           7/escape    7/escape       7/escape    0BFh
           red           red       red7-4      red
           green       green       red3-0      green
           blue           blue       green7-4    blue
           address     address       green3-0    address
                       blue7-4
                       blue3-0
                       address
03C7  R-  VGA    DAC state register
        bit7-2 reserved
        bit1-0: 00b write palette cycle (write mode)
            01h reserved
            10b reserved
            11b read palette cycle (read mode)
03C8  RW  (VGA,MCGA) PEL address register (write mode)
         Sets DAC in write mode and assign start of color register
         index (0..255) for following write accesses to 3C9h.
         Don't read from 3C9h while in write mode. Next access to
         03C8h will stop pending mode immediatly.
03C8  RW  (Genoa SuperEGA) SuperEGA control register (all emulation modes)
          bit7-2: reserved
          bit1    : 0=EGA mode, 1=backward compatibility mode
          bit0    : not used
03C9  RW  (VGA,MCGA) PEL data register
         Three consequtive reads (in read mode) or writes (in write
         mode) in the order: red, green, blue. The internal DAC index
         is incremented each 3rd access.
          bit7-6: HiColor VGA DACs only: color-value bit7-6
          bit5-0:             color-value bit5-0
03CA  -W  EGA    graphics 2 position register
03CA  R-  VGA    feature control register (see PORT 03BAh,PORT 03DAh-W)
03CB  RW  (ET4000/W32) GDC segment select register 2 ('key' protected?)
        The existence of this r/w register 0..255 is often
         used to decide between ET4000 and ET4000/W32.
         bit7-6: reserved, but existent
         bit5-4: bits 5-4 of read segment pointer
         bit3-2: reserved, but existent
         bit1-0: bits 5-4 of write segment pointer
03CC  -W  EGA    graphics 1 position register
03CC  R-  VGA    miscellaneous output register (see PORT 03C2h-W,#P165)
03CD  RW  (ET3000, ET4000, ET4000/W32) GDC segment select ('key' protected)
        The existence of this r/w register is often used as
        detection of ET3000, ET4000 and ET4000/W32 chips.
         bit7-4: read segment pointer for mapping to A0000h
         bit3-0: write segment pointer for mapping to A0000h
03CE  -W  EGA    GDC index register
03CE  RW  VGA    graphics address register / GDC index
              bit7-4: reserved
              bit3-0: index
03CF  -W  EGA    GDC data register
03CF  RW  VGA    other graphics register (see #P166)

(Table P154)
Values for EGA/VGA indexed registers in ATC:
 00h-0Fh 16 palette registers (see #P155)
 10h    mode control register (see #P156)
 11h    (EGA) overscan color register (see #P157) (default: 00h)
 11h    (VGA) overscan color register (see #P158) (default: 00h)
 12h    color enable register (see #P159)
 13h    horizontal pixel panning register
    bit7-4: reserved
    bit3-0: horizontal pixel panning
 14h    (VGA) color select register (default: 00h)
    bit7-4: reserved
    bit3  : s-color 7
    bit2  : s-color 6
    bit1  : s-color 5 (only with 16 pages á 16 regs)
    bit0  : s-color 4 (only with 16 pages á 16 regs)
 16h    ET3000, ET4000 only: ATC miscellanenous
    (at least on ET4000 'key' protected)
    This register is also supported by ET3000, but the
    description is proved for ET4000 only.
    bit7  : bypass the internal palette
        (e.g. for HiColor modes with Sierra RAMDACs)
    bit6  : reserved
    bit5-4: select high resolution / color mode
    bit3-0: reserved
SeeAlso: #P160,#P166

Bitfields for EGA/VGA indexed ATC palette register:
Bit(s)    Description    (Table P155)
 7-6    reserved
 5    secondary red video
 4    secondary green/intensity video
 3    secondary blue/mono video
 2    primary red video
 1    primary green video
 0    primary blue video
SeeAlso: #P154

Bitfields for EGA/VGA ATC mode control register:
Bit(s)    Description    (Table P156)
 7    (VGA) SB/SG select (0=4 pages of 64 regs, 1=16 pages of 16 regs)
 6    (VGA) PELCLK/2 (0=4bit color, 1=8bit color)
 5    (VGA) enable pixel panning (0=all, 1=up to line compare register value)
 4    reserved
 3    background intensity (0=16 colors, 1=blink)
 2    line graphics enable (0=background, 1=line 8=9)
 1    1=mono, 0=color select
 0    1=graphics, 0=text select
SeeAlso: #P154

Bitfields for EGA overscan color register:
Bit(s)    Description    (Table P157)
 7-6    reserved
 5    secondary red (SR)
 4    secondary green (SR) / intensity
 3    secondary blue (SB)
 2    primary red (PR)
 1    primary green (PG)
 0    primary blue (PB)
SeeAlso: #P154,#P158

Bitfields for VGA overscan color register:
Bit(s)    Description    (Table P158)
 7    secondary intensity border color (SI)
 6    secondary red (SR)
 5    secondary green (SG)
 4    secondary blue (SB)
 3    intensity border color (PI)
 2    primary red (PR)
 1    primary green (PG)
 0    primary blue (PB)
SeeAlso: #P154,#P157

Bitfields for EGA/VGA color enable register:
Bit(s)    Description    (Table P159)
 7-6    reserved
 5-4    diagnose / video status select
    EGA:        VGA, ET4000:
    00b = PR/PB       PR/PB
    01b = SB/PG       SG/SB
    10b = SR/SG       PI/PG
    11b = reserved       SI/SR
 3    enable plane 3
 2    enable plane 2
 1    enable plane 1
 0    enable plane 0
SeeAlso: #P154

(Table P160)
Values for EGA/VGA indexed TS (sequencer) registers:
 00h    reset register
    bit7-2 : reserved
    bit1 =0: synchronous reset (EGA/VGA)
    bit0 =0: asynchronous reset (EGA, ET4000)
         synchronous reset, also (VGA)
 01h    clocking mode register / TS mode (see #P161)
 02h    map mask register (see #P162)
 03h    character map select register / font select (see #P163)
 04h    memory mode register
    bit7-4 : reserved
    bit3 =1: (VGA) enable chain 4 linear graphics mode
    bit2    : 0=odd/even mode, 1=sequential mode
    bit1 =1: extended memory (0=64KB, 1=more)
    bit0    : (EGA) 1=textmode, 0=graphics mode
 06h    ET3000 only: Zoom control register
 06h    ET4000 only: TS state control (protected by 'key')
    bit7-3 : reserved
    bit2-1 : timing sequencer state bit2-1
           (bit0 is bit0 TS mode register)
           00 0b=  9 dots
           00 1b=  8 dots
           01 0b= 10      (10-16 are ET4000 only)
           01 1b= 11
           10 0b= 12
           11 1b= 16
    bit0    : reserved
 07h    ET3000/ET4000 only: TS auxiliary mode (see #P164)
 08h    S3 765 (Trio64V): key register -- enable access to S3 extended
      registers when set to 06h
---S3 756 (Trio64V) extended registers---
 09h    ???
 0Dh    DPMS
    bits 7-4: DPMS power mode
        0000 On
        0001 Standby
        0100 Suspend
        0101 Off
    bits 1-0: ???
 10h    ???  \
 11h    ???  / paired
 12h    ???  \
 13h    ???  / paired
 15h    ???
    bit 4: ???
 18h    bit 5 set while reduced-power modes active
    bit 7: ???
 1Ch    bit 0: enable ??? at 000A0000h
    bit 1: enable ??? at 01000000h

Bitfields for EGA/VGA sequencer clocking mode register:
Bit(s)    Description    (Table P161)
 7-6    reserved
 5    (VGA) =1: screen refresh off
 4    (VGA) shift load (0=4x8, 1=1x32)
 3    dot clock (0=normal, 1=clock/2)
 2    serial shift video load (0=4x8, 1=2x16)
 1    (EGA) CRTC bandwidth (0=4/5, 1=2/5)
 0    dot clocks (0=9, 1=8) (ET4000: see 06h)
SeeAlso: #P160

Bitfields for EGA/VGA sequencer map mask register:
Bit(s)    Description    (Table P162)
 7-4    reserved
 4    Genoa SuperEGA only: plane4 ???
 3    write enable display memory plane 3
 2    write enable display memory plane 2
 1    write enable display memory plane 1
 0    write enable display memory plane 0
SeeAlso: #P160

Bitfields for EGA/VGA sequencer character map select register:
Bit(s)    Description    (Table P163)
 7-6    reserved
 5    (VGA) bit3 for 2nd text-font
 4    (VGA) bit3 for 1st text-font
 3-2    2nd text-font (attr bit3=1)
 1-0    1st text-font (attr bit3=0)
    offset in font memory (4-7: VGA only)
       0 00b =  0KB
       0 01b = 16KB
       0 10b = 32KB
       0 11b = 48KB
       1 00b =  8KB
       1 01b = 24KB
       1 10b = 40KB
       1 11b = 56KB
SeeAlso: #P160

Bitfields for ET3000/ET4000 sequencer auxiliary mode:
Bit(s)    Description    (Table P164)
 7    compatibility mode (1=VGA, 0=EGA)
 6    select MCLK/2 (with bit0=0)
 5    BIOS ROM address map 2
 4    reserved
 3    BIOS ROM address map 1
 2    reserved (1)
 1    select SCLK input from MCLK
 0    select MCLK/4 (with bit6=1)
 5+3    ROM address
    00 C0000-C3FFF
    01 disabled
    10 C0000-C5FFF, C6800-C7FFF
    11 C0000-C7FFF (default)
Notes:    at least on the ET4000, this register is protected by a 'key'
    this register is also supported by ET3000, but the above description
      is based on the ET4000
SeeAlso: #P160

Bitfields for EGA/VGA miscellaneous output register:
Bit(s)    Description    (Table P165)
---Genoa SuperEGA in all emulation modes---
 7-6: vertical resolution
    00 (EGA) 200 lines
    01 (VGA) 400 lines
    10 (EGA/VGA) 350 lines
    11 (VGA) 480 lines
------
 7    vertical sync polarity (0=positive, 1=negative)
 6    horizontal sync polarity (0=positive, 1=negative)
 5    odd/even pagebit
 4    EGA: 0=video driver on,
         1=video driver off (feature connector used)
 3-2    pixelclock
    00 14/25MHz (EGA/VGA)
    01 16/28Mhz (EGA/VGA)
    10 (EGA/VGA) external clock (EGA)
    11 (EGA/VGA) reserved
    10 (Genoa SuperEGA) 39Mhz
    11 (Genoa SuperEGA) 26.824Mhz
 1    enable CPU RAM access
 0    CRTC port address
    0=3B4 mono
    1=3D4 color
       (color EGA: enable feature control at 3DAh,status reg 1 at 3D2h)

Bitfields for EGA/VGA indexed registers in GDC:
Bit(s)    Description    (Table P166)
 00h    set/reset register (default 00h)
    functionality depending on write mode (register 05h) (see #P169)
    bit7-4: reserved
    bit3  : 0=write 00h, 1=write FFh in plane 3
    bit2  : 0=write 00h, 1=write FFh in plane 2
    bit1  : 0=write 00h, 1=write FFh in plane 1
    bit0  : 0=write 00h, 1=write FFh in plane 0
 01h    enable set/reset register (default 00h) (see #P167)
 02h    color compare register (default 00h) (see #P168)
 03h    data rotate register (default 00h)
    bit7-5: reserved
    bit4-3: logical function select
        00b= CPU-data overwrites
        01b= CPU-data AND with latch-register
        10b= CPU-data OR with latch-register
        11b= CPU-data XOR with latch-register
    bit2-0: rotate count
 04h    read map select register (default 00h)
    bit7-3: reserved
    bit2  : EGA?? & Genoa SuperEGA: map select bit2
    bit1-0: map select (0..3)
 05h    mode register (see #P169)
 06h    miscellaneous register
    bit7-4: reserved (=0)
    bit3-2: memory map
           00b = A0000..BFFFF (128KB)
           01b = A0000..AFFFF (64KB)
           10b = B0000..B7FFF (32KB)
           11b = B8000..BFFFF (32KB)
    bit1  : chain odd maps to even, 1=subst addess bit0
    bit0  : 0=testmode, 1=graphics mode
 07h    color don't care register
    bit7-4: reserved
    bit3=1: color plane 3 don't care (ignore bit3)
    bit2=1: color plane 2 don't care (ignore bit2)
    bit1=1: color plane 1 don't care (ignore bit1)
    bit0=1: color plane 0 don't care (ignore bit0)
 08h    bit mask register (default FFh)
    bit7-0: bitmask for latch/databyte
          (bit set=change allowed)
 0Fh    (Paradise SuperVGA) lock register
    The ability to write and reread 00h..07h to this register
    is often used as detection of Paradise chips.
    bit7-0 = 01h lock/hide Paradise specific registers
           = 05h unlock Paradise specific registers
    bit7-3: reserved
    bit2-0: flipflops, reserved

Bitfields for EGA/VGA GDC enable set/reset register:
Bit(s)    Description    (Table P167)
 7-4    reserved (used on Genoa SuperEGA???)
 3    enable set/reset plane 3
 2    enable set/reset plane 2
 1    enable set/reset plane 1
 0    enable set/reset plane 0
 3-0    0=CPU access, 1=set/reset access to plane
SeeAlso: #P166

Bitfields for EGA/VGA GDC color compare register:
Bit(s)    Description    (Table P168)
 7-4    reserved
 3    color compare 3
 2    color compare 2
 1    color compare 1
 0    color compare 0
 3-0    (color number)
SeeAlso: #P166

Bitfields for EGA/VGA GDC mode register:
Bit(s)    Description    (Table P169)
 7    reserved
 6    (VGA) 0=standard, 1=enable 256 colors
 5    shift register mode, 0=standard, 1=CGA-graphics
      (not used on Genoa SuperEGA???)
 4=1    enable odd/even address mode
 3    read mode, 0=mode0, 1=mode1
 2    (EGA) test condition, 0=standard, 1=output tristate
 1-0    write mode
    00 mode0, plane source is CPU or set/reset
    01 mode1, plane source is latch-register
    10 mode2, plane source is CPU as set/reset
    11 (VGA) mode3, CPU as set/reset AND bitmask
SeeAlso: #P166

(Table P170)
Values for EDSUN CEG (Continuous Edge Graphics) modes::
 x:  mode:     colors:  mix:    pixel depth:  effective colors:
 0 = disabled       256       -         8            256
 1 = A            16      16         8           1920
 2 = A+REP        16      16      8 dblscn       1920
 3 = A+EDP        15      16            truecolor
 4 = reserved         -       -         -             -
 5 = B            16       8         8            960
 6 = B+REP        16       8      8 dblscn        960
 7 = B+EDP        15       8            truecolor
 8 = reserved         -       -         -             -
 9 = C             8       8         4            224
 10 = C+REP         8       8      4 dblscn        224
 11 = C+EDP         7       8            truecolor
 12 = reserved         -       -         -             -
 13 = D           223      32         8         792096
 14 = D+REP       223      32      8 dblscn     792096
 15 = D+EDP       223      32            truecolor
SeeAlso: #P171

(Table P171)
Values for EDSUN CEG mixing codes:
 Mode A:           |  Mode C:
 mix: new:    old:   |   mix: new:   old:   colorcode:
   0 = 32/32    0/32   |    0 =      -     -     0
   1 = 30/32    2/32   |    1 =      -     -     1
   2 = 28/32    4/32   |    2 =      -     -     2
   3 = 26/32    6/32   |    3 =      -     -     3
   4 = 24/32    8/32   |    4 =      -     -     4
   5 = 22/32   10/32   |    5 =      -     -     5
   6 = 20/32   12/32   |    6 =      -     -     6
   7 = 18/32   14/32   |    7 =      -     -     7/EDP
   8 = 16/32   16/32   |    8 = 30/32    2/32   -
   9 = 14/32   18/32   |    9 = 28/32    4/32   -
  10 = 12/32   20/32   |   10 = 26/32    6/32   -
  11 = 10/32   22/32   |   11 = 24/32    8/32   -
  12 =    8/32   24/32   |   12 = 22/32  10/32   -
  13 =    6/32   26/32   |   13 = 20/32  12/32   -
  14 =    4/32   28/32   |   14 = 18/32  14/32   -
  15 =    2/32   30/32   |   15 = 16/32  16/32   -
---Mode B:           |  Mode D:
 mix: new:    old:   |   mix:          new:   old:  description:
   0 = 30/32    2/32   |   00h..BEh =    -      -   normal color
   1 = 26/32    6/32   |   BFh        =    -      -   EDP
   2 = 22/32   10/32   |   C0h        = 32/32   0/32
   3 = 18/32   14/32   |   C1h        = 31/32   1/32
   4 = 14/32   18/32   |   C2h        = 30/32   2/32
   5 = 10/32   22/32   |   ...        =  ...    ...
   6 =    6/32   26/32   |   DFh        =  0/32  32/32
   7 =    2/32   30/32   |   E0h-FFh  =    -      -   normal color
SeeAlso: #P170
----------P03CE03CF--------------------------
PORT 03CE-03CF - Compaq Qvision - Functionality Level

03CE  -W  graphics address register (index for next port) (see #P172)
03CF  RW  other graphics register

(Table P172)
Values for Compaq QVision graphics register index:
 0Ch  RO    controller version
        2Fh Advanced VGA
        37h early QVision 1024
        71h QVision 1280 or later QVision 1024
 0Dh        extended controller version
 0Eh        extended controller capabilities
 0Fh        environment info
 54h        available memory
 55h        phase-locked-loop clock
 56h-57h    controller capabilities
----------P03D003DF--------------------------
PORT 03D0-03DF - CGA   (Color Graphics Adapter)

03D0  -W  same as PORT 03D4h
03D1  RW  same as PORT 03D5h
03D2  -W  same as PORT 03D4h
03D3  RW  same as PORT 03D5h
03D4  rW  CRT (6845) index register   (CGA/MCGA/color EGA/color VGA)
    selects which register (0-11h) is to be accessed through 03D5
    this port is r/w on some VGA, e.g. ET4000
        bit 7-6 =0: (VGA) reserved
        bit 5   =0: (VGA) reserved for testage
        bit 4-0   : selects which register is to be accessed through 03D5
03D5  -W  CRT (6845) data register    (CGA/MCGA/color EGA/color VGA)
    selected by PORT 03D4h. registers 0C-0F may be read
      (see also PORT 03B5h)
    MCGA, native EGA and VGA use very different defaults from those
      mentioned for the other adapters; for additional notes and
      registers 00h-0Fh and EGA/VGA registers 10h-18h and ET4000
      registers 32h-37h see PORT 03B5h (see #P137)
    registers 10h-11h on CGA, EGA, VGA and 12h-14h on EGA, VGA are
      conflictive with MCGA (see #P173)
03D6  -W  same as 03D4
    (under OS/2, reads return 0 if full-screen DOS session,
      nonzero if windowed DOS session)
03D7  RW  same as 03D5
03D8  RW  CGA mode control register  (except PCjr) (see #P178)
    cannot be found on native color EGA, color VGA, but on most clones
03D9  RW  CGA palette register (see #P180)
    (MCGA) CGA border control register
    Cannot be found on native EGA, VGA (without translation ROM) but
      only most clones. Read access on Genoa SuperEGA is 'reset'???
03DA  R-  CGA status register (see #P179)
    color EGA/VGA: input status 1 register
03DA  -W  color EGA/color VGA feature control register (see #P181)
    (at PORT 03BAh w in mono mode, VGA: 3CAh r)
03DA  -W  HZ309 (MDA/HGC/CGA clone) card from in Heath/Zenith HZ150 PC
    bit7-1=0: unknown, zero is default and known to function
           properly at least in CGA modes.
    bit 0 = 1 override 3x8h bit3 control register that switches
           CRT beam off if bit3 is cleared. So screens always
           stays on.
    bit 0 = 0 3x8h bit3 indicates if CRT beam is on or off.
           No more info available. Might conflict with EGA/VGA.
03DB  rW  clear light pen latch    (not MCGA)
          (R/W only with Genoa SuperEGA)
03DC  RW  (not MCGA) preset light pen latch
03DC  -W  (CGA) set light pen latch
03DD  -W  (MCGA)  Extended mode control register
      (Plantronics & Genoa SuperEGA: Plantronics ColorPlus control,
              compatible with MCGA???)
    (default is 00h, in mode 13h: 04h)
    bit7 =1: DAC active, cannot be read
         =0: DAC not active, read allowed
    bit6-3 : reserved
    bit2 =1: videomode 13h with 256 colors active
    bit1    : reserved
    bit0 =0: reserved
03DE  --  (MCGA) reserved
03DE  -W  AT&T & color ET4000 in AT&T compatibility mode: AT&T mode control
      register (see #P182)
    (register enabled in ET4000, if bit7=1 in CRTC 3D4h/34h.)
03DF  --  (MCGA) reserved
03DF  ?W  CRT/CPU page register     (PCjr only)

(Table P173)
Values for MCGA (only) CRT Controller register index:
 10h  W mode control register (defaults 18h, 1Ah, 19h) (see #P174)
 10h R    mode control status register (see #P175)
 11h    interrupt control register (default 30h) (see #P176)
 12h    character generator/sync polarity register (see #P177)
 12h R    display sense register (11h, bit7=1)
    bit 7-2     : not used
    bit 1-0     : pins 11 & 12 in monitor cable
        00b = reserved
        01b = analogue monochrom monitor
        10b = analogue color graphics monitor
        11b = no monitor
 13h W    character font pointer register
    only 00h, 10h, 20h, 30h (default 00h) are allowed here
      for textmode fonts at A0000, A2000, A4000, A6000
 14h W    number of characters to load during vert. retrace period (default FFh)
SeeAlso: #P137

Bitfields for MCGA (only) CRT mode control register:
Bit(s)    Description    (Table P174)
 7    suppress hsync/vsync
 6    reserved (0)
 5    reserved
 4    dot clock rate
 3    refresh calculations in 80x25 modes
 2    reserved
 1    videomode 11h active
 0    videomode 13h active
SeeAlso: #P173,#P175

Bitfields for MCGA (only) CRT mode control status register:
Bit(s)    Description    (Table P175)
 7    status bit0 CGA mode control register
 6    reserved
 5    clockrate 640 pixel, =0: clockrate/2 320 pixel
 4    clock rate is 25,175Mhz
 3    currently in textmode
 2    double-scan activated
 1    videomode 11h active
 0    videomode 13h active
SeeAlso: #P173,#P174

Bitfields for MCGA (only) CRT interrupt control register:
Bit(s)    Description    (Table P176)
 7    set output driver to tristate
    =0: for reading of character generator reg (12h)
    =1: for reading of display sense register (12h)
 6   R    intr generated by memory controller
 5    =0 requested intr ok to handle
 4    =0 free interrupt latch register
 3-0    reserved
SeeAlso: #P173

Bitfields for MCGA (only) CRT character generator/sync polarity register:
Bit(s)    Description    (Table P177)
 7    character generator active
 6    =1 load codepage during display
    =0 load codepage during retrace
 5    codepage number (0,1)
 4    512 characters active
 3    reserved (0)
 2    enable hsync/vsync
 1    positive vsync polarity
 0    positive hsync polarity
Note:    default 46h in all modes, except 04h in mode 11h)
SeeAlso: #P173

Bitfields for CGA mode control register:
Bit(s)    Description    (Table P178)
 7-0    =A0h color ET4000: second part of 'key', see Hercules compatibility
      register (see PORT 03BFh) for details. For resetting the key, e.g.
      write 01h to PORT 03BFh and 29h to PORT 03D8h.
 7-6    not used
 6    color ET4000 only, read-only: report status of bit 1 (enable 2nd page)
      of hercules compatibility register (see PORT 03BFh)
 5    =1  blink enabled instead of foreground high-int.
 4    =1  640*200 graphics mode
 3    =1  video enabled (HZ309, see PORT 03DAh bit 0)
 2    =1  monochrome signal
                   (MCGA) in mode 6 and 11h color comes from pal-
                   regs 00 (black) and 07 (white), and can be
                   changed there.
 1    =0  text mode
    =1  320*200 graphics mode
 0    text columns (0 = 40*25 text mode, 1 = 80*25 text mode)
SeeAlso: #P179

Bitfields for CGA status register:
Bit(s)    Description    (Table P179)
 7-6    not used
 5-4    color EGA, color ET4000: diagnose video display feedback, select
      from color plane enable
 3    in vertical retrace
 2    (CGA,color EGA) light pen switch is off
    (MCGA,color ET4000) reserved (0)
 1    (CGA,color EGA) positive edge from light pen has set trigger
    (MCGA,color ET4000) reserved (0)
 0    horizontal retrace in progress
    =0  do not use memory
    =1  memory access without interfering with display
        (Genoa SuperEGA) horizontal or vertical retrace
SeeAlso: #P178,#P180

Bitfields for CGA palette register:
Bit(s)    Description    (Table P180)
 7-6    not used
 5    =0 active 320x200x4 color set: red, green brown
    =1 active 320x200x4 color set: cyan, magenta, white
 4    intense colors in graphics, background colors text
 3    intense border in 40*25, intense background in 320*200, intense
      foreground in 640*200
 2    red border in 40*25, red background in 320*200,    red foreground in
      640*200
 1    green border in 40*25, green background in 320*200, green foreground
      in 640*200
 0    blue border in 40*25, blue background in 320*200, blue foreground in
       640*200
SeeAlso: #P178,#P179

Bitfields for color EGA/VGA feature control register:
Bit(s)    Description    (Table P181)
 7    ET4000 only: enable NMI generation ('key' protected)
 6-4    not used
 3    (VGA) 0 = normal vsync, 1 = vsync OR display enable
 2    reserved
 1    EGA and ET4000 only: FEAT1 control bit1 (pin17 feature connector)
 0    EGA and ET4000 only: FEAT0 control bit0 (pin19 feature connector)

Bitfields for AT&T mode control register:
Bit(s)    Description    (Table P182)
 7    reserved
 6    underline color attribute enable
    ET4000: enabled, if bit6=1 in CRTC 3D4h/34h.
 5    reserved
 4    reserved
 3    alternate page select (=1: 2nd 16KB page, with bit0=0)
 2    alternate font select (0=default font block)
 1    reserved
 0    double scan line mode (0=IBM 200, 1=AT&T 400 line graphics)
    (ET4000) enabled, if bit7-6=11b in CRTC 3D4h/34h.
----------P03E003E8--------------------------
PORT 03E0-03E8    - LPT port address on the UniRAM card by German magazine c't
Range:    selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P03E003EF--------------------------
PORT 03E0-03EF - COM port addresses on UniRAM card by German magazine c't
Range:    selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
----------P03E803EF--------------------------
PORT 03E8-03EF - serial port, same as 02E8, 02F8 and 03F8 (COM3)
SeeAlso: PORT 03F8h-03FFh
----------P03E803EF--------------------------
PORT 03E8-03EF    -  LPT port address on the UniRAM card by German magazine c't
Range:    selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P03EB------------------------------
PORT 03EB - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
      PORT 036Bh, PORT 03ABh
----------P03EC------------------------------
PORT 03EC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P03F003F7--------------------------
PORT 03F0-03F7 - FDC 1    (1st Floppy Disk Controller)    second FDC at 0370
Note:    floppy disk controller is usually an 8272, 8272A, NEC765 (or
      compatible), or an 82072 or 82077AA for perpendicular recording at
      2.88M
SeeAlso: PORT 0370h-0377h

03F0  R-  diskette controller status A (PS/2) (see #P183)
03F0  R-  diskette controller status A (PS/2 model 30) (see #P184)
03F0  R-  diskette EHD controller board jumper settings (82072AA) (see #P185)
03F1  R-  diskette controller status B (PS/2) (see #P186)
03F1  R-  diskette controller status B (PS/2 model 30) (see #P187)
03F2  -W  diskette controller DOR (Digital Output Register) (see #P188)
03F3  ?W  tape drive register (on the 82077AA)
    bit 7-2     reserved, tri-state
    bit 1-0     tape select
        =00  none, drive 0 cannot be a tape drive.
        =01  drive1
        =10  drive2
        =11  drive3
03F4  R-  diskette controller main status register (see #P191)
    Note:    in non-DMA mode, all data transfers occur through
          PORT 03F5h and the status registers (bit 5 here
          indicates data read/write rather than than
          command/status read/write)
03F4  -W  diskette controller data rate select register (see #P192)
03F5  R-  diskette command/data register 0 (ST0) (see #P193)
    status register 1 (ST1) (see #P194)
    status register 2 (ST2) (see #P195)
    status register 3 (ST3) (see #P196)
03F5  -W  diskette command register.  The commands summarized here are
      mostly multibyte commands. This is for brief recognition only.
      (see #P199)
03F6  --  reserved on FDC
03F6  rW  FIXED disk controller data register (see #P197)
03F7  RW  harddisk controller (see #P198)
03F7  R-  diskette controller DIR (Digital Input Register, PC/AT mode)
         bit 7 = 1 diskette change
         bit 6-0   tri-state on FDC
03F7  R-  diskette controller DIR (Digital Input Register, PS/2 mode)
      (see #P189)
03F7  R-  diskette controller DIR (Digital Input Register, PS/2 model 30)
      (see #P190)
03F7  -W  configuration control register (PC/AT, PS/2)
         bit 7-2       reserved, tri-state
         bit 1-0 = 00  500 Kb/S mode (MFM)
             = 01  300 Kb/S mode (MFM)
             = 10  250 Kb/S mode (MFM)
             = 11  1   Mb/S mode (MFM) (on 82072/82077AA)
    conflict bit 0       FIXED DISK drive 0 select
03F7  -W  configuration control register (PS/2 model 30)
         bit 7-3       reserved, tri-state
         bit 2           NOPREC (has no function. set to 0 by hardreset)
         bit 1-0 = 00  500 Kb/S mode (MFM)
             = 01  300 Kb/S mode (MFM)
             = 10  250 Kb/S mode (MFM)
             = 11  1   Mb/S mode (MFM) (on 82072/82077AA)
    conflict bit 0       FIXED DISK drive 0 select

Bitfields for diskette controller status A (PS/2):
Bit(s)    Description    (Table P183)
 7    interrupt pending
 6    -DRV2    second drive installed
 5    step
 4    -track 0
 3    head 1 select
 2    -index
 1    -write protect
 0    +direction
SeeAlso: #P184,#P186

Bitfields for diskette controller status A (PS/2 model 30):
Bit(s)    Description    (Table P184)
 7    interrupt pending
 6    DRQ
 5    step F/F
 4    -track 0
 3    head 1 select
 2    +index
 1    +write protect
 0    -direction
SeeAlso: #P183,#P185,#P187

Bitfields for diskette EHD controller board jumper settings:
Bit(s)    Description    (Table P185)
 7-6    drive 3
 5-4    drive 2
 3-2    drive 1
 1-0    drive 0
     00  1.2Mb
     01  720Kb
     10  2.8Mb
     11  1.4Mb
SeeAlso: #P183

Bitfields for diskette controller status B (PS/2):
Bit(s)    Description    (Table P186)
 7-6    reserved (1)
 5    drive select (0=A:, 1=B:)
 4    write data
 3    read data
 2    write enable
 1    motor enable 1
 0    motor enable 0
SeeAlso: #P183,#P187

Bitfields for diskette controller status B (PS/2 model 30):
Bit(s)    Description    (Table P187)
 7    -DRV2 second drive installed
 6    -DS1
 5    -DS0
 4    write data F/F
 3    read data F/F
 2    write enable F/F
 1    -DS3
 0    -DS2
SeeAlso: #P184,#P186

Bitfields for diskette controller Digital Output Register (DOR):
Bit(s)    Description    (Table P188)
 7-6    reserved on PS/2
 7    drive 3 motor enable
 6    drive 2 motor enable
 5    drive 1 motor enable
 4    drive 0 motor enable
 3    diskette DMA enable (reserved PS/2)
 2    =1  FDC enable    (controller reset)
    =0  hold FDC at reset
 1-0    drive select (0=A 1=B ..)
SeeAlso: #P183,#P191,#P192,#P189

Bitfields for diskette controller Digital Input Register (PS/2 mode):
Bit(s)    Description    (Table P189)
 7    = 1 diskette change
 6-3    = 1
 2    datarate select1
 1    datarate select0
 0    = 0 high density select (500Kb/s, 1Mb/s)
 0    (conflict) FIXED DISK drive 0 select
SeeAlso: #P190,#P188

Bitfields for diskette controller Digital Input Register (PS/2 model 30):
Bit(s)    Description    (Table P190)
 7    = 0 diskette change
 6-4    = 0
 3    -DMA gate (value from DOR register)
 2    NOPREC (value from CCR register)
 1    datarate select1
 0    datarate select0
 0    (conflict) FIXED DISK drive 0 select
SeeAlso: #P189

Bitfields for diskette controller main status register:
Bit(s)    Description    (Table P191)
 7    =1  RQM     data register is ready
    =0  no access is permitted
 6    =1  transfer is from controller to system
    =0  transfer is from system to controller
 5    non-DMA mode
 4    diskette controller is busy
 3    drive 3 busy (reserved on PS/2)
 2    drive 2 busy (reserved on PS/2)
 1    drive 1 busy (= drive is in seek mode)
 0    drive 0 busy (= drive is in seek mode)
SeeAlso: #P188

Bitfields for diskette controller data rate select register:
Bit(s)    Description    (Table P192)
 7-2    reserved on 8272
 7    software reset (self clearing)    82072/82077AA
 6    power down            82072/82077AA
 5    (8272/82077AA) reserved (0)
    (82072) PLL select bit
 4-2    write precompensation value, 000 default
 1-0    data rate select
    =00  500 Kb/S MFM    250 Kb/S FM
    =01  300 Kb/S MFM    150 Kb/S FM
    =10  250 Kb/S MFM    125 Kb/S FM
    =11  1Mb/S    MFM    illegal     FM on 8207x
SeeAlso: #P188

Bitfields for diskette command/data register 0 (ST0):
Bit(s)    Description    (Table P193)
 7-6    last command status
    00  command terminated successfully
    01  command terminated abnormally
    10  invalid command
    11  terminated abnormally by change in ready signal
 5    seek completed
 4    equipment check occurred after error
 3    not ready
 2    head number at interrupt
 1-0    unit select (0=A 1=B .. ) (on PS/2: 01=A  10=B)
SeeAlso: #P194,#P195,#P196

Bitfields for diskette status register 1 (ST1):
Bit(s)    Description    (Table P194)
 7    end of cylinder; sector# greater then sectors/track
 6    =0
 5    CRC error in ID or data field
 4    overrun
 3    =0
 2    sector ID not found
 1    write protect detected during write
 0    ID address mark not found
SeeAlso: #P193,#P195,#P196

Bitfields for diskette status register 2 (ST2):
Bit(s)    Description    (Table P195)
 7    =0
 6    deleted Data Address Mark detected
 5    CRC error in data
 4    wrong cylinder detected
 3    scan command equal condition satisfied
 2    scan command failed, sector not found
 1    bad cylinder, ID not found
 0    missing Data Address Mark
SeeAlso: #P193,#P194,#P196

Bitfields for diskette status register 3 (ST3):
Bit(s)    Description    (Table P196)
 7    fault status signal
 6    write protect status
 5    ready status
 4    track zero status
 3    two sided status signal
 2    side select (head select)
 1-0    unit select (0=A 1=B .. )
SeeAlso: #P193,#P194,#P195

Bitfields for fixed disk controller data register:
Bit(s)    Description    (Table P197)
 7-4    reserved
 3    =0  reduce write current
    =1  head select 3 enable
 2    disk reset enable
 1    disk initialization disable
 0    reserved
SeeAlso: #P188,#P198

Bitfields for hard disk controller:
Bit(s)    Description    (Table P198)
 6    FIXED DISK write gate
 5    FIXED DISK head select 3 / reduced write current
 4    FIXED DISK head select 2
 3    FIXED DISK head select 1
 2    FIXED DISK head select 0
 1    FIXED DISK drive 1 select
 0    FIXED DISK drive 0 select
SeeAlso: #P197

(Table P199)
Values for diskette commands:
    MFM = MFM mode selected, opposite of MF mode
    HDS = head select
    DS  = drive select
    MT  = multi track operation
    SK  = skip deleted data address mark
   Command         # bytes    D7  6    5   4    3   2    1   0
 read track        9    0  MFM    0   0    0   0    1   0
                0   0    0   0    0 HDS DS1 DS0
 specify        3    0   0    0   O    O   O    1   1
 sense drive status    2    0   0    0   0    0   1    0   0
                0   0    0   0    0 HDS DS1 DS0
 write data        9    MT MFM    0   0    0   1    0   1
                0   0    0   0    0 HDS DS1 DS0
 read data        9    MT MFM SK   0    0   1    1   0
                0   0    0   0    0 HDS DS1 DS0
 recalibrate        2    0   0    0   0    0   1    1   1
                0   0    0   0    0   0 DS1 DS0
 sense interrupt status 1    0   0    0   0    1   0    0   0
 write deleted data    9    MT MFM    0   0    1   0    0   1
                0   0    0   0    0 HDS DS1 DS0
 read ID        2    0  MFM    0   0    1   0    1   0
                0   0    0   0    0 HDS DS1 DS0
 read deleted data    9    MT MFM SK   0    1   1    0   0
                0   0    0   0    0 HDS DS1 DS0
 format track        10    0  MFM    0   0    1   1    0   1
                0   0    0   0    0 HDS DS1 DS0
 dumpreg **        1    0   0    0   0    1   1    1   0
 seek            3    0   0    0   0    1   1    1   1
                0   0    0   0    0 HDS DS1 DS0
 version **        1    0   0    0   1    0   0    0   0
 scan equal *        9    MT MFM SK   1    0   0    0   1
                0   0    0   0    0 HDS DS1 DS0
 perpendicular mode **    2    0   0    0   1    0   0    1   0
                0   0    0   0    0   0 WGATE GAP
 configure **        4    0   0    0   1    0   0    1   1
                0   0    0   0    0   0    0   0
 verify            9    MT MFM SK   1    0   1    1   0
                EC  0    0   0    0 HDS DS1 DS0
 scan low or equal *    9    MT MFM SK   1    1   0    0   1
                0   0    0   0    0 HDS DS1 DS0
 scan high or equal *    9    MT MFM SK   1    1   1    0   1
                0   0    0   0    0 HDS DS1 DS0
 relative seek **    3    1  DIR    0   0    1   1    1   1
                0   0    0   0    0 HDS DS1 DS0
BEWARE: not every invalid command is treated as invalid!
 *  Note: the scan commands aren't mentioned for the 82077AA.
 ** Note: EHD controller commands.
----------P03F003F1--------------------------
PORT 03F0-03F1 - PCTech RZ1000 IDE controller
Note:    to unlock access to these ports instead of the standard floppy
      controller status ports at these two addresses, you must perform
      two immediately successive 8-bit OUTs of 55h to PORT 03F0h (there
      is a fairly small time limit between the two accesses, so there
      should be no other instructions between the two OUTs); after
      that, values written to PORT 03F0h select the data accessed through
      PORT 03F1h until an AAh is written to 03F0h
SeeAlso: #0629

03F0  ?W  index port (see #P200)
03F1  RW  data port

(Table P200)
Values for RZ1000 IDE controller registers:
 00h    ???
    bit 7:
    bit 1:
    bit 0:
 01h    ???
 02h    ???
 03h    ???
 04h    ???
 05h    ???
    bit 1:
 AAh    lock control port
----------P03F803FF--------------------------
PORT 03F8-03FF - Serial port (8250,8250A,8251,16450,16550,16550A,etc.) COM1
Range:    PORT 02E8h-02EFh (COM2), PORT 02F8h-02FFh (typical non-PS/2 COM3), and
      PORT 03E8h-03EFh (typical non-PS/2 COM4)
Note:    chips overview:
     8250  original PC, specified up to 56Kbd, but mostly runs
           only 9600Bd, no scratchregister, bug: sometimes shots
           ints without reasons
     8250A, 16450, 16C451: ATs, most chips run up to 115KBd,
           no bug: shots no causeless ints
     8250B: PC,XT,AT, pseudo bug: shots one causeless int for
        compatibility with 8250, runs up to 56KBd
     16550, 16550N, 16550V: early PS/2, FIFO bugs
     16550A,16550AF,16550AFN,16550C,16C551,16C552: PS/2, FIFO ok
     82510: laptops & industry, multi emulation mode
        (default=16450), special-FIFO.
     8251: completely different synchronous SIO chip, not compatible!
SeeAlso: INT 14/AH=00h"SERIAL"

03F8  -W  serial port, transmitter holding register (THR), which contains the
      character to be sent. Bit 0 is sent first.
        bit 7-0      data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  R-  receiver buffer register (RBR), which contains the received
      character. Bit 0 is received first
         bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  RW  divisor latch low byte (DLL) when DLAB=1 (see #P201)
03F9  RW  divisor latch high byte (DLM) when DLAB=1 (see #P201)
03F9  RW  interrupt enable register (IER) when DLAB=0 (see #P202)
03FA  R-  interrupt identification register (see #P203)
    Information about a pending interrupt is stored here. When the ID
      register is addressed, thehighest priority interrupt is held, and
      no other interrupts are acknowledged until the CPU services that
      interrupt.
03FA  -W  16650 FIFO Control Register (FCR) (see #P204)
03FB  RW  line control register (LCR) (see #P205)
03FC  RW  modem control register (see #P206)
03FD  R-  line status register (LSR) (see #P207)
03FE  R-  modem status register (MSR) (see #P208)
03FF  RW  scratch register (SCR)
    (not used for serial I/O; available to any application using 16450,
      16550) (not present on original 8250)

(Table P201)
Values for serial port divisor latch registers:
 Some baudrates (using standard 1.8432 Mhz clock):
       baudrate       divisor     DLM  DLL
        50       2304          09h 00h
        75       1536          06h 00h
       110       1047          04h 17h
       134,5    857          03h 59h
       150        768          03h 00h
       300        384          01h 80h
       600        192          00h C0h
      1200         96          00h 60h
      1800         64          00h 40h
      2000         58          00h 3Ah
      2400         48          00h 30h
      3600         32          00h 20h
      4800         24          00h 18h
      7200         16          00h 10h
      9600         12          00h 0Ch
     19200          6          00h 06h
     38400          3          00h 03h
     57600          2          00h 02h
    115200          1          00h 01h
Note:    MIDI baudrate 32250Bd with 4Mhz quarz for c't MIDI interface
      following c't 01/1991:   '14400'      00h 08h

Bitfields for serial port interrupt enable register (IER):
Bit(s)    Description    (Table P202)
 7-4    reserved (0)
 3    modem-status interrupt enable
 2    receiver-line-status interrupt enable
 1    transmitter-holding-register empty interrupt enable
 0    received-data-available interrupt enable
      (also 16550(A) timeout interrupt)
Note:    16550(A) will interrupt with a timeout if data exists in the FIFO
      and isn't read within the time it takes to receive four bytes or if
      no data is received within the time it takes to receive four bytes
SeeAlso: #P203

Bitfields for serial port interrupt identification register (IIR):
Bit(s)    Description    (Table P203)
 7-6    =00  reserved on 8250, 8251, 16450
    =01  if FIFO queues enabled but unusable (16550 only)
    =11  if FIFO queues are enabled (16550A only) (see also #P204)
 6-5    (used by 82510 for FIFO status???)
 5-4    reserved (0)
 3    (8250,16450) reserved (0)
    (16550) timeout interrupt pending
 2-1    identify pending interrupt with the highest priority
    11    receiver line status interrupt. priority=highest
    10    received data available register interrupt. pr.=second
    01    transmitter holding register empty interrupt. pr.=third
    00    modem status interrupt. priority=fourth
 0    =0 interrupt pending. contents of register can be used as a pointer
      to the appropriate interrupt service routine
    =1 no interrupt pending
Notes:    interrupt pending flag uses reverse logic, 0=pending, 1=none
    interrupt will occur if any of the line status bits are set
    THRE bit is set when THRE register is emptied into the TSR
SeeAlso: #P202

Bitfields for serial port FIFO control register (FCR):
Bit(s)    Description    (Table P204)
 7-6    received data available interrupt trigger level (16550)
    00  1 byte
    01  4 bytes
    10  8 bytes
    11 14 bytes
 6-5    =00  (used to enable 4 byte Rx/Tx FIFOs on 82510???)
    =10 ???
 5-4    reserved (00)
 3    change RXRDY  TXRDY pins from mode 0 to mode 1
 2    clear XMIT FIFO
 1    clear RCVR FIFO
 0    enable clear XMIT and RCVR FIFO queues
 4-0    (other purpose on 82510???)
Notes:    bit 0 must be set in order to write to other FCR bits
    bit 1 when set    the RCVR FIFO is cleared and this bit is reset
      the receiver shift register is not cleared
    bit 2 when set    the XMIT FIFO is cleared and this bit is reset
      the transmit shift register is not cleared
    due to a hardware bug, 16550 FIFOs don't work correctly (this
      was fixed in the 16550A)
SeeAlso: #P203

Bitfields for serial port Line Control Register (LCR):
Bit(s)    Description    (Table P205)
 7    =1  divisor latch access bit (DLAB)
    =0  receiver buffer, transmitter holding, or interrupt enable register
      access
 6    set break enable. serial ouput is forced to spacing state and remains
      there.
 5-3    PM2 PM1 PM0
     x   x     0 = no parity
     0   0     1 = odd parity
     0   1     1 = even parity
     1   0     1 = high parity (sticky)
     1   1     1 = low parity (sticky)
     x   x     1 = software parity
 2    stop bit length (STB/SBL)
    0  one stop bit
    1  2 stop bits with (word length 6, 7, 8)
       1.5 stop bits with word length 5
 1-0    (WLS1-0, CL1-0)
    00 word length is 5 bits
    01 word length is 6 bits
    10 word length is 7 bits
    11 word length is 8 bits
SeeAlso: #P206,#P207,#P208

Bitfields for serial port Modem Control Register (MCR):
Bit(s)    Description    (Table P206)
 7-5    reserved (0)
 4    loopback mode for diagnostic testing of serial port
    output of transmitter shift register is looped back to receiver
      shift register input. In this mode, transmitted data is received
      immediately so that the CPU can verify the transmit data/receive
      data serial port paths.
    If OUT2 is disabled, there is no official way to generate an IRQ
      during loopback mode.
 3    auxiliary user-designated output 2 (OUT2)
    because of external circuity OUT2 must be 1 to master-intr-enableing.
    BUG: Some Toshiba Laptops utilize this bit vice versa, newer Toshiba
      machines allow assignment of the bit's polarity in system setup.
    82050: This bit is only effective, if the chip is being used with an
      externally-generated clock.
 2    =1/0  auxiliary user-designated output 1 (OUT1)
    should generally be cleared!!
    Some external hardware, e.g. c't MIDI interface (and compatibles) use
      this bit to change the 8250 input clock from 1,8432 MHz to 4Mhz
      (enabling MIDI-conformant baudrates) and switching to
      MIDI-compatible current loop connectors.
 1    force request-to-send active (RTS)
 0    force data-terminal-ready active (DTR)
SeeAlso: #P205,#P207,#P208

Bitfields for serial port Line Status Register (LSR):
Bit(s)    Description    (Table P207)
 7    =0  reserved
    =1  on some chips produced by UMC
 6    transmitter shift and holding registers empty
 5    transmitter holding register empty (THRE)
    Controller is ready to accept a new character to send.
 4    break interrupt. the received data input is held in the zero bit
      state longer than the time of start bit + data bits + parity bit +
      stop bits.
 3    framing error (FE). the stop bit that follows the last parity or data
      bit is a zero bit
 2    parity error (PE). Character has wrong parity
 1    overrun error (OE). a character was sent to the receiver buffer
      before the previous character in the buffer could be read. This
      destroys the previous character.
 0    data ready. a complete incoming character has been received and sent
      to the receiver buffer register.
SeeAlso: #P205,#P206,#P208

Bitfields for serial port Modem Status Register (MSR):
Bit(s)    Description    (Table P208)
 7    data carrier detect (-DCD)
 6    ring indicator (-RI)
 5    data set ready (-DSR)
 4    clear to send (-CTS)
 3    delta data carrier detect (DDCD)
 2    trailing edge ring indicator (TERI)
 1    delta data set ready (DDSR)
 0    delta clear to send (DCTS)
Notes:    bits 0-3 are reset when the CPU reads the MSR
    bit 4 is the Modem Control Register RTS during loopback test
    bit 5 is the Modem Control Register DTR during loopback test
    bit 6 is the Modem Control Register OUT1 during loopback test
    bit 7 is the Modem Control Register OUT2 during loopback test
SeeAlso: #P205,#P206,#P207
--------!---Note-----------------------------
Note:    Adresses above 03FF generally apply to EISA and PCI machines only !
    EISA port assignments:
        1000-1FFF    slot 1 EISA
        2000-2FFF    slot 2 EISA
        3000-3FFF    slot 3 EISA
        4000-4FFF    slot 4 EISA
        5000-5FFF    slot 5 EISA
        6000-6FFF    slot 6 EISA
        7000-7FFF    slot 7 EISA
----------P0401040B--------------------------
PORT 0401-040B - EISA DMA Controller
SeeAlso: PORT 0481h-048Bh"EISA",PORT 04D4h-04D6h"EISA"

0401  RW  DMA channel 0 word count byte 2 (high)
0403  RW  DMA channel 1 word count byte 2 (high)
0405  RW  DMA channel 2 word count byte 2 (high)
0407  RW  DMA channel 3 word count byte 2 (high)
040A  -W  extended DMA chaining mode register, channels 0-3 (see #P209)
040A  R-  channel interrupt (IRQ13) status register (see #P210)
040B  -W  DMA extended mode register for channels 0-3 (see #P211)
    (bit settings same as PORT 04D6h)

Bitfields for EISA extended DMA chaining mode register (channels 0-3):
Bit(s)    Description    (Table P209)
 7-5    reserved
 4    =0  generate IRQ13
    =1  generate terminal count
 3    =0  do not start chaining
    =1  programming complete
 2    =0  disable buffer chaining mode (default)
    =1  enable buffer chaining mode
 1-0    DMA channel select
SeeAlso: #P210,#P211,#P215

Bitfields for EISA channel interrupt (IRQ13) status register:
Bit(s)    Description    (Table P210)
 7-5  interrupt on channels 7-5
 4      reserved
 3-0  interrupt on channels 3-0
SeeAlso: #P209

Bitfields for EISA DMA extended mode register (channels 0-3):
Bit(s)    Description    (Table P211)
 7    =0 enable stop register
 6    =0 terminal count is an output for this channel    (default)
 5-4    DMA cycle timing
    00 ISA-compatible (default)
    01 type A timing mode
    10 type B timing mode
    11 burst DMA mode
 3-2    Address mode
    00 8-bit I/O, count by bytes (default)
    01 16-bit I/O, count by words, address shifted
    10 32-bit I/O, count by bytes
    11 16-bit I/O, count by bytes
 1-0    DMA channel select
SeeAlso: #P209,#P216
---------------------------------------------
PORT 040A-043F - Intel 82378ZB embedded DMA controller
Range:    relocatable via Relocation Base Address register (see #3341)
SeeAlso: PORT 0401h"EISA",#0642,#3341

040A  R-  scatter/gather interrupt status (see #P275)
040B  -W  DMA1 extended mode
0410  -W  CH0 scatter/gather command (see #P273)
0411  -W  CH1 scatter/gather command
0412  -W  CH2 scatter/gather command
0413  -W  CH3 scatter/gather command
0414  -W  CH4 scatter/gather command
0415  -W  CH5 scatter/gather command
0416  -W  CH6 scatter/gather command
0417  -W  CH7 scatter/gather command (see #P273)
0418  R-  CH0 scatter/gather status (see #P274)
0419  R-  CH1 scatter/gather status
041A  R-  CH2 scatter/gather status
041B  R-  CH3 scatter/gather status
041C  R-  CH4 scatter/gather status
041D  R-  CH5 scatter/gather status
041E  R-  CH6 scatter/gather status
041F  R-  CH7 scatter/gather status (see #P274)
0420d RW  CH0 scatter/gather descriptor table address
0424d RW  CH1 scatter/gather descriptor table address
0428d RW  CH2 scatter/gather descriptor table address
042Cd RW  CH3 scatter/gather descriptor table address
0430d RW  CH4 scatter/gather descriptor table address
0434d RW  CH5 scatter/gather descriptor table address
0438d RW  CH6 scatter/gather descriptor table address
043Cd RW  CH7 scatter/gather descriptor table address

(Table P275)
Call Intel 82378ZB Scatter/Gather Interrupt Status Register with:
 7    channel 7 has interrupt due to S/G transfer
 ...
 0    channel 0 has interrupt due to S/G transfer
SeeAlso: #P273,#P274

Bitfields for Intel 82378ZB Scatter/Gather Command Register:
Bit(s)    Description    (Table P273)
  7    select last-buffer termination type
    =0 assert IRQ13 on completion
    =1 assert EOP on completion
 6    enable bit 7 termination-type selection
 5-2    reserved (0)
 1-0    scatter-gather command
    00 none
    01 start S/G command
    10 stop S/G command
    11 reserved
SeeAlso: #P275,#P274,#3341

Bitfields for Intel 82378ZB Scatter/Gather Status Register:
Bit(s)    Description    (Table P274)
 7    no next link
 6    reserved
 5    issue IRQ13 instead of EOP at end of last buffer
 4    reserved
 3    scatter/gather Base Register status
    =1 buffer link has been loaded
    =0 empty
 2    scatter/gather Current Register status
    =1 buffer link has been loaded
    =0 empty
 1    reserved
 0    scatter/gather is active
SeeAlso: #P273
----------P04610462--------------------------
PORT 0461-0462 - EISA NMI CONTROL

0461  RW  Extended NMI status/control register (see #P212)
0462  -W  Software NMI register. writing to this register causes an NMI    if
      NMIs are enabled
    bit 7 = 1  generates an NMI

Bitfields for EISA extended NMI status control register:
Bit(s)    Description    (Table P212)
 7    NMI pending from fail-safe timer (read only)
 6    NMI pending from bus timeout NMI status (read only)
 5    NMI pending (read only)
 4    reserved
 3    bus timeout NMI enable (read/write)
 2    fail-safe NMI enable (read/write)
 1    NMI I/O port enable (read/write)
 0    RSTDRV. bus reset (read/write)
    =0  NORMAL bus reset operation
    =1  reset bus asserted
--------X-P04640465--------------------------
PORT 0464-0465 - EISA BUS MASTER STATUS

0464w R      bus master status latch register (slots 1-16)
    identifies the last bus master that had control of the bus (bit N =
      slot N+1 had control last)
----------P0481048B--------------------------
PORT 0481-048B - EISA DMA page registers
Note:    these registers are also supported on many non-EISA machines, e.g. by
      most machines using Intel PCI chipsets
SeeAlso: PORT 0401h-040Bh"EISA",PORT 04C6h-04CFh"EISA"

0481  RW  DMA channel 2 address byte 3 (high)
0482  RW  DMA channel 3 address byte 3 (high)
0483  RW  DMA channel 1 address byte 3 (high)
0487  RW  DMA channel 0 address byte 3 (high)
0489  RW  DMA channel 6 address byte 3 (high)
048A  RW  DMA channel 7 address byte 3 (high)
048B  RW  DMA channel 5 address byte 3 (high)
----------P04C604CF--------------------------
PORT 04C6-04CF - EISA DMA count registers
SeeAlso: PORT 0401h-040Bh"EISA",PORT 0481h-048Bh"EISA",PORT 04E0h-04FFh"EISA"

04C6  RW  DMA channel 5 word count byte 2 (high)
04CA  RW  DMA channel 6 word count byte 2 (high)
04CE  RW  DMA channel 7 word count byte 2 (high)
--------X-P04D004D1--------------------------
PORT 04D0-04D1 - EISA IRQ control
Note:    these registers are also supported on many non-EISA machines, e.g. by
      most machines using Intel PCI chipsets
SeeAlso: PORT 04D4h-040Bh"EISA"

04D0  -W  IRQ 0-7 interrupt edge/level registers (see #P213)
04D1  -W  IRQ 8-15 interrupt edge/level registers (see #P214)

Bitfields for EISA IRQ 0-7 interrupt edge/level register:
Bit(s)    Description    (Table P213)
 7    IRQ 7 is level sensitive
 6    IRQ 6 is level sensitive
 5    IRQ 5 is level sensitive
 4    IRQ 4 is level sensitive
 3    IRQ 3 is level sensitive
 2-0    reserved
SeeAlso: #P214

Bitfields for EISA IRQ 8-15 interrupt edge/level register:
Bit(s)    Description    (Table P214)
 7    IRQ 15 is level sensitive
 6    IRQ 14 is level sensitive
 5    reserved (1)
 4    IRQ 12 is level sensitive
 3    IRQ 11 is level sensitive
 2    IRQ 10 is level sensitive
 1    IRQ 9  is level sensitive
 0    reserved
SeeAlso: #P213
----------P04D404D6--------------------------
PORT 04D4-04D6 - EISA DMA control
Note:    PORT 04D6h is also supported by the Intel 82378ZB System I/O controller
SeeAlso: PORT 0401h-040Bh"EISA",PORT 04D0h-04D1h"EISA"

04D4  R-  DMA chaining status
04D4  -W  extended DMA chaining mode register, channels 4-7 (see #P215)
04D6  -W  DMA extended mode register for channels 4-7 (see #P216)
    bit settings same as PORT 040Bh

Bitfields for EISA extended DMA chaining mode register (channels 4-7):
Bit(s)    Description    (Table P215)
 7-5    reserved (0)
 4    =0  generate IRQ 13
    =1  generate terminal count
 3    =0  do not start chaining
    =1  programming complete
 2    =0  disable buffer chaining mode (default)
    =1  enable buffer chaining mode
 1-0    DMA channel select
SeeAlso: #P209,#P216

Bitfields for EISA DMA extended mode register (channels 4-7):
Bit(s)    Description    (Table P216)
 7    =0  enable stop register
 6    =0  terminal count is an output for this channel (default)
 5-4    DMA cycle timing
    00 ISA-compatible (default)
    01 type A timing mode
    10 type B timing mode
    11 burst DMA mode
 3-2    Address mode
    00 8-bit I/O, count by bytes (default)
    01 16-bit I/O, count by words, address shifted
    10 32-bit I/O, count by bytes
    11 16-bit I/O, count by bytes
 1-0    DMA channel select
SeeAlso: #P211,#P215
----------P04E004FF--------------------------
PORT 04E0-04FF - EISA DMA stop registers
SeeAlso: PORT 0481h-048Bh"EISA"

04E0-04E2  RW    channel 0
04E4-04E6  RW    channel 1
04E8-04EA  RW    channel 2
04EC-04EE  RW    channel 3
04F4-04F6  RW    channel 5
04F8-04FA  RW    channel 6
04FC-04FE  RW    channel 7
----------P05300533--------------------------
PORT 0530-0533 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:    dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
      PORT 0E80h-0E83h, and PORT 0F40h-0F43h

0530  RW  address select
0531  RW  data
0532  RW  status
0533  RW  PIO
----------P05300537--------------------------
PORT 0530-0537 - Windows Sound System (default address)
Range:    dipswitch selectable among PORT 0530h-0537h,PORT 0604h-060Bh,
      PORT 0E80h-0E87h, and PORT 0F40h-0F47h
Notes:    the Sound Galaxy NX16 sound cards contains a Crystal CS4231, and thus
      support the CODEC portion of the WSS on ports 0534h-0537h
      (or 0608h-060Bh, etc.)
    the AMD InterWave chip supports a superset of the WSS CS4231 Codec,
      though by default it is not placed at any of the addresses used by
      the WSS

0534  ?W  register select (index) (see #P217)
0535  RW  data register (selected by PORT 0534h)

(Table P217)
Values for Windows Sound System CS4231 Codec register number:
 00h    Mixer: ADC volume (left)
 01h    Mixer: ADC volume (right)
 02h    Mixer: Line In volume (right) (see #P218)
 03h    Mixer: Line In volume (left) (see #P218)
 04h    Mixer: FM volume (right) (see #P218)
 05h    Mixer: FM volume (left) (see #P218)
 06h    Mixer: playback DAC volume (left)
 07h    Mixer: playback DAC volume (right)
 08h    playback data format
 09h    configuration register 1
 0Ah    external control
 0Bh    Codec status register 2
 0Ch    mode select
    bit 6: ???
 0Dh    loopback control
    (Sound Galaxy) microphone input enabled by bit 0 ???
 0Eh    playback count (high)
 0Fh    playback count (low)
 10h    configuration register 2
 11h    configuration register 3
 12h    Mixer: CD volume (right) (see #P218)
 13h    Mixer: CD volume (left) (see #P218)
 14h    timer (low)
 15h    timer (high)
 16h    Mixer: microphone input control (left)
 17h    Mixer: microphone input control (right)
 18h    Codec status register 3
 19h    Mixer: output attenuation (left)
 1Ah    mono input/output control
    (Sound Galaxy) SB volume (see #P219)
 1Bh    Mixer: output attenuation (right)
 1Ch    record data format
 1Dh    playback variable frequency
 1Eh    record count (high)
 1Fh    record count (low)
 48h    (Sound Galaxy) ???
Notes:    to enable the microphone input on the Sound Galaxy, ALL of the
      following registers must be set: 00h set to 80h, 01h set to 80h,
      07h to 00h, 0Dh to 01h, and 48h to 4Bh
    on the Sound Galaxy NX16, only bits 0-4 of the register number are
      fully decoded, so most registers above 1Fh are aliases of the
      first 32 registers

Bitfields for WSS mixer volume:
Bit(s)    Description    (Table P218)
 7    disable input source
 6-5    reserved???
 4-0    volume (00h = highest, 1Fh = lowest)
SeeAlso: #P217,#P219
Note:    the GW2000 GWBVOL.EXE only permits the setting of volume levels
      08h (reported as 16) to 18h (reported as 0, and sets bit 7 as well)

Bitfields for WSS mixer volume (SoundBlaster):
Bit(s)    Description    (Table P219)
 7    disable input source
 6-4    reserved???
 3-0    volume (00h = highest, 0Fh = lowest)
SeeAlso: #P217,#P218
----------P0601------------------------------
PORT 0601 - Headland HL21, Acer M5105 chipsets - SYSTEM CONTROL

0601  -W  system control (see #P220)
0601  R-  status (see #P221)

Bitfields for Headland HL21/Acer M5105 system control register:
Bit(s)    Description    (Table P220)
 7    =1  power LED on
 6    =1  LCD backlight off
 5    ???
 4    ???
 3    ???
 2    =1  video chips disabled, screen blanked.
 1    ???
 0    =1  will lock up your machine!
SeeAlso: #P221

Bitfields for Headland HL21/Acer M5105 status register:
Bit(s)    Description    (Table P221)
 7    =0  if screen enabled always these values
 6    =0
 5    =0
 4    =0
 3    =0
 2    =1  (=0 at low power)
 1    =0  power OK
 0    =0
SeeAlso: #P220
----------P06040607--------------------------
PORT 0604-0607 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:    dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
      PORT 0E80h-0E83h, and PORT 0F40h-0F43h
----------P0604060B--------------------------
PORT 0604-060B - Windows Sound System
Range:    PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
----------P06200627--------------------------
PORT 0620-0627 - PC network (adapter 1)
0628-062F - PC network (adapter 2)
----------P06800681--------------------------
PORT 0680-0681 - Microchannel POST Diagnostic (write only)

0680  -W  Microchannel POST Diagnostic (write only)
0681  -W  secondary MCA POST diagnostic
----------P06A006A8--------------------------
PORT 06A0-06A8 - non-standard COM port addresses
Range:    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
Note:    V20-XT by German magazine c't
----------P06A806AF--------------------------
PORT 06A8-06AF - non-standard COM port addresses
Range:    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
Note:    V20-XT by German magazine c't
----------P06E206E3--------------------------
PORT 06E2-06E3 - data aquisition (adapter 1)
----------P06E8------------------------------
PORT 06E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P06E806EF--------------------------
PORT 06E8-06EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)
SeeAlso: PORT 02E8h-02EFh,PORT 0AE8h,PORT 96E8h,PORT 9AE8h

06E8w -W  CRT control: horizontal displayed
----------P0746------------------------------
PORT 0746 - Gravis Ultra Sound by Advanced Gravis - BOARD VERSION / MIXER
SeeAlso: PORT 0240h-024Fh,PORT 0340h-034Fh

0746  R-  board version (rev 3.7+)
        FFh      Pre 3.6 boards, ICS mixer NOT present
        05h      Rev 3.7 with ICS Mixer. Some R/L: flip problems.
        06h-09h      Revision 3.7 and above. ICS Mixer present
        0Ah-      UltraMax. CS4231 present, no ICS mixer
0746  -W  Mixer Control Port
----------P07900793--------------------------
PORT 0790-0793 - cluster (adapter 1)
----------P080008FF--------------------------
PORT 0800-08FF - I/O port access registers for extended CMOS RAM or SRAM
        (256 bytes at a time)
Note:    sometimes plain text can be seen here
--------X-P080008FF--------------------------
PORT 0800-08FF - reserved for EISA system motherboard
----------P0A200A23--------------------------
PORT 0A20-0A23 - Token Ring (adapter 1)
0A24-0A27 - Token Ring (adapter 2)
----------P0A79------------------------------
PORT 0A79 - Plug-and-Play - WRITE DATA PORT
Desc:    all data written to the Plug-and-Play configuration registers is
      written to this port, including the configuration byte which
      indicates the I/O port from which data is to be read when reading
      the configuration registers
SeeAlso: PORT 0279h

0A79  -W  Plug-and-Play data writes
----------P0AE20AE3--------------------------
PORT 0AE2-0AE3 - cluster (adapter 2)
----------P0AE8------------------------------
PORT 0AE8 - S3 86C928 video controller (ELSA Winner 1000)
----------P0AE80AEF--------------------------
PORT 0AE8-0AEF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

0AE8w -W  CRT control: horizontal sync start
----------P0B900B93--------------------------
PORT 0B90-0B93 - cluster (adapter 2)
----------P0C00------------------------------
PORT 0C00 - EISA??? - PAGE REGISTER

0C00  RW  page register to write to SRAM or I/O
--------X-P0C000CFF--------------------------
PORT 0C00-0CFF - reserved for EISA system motherboard
----------P0C7C------------------------------
PORT 0C7C        bit 7-4 (Compaq)
--------X-P0C800C83--------------------------
PORT 0C80-0C83 - EISA system board ID registers

0C80  R?  bit 7: unused (0)
      bits 6-2: manufacturer ID, first compressed ASCII char
      bits 1-0: manufacturer ID, second compressed ASCII char (high)
0C81  R?  bits 7-5: manufacturer ID, second compressed ASCII char (low)
      bits 4-0: manufacturer ID, third compressed ASCII char
0C82  R?  reserved for manufacturer's use
0C83  R?  bits 7-3: reserved for manufacturer's use
      bits 2-0: EISA bus version
--------X-P0CF80CFF--------------------------
PORT 0CF8-0CFF - PCI Configuration Mechanism 1 - Configuration Registers
SeeAlso: PORT 0CF8h"Mechanism 2"

0CF8d -W  configuration address port (see #P222)
0CFCd RW  configuration data port (when PORT 0CF8h bit 31 is set)

Bitfields for PCI configuration address port:
Bit(s)    Description    (Table P222)
 1-0    reserved (00)
 7-2    configuration register number (see #0628)
 10-8    function
 15-11    device number
 23-16    bus number
 30-24    reserved (0)
 31    enable configuration space mapping
Note:    configuration registers are considered DWORDs, so the number in bits
      7-2 is the configuration space address shifted right two bits
SeeAlso: #P223
--------X-P0CF80CFA--------------------------
PORT 0CF8-0CFA - PCI Configuration Mechanism 2 - Configuration Registers
Notes:    this configuration mechanism is deprecated as of PCI version 2.1;
      only mechanism 1 should be used for new systems
    to access the configuration space, write the target bus number to
      the Forward Register, then write to the Configuration Space
      Enable register, and finally read or write the appropriate I/O
      port(s) in the range C000h to CFFFh (where Cxrrh accesses location
      'rr' in physical device 'x's configuration data)
    the Intel "Saturn" and "Neptune" chipsets use configuration mechanism 2
SeeAlso: PORT 0CF8h"Mechanism 1",PORT C000h"PCI Configuration"

0CF8  RW  Configuration Space Enable (CSE) (see #P223)
0CFA  RW  Forward Register (selects target bus number)

Bitfields for PCI Configuration Space Enable:
Bit(s)    Description    (Table P223)
 0    Special Cycle Enable (SCE)
 3-1    target function number (PCI logical device within physical device)
 7-4    key (non-zero to allow configuration)
SeeAlso: #P222
----------P0CF9------------------------------
PORT 0CF9 - Intel 82420EX chipset - TURBO/RESET CONTROL REGISTER
Notes:    this port can only be accessed via 8-bit IN or OUT instructions by
      the CPU
    also supported by the Intel "Saturn" and "Neptune" chipsets
SeeAlso: PORT C051h,#3434

0CF9  RW  reboot system, optionally selecting de-turbo mode (see #P224)

(Table P224)
Call Intel 82420EX turbo/reset control register with:
 7-3    reserved (0)
 2    reset CPU
 1    reset mode
    0 soft reset
    1 hard reset
 0    deturbo mode
Note:    when resetting the CPU, two writes are required: the first sets the
      state of bit 1 while keeping bit 2 cleared, and the second sets
      bit 2; the reset occurs on bit 2's transition from 0 to 1.
--------s-P0E800E83--------------------------
PORT 0E80-0E83 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:    dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
      PORT 0E80h-0E83h, and PORT 0F40h-0F43h
--------s-P0E800E87--------------------------
PORT 0E80-0E87 - Windows Sound System
Range:    PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------V-P0EE8------------------------------
PORT 0EE8 - S3 86C928 video controller (ELSA Winner 1000)
--------V-P0EE80EEF--------------------------
PORT 0EE8-0EEF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

0EE8w -W  CRT control: horizontal sync width
----------P0F400F43--------------------------
PORT 0F40-0F43 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:    dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
      PORT 0E80h-0E83h, and PORT 0F40h-0F43h
----------P0F400F47--------------------------
PORT 0F40-0F47 - Windows Sound System
Range:    PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------X-P100010FF--------------------------
PORT 1000-10FF - available for EISA slot 1
----------P12E812EF--------------------------
PORT 12E8-12EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

12E8w -W  CRT control: vertical total
--------V-P12EE------------------------------
PORT 12EE - ATI Mach32 - CONFIGURATION STATUS 0
SeeAlso: PORT 16EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
----------P13901393--------------------------
PORT 1390-1393 - cluster (adapter 3)
--------X-P140014FF--------------------------
PORT 1400-14FF - available for EISA slot 1
----------P16E816EF--------------------------
PORT 16E8-16EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

16E8w -W  CRT control: vertical displayed
--------V-P16EE------------------------------
PORT 16EE - ATI Mach32 - CONFIGURATION STATUS 1
SeeAlso: PORT 12EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
--------X-P180018FF--------------------------
PORT 1800-18FF - available for EISA slot 1
----------P1AE81AEF--------------------------
PORT 1AE8-1AEF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

1AE8w -W  CRT control: vertical sync start
--------X-P1C001CFF--------------------------
PORT 1C00-1CFF - available for EISA slot 1
----------P1C65------------------------------
PORT 1C65 - Compaq Contura Aero
SeeAlso: PORT 2065h

1C65  R?  bit 6: operating on battery power
--------X-P1C801C8F--------------------------
PORT 1C80-1C8F - VESA XGA Video in EISA slot 1

1C80-1C83  RW    EISA Video ID
1C84  RW    EISA Video expansion board control (see #P225)
1C85  RW    EISA Setup control
1C88  RW    EISA Video Programmable Option Select 0
1C89-1C8F  RW    EISA Video Programmable Option Select 1-7
--------X-P1C801C83--------------------------
PORT 1C80-1C83 - EISA board product ID (board in slot 1)

1C80  R?  bit 7: unused (0)
      bits 6-2: manufacturer ID, first compressed ASCII char
      bits 1-0: manufacturer ID, second compressed ASCII char (high)
1C81  R?  bits 7-5: manufacturer ID, second compressed ASCII char (low)
      bits 4-0: manufacturer ID, third compressed ASCII char
1C82  R?  bits 7-4: first hex digit of product type
      bits 3-0: second hex digit of product type
1C83  R?  bits 7-4: third hex digit of product type
      bits 3-0: product revision number (hex digit)
--------X-P1C84------------------------------
PORT 1C84 - EISA CONFIGURATION FLAGS (board in slot 1)

1C84  RW  configuration flags (see #P225)

Bitfields for EISA Add-in Card configuration flags:
Bit(s)    Description    (Table P225)
 0    enable
 1    IOCHKERR (read-only) card is generating CHCHK#, causing an NMI
 2    IOCHKRST reset card
 7-3    card-specific
--------X-P1C85------------------------------
PORT 1C85 - EISA SETUP CONTROL (board in slot 1)
--------V-P1C85------------------------------
PORT 1C85 - Compaq Qvision EISA - Virtual Controller ID
--------X-P1C881C8F--------------------------
PORT 1C88-1C8F - EISA PROGRAMMABLE OPTION SELECT (board in slot 1)
--------V-P1EE81EEF--------------------------
PORT 1EE8-1EEF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

1EE8w -W  CRT control: vertical sync width
--------V-P1EEC------------------------------
PORT 1EEC - Mach64 - ???

1EEC  RW  display power and other controls
    bits 3-2: DPMS power mode
        00 normal
        01 standby
        10 suspend
        11 off
--------X-P200020FF--------------------------
PORT 2000-20FF - available for EISA slot 2
----------P2065------------------------------
PORT 2065 - Compaq Contura Aero
SeeAlso: PORT 1C65h"Compaq",PORT 2465h"Compaq"

2065  -W  ??? (84h seen)
--------V-P2100------------------------------
PORT 2100 - XGA Video Operating Mode Register
Note:    this port is for the first XGA in the system; 2110-2170 are used for
      the second through eighth XGAs
--------V-P2101------------------------------
PORT 2101 - XGA Video Aperture Control
Note:    this port is for the first XGA in the system; 2111-2171 are used for
      the second through eighth XGAs
--------V-P21022103--------------------------
PORT 2102-2103 - XGA ???
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2104------------------------------
PORT 2104 - XGA Video Interrupt Enable
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2105------------------------------
PORT 2105 - XGA Video Interrupt Status
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2106------------------------------
PORT 2106 - XGA Video Virtual Memory Control
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2107------------------------------
PORT 2107 - XGA Video Virtual Memory Interrupt Status
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2108------------------------------
PORT 2108 - XGA Video Aperture Index
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P2109------------------------------
PORT 2109 - XGA Video Memory Access Mode
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P210A------------------------------
PORT 210A - XGA Video Index for Data
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P210B------------------------------
PORT 210B - XGA Video Data (byte)
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
--------V-P210C210F--------------------------
PORT 210C-210F - XGA Video Data (word/dword)
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs

210C  RW  byte data
210Cw RW  word data
210Cd RW  dword data
--------V-P2110211F--------------------------
PORT 2110-211F - IBM XGA (eXtended Graphics Adapter  8514/A) (second installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2120212F--------------------------
PORT 2120-212F - IBM XGA (eXtended Graphics Adapter  8514/A) (third installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2130213F--------------------------
PORT 2130-213F - IBM XGA (eXtended Graphics Adapter  8514/A) (fourth installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2140214F--------------------------
PORT 2140-214F - IBM XGA (eXtended Graphics Adapter  8514/A) (fifth installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2150215F--------------------------
PORT 2150-215F - IBM XGA (eXtended Graphics Adapter  8514/A) (sixth installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2160216F--------------------------
PORT 2160-216F - IBM XGA (eXtended Graphics Adapter 8514/A) (seventh installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P2170217F--------------------------
PORT 2170-217F - IBM XGA (eXtended Graphics Adapter 8514/A) (eighth installed)
Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
--------V-P217A217B--------------------------
PORT 217A-217B - ET4000/W32 CRTC-B/Sprite
Note:    Alternative addresses may depend on adapter manufacturer,
      Tseng claims 21xA with x=three address bits, selected by IOD2..0
      during power up reset.

21xA  RW  ET4000/W32(i) CRTC-B/Sprite index register
    bit7-0: index
21xB  RW  ET4000/W32(i) CRTC-B/Sprite data register (see #P226)

(Table P226)
Values for ET4000/W32(i) CRTC-B/Sprite data register index:
 E0h    CRTC-B / Sprite Horizontal Pixel Position, Low
       bit7-0: horizontal pixel position bit7-0
 E1h    CRTC-B / Sprite Horizontal Pixel Position, High
       bit7-4: reserved
       bit3-0: horizontal pixel position bit11-8
 E2h    CRTC-B Width Low / Sprite Horizontal Preset
       bit7-0: width of CRTC-B bit7-0
       bit5-0: horizontal preset for sprite
 E3h    CRTC-B Width High / Sprite Horizontal Preset
       bit7-4: reserved
       bit3-0: width of CRTC-B bit11-8
 E4h    CRTC-B / Sprite Vertical Pixel Position, Low
       bit7-0: vertical pixel position bit7-0
 E5h    CRTC-B / Sprite Vertical Pixel Position, High
       bit7-4: reserved
       bit3-0: vertical pixel position bit11-8
 E6h    CRTC-B Height Low / Sprite Vertical Preset
       bit7-0: height of CRTC-B bit7-0
       bit5-0: vertical preset for sprite
 E7h    CRTC-B Height High / Sprite Vertical Preset
       bit7-4: reserved
       bit3-0: height of CRTC-B bit11-8
 E8h    CRTC-B / Sprite Starting Address Low
       pointer to CRTC-B / sprite image in display memory.
       (maximum size of sprites 64x64x4=1KB with 4 colors:
        00b=color-0, 01b=color-255, 10b=transparent, 11b=reserved)
       bit7-0: startaddress bit7-0
 E9h    CRTC-B / Sprite Starting Address Middle
       bit7-0: startaddress bit15-8
 EAh    CRTC-B / Sprite Starting Address High
       bit7-4: reserved
       bit3-0: startaddress bit19-16
 EBh    CRTC-B / Sprite Row Offset Low
       bit7-0: offset bit7-0
 ECh    CRTC-B / Sprite Row Offset High
       bit7-4: revision ID (any ET4000/W32)
            0000b=W32         0100b-1111b reserved
            0001b=W32i
            0010b=W32p
            0011b=W32i, new
       bit3-0: offset bit11-8
 EDh    CRTC-B Pixel Panning
       bit7-3: reserved
       bit2-0: CRTC-B pixel panning
 EEh    CRTC-B Color-Depth-Register / Hardware-Zoom
       bit7-4: reserved (concerning databook ET4000/W32)
       bit7-6: vertical zoom (undocumented)
           (original ET4000/W32 ok, doesn't work properly
            with some ET4000/W32i)
            00b=zoomx1       10b=zoomx3
            01b=zoomx2       11b=zoomx4
       bit5-4: horizontal zoom (undocumented)
           (original ET4000/W32 ok, doesn't work properly
            with some ET4000/W32i)
            00b=zoomx1       10b=zoomx3
            01b=zoomx2       11b=zoomx4
       bit3-0: bit/pixel
            0000b=1       0011b=8
            0001b=2       0100b=16
            0010b=4
 EFh    CRTC-B / Sprite Control
       bit7-2: reserved
       bit1     : 1=2nd CRTC-B image overlays main CRTC-A image
           0=CRTC-B image at pin SP1/0
       bit0     : 1=enable CRTC-B
           0=enable sprite (see F7h)
 F7h    Image Port Control
       bit7     : 1=CRTC-B or sprite active
           0=CRTC-B and sprite not active
       bit6-0: reserved
----------P22E822EF--------------------------
PORT 22E8-22EF - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)

22E8w -W  CRT control: display control
----------P23902393--------------------------
PORT 2390-2393 - cluster (adapter 4)
--------V-P23C023CF--------------------------
PORT 23C0-23CF - Compaq QVision - BitBLT engine
--------X-P240024FF--------------------------
PORT 2400-24FF - available for EISA slot 2
----------P2465------------------------------
PORT 2465 - Compaq Contura Aero
SeeAlso: PORT 1C65h"Compaq",PORT 2065h"Compaq"

2465  R-  current battery power level
        (166 fully-charged, 130 = LowBat1)
----------P27C6------------------------------
PORT 27C6 - Compaq LTE Lite - LCD TIMEOUT

27C6  RW  LCD timeout in minutes
--------X-P280028FF--------------------------
PORT 2800-28FF - available for EISA slot 2
--------V-P28E9------------------------------
PORT 28E9 - 8514/A - WD Escape Functions
--------V-P2C802C8F--------------------------
PORT 2C80-2C8F - VESA XGA Video in EISA slot 2
SeeAlso: PORT 1C80h-1C83h,PORT 1C88h-1C8Fh
--------X-P2C802C83--------------------------
PORT 2C80-2C83 - EISA board product ID (board in slot 2)
SeeAlso: PORT 1C80h-1C83h
--------X-P2C84------------------------------
PORT 2C84 - EISA CONFIGURATION FLAGS (board in slot 2)

2C84  RW  configuration flags (see #P225)
--------X-P300030FF--------------------------
PORT 3000-30FF - available for EISA slot 3
--------S-P32203227--------------------------
PORT 3220-3227 - serial port 3, description same as 03F8
--------S-P3228322F--------------------------
PORT 3228-322F - serial port 4, description same as 03F8
--------V-P33C033CF--------------------------
PORT 33C0-33CF - Compaq QVision - BitBLT engine
--------X-P340034FF--------------------------
PORT 3400-34FF - available for EISA slot 3
--------d-P35103513--------------------------
PORT 3510-3513 - ESDI primary harddisk controller
Range:    PORT 3510h-3513h (primary) or PORT 3518h-351Bh (secondary)
SeeAlso: PORT 3518h,PORT 01F0h-01F7h

3510w R-  status word
3510w -W  command word
3512  R-  basic status
3512  -W  basic control
3513  R-  interrupt status
3513  -W  attention
--------d-P3518351B--------------------------
PORT 3518-351B - ESDI secondary harddisk controller
Range:    PORT 3510h-3513h (primary) or PORT 3518h-351Bh (secondary)
SeeAlso: PORT 3510h,PORT 01F0h-01F7h

3518w R-  status word
3518w -W  command word
351A  R-  basis status
351A  -W  basic control
351B  R-  interrupt status
351B  -W  attention
--------d-P3540354F--------------------------
PORT 3540-354F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3550355F--------------------------
PORT 3550-355F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3560356F--------------------------
PORT 3560-356F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3570357F--------------------------
PORT 3570-357F - IBM SCSI (Small Computer System Interface) adapter
--------V-P36EE------------------------------
PORT 36EE - ATI Mach8/Mach32 - FIFO OPTION
SeeAlso: PORT 6AEEh,PORT 6EEEh,PORT 72EEh,PORT 76EEh,PORT 7AEEh,PORT 8EEEh

36EE  -W  FIFO option
        bit 0: generate wait states if FIFO >= half full
            (0=only when FIFO full)
        bit 1: force 8-bit host data I/O
--------X-P380038FF--------------------------
PORT 3800-38FF - available for EISA slot 3
--------X-P3C003CFF--------------------------
PORT 3C00-3CFF - available for EISA slot 3
--------V-P3C803C8F--------------------------
PORT 3C80-3C8F - VESA XGA Video in EISA slot 3

3C80-3C83  RW    EISA Video ID
3C84  RW    EISA Video expansion board control
3C85  RW    EISA Setup control
3C88  RW    EISA Video Programmable Option Select 0
3C89-3C8F  RW    EISA Video Programmable Option Select 1-7

SeeAlso: PORT 1C80h-1C8Fh"XGA",PORT 2C80h-2C8Fh"XGA",PORT 7C80h-7C8Fh"XGA"
--------X-P3C803C83--------------------------
PORT 3C80-3C83 - EISA board product ID (board in slot 3)
SeeAlso: PORT 1C80h-1C83h
--------X-P3C84------------------------------
PORT 3C84 - EISA CONFIGURATION FLAGS (board in slot 3)

3C84  RW  configuration flags (see #P225)
--------X-P400040FF--------------------------
PORT 4000-40FF - available for EISA slot 4
----------P42204227--------------------------
PORT 4220-4227 - serial port, description same as 03F8
----------P4228422F--------------------------
PORT 4228-422F - serial port, description same as 03F8
----------P42E042EF--------------------------
PORT 42E0-42EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

42E1  RW  GPIB (adapter 2)
--------V-P42E8------------------------------
PORT 42E8 - 8514/A and hardware-compatible video cards
Note:    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

42E8w R-  Misc. control: Subsystem Status
42E8w -W  Misc. control: Subsystem Control (see #P227)

Bitfields for 8514/A Subsystem Control Register:
Bit(s)    Description    (Table P227)
 15-14    GP_RESET
      W    00 no change
    01 normal operation
    02 reset graphics processor and FIFO
 11   W    enable interrupt when processor idle
 10   W    enable interrupt on invalid I/O
 9    W    enable interrupt if inside scissors region
 8    W    enable vertical blanking interval interrupt
 6-4 R    monitor ID
 3    acknowledge idle interrupt (and clear)
 2    acknowledge invalid I/O interrupt (and clear)
 1    acknowledge inside-scissors interrupt (and clear)
 0    acknowledge vertical blanking interrupt (and clear)
--------V-P42EC------------------------------
PORT 42EC - ATI Mach64 - ???
SeeAlso: PORT 42EDh"Mach64"

42EC  RW  ???
    bits 1-0: ???
--------V-P42ED------------------------------
PORT 42ED - ATI Mach64 - ???
SeeAlso: PORT 42ECh"Mach64",PORT 42EFh

42ED  R?  ???
--------V-P42EE------------------------------
PORT 42EE-42EF - ATI Mach32 - MEMORY BOUNDARY REGISTER
SeeAlso: PORT 5EEEh"Mach32"

42EEw RW  memory boundary
    bits 3-0: VGA/8514 boundary in 256K units (VGA only below, 8514 above)
    bit 4: partition enable: VGA and 8514 drawing engines may only write
          within their respective partitions
    bits 15-5: reserved
--------V-P42EF------------------------------
PORT 42EF - ATI Mach64 - ???
SeeAlso: PORT 42EDh"Mach64"

42EF  R?  ???
--------X-P440044FF--------------------------
PORT 4400-44FF - available for EISA slot 4
--------V-P46E8------------------------------
PORT 46E8 - VGA video adapter enable
Note:    IBM uses this port for adapter-card VGAs only, and PORT 03C3h for
      motherboard VGA only (see 03C3 for details)
SeeAlso: PORT 03C3h,PORT 46E8h"8514/A"

46E8  rW  Misc. control: enable flags / select ROM page (8514/A) (see #P228)

Bitfields for VGA miscellaneous control register:
Bit(s)    Description    (Table P228)
 7-5    unused or vendor-specific
 4    setup for POS registers (MCA)
 3    enable video I/O ports and video buffer
 2-0    unused or vendor-specific
--------V-P46E8------------------------------
PORT 46E8 - 8514/A and compatible video cards (e.g. ATI Graphics Ultra)
Note:    this register is readable on the C&T 82c480 chipset
SeeAlso: PORT 46E8h"VGA"

46E8w -W  ROM page select (see #P229)

Bitfields for 8514/A ROM page select register:
Bit(s)    Description    (Table P229)
 2-0    select which 4K page of 32K ROM to map at segment C700h
 3    enable VGA
 4    select VGA setup mode
 15-5    reserved (0)
--------V-P46EE------------------------------
PORT 46EE - ATI Mach32 - ???

46EEw RW  ???
--------V-P46EF------------------------------
PORT 46EF - ATI Mach64 - ???
Note:    the Mach64 BIOS reads the value of this port and multiplies it by 100
SeeAlso: PORT 66ECh"Mach64"
--------X-P480048FF--------------------------
PORT 4800-48FF - available for EISA slot 4
--------V-P4AE84AEF--------------------------
PORT 4AE8-4AEF - 8514/A and compatible video cards - CRT CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

4AE8w -W  CRT control: Advanced function control (see also #P230)
    (02h = VGA mode, 03h = 480-line mode, 07h = 768-line mode)

Bitfields for S3 8514/A-compatible Advanced Function Control register:
Bit(s)    Description    (Table P230)
 0    enable enhanced functions
 1    reserved (1)
 2    (911-928) screen size (1 = 800x600 or 1024x768, 0=640x480)
 4    (928+) enable linear addressing
 5    (928+) enable memory-mapped I/O
 6    (928 only) enable Write Posting
--------V-P4AEE------------------------------
PORT 4AEE - ATI Mach32 - ???

4AEEw RW  ???
--------X-P4C004CFF--------------------------
PORT 4C00-4CFF - available for EISA slot 4
--------X-P4C804C83--------------------------
PORT 4C80-4C83    EISA board product ID (board in slot 4)
SeeAlso: PORT 1C80h-1C83h
--------V-P4C804C8F--------------------------
PORT 4C80-4C8F - VESA XGA Video in EISA slot 4 (see 3C80-3C8F)
SeeAlso: PORT 1C80h-1C8Fh,PORT 6C80h-6C8Fh
--------X-P4C84------------------------------
PORT 4C84 - EISA CONFIGURATION FLAGS (board in slot 4)

4C84  RW  configuration flags (see #P225)
--------X-P500050FF--------------------------
PORT 5000-50FF - available for EISA slot 5
--------S-P52205227--------------------------
PORT 5220-5227 - serial port, description same as 03F8
--------S-P5228522F--------------------------
PORT 5228-522F - serial port, description same as 03F8
--------V-P52E852E9--------------------------
PORT 52E8-52E9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 0
Note:    the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 56E8h"C&T",PORT 5AE8h"C&T",PORT 5EE8h"C&T"

52E8w RW  Extended Configuration Register 0
--------V-P52EE52EF--------------------------
PORT 52EE-52EF - ATI Mach32 - SCRATCH REGISTER 0 (USED FOR ROM LOCATION)
Note:    ATI video BIOS sets this port according to the segment address of the
      BIOS if >= C000h, as ((seg-C000h) shr 7)
SeeAlso: PORT 56EEh"Mach32"

52EEw RW  scratch register 0: Video ROM address
--------X-P540054FF--------------------------
PORT 5400-54FF - available for EISA slot 5
--------V-P56E856E9--------------------------
PORT 56E8-56E9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 1
Note:    the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 5AE8h"C&T",PORT 5EE8h"C&T"

56E8w RW  Extended Configuration Register 1
--------V-P56EE56EF--------------------------
PORT 56EE-56EF - ATI Mach32 - SCRATCH REGISTER 1
SeeAlso: PORT 52EEh"Mach32"

56EEw RW  scratchpad
--------X-P580058FF--------------------------
PORT 5800-58FF - available for EISA slot 5
--------V-P5AE85AE9--------------------------
PORT 5AE8-5AE9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 2
Note:    the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 56E8h"C&T",PORT 5EE8h"C&T"

5AE8w RW  Extended Configuration Register 2
--------V-P5AEE------------------------------
PORT 5AEE - ATI Mach32 - ???

5AEE  RW  ???
--------X-P5C005CFF--------------------------
PORT 5C00-5CFF - available for EISA slot 5
--------V-P5C805C8F--------------------------
PORT 5C80-5C8F - VESA XGA Video in EISA slot 5
SeeAlso: PORT 2C80h-2C8Fh,PORT 4C80h-4C8Fh,PORT 6C80h-6C8Fh

5C80d RW  EISA Video ID
5C84  RW  EISA Video expansion board control
5C85  RW  EISA Setup control
5C88  RW  EISA Video Programmable Option Select 0
5C89  RW  EISA Video Programmable Option Select 1
5C8A  RW  EISA Video Programmable Option Select 2
5C8B  RW  EISA Video Programmable Option Select 3
5C8C  RW  EISA Video Programmable Option Select 4
5C8D  RW  EISA Video Programmable Option Select 5
5C8E  RW  EISA Video Programmable Option Select 6
5C8F  RW  EISA Video Programmable Option Select 7
--------X-P5C805C83--------------------------
PORT 5C80-5C83    EISA board product ID (board in slot 5)
SeeAlso: PORT 1C80h-1C83h
--------X-P5C84------------------------------
PORT 5C84 - EISA CONFIGURATION FLAGS (board in slot 5)

5C84  RW  configuration flags (see #P225)
--------V-P5EE85EE9--------------------------
PORT 5EE8-5EE9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 3
Note:    the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 56E8h"C&T",PORT 5AE8h"C&T"

5EE8w RW  Extended Configuration Register 3
---------------------------------------------
PORT 5EEE - ATI Mach32 - MEMORY APERTURE CONFIGURATION REGISTER
SeeAlso: PORT 42EEh"Mach32"

5EEEw RW  Memory Aperture Configuration (see #P240)

Bitfields for ATI Mach32 Memory Aperture Configuration Register:
Bit(s)    Description    (Table P240)
 1-0    direct memory interface mapping
    00 disabled
    01 1M aperture (not on PCI)
    10 4M aperture
    11 reserved
 3-2    1M page select (not on PCI)
    00 page 0
    01 page 1
    10 page 2
    11 page 3
 11-8    (ISA) memory aperture location, 0-15 MB
 13-8    (EISA) memory aperture location, 0-63 MB
 14-8    (VLB) memory aperture location, 0-127 MB [*]
 15-4    (PCI) memory aperture location, 0-4095 MB
 13-8    (MCA 16-bit) memory aperture location, 0-63 MB
 14-8    (MCA 32-bit) memory aperture location, 0-127 MB
Note:    [*] if PORT 16EEh bit 3 is set and PORT FAEEh is non-zero, bits 15-4
      are used to specify an address from 0-4095 MB
--------X-P600060FF--------------------------
PORT 6000-60FF - available for EISA slot 6
----------P62E062EF--------------------------
PORT 62E0-62EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

62E1  RW  GPIB (adapter 3)
--------V-P63C063CF--------------------------
PORT 63C0-63CF - Compaq QVision - BitBLT engine
--------X-P640064FF--------------------------
PORT 6400-64FF - available for EISA slot 6
--------V-P66EC------------------------------
PORT 66EC - ATI Mach64 - ???
SeeAlso: PORT 6AECh"Mach64"
--------X-P680068FF--------------------------
PORT 6800-68FF - available for EISA slot 6
--------V-P6AEC------------------------------
PORT 6AEC-6AED - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64"
--------V-P6AEE------------------------------
PORT 6AEE - ATI Mach8/Mach32 - MAXIMUM WAIT STATES
SeeAlso: PORT 36EEh,PORT 6EEEh,PORT 76EEh,PORT 7AEEh,PORT 8EEEh

6AEE  RW  maximum wait states (see #P231)

Bitfields for ATI Mach8/Mach32 wait state configuration:
Bit(s)    Description    (Table P231)
 10    leave alone ("PASSTHROUGH_OVERRIDE")
 9    enable for 16-bit I/O
 8    0=horizontal degree-mode line draws
--------X-P6C006CFF--------------------------
PORT 6C00-6CFF - available for EISA slot 6
--------X-P6C806C83--------------------------
PORT 6C80-6C83 - EISA board product ID (board in slot 6)
SeeAlso: PORT 1C80h-1C83h
--------V-P6C806C8F--------------------------
PORT 6C80-6C8F - VESA XGA Video in EISA slot 1
SeeAlso: PORT 1C80h-1C8Fh"XGA",PORT 2C80h-2C8Fh"XGA",PORT 5C80h-5C8Fh"XGA"

6C80d RW  EISA Video ID (see PORT 1C80h-1C83h)
6C84  RW  EISA Video expansion board control
6C85  RW  EISA Setup control
6C88  RW  EISA Video Programmable Option Select 0
6C89  RW  EISA Video Programmable Option Select 1
6C8A  RW  EISA Video Programmable Option Select 2
6C8B  RW  EISA Video Programmable Option Select 3
6C8C  RW  EISA Video Programmable Option Select 4
6C8D  RW  EISA Video Programmable Option Select 5
6C8E  RW  EISA Video Programmable Option Select 6
6C8F  RW  EISA Video Programmable Option Select 7
--------X-P6C84------------------------------
PORT 6C84 - EISA CONFIGURATION FLAGS (board in slot 6)

6C84  RW  configuration flags (see #P225)
--------V-P6EEC------------------------------
PORT 6EEC - ATI Mach64 - ???
SeeAlso: PORT 6AECh"Mach64"
--------V-P6EEE------------------------------
PORT 6EEE - ATI Mach8/Mach32 - ENGINE VIDEO BUFFER OFFSET LOW
SeeAlso: PORT 72EEh

6AEEw -W  low 16 bits of video buffer starting offset
--------X-P700070FF--------------------------
PORT 7000-70FF - available for EISA slot 7
--------V-P72EC------------------------------
PORT 72EC - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64",PORT 72EFh"Mach64"
--------V-P72EE------------------------------
PORT 72EE - ATI Mach8/Mach32 - ENGINE VIDEO BUFFER OFFSET HIGH
SeeAlso: PORT 6EEEh

72EE  -W  high bits of video buffer starting offset
        bits 1-0 for Mach-8
        bits 3-0 for Mach-32
--------V-P72EE------------------------------
PORT 72EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (LEFT)
SeeAlso: PORT 76EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"

72EEw R-  left edge of bounding box for points written via Line Draw register
--------V-P72EF------------------------------
PORT 72EF - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64",PORT 72ECh"Mach64"
--------X-P740074FF--------------------------
PORT 7400-74FF - available for EISA slot 7
--------V-P76EE------------------------------
PORT 76EE - ATI Mach8/Mach32 - ENGINE DISPLAY PITCH
SeeAlso: PORT 6AEEh,PORT 7AEEh

76EE  -W  display pitch
--------V-P76EE------------------------------
PORT 76EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (TOP)
SeeAlso: PORT 72EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"

76EEw R-  top edge of bounding box for points written via Line Draw register
--------X-P780078FF--------------------------
PORT 7800-78FF - available for EISA slot 7
--------V-P7AEE------------------------------
PORT 7AEE - ATI Mach8/Mach32 - EXTENDED GRAPHICS ENGINE CONGIFURATION
SeeAlso: PORT 8EEEh

7AEEw -W  extended graphics engine configuration (see #P232)

Bitfields for Mach8/Mach32 extended graphics engine configuration:
Bit(s)    Description    (Table P232)
 15    drawing pixel size to be written next (68800-6 only)
 14    enable 8-bit DAC (Mach-32 only)
 13-12    DAC address inputs RS(3:2) control (Mach-32 only)
 11    display pixel size to be written next (68800-6 only)
 10    24-bit color order (Mach-32 only)
    0 = RGB
    1 = BGR
 9    24-bit color configuration: pixels use 4 bytes instead of three
 8    DAC processes four pixels in parallel (Mach-32 only)
 7-6    16-bits-per-color word format (Mach-32 only)
    00 RGB(5,5,5)
    01 RGB(5,6,5)
    10 RGB(6,5,5)
    11 RGB(6,6,4)
 5-4    number of bits per pixel (Mach-32 only)
    00 four
    01 eight
    10 sixteen
    11 twenty-four
 3    report monitor alias instead of actual monitor
 2-0    alternate monitor ID (alias)
--------V-P7AEE------------------------------
PORT 7AEE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (RIGHT)
SeeAlso: PORT 72EEh"BOUNDS",PORT 76EEh"BOUNDS",PORT 7EEEh"BOUNDS"

7AEEw R-  right edge of bounding box for points written via Line Draw register
--------X-P7C007CFF--------------------------
PORT 7C00-7CFF - available for EISA slot 7
--------X-P7C807C83--------------------------
PORT 7C80-7C83 - EISA board product ID (board in slot 7)
SeeAlso: PORT 1C80h-1C83h
--------V-P7C807C8F--------------------------
PORT 7C80-7C8F - VESA XGA Video in EISA slot 7
SeeAlso: PORT 1C80h-1C8Fh,PORT 6C80h-6C8Fh

7C80-7C83  RW    EISA Video ID
7C84  RW    EISA Video expansion board control
7C85  RW    EISA Setup control
7C88  RW    EISA Video Programmable Option Select 0
7C89-7C8F  RW    EISA Video Programmable Option Select 1-7
--------X-P7C84------------------------------
PORT 7C84 - EISA CONFIGURATION FLAGS (board in slot 7)

7C84  RW  configuration flags (see #P225)
--------V-P7EEE------------------------------
PORT 7EEE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (RIGHT)
SeeAlso: PORT 72EEh"BOUNDS",PORT 76EEh"BOUNDS",PORT 7AEEh"BOUNDS"

7EEEw R-  right edge of bounding box for points written via Line Draw register
--------X-P800080FF--------------------------
PORT 8000-80FF - available for EISA slot 8
----------P82E082EF--------------------------
PORT 82E0-82EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

82E1  RW  GPIB (adapter 4)
--------V-P82E882EF--------------------------
PORT 82E8-82EF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 86E8h

82E8w -W  drawing control: current Y position
--------S-P82F882FF--------------------------
PORT 82F8-82FF - serial port, description same as 03F8
--------V-P83C083CF--------------------------
PORT 83C0-83CF - Compaq QVision - Line Draw Engine
--------V-P83C4------------------------------
PORT 83C4 - Compaq Qvision EISA - Virtual Controller Select
--------V-P83C683C9--------------------------
PORT 83C6-83C9 - Compaq Qvision EISA - DAC color registers
--------S-P83F883FF--------------------------
PORT 83F8-83FF - serial port, description same as 03F8
--------X-P840084FF--------------------------
PORT 8400-84FF - available for EISA slot 8
--------V-P86E886EF--------------------------
PORT 86E8-86EF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 82E8h,PORT 8AE8h

86E8w -W  drawing control: current X position
--------X-P880088FF--------------------------
PORT 8800-88FF - available for EISA slot 8
--------V-P8AE88AEF--------------------------
PORT 8AE8-8AEF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 82E8h,PORT 86E8h

8AE8w -W  drawing control: destination Y position / axial step constant
Note:    this port may be read on S3 chipsets
--------X-P8C008CFF--------------------------
PORT 8C00-8CFF - available for EISA slot 8
--------X-P8C808C83--------------------------
PORT 8C80-8C83 - EISA board product ID (board in slot 8)
SeeAlso: PORT 1C80h-1C83h
--------X-P8C84------------------------------
PORT 8C84 - EISA CONFIGURATION FLAGS (board in slot 8)

8C84  RW  configuration flags (see #P225)
--------V-P8EE88EEF--------------------------
PORT 8EE8-8EEF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT DAEEh"Mach32"

8EE8w -W  drawing control: destination X position / axial step constant
--------V-P8EEE------------------------------
PORT 8EEE - ATI Mach32 - READ EXTENDED GRAPHICS CONFIGURATION
SeeAlso: PORT 72EEh

8EEE  R-  read extended graphics configuration (see #P232)
--------X-P900090FF--------------------------
PORT 9000-90FF - available for EISA slot 9
--------V-P92E892EF--------------------------
PORT 92E8-92EF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

92E8w -W  drawing control: Bresenham error term
--------X-P940094FF--------------------------
PORT 9400-94FF - available for EISA slot 9
--------V-P96E896EF--------------------------
PORT 96E8-96EF - 8514/A and hardware-compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

96E8w R-  enter WD Enhanced Mode
96E8w -W  drawing control: major axis pixel count
--------X-P980098FF--------------------------
PORT 9800-98FF - available for EISA slot 9
--------V-P9AE89AE9--------------------------
PORT 9AE8-9AE9 - 8514/A Graphics Processor Status
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

9AE8w R-  drawing control: graphic processor status (see #P233)
9AE8w -W  drawing control: command register (see #P234)

Bitfields for 8514/A graphic processor status:
Bit(s)    Description    (Table P233)
 15-10    reserved
 9    hardware busy
 8    data ready
 7-0    status of queue (0=empty, 1=filled)
    (each bit represents a position in queue)
SeeAlso: #P234

Bitfields for 8514/A command register :
Bit(s)    Description    (Table P234)
 15-13    command
    000 = no operation
    001 = draw vector
    010 = fast rectangle fill
    011 = rectangle fill vertical #1
    100 = rectangle fill vertical #2 (4 pixels)
    101 = draw vector, 1 pixel/scanline
    110 = copy rectangle
    111 = reserved
 12    byte sequence (0=high byte first, 1=low byte first)
 11-10    reserved
 9    enable 16-bit write access (16BIT)
 8    0=use 8514/A data, 1=pixel data trans reg (PCDATA)
 7    0=draw vector above, 1=draw vector below (INC_Y)
 6    0=x is maj. axis, 1=y is maj. axis (YMAJAXIS)
 5    0=draw vector left, 1=draw vector right (INC_X)
 4    0=move only, 1=draw and move (DRAW)
 3    0=Bresenham line, 1=direct vector (LINETYPE)
 2    0=draw last pixel, 1=don't draw last pixel (LASTPIX)
 1    0=single pixel, 1=4pixel (PLANAR)
 0    0=read data, 1=write data (RD/WR)
SeeAlso: #P233
--------V-P9AEE------------------------------
PORT 9AEE - ATI Mach8/Mach32 - LINEDRAW INDEX REGISTER
SeeAlso: PORT FEEEh

9AEE  -W  linedraw index register (specifies interpretation of PORT FEEEh)
      (see #P235)

(Table P235)
Values for ATI Mach8/Mach32 Linedraw Index Register:
 00h    set current X
 01h    set current Y
 02h    set Line End X
 03h    set Line End Y, draw line, and reset register to 02h
 04h    set current X (perform moves instead of draws)
 05h    set current Y and reset register to 04h
--------X-P9C009CFF--------------------------
PORT 9C00-9CFF - available for EISA slot 9
--------X-P9C809C83--------------------------
PORT 9C80-9C83 - EISA board product ID (board in slot 9)
SeeAlso: PORT 1C80h-1C83h
--------X-P9C84------------------------------
PORT 9C84 - EISA CONFIGURATION FLAGS (board in slot 9)

9C84  RW  configuration flags (see #P225)
--------V-P9EE8------------------------------
PORT 9EE8 - 8514/A and compatible video cards - SHORT STROKE
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

9EE8w -W  short line vector transfer
--------S-PA220------------------------------
PORT A220 - soundblaster support in AMI Hi-Flex BIOS  ????
----------PA2E0A2EF--------------------------
PORT A2E0-A2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

A2E1  RW  GPIB (adapter 5)
--------V-PA2E8A2EF--------------------------
PORT A2E8-A2EF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT A6E8h

A2E8w -W  drawing control: background color
--------V-PA2EEA2EF--------------------------
PORT A2EE-A2EF - ATI Mach8/Mach32 - LINE DRAW OPTIONS
SeeAlso: PORT 8EEEh,PORT CEEEh

A2EEw RW  line drawing options (see #P236)

Bitfields for ATI Mach8/Mach32 line drawing options:
Bit(s)    Description    (Table P236)
 10-9    clipping mode
    00 disable clip exception
    01 stroked plain lines
    10 polygon boundary lines
    11 patterned lines
 8    reset all Bounds Accumulator registers
 7-5    OCTANT: direction for BitBlts or lines
 3    direction specification
    0 = Bresenham/Octant
        bit 7: increment Y
        bit 6: Y is major axis instead of X
        bit 5: increment X
    1 = line-length and degrees
        OCTANT field species N*45 degrees
 2    do NOT draw last pixel of a line
 1    polyline draw
--------V-PA6E8A6EF--------------------------
PORT A6E8-A6EF - 8514/A and compatible video cards - DRAWING CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT A2E8h

A6E8w -W  drawing control: foreground color
--------V-PAAE8AAEF--------------------------
PORT AAE8-AAEF - 8514/A and compatible video cards - WRITE MASK
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT AEE8h

AAE8w -W  drawing control: write mask
--------V-PAEE8AEEF--------------------------
PORT AEE8-AEEF - 8514/A and compatible video cards - READ MASK
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT AAE8h

AEE8w -W  drawing control: read mask
--------V-PAFFF------------------------------
PORT AFFF - VIDEO REGISTER

AFFF  RW  plane 0-3 system latch (video register)
--------S-PB220B227--------------------------
PORT B220-B227 - serial port, description same as 03F8
--------S-PB228B22F--------------------------
PORT B228-B22F - serial port, description same as 03F8
--------V-PB2E8B2EF--------------------------
PORT B2E8-B2EF - 8514/A and compatible video cards - COLOR COMPARE
Notes:    supported by ATI Graphics Ultra
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

B2E8w -W  drawing control: color compare
--------V-PB2EE------------------------------
PORT B2EE - ATI Mach32 - ???

B2EEw RW  ???
--------V-PB6E8B6EF--------------------------
PORT B6E8-B6EF - 8514/A and compatible video cards - BACKGROUND MIX
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT BAE8h

B6E8w -W  drawing control: background mix
--------V-PB6EE------------------------------
PORT B6EE - ATI Mach32 - ???

B6EEw RW  ???
--------V-PBAE8BAEF--------------------------
PORT BAE8-BAEF - 8514/A and compatible video cards - FOREGROUND MIX
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT B6E8h

BAE8w -W  drawing control: foreground mix
--------V-PBAEE------------------------------
PORT BAEE - ATI Mach32 - ???

BAEEw RW  ???
--------V-PBEE8BEEF--------------------------
PORT BEE8-BEEF - 8514/A and compatible video cards - MULTIFUNCTION CONTROL
Notes:    supported by ATI Mach8 and Mach32 chipsets
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

BEE8w -W  drawing control: multi-function control
      (index in bits 15-12, data in bits 11-0) (see #P237)
BEE8w R-  (S3) value of register specified by current value of multi-function
      index 0Fh

(Table P237)
Values for index into 8514/A multi-function drawing control registers:
 00h RW minor axis pixel count
 01h RW top scissors
 02h RW left scissors
 03h RW bottom scissors
 04h RW right scissors
 05h -W memory control register
 08h -W fixed pattern low
 09h -W fixed pattern high
 0Ah RW data manipulation control
---S3 chipsets---
 0Dh RW (S3 864/964) miscellaneous 2
 0Eh RW (S3 801+) miscellaneous
 0Fh -W (S3 801/805/928) read register select (see #P238)

(Table P238)
Values for S3 multifunction read select register:
 00h    PORT BEE8h register 00h
 01h    PORT BEE8h register 01h
 02h    PORT BEE8h register 02h
 03h    PORT BEE8h register 03h
 04h    PORT BEE8h register 04h
 05h    PORT BEE8h register 0Ah
 06h    PORT BEE8h register 0Eh
 07h    PORT 9AE8h (bits 11-0 only)
---S3 864/964 only---
 08h    PORT 42E8h (bits 11-0 only)
 09h    PORT 46E8h
 0Ah    PORT BEE8h register 0Dh
SeeAlso: #P237
----------PC000C004--------------------------
PORT C000-C004 - Intel Pentium mboard ("Neptune" chipset)
SeeAlso: PORT C050h,PORT C200h-C204h,INT 15/AX=DA8Ch,#0628 at INT 1A/AX=B10Ah
--------X-PC000CFFF--------------------------
PORT C000-CFFF - PCI Configuration Mechanism 2 - CONFIGURATION SPACE
Note:    to access the configuration space, write the target bus number to
      PORT 0CFAh, then write to the Configuration Space Enable register
      (PORT 03F8h), and finally read or write the appropriate I/O
      port(s) in the range C000h to CFFFh (where Cxrrh accesses location
      'rr' in physical device 'x's configuration data)
SeeAlso: PORT 0CF8h"Mechanism 2",PORT 0CFAh"Mechanism 2"
SeeAlso: #0628 at INT 1A/AX=B10Ah
--------X-PC008------------------------------
PORT C008 - Intel Pentium mboard ("Neptune" chipset) - CHIPSET REVISION
Desc:    the host/PCI bridge revision ID register is visible on this port when
      the PCI configuration space has been opened via ports 0CF8h and 0CFAh
SeeAlso: PORT 0CF8h,PORT 0CFAh,PORT C000h-C004h,PORT C050h,PORT C065h
--------X-PC050------------------------------
PORT C050 - Intel Pentium mboard ("Neptune" chipset)
SeeAlso: PORT C052h

C050  RW  ???
      bit 0: ???
      bit 1: ???
      bit 2: enable secondary (L2) cache
--------X-PC051------------------------------
PORT C051 - Intel Pentium mboard ("Neptune" chipset) - DETURBO SPEED CONTROL
SeeAlso: PORT 0CF9h

C051  RW  slowdown factor when in de-turbo mode
--------X-PC052------------------------------
PORT C052 - Intel Pentium mboard ("Neptune" chipset)
SeeAlso: PORT 0CF8h,PORT 0CFAh,PORT C050h,PORT C059h,PORT C065h

C052  RW  bit 0: ???
      bit 1: ???
      bits 6,7: ???
--------X-PC054------------------------------
PORT C054 - Intel Pentium mboard ("Neptune" chipset)
SeeAlso: PORT 0CF8h,PORT 0CFAh

C054  RW  bit 2: ??? (set immediately upon booting)
--------X-PC059------------------------------
PORT C059 - Intel Pentium mboard ("Neptune" chipset)
--------X-PC065------------------------------
PORT C065 - Intel "Neptune" chipset - MEMORY SIZE???
SeeAlso: INT 15/AX=DA88h

C065  R      system memory in MB??? (10h on a 16MB machine)
--------d-PC100C1FF--------------------------
PORT C100-C1FF - Intel Pentium mboard - PCTech RZ1000 EIDE controller
Desc:    the PCI configuration registers for the EIDE controller are visible
      on these ports when the PCI configuration space has been opened via
      ports 0CF8h and 0CFAh
SeeAlso: PORT 03F0h"RZ1000",PORT 0CF8h,#0628 at INT 1A/AX=B10Ah
----------PC200C204--------------------------
PORT C200-C204 - Intel Pentium mboard ("Neptune" chipset)
Desc:    the PCI configuration registers for the motherboard chipset are visible
      on these ports when the PCI configuration space has been opened via
      ports 0CF8h and 0CFAh
SeeAlso: #0628 at INT 1A/AX=B10Ah
--------S-PC220C227--------------------------
PORT C220-C227 - serial port, description same as 03F8
--------S-PC228C22F--------------------------
PORT C228-C22F - serial port, description same as 03F8
----------PC244------------------------------
PORT C244 - Intel Pentium mboard ("Neptune" chipset)
----------PC2E0C2EF--------------------------
PORT C2E0-C2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

C2E1  RW  GPIB (adapter 6)
--------V-PC2EE------------------------------
PORT C2EE - ATI Mach32 - ???

C2EEw RW  ???
--------V-PC6EE------------------------------
PORT C6EE - ATI Mach32 - SHORT-STROKE VECTOR

C6EEw -W  short-stroke vector
--------V-PCAEE------------------------------
PORT CAEE - ATI Mach32 - ???

CAEEw RW  ???
----------PCEEE------------------------------
PORT CEEE - ATI Mach8/Mach32 - DATAPATH CONFIGURATION
SeeAlso: PORT 8EEEh

CEEEw -W  datapath configuration (see #P239)

Bitfields for ATI Mach8/Mach32 datapath configuration:
Bit(s)    Description    (Table P239)
 15-13    foreground color source
    000 background color reg
    001 foreground color reg
    010 pixel transfer reg
    011 VRAM BitBlt source
    101 color pattern shift register
 12    least-significant byte first
 9    data width is 16 bits instead of 8 bits
 8-7    background color source
    00 background color reg
    01 foreground color reg
    10 pixel transfer reg
    11 VRAM BitBlt source
 6-5    monochrome data source
    00 always one
    01 mono pattern register
    10 pixel transfer register
    11 VRAM BitBlt source
 4    enable drawing
 2    read color data instead of monochrome data
 1    enable polygon fill BitBlt
 0    write data to drawing trajectory instead of reading from trajectory
--------S-PD220D227--------------------------
PORT D220-D227 - serial port, description same as 03F8
SeeAlso: PORT 03F8h,PORT D228h
--------S-PD228D22F--------------------------
PORT D228-D22F - serial port, description same as 03F8
SeeAlso: PORT 03F8h,PORT D220h
--------V-PD2EE------------------------------
PORT D2EE - ATI Mach32 - ???

D2EEw RW  ???
--------V-PDAEEDAEF--------------------------
PORT DAEE-DAEF - ATI Mach8/Mach32 - SCISSORS REGION (LEFT)
SeeAlso: PORT 8EE8h,PORT DEEEh"SCISSORS",PORT E2EEh"SCISSORS"
SeeAlso: PORT E6EEh"SCISSORS"

DAEEw -W  left edge of "scissors" drawing area (bits 11-0)
--------V-PDEEEDEEF--------------------------
PORT DEEE-DEEF - ATI Mach8/Mach32 - SCISSORS REGION (TOP)
SeeAlso: PORT DAEEh"SCISSORS",PORT E2EEh"SCISSORS",PORT E6EEh"SCISSORS"

DEEEw -W  top edge of "scissors" drawing area (bits 11-0)
----------PE2E0E2EF--------------------------
PORT E2E0-E2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

E2E1  RW  GPIB (adapter 7)
--------V-PE2E8E2EF--------------------------
PORT E2E8-E2EF - 8514/A and compatible video cards - PIXEL DATA TRANSFER
Notes:    supported by ATI Graphics Ultra
    supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

E2E8w -W  drawing control: pixel data transfer
E2EAw rW  drawing control: pixel data transfer (S3 801+) for 32-bit transfers
--------V-PE2EEE2EF--------------------------
PORT E2EE-E2EF - ATI Mach8/Mach32 - SCISSORS REGION (BOTTOM)
SeeAlso: PORT DAEEh"SCISSORS",PORT DEEEh"SCISSORS",PORT E6EEh"SCISSORS"

E2EEw -W  bottom edge of "scissors" drawing area (bits 11-0)
--------V-PE6EEE6EF--------------------------
PORT E6EE-E6EF - ATI Mach8/Mach32 - SCISSORS REGION (RIGHT)
SeeAlso: PORT DAEEh"SCISSORS",PORT DEEEh"SCISSORS",PORT E2EEh"SCISSORS"

E6EEw -W  right edge of "scissors" drawing area (bits 11-0)
--------V-PFAEE------------------------------
PORT FAEE - ATI Mach32 - CHIP IDENTIFICATION REGISTER
SeeAlso: PORT 56EEh"Mach32",PORT 5EEEh"Mach32"
--------V-PFEEEFEEF--------------------------
PORT FEEE-FEEF - ATI Mach8/Mach32 - DIRECT LINE DRAW REGISTER
SeeAlso: PORT 9AEEh

FEEEw -W  direct line-draw register
--------d-Pxxxx------------------------------
PORT xxxx - Intel 82371 - Bus Master IDE Registers

+000  RW  command register, primary channel (see #P252)
+002  Rw  status register, primary channel (see #P253)
+004d RW  IDE descriptor table pointer, primary channel (see #P254)
+008  RW  command register, secondary channel (see #P252)
+00A  Rw  status register, secondary channel (see #P253)
+00Cd RW  IDE descriptor table pointer, secondary channel (see #P254)

Bitfields for Intel 82371 Bus Master IDE command register:
Bit(s)    Description    (Table P252)
 7-4    reserved
 3    bus master read/write control
    =0 read
    =1 write
 2-1    reserved
 0    start/stop bus master
    =1 start
    =0 stop
SeeAlso: #P253,#P254

Bitfields for Intel 82371 Bus Master IDE status register:
Bit(s)    Description    (Table P253)
 7    reserved (0)
 6    drive 1 is DMA-capable
 5    drive 0 is DMA_capable
 4-3    reserved
 2    IDE interrupt pending
    write 1 to this bit to clear it
 1    IDE DMA error
    write 1 to this bit to clear it
 0    bus master IDE active (read-only)
SeeAlso: #P252,#P254

Bitfields for Intel 82371 Bus Master IDE descriptor table pointer register:
Bit(s)    Description    (Table P254)
 31-2    descriptor table base address bits 31-2
 1-0    reserved
Note:    the descriptor table must not cross a 4K boundary
SeeAlso: #P252,#P253
---------------------------------------------
PORT xxxx - Intel 82371SB - USB Host I/O Registers
InstallCheck: see #3414 at INT 1A/AX=B10Ah
SeeAlso: #3414

+000w RW  USB command register (see #P255)
+002w Rw  USB status (see #P256)
+004w RW  USB interrupt enable (see #P257)
+006w RW  Frame Number (see #P258)
+008d RW  Frame List Base Address
       (bits 11-0 must be written as zeros)
+00C  RW  Start of Frame Modify (see #P259)
+010w RW  port 1 status/control (see #P260)
+012w RW  port 2 status/control (see #P260)

Bitfields for Intel 82371SB USB command register:
Bit(s)    Description    (Table P255)
 15-8    reserved
 7    maximum packet size (0=32 bytes, 1=64 bytes)
 6    Host Controller has been configured (set by software)
 5    software debug mode
 4    force global resume
 3    enter global suspend mode
 2    global reset
 1    host controller reset
 0    run/stop schedule (0=stop, 1=run)
SeeAlso: #P256

Bitfields for Intel 82371SB USB status register:
Bit(s)    Description    (Table P256)
 15-6    reserved
 5    host controller halted
 4    host controller process error
 3    PCI bus error
 2    resume received
 1    USB error interrupt
 0    USB interrupt
Note:    to clear a bit in this register, write a 1 to it
SeeAlso: #P255

Bitfields for Intel 82371SB USB interrupt enable register:
Bit(s)    Description    (Table P257)
 15-4    reserved
 3    enable short packet interrupts
 2    enable Interrupt On Complete
 1    enable Resume
 0    enable Timeout/CRC
SeeAlso: #P256,#P258

Bitfields for Intel 82371SB Frame Number register:
Bit(s)    Description    (Table P258)
 15-11    reserved
 10-0    Frame List Current Index/Frame Number
    incremented at end of each time frame (~1ms)
Note:    only WORD writes are allowed to this register
SeeAlso: #P255,#P257

Bitfields for Intel 82371SB Start of Frame Modify register:
Bit(s)    Description    (Table P259)
 7    reserved
 6-0    SOF timing value (default 64)
Note:    SOF cycle time equals 11936+timing value
SeeAlso: #P255

Bitfields for Intel 82371SB Port 1/2 status/control register:
Bit(s)    Description    (Table P260)
 15-13    reserved (0)
 12    suspend port
 11-10    reserved
 9    port in Reset State
 8    low-speed device is attached (read-only)
 7    reserved (1)
 6    resume detected (read-only)
 5-4    line status (read-only)
    bit 4: D+ signal line
    bit 5: D- signal line
 3    port enabled/disabled status has changed
    write 1 to this bit to clear it
 2    port is enabled
 1    connect status has changed
    write 1 to this bit to clear it
 0    current connect status (read-only)
Note:    only WORD writes are permitted to this register
SeeAlso: #P255
--------!---CREDITS--------------------------
Wim Osterholt        <[e-mail]>        Original File
Chuck Proctor        <[e-mail]>
Richard W. Watson    <[e-mail]>
Matthias Paul        <[e-mail]>

Some of the information in this list was extracted from Frank van Gilluwe's
_The_Undocumented_PC_, a must-have book for anyone programming down to the
"bare metal" of a PC.

Some of the information in this list from the shareware version of Dave
Williams' DOSREF, v3.0.

8514/A hardware ports found in FractInt v18.0 source file FR8514A.ASM

Compaq QVision info from the _COMPAQ_QVision_Graphics_System_Technical_
_Reference_Guide_, second edition (October 1993).  Compaq part number
073A/0693.  Much more to come!

AMI keyboard controller PORT 0064h commands from the American Megatrends, Inc.
_Version_KF_and_KH_Keyboard_Controller_BIOS_Reference_, available on the
AMI BBS and american.megatrends.com as KFKHMAN.ZIP.

Various chipset infos from "Het BIOS Boekje" 2nd edition, by Alle Metzlar,
ISBN 90-72260-59-7 (1995).

[ATA-3 info from "AT Attachment-3 Interface (ATA-3) Revision 1", dated
April 21, 1995.]

Some additional EISA info from _EISA_System_Architecture_ (second edition),
by MindShare, Inc. (Addison-Wesley 1995, ISBN 0-201-40995-X).

AMI BIOS diagnostics codes (port 0080h) from file CHECKPTS on AMI BBS.

Some S3 and additional ATI Mach8/Mach32 info from Richard F. Ferraro's
_Programmer's_Guide_to_the_EGA,_VGA,_and_Super_VGA_Cards_, third edition.

PCnet-ISA info from _Am79C960_PCnet-ISA(tm)_Technical_Manual_, May 1992,
available from www.amd.com as 16850B.PDF; additional details from file
16907B.PDF.

PCnet-SCSI info from _Am79C974 PCnet(tm)-SCSI_Combination_Ethernet_and_SCSI_
_Controller_for_PCI_Systems_, available from www.amd.com as 18681B.PDF.

PCnet-FAST info from _Am79C971 PCnet(tm)-FAST_Single-Chip_Full-Duplex_10/100_
_Mbps_Ethernet_Controller_for_PCI_Local_Bus_, available from www.amd.com as
20550B.PDF.
--------!---Admin----------------------------
Highest Table Number = P283
--------!---FILELIST-------------------------
Please redistribute all of the files comprising the interrupt list (listed at
the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
quartet of archives named INTER53A through INTER53D (preferably the original
authenticated PKZIP archives), and the utility and hypertext programs in a trio
of additional archives called INTER53E.ZIP to INTER53G.ZIP.

Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997 Ralf Brown
--------!---CONTACT_INFO---------------------
Internet: [e-mail] (currently forwards to [e-mail])
UUCP: {uunet,harvard}!pobox.com!ralf
FIDO: Ralf Brown 1:129/26.1
    or post a message to me in the DR_DEBUG echo (I probably won't see it
    unless you address it to me)
CIS:  >INTERNET:[e-mail]