Collection of Hack-Phreak Scene Programs/cleanhpvac.zip/cleanhpvac/FAQSYS18.ZIP/FAQS.DAT/VGA.DOC

INI File | 1995-10-08 | 667KB | 14,811 lines

[Start of file: vga.doc]


0.    Preamble: about this document
==    =============================


0.01  Title, subtitle, author, version, copyright
====  ===========================================


      TITLE:       VGA Programmers Master Reference Manual


      SUBTITLE:    Concepts and pragmatics of computational modelling,
                   visual model representation and manipulation, using
                   a Video Graphics Array controller chip.

                   {This is a somewhat expansive subtitle, suitable for }
                   {a somewhat more comprehensive work than the present.}
                   {This is justified only when additional work is done.}


      EDITION:     First edition,  Summer 1991,  Identity:  91.07.52


      AUTHOR:      Andrew Scott


      COPYRIGHT:   (c) 1991 by Andrew Scott, world rights reserved




0.02  List of contents
====  ================


0.           Preamble: about this document

     0.01    Title, subtitle, author, version, copyright
     0.02    List of contents
     0.03    Notice of copyright
     0.04    Suggested license fees
     0.05    Shareware and how it works
     0.06    Obtaining a print of this document
     0.07    Your expert input to this document
     0.08    Contacting the author
     0.09    Registration and Receipt Form
     0.s     Summary


1.           Preface: how this document will help you

     1.01    Goals of this document
     1.02    Suggested audience orientation
     1.03    How to use this document
     1.s     Summary


2.           Components of a computer system

     2.01    A computer system structure
     2.02    Hardware of a computer system
     2.03    Hardware: the input unit
     2.04    Hardware: the processing unit
     2.05    Hardware: the memory unit
     2.06    Hardware: the control unit
     2.07    Hardware: the output unit
     2.08    Hardware: the external environment
     2.09    Hardware: control by program
     2.s     Summary


3.           Modelling using a computer system

     3.01    Computer system operation
     3.02    The original computer
     3.03    Computation as modelling
     3.04    The essentials of computation
     3.05    Problem solving through model building
     3.06    Types of models
     3.07    Objects and structural models
     3.08    Attributes, values and value spaces
     3.09    Some properties of value spaces
     3.10    Simple values, collected values
     3.11    Models with memory
     3.12    The memory store operation
     3.13    The memory load operation
     3.14    Modelling constants, variables
     3.15    The problem of addresses
     3.16    Structures expressed by means of values
     3.17    The program as a model
     3.18    The simplest operations for computation
     3.s     Summary


4.           Visual modelling

     4.01    Complexity control and abstraction
     4.02    Human interaction with a computer system
     4.03    Display quality issues
     4.04    Context representation
     4.05    Building blocks of a visual modelling scheme
     4.s     Summary


5.           Display device characteristics

     5.01    Raster scan display systems
     5.02    Raster scan image refresh
     5.03    Signals for image generation
     5.04    Timing issues
     5.05    Image generation can be dangerous!
     5.06    Persistance in human vision
     5.07    Interlaced display
     5.08    Screen border display
     5.09    Cursor generation
     5.10    Multi-synch monitors
     5.s     Summary


6.           VGA controller: Computer interface

     6.01    Memory interface
     6.02    Input, output, port interface
     6.03    Complete input, output port accessible register list
     6.04    Register specifications: Sequencer
     6.05    Register specifications: CRT Controller
     6.06    Register specifications: Graphics Controller
     6.07    Register specifications: Attribute Controller
     6.08    Register specifications: DAC Support Logic
     6.09    Register specifications: General Registers
     6.10    Register specifications: Special Registers
     6.s     Summary


7.           VGA controller: Architecture

     7.01    Controller timing generator:    { Sequencer            }
     7.02    Display timing generator:       { CRT Controller       }
     7.03    Image information processor:    { Graphics Controller  }
     7.04    Image presentation processor:   { Attribute Controller }
     7.05    Colour presentation processor:  { DAC Support Logic    }
     7.s     Summary


8.           VGA controller: Text
             {Only available in second edition}

     8.01    Text image generation
     8.02    Text font representation
     8.03    Text attribute representation
     8.04    Text character set extensions
     8.05    Text mode support for graphics


9.           VGA controller: Graphics
             {Only available in second edition}

     9.01    Graphic image generation
     9.02    Graphic multi-plane memory
     9.03    Graphic packed pixel memory
     9.04    Graphic line drawing
     9.05    Graphic object drawing


10.          VGA controller: Hardware Interface

     10.01   Hardware connector layout
     10.02   Monitor auto-detection operation
     10.03   Monitor auto-configuration operation



             References.


             Glossary.


             Index.




0.03  Notice of copyright
====  ===================


This file is copyright (c) 1991 by A.J.B. Scott.  Restricted permission to copy
is given provided that the following conditions are met in full, without any
qualification:


  1.  No fee shall be charged for the material content of this file, excepting
      only that a small fee for media and copying time may be charged for.

  2.  The file shall be copied entirely, without modification or ammendment,
      the copyright notice shall be present in the original form, and these
      conditions shall appear intact.

  3.  The copying of this material shall not be for commercial gain with
      the intent or effect of depriving the copyright owner of legitimate
      income deriving from licenses granted to users for this work.

  4.  The material appearing here is assigned by the author to distribution as
      shareware.  This means that copyright remains with the author, and that
      this material may be used in entirety for a short period for review.  At
      completion of review, the user may decide that the material is useful,
      in which case a registration fee presented by the user to the author will
      secure a license to use, for the registering user.  The user may decide
      what to pay for the license to use, depending upon the value to the user
      of the material.  Guidelines are given below regarding a suitable fee.
      A suggested period for review is thirty (30) days elapsed time.  After
      this time, either the material should be licensed, or if unsuitable for
      the purpose intended by the user, it should be passed in entirety to
      another interested person or else completely destroyed.  Erasure from
      the carrier medium is for this purpose equivalent to destruction.  Any
      printed version must also be destroyed.

  5.  The user is responsible for deciding the suitability or otherwise of this
      material for purposes decided by the user.  The user makes use of this
      work at the users own risk.  The author explicitly forbids any user from
      using any material contained in this document in connection with any and
      all life critical systems.




0.04  Suggested license fees
====  ======================


A suggested scale of license fees is given below, based upon the degree
of use to which the user puts or expects to put the enclosed material:

  1.  If you find that certain portions of the material are sufficiently
      useful that you need to refer to them in order to PROGRESS SOME
      PROJECT that you are involved in, then you really are depending on
      the material, so an appropriate payment would be SIXTEEN (16) POUNDS
      U.K. STERLING.  This is the LICENSE FEE applicable when you make ONE
      PRINTED COPY of this document.

  2.  For registered users as in (1) above, FURTHER PRINTED COPIES of
      the document may be taken, and registered for use, by payment of
      FOUR (4) POUNDS U.K. STERLING PER PRINTED COPY.  There is NO
      discount available for additional printed copies.

  3.  If as a user, you find the material sufficiently interesting or
      relevant that you READ ALL THE MATERIAL, then you could consider
      that the material was either entertaining or extremely relevant to
      you and your interests.  In this case an appropriate payment would
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      NOT MADE A PRINTED COPY.

  4.  If you find that although you cannot use the material at this time,
      you would EXPECT TO USE it at some time IN the FUTURE, you are of
      the opinion that the material is potentially useful to you, so a
      registration fee of EIGHT (8) U.K. POUNDS STERLING is appropriate.
      This assumes that you have NOT MADE A PRINTED COPY.

  5.  If you simply want to maintain the RIGHT TO LEGALLY USE the material
      WHEN IT BECOMES IMPORTANT to you, then IN ORDER TO RETAIN it ON YOUR
      COMPUTER SYSTEM, a payment of FOUR (4) U.K. POUNDS STERLING is the
      suggested license fee.  This applies when you wish to KEEP material
      for BACKUP PURPOSES or for "what if" or "just in case" situations.
      This assumes that you have NOT MADE A PRINTED COPY.

  6.  For REGISTERED USERS who wish to INCREASE their LEVEL OF REGISTRATION
      at a later date, A DISCOUNT IS AVAILABLE.  To take advantage of this,
      include your registration number with your order, and deduct ONE pound
      sterling FOR EACH FOUR pounds DIFFERENCE in your existing and upgraded
      registration levels.  This does NOT APPLY TO additional PRINTED COPIES
      of this work.  See (2) above.

  7.  IF you reviewed the material but do not find it interesting, or if
      YOU CANNOT MAKE any USE OF IT, THEN you are requested to pass all the
      material to someone who may be interested, or ENTIRELY DESTROY your
      COPY of it, INCLUDING any PRINTED VERSION you may have made for review
      purposes.  THIS PROVIDES you with a LEGITIMATE way of stating that
      the material DOES NOT MEET your NEEDS.  If you need to KEEP A COPY,
      then you SHOULD consider REGISTERING as in (5) above.




0.05  Shareware and how it works
====  ==========================


It is important to emphasise that this material did not just suddenly appear
as if by magic.  It had to be created, but only after the expenditure of much
thought and effort.  As with any human endevour, people who create works or
perform work for other people do expect and do need to be rewarded for their
efforts.

The purpose of the shareware concept is to provide a vehicle whereby talented
people can produce high quality work, which may subsequently be distributed
by many different channels, but always at low cost.  The ultimate goal is that
clients who use shareware, can obtain useful relevant products at a very low
price, without any compromise on quality.

For a shareware author, the business of marketing and distribution is taken
care of, leaving the author with the time and energy to concentrate on product
development, helping to ensure production of a quality product.

So, if you find any shareware product useful, make sure that you take the time
to give your vote of confidence in the product and its author, by registering
the product enclosing the appropriate fee to the author.

If you do not do this, the author will not be in a position to produce further
products that you will find useful, and, ultimately, you will be saying that
you do not respect the product you are using, the author who produced it, and
that you would rather buy an expensive product in a shiny wrapper than support
the shareware concept.

The simple fact is, you either register your use of a product, or see the means
that brought you that product (shareware) wither and die.  The choice is yours.

On the other hand, you should definately not register a product which is no use
to you, and will never be any use to you.  Many authors like to hear why their
product does not provide what you actually need, and would like your comments.

Why not support them and provide your views?  You can only benefit long term.
Some people  have found that authors of shareware products can be very flexible
when new updates are issued.  Some users have suddenly found that their views
have helped give them exactly what they need in a new product.

So, it's over to you.  Enjoy using this material or let me know how you would
like to see it improved or reoriented.  Thank you and good luck.




0.06  Obtaining a print of this document
====  ==================================


To make best use of this document, for evaluation purposes, or, after you have
registered and paid the appropriate license fee (see above for details), for
reference use, it is beneficial to obtain a printed version of this document.

For those of you who wish to print this document, it is necessary to make note
that the ascii text comprising this document is completely devoid of control
characters, excepting only cr {carriage return} and lf {line feed}.  No other
non-printing characters are used.  This has been done on purpose, so that any
printing device which supports ascii character sets may successfully produce
a print.

The absence of ff {form feed} control characters means that there will not be
a division of this document into complete page sections.  This should not be a
problem, since the material is indexed by the contents list, and there are
differences of page lengths supported by different printing devices, which in
practise would change the page numbering.

For these reasons, the concept of page has been completely ignored throughout
this document.

The printable width of lines is constrained to be 80 characters or less.  In
this way, virtually any industry standard output device may be used to create
a readable image of this text, whether on video display unit, or print device.
Note however, that the actual size of a line may be just over 80 characters
when the carriage return, line feed pair are taken into account.  This might
affect the setup of certain types of printer drivers.

If you do make a printed version of this document, and then decide that you do
not wish to register your copy, you should either pass the printed copy with
the computer readable copy to another person who may have an interest, or you
should destroy both copies.  This removes any obligation from you to register
your use by making a payment to the author.

UNDER NO CIRCUMSTANCES SHOULD YOU PRODUCE MORE THAN ONE PRINTED COPY WITHOUT
PAYMENT OF A REGISTRATION FEE TO THE AUTHOR.  If you have registered your use
and need to register more than one printed copy, please see above for the
beneficial rates available for this situation.




0.07  Your expert input to this document
====  ==================================


If you are an expert or have recently become an expert in areas from which this
work would benefit, and you would like to provide input to the author so that
others may benefit from your knowledge, please contact the author.  Any extra
materials provided will be included at this authors sole discretion, but such
included material will always be given special acknowledgement.  Any anonymous
material will be excluded unconditionally from further consideration.

If you have found this document to be useful but feel that it could be better,
please write to the author and make constructive suggestions.  Criticism will
be welcomed but only if it is of a constructive nature.  Your input as a user
is needed to help ensure that this document meets your needs today, tomorrow,
and into the future.

If you do wish to provide updates to this material, please provide these on a
1.44M or 720K 3.5 inch floppy disk.  Use a simple ascii file format without
using any control codes except carriage return and line feed.  When marking
changes in the existing text, use the following conventions.

Any source material which is to be changed, should be surrounded with special
brackets, indicating that it is subject to change.  These brackets appear as
follows:


           !-!...original text to modify...!=!...new replacement text...!+!


It may be most useful to use this convention with complete lines of text, then
less confusion will result when many small changes are made to detail:


!-!
           original body of text
           which needs
           some changes made
!=!
           new text as
           a replacement
           for the above
!+!


Source material which is to be unconditionally deleted is dealt with as in the
following manner:


!-!
           body of text which needs
           deleting without replacement
!-!


Source material which is to be inserted as entirely new text, is introduced in
the following way:


!+!
           body of text which needs
           interting as entirely
           new material
!+!


Comments which need to be made, but which should not be included in the body of
the text, may be enclosed with appropriate brackets as follows:


!'!
           Note ' is a single quote !
           comments which describe
           the reasons for performing
           edits, deletion or insertion
           of new material
           Note " is a double quote !
!"!


Please note that the above markers cannot contain each other.  That is, it is
possible only to operate with a flat file, and nesting of markers is illegal.
Markers can however be conjoined together one set following immediately after
another set, without intervening text.

These conventions must be adopted since the author relies on automated library
processing software.

All such material will become the property and copyright of the present author.
Regretfully, no payment can be made for any material provided in this way, and
disks will not be returned.  The reasons for these conditions are simple.  The
author does not have unlimited time available to service this work, so any way
of making administration easier must be seriously considered.   Who knows, if
this material attracts sufficient registrations, more time might be available.




0.08  Contacting the author
====  =====================


The author is a practising software/hardware engineer who often travels abroad
in connection with an international consultancy business.  The contact address
to use (which is only a forewarding address) is as follows:

      _____________________
     |                     |
     |   Andrew Scott      |
     |   SHAREWARE 01      |
     |   c/o 1 Bramcote    |
     |   Aylesbury         |
     |   Buckinghamshire   |
     |   HP20 1QE          |
     |   ENGLAND           |
     |_____________________|


There is no possibility of telephone contact simply because the author spends
long periods of time abroad.  This situation is regretted but could change if
sufficient registrations warrant a different approach.

If you wish to communicate put your letter on a 720K or 1.44M  3.5 inch disc
with a filename of 'letter.doc'.  Do not forget to put your name and address
on the disc in a file called 'address.doc' then mail it to the above address.

All files should be in plain ascii, without control codes other than carriage
return and line feed.  No other file formats are acceptable.  An 'address.doc'
file should print your name and address exactly as it should be written on an
envelope to be posted to you.  Please note that discs will not be accepted if
they contain executable files of any type whatsoever.  This is to prevent any
difficulties with software licensing, and to help ensure freedom from viruses.

Please note that the author uses a standard procedure with any received discs.
This involves using a special bootable program to wipe all files from the disc
which do not have the extension '.doc'.  In particular, the disc is rendered
unbootable.  Only after this special virus proof program has been run is the
disc read using a conventional industry standard operating system, with a set
of appropriate adjustments made to the floppy disc drive control software for
further security protection.

Do please remember this if you need to send a disc.

If you need to send program code, then it must be sent in source form, and you
must be the author, or possess a license sufficient to transmit source to a
third party.  Please include details of this license in a separate file with
the name 'license.doc'.

In any case, program fragments are to be preferred, since they make a technical
point without introducing irrelevant detail.  Source should be in some genus of
80x86 assembly language.

No written communications can be accepted, since they involve so much handling
overhead.  All discs become the property of the present author on receipt.

The author regrets that failure to observe these requirements will prevent any
attempted communication from taking place.

The policy of the author is that any licensed files will be erased as soon as
it is practically possible to do so.  The author does not have any interest
whatsoever in 'data collection' of any type.  This is particularly true in the
case of material which may be the licensable property of others.

Although the author will attempt to respond where appropriate, no undertaking
can be given on this point, simply due to pressure of time.  This unfortunate
circumstance could change should the level of user support of this work prove
to be of an appropriate level.




0.09  Registration and Receipt Form
====  =============================


Registrations are made only by means of a cheque drawn on a U.K. bank in pounds
sterling as detailed above.  Please make the cheque payable to:

      ___________________
     |                   |
     |   Andrew Scott    |
     |___________________|


All registrations MUST be accompanied by the Registration and Receipt Form that
appears below.  Use your text editor to extract this form then fill it in, or
alternatively, use the separate file 'register.doc' in the same way.  Having
filled in the form, print it out and enclose it with your cheque.  As before,
the motivation for this is the saving of administration time.  Cheques provided
without the form will be accepted, but of course, no receipt can then be given.

It may be necessary to allow some time to elapse before receiving your receipt.
Do not be alarmed by this.  If you do not require a receipt, please either tick
the box to state this, or alternatively, just send your cheque unaccompanied.

Please note that it is not the authors policy to keep names and addresses of
registrees in computer readable form, since this can cause difficulties with
existing U.K. legislation in terms of overhead cost in time and money.

Please find below the form which MUST accompany your registration cheque.  It
is followed by an example which has been filled in for a ficticious client at
a U.K. address.  After that, another example follows, for a foreign client.




==============================================================================
                   Registration and Receipt Form  [Start]
==============================================================================


   When completed, please send a printed version of this form together
   with the appropriate value cheque to the address following:

                    _____________________
                   |                     |
                   |   Andrew Scott      |
                   |   SHAREWARE 01      |
                   |   c/o 1 Bramcote    |
                   |   Aylesbury         |
                   |   Buckinghamshire   |
                   |   HP20 1QE          |
                   |   ENGLAND           |
                   |_____________________|


   Client Name and Address (as for an envelope to be posted).
   You MUST use your text editor; handwriting is unreliable.
   Simply leave any unused lines free of text.  Please leave
   the numeric fields as they stand, unaltered.  Use a clear
   simple typeface when printing this form prior to mailing.


         001:
         ----------------------------------------------------
         002:
         ----------------------------------------------------
         003:
         ----------------------------------------------------
         004:
         ----------------------------------------------------
         005:
         ----------------------------------------------------
         006:
         ----------------------------------------------------
         007:
         ----------------------------------------------------
         008:
         ----------------------------------------------------
         009:
         ----------------------------------------------------
         010:
         ----------------------------------------------------
         011:
         ----------------------------------------------------
         012:
         ----------------------------------------------------


   Receipt Required?  Please delete 'Yes' if no receipt is required.


         120:      Yes
         -------------


   Please indicate here the actual license REGISTRATION FEE you are paying,
   WITHOUT including any provision for U.K. local tax {V.A.T.}.


         230:
         -------------


   If you have an ADDRESS in the U.K. (V.A.T. area) you MUST INCLUDE V.A.T.
   at the CURRENT RATE.  It is 17.5% at this time, but may of course change
   later.  Your RECEIPT will PROVIDE you with PROOF of V.A.T. SPENDING.
   OVERSEAS client ADDRESSES do NOT pay V.A.T., so for them, this is zero.
   Please indicate here the amount of V.A.T. you are paying.


         231:
         -------------


   This amount MUST match the VALUE of your CHEQUE.
   YOUR CHEQUE MUST BE DRAWN ON A U.K. BANK IN POUNDS STERLING.
   If you have a U.K. address YOU MUST INCLUDE V.A.T.
   If you have a FOREIGN address, you DO NOT pay V.A.T.
   Please indicate here the value of your registration fee together with any
   local U.K. tax {V.A.T.} you are paying.


         234:
         -------------


   Registration Number issued in receipt.  Please leave this blank
   unless you have already registered and are increasing the level
   of your existing registration.  Do not forget a discount may be
   available to you.  See {0.04} Suggested license fees.


         340:
         ---------------------------------------------------------


==============================================================================
                   Registration and Receipt Form  [End]
==============================================================================




==============================================================================
EXAMPLE UK         Registration and Receipt Form  [Start]  EXAMPLE UK
==============================================================================


   When completed, please send a printed version of this form together
   with the appropriate value cheque to the address following:

                    _____________________
                   |                     |
                   |   Andrew Scott      |
                   |   SHAREWARE 01      |
                   |   c/o 1 Bramcote    |
                   |   Aylesbury         |
                   |   Buckinghamshire   |
                   |   HP20 1QE          |
                   |   ENGLAND           |
                   |_____________________|


   Client Name and Address (as for an envelope to be posted).
   You MUST use your text editor; handwriting is unreliable.
   Simply leave any unused lines free of text.  Please leave
   the numeric fields as they stand, unaltered.  Use a clear
   simple typeface when printing this form prior to mailing.


         001:       John Smith
         ----------------------------------------------------
         002:       Basement Flat
         ----------------------------------------------------
         003:       Number 3
         ----------------------------------------------------
         004:       Holly Lane
         ----------------------------------------------------
         005:       Beringsbeare
         ----------------------------------------------------
         006:       Tullingdon
         ----------------------------------------------------
         007:       Near Great Minsforth
         ----------------------------------------------------
         008:       Shrafton
         ----------------------------------------------------
         009:       Shropshire
         ----------------------------------------------------
         010:       SH12 4PB
         ----------------------------------------------------
         011:
         ----------------------------------------------------
         012:
         ----------------------------------------------------


   Receipt Required?  Please delete 'Yes' if no receipt is required.


         120:      Yes
         -------------


   Please indicate here the actual license REGISTRATION FEE you are paying,
   WITHOUT including any provision for U.K. local tax {V.A.T.}.


         230:   16.00
         -------------


   If you have an ADDRESS in the U.K. (V.A.T. area) you MUST INCLUDE V.A.T.
   at the CURRENT RATE.  It is 17.5% at this time, but may of course change
   later.  Your RECEIPT will PROVIDE you with PROOF of V.A.T. SPENDING.
   OVERSEAS client ADDRESSES do NOT pay V.A.T., so for them, this is zero.
   Please indicate here the amount of V.A.T. you are paying.


         231:   2.80
         -------------


   This amount MUST match the VALUE of your CHEQUE.
   YOUR CHEQUE MUST BE DRAWN ON A U.K. BANK IN POUNDS STERLING.
   If you have a U.K. address YOU MUST INCLUDE V.A.T.
   If you have a FOREIGN address, you DO NOT pay V.A.T.
   Please indicate here the value of your registration fee together with any
   local U.K. tax {V.A.T.} you are paying.


         234:  18.80
         -------------


   Registration Number issued in receipt.  Please leave this blank
   unless you have already registered and are increasing the level
   of your existing registration.  Do not forget a discount may be
   available to you.  See {0.04} Suggested license fees.


         340:
         ---------------------------------------------------------


==============================================================================
EXAMPLE UK         Registration and Receipt Form  [End]  EXAMPLE UK
==============================================================================




==============================================================================
EXAMPLE FOREIGN    Registration and Receipt Form  [Start]  EXAMPLE FOREIGN
==============================================================================


   When completed, please send a printed version of this form together
   with the appropriate value cheque to the address following:

                    _____________________
                   |                     |
                   |   Andrew Scott      |
                   |   SHAREWARE 01      |
                   |   c/o 1 Bramcote    |
                   |   Aylesbury         |
                   |   Buckinghamshire   |
                   |   HP20 1QE          |
                   |   ENGLAND           |
                   |_____________________|


   Client Name and Address (as for an envelope to be posted).
   You MUST use your text editor; handwriting is unreliable.
   Simply leave any unused lines free of text.  Please leave
   the numeric fields as they stand, unaltered.  Use a clear
   simple typeface when printing this form prior to mailing.


         001:       Johan Schmidt
         ----------------------------------------------------
         002:       Heliger Strasse 13
         ----------------------------------------------------
         003:       Markt Windsheim
         ----------------------------------------------------
         004:       Langenburg
         ----------------------------------------------------
         005:       Aschaffenburg
         ----------------------------------------------------
         006:       Frankfurt a/d Main
         ----------------------------------------------------
         007:       Germany
         ----------------------------------------------------
         008:
         ----------------------------------------------------
         009:
         ----------------------------------------------------
         010:
         ----------------------------------------------------
         011:
         ----------------------------------------------------
         012:
         ----------------------------------------------------


   Receipt Required?  Please delete 'Yes' if no receipt is required.


         120:      Yes
         -------------


   Please indicate here the actual license REGISTRATION FEE you are paying,
   WITHOUT including any provision for U.K. local tax {V.A.T.}.


         230:   16.00
         -------------


   If you have an ADDRESS in the U.K. (V.A.T. area) you MUST INCLUDE V.A.T.
   at the CURRENT RATE.  It is 17.5% at this time, but may of course change
   later.  Your RECEIPT will PROVIDE you with PROOF of V.A.T. SPENDING.
   OVERSEAS client ADDRESSES do NOT pay V.A.T., so for them, this is zero.
   Please indicate here the amount of V.A.T. you are paying.


         231:   0.0
         -------------


   This amount MUST match the VALUE of your CHEQUE.
   YOUR CHEQUE MUST BE DRAWN ON A U.K. BANK IN POUNDS STERLING.
   If you have a U.K. address YOU MUST INCLUDE V.A.T.
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0.s   Summary
===   =======


This document is a copyright work, for which a license to use is required.
Details are given for registering a user license, with appropriate payment.

Technical notes on the source character set employed in this document are
made for those needing to produce a printed version of this work.

Expert input from people who have seen this document is invited with a view to
increasing the usefulness, relevance and quality for existing and prospective
registered users.

Details are given on procedure for contact with the author, and for making
payment for a user license.

A disclaimer is presented concerned with fitness for use of this work.




1.    Preface: how this document will help you
==    ========================================


1.01  Goals of this document
====  ======================


The goal of this document is the description of means for programming the VGA
controller chips found in contemporary Intel 80x86 processor powered industry
standard architecture computer systems.

To program any device effectively requires intimate knowledge of environmental
issues which determine the context within which the device finds application,
the technical issues which determine the structure of the device, and finally,
full details of the programming interface available to the host machine.

We will first consider the background against which any computer system works.
This will broaden into a brief overview of the structures which comprise any
computer system, and which are necessary to support computation.  Computation
is then considered as a modelling activity.  We will consider means for making
models, and the representation of models in people oriented terms.

These considerations will naturally broaden into a discussion of video image
generation and the employment of images as an essential part of the process
of communication between people and computer systems.

We consider the reasons why images can be appropriate for the expression of
complex modelling relations, which then leads naturally to considerations for
the technical specification of image generating capabilities.

The architectural aspects of the host machine are then discussed, in particular
the implications of memory mapped interfaces, and the means for controlling the
operation of a very highly configurable video image generator chip.  This gives
reasons for the register input output structures commonly used when programming
the VGA controller chip.

Details of the conceptual and physical structure of the video image generator
are examined, with discussion of the motivation for the various programmable
features introduced into the hardware.  The characteristics of the hardware
are given, with details of the user oriented operations which motivate them,
and the programming strategies to be adopted in their use for achievement of
maximally high image manipulation performance.

The main part of this work is centred upon the highly complex register set that
provides the VGA controller with all its many programmable option settings.  It
is the interaction of these settings which, for the most part, makes the VGA so
difficult to understand and program.  We will describe the data content of each
register, in a systematic manner.  There will be discussion concerning the real
design motivation for providing the particular feature which is being described
which will in most cases considerably clarify complex issues.  Further, related
features are brought into focus, with either a useful comment as introduction,
or with a full discussion.  In all cases, cross references are given at the top
of each register description.  These will yield considerable insight, when used
to direct attention on a particular point of interest.

By following the cross references in a random manner the informed reader will
very quickly build up a complete picture of essential VGA operation.  This is
very important prior to starting any serious programming for this very highly
flexible but very complex device.  Excellent advice to follow before creating
any program for the VGA device is to obtain from the original manufacturer of
your particular VGA absolutely all the technical documentation available.  In
this way, you will hopefully have some chance of being adequately informed as
most VGA controller chips now available support extensive additional features
which will, for the most part, be completely non-standard.




1.02  Suggested audience orientation
====  ==============================


This document is primarily concerned with a particularly technical aspect of
programming the industry standard architecture machines employing Intel 80x86
processor chips.  As such, the reader would benefit considerably from a good
knowledge of Intel 80x86 assembly language programming, including architectural
appreciation of that line of processor chips.  In particular, the memory access
and input output model of the 8086 processor chip should be understood.

If the reader is not concerned with the intimate details of VGA programming,
this document should provide all the source material neeeded to form a view of
the capabilities and attendant design issues facing a VGA programmer.  This
might be of interest to a system designer who is addressing the question of
whether to develop a product using the full capability of the VGA video system.

Knowledge of hardware structures would be useful, but should not be essential
for obtaining spectacular performance from the hardware described.  However,
some degree of conceptual awareness of hardware structures will be developed in
this document, and without this knowledge, it would be very difficult to obtain
original practical results for a special application.  This level of knowledge
is fairly simple, so should not prove onerous to even the most wisened hardware
illiterate programmer.

Programming templates will be given in a generic 8086 assembly language,
without any pseudo-operation context.  The intention is to produce practical
conceptual knowledge, which is perpetually reuseable, rather than a set of
recipes for various commonly occuring problems.  The emphasis is firmly on
high performance, which means writing code with a solid understanding of what
is happening in the hardware.  Only in this way can the full power of the VGA
controller chip be realised in practical application.

It should be fairly clear by now that we will not be concerned with means by
which the VGA can be programmed with involvement of a video bios {basic input
output system}.  We will instead consider the questions involved in writing
our own application specific bios, using only the naked resources provided by
the VGA controller chip itself.  People interested in programming using the
various bios facilities will, nevertheless, find this document interesting in
the sense that having understood this material, the operations of the bios
will become much clearer.  This means more effective programming, even at the
more constrained level of bios operations.  In addition, the potential always
exists to perform mixed bios and customised high speed programming of the VGA
controller for special applications which do not warrant the development of a
full custom programmed solution.  In all these situations, the material given
here should help the programmer to obtain the desired results without too much
fuss or heartache.

Since the price of VGA controllers with massive amounts of memory has reached
a very affordable level at the time of writing {summer of 1991}, we will not
dwell on the various video standards which preceeded VGA, but will from time
to time make parenthetic notes about particular compatibility considerations
which motivate various aspects of the hardware design.  This will represent
the full extent of our interest in such compatibility issues.  In particular,
we will often assume that we are using a VGA controller with certain specific
characteristics.  That is, we assume a Trident 8900 VGA controller chip, with
a full one megabyte of video memory.  These assumptions will not generally
upset the validity of the concepts and programming techniques discussed, but
do serve to provide a complete specification of the environment within which
this document was conceived and written.

The most important qualification for gaining benefit from this document is an
interest in understanding the subject matter, and a relatively keen intellect.
The rest is the ability to author well conceived program code, and the strength
to accept that mistakes need to be made before outstanding results are seen.

Do remember that when dealing with inherantly complex issues, the only way to
succeed is to use the appropriate approach.  As Sir Winston Churchill once said
when speaking to the Oxford University Student Union:

"Never give up".   "Never, never, give up".   "Never, never, never, give up".

This was his address in its entirety, which received rapturous applause and
doubtless helped to change the lives of many as a result.




1.03  How to use this document
====  ========================


We spend some time developing a model of computation, which embraces the
hardware and software structures necessary for practical problem solving
using computer based modeling techniques.  This material can be ommited
by those who are interested in serious descriptions of the hardware form
of the VGA controller chip, and the software interface available providing
control using the host machine.

Students of computation may find the discussion of interst, since it draws a
parallel between the general basis for computation and the generic hardware
manipulation facilities provided within the VGA controller chip.  In this
way, the VGA controller chip can be seen as a specialised processor adapted
for the specific operations required for image transformation and transport.

Specifically, some VGA controller image manipulation primitives can be seen
to have the control element of the image computation provided explicitly by
the host processor.  This partitioning of the control leads to a flexibility
which would not otherwise exist, and can be interpreted as a natural extension
of the classical architecture of a general purpose digital computer system.
To employ the Intel nomenclature, the VGA controller chip can under practical
conditions be viewed as a very specialised (so therefore complex) co-processor
device.




1.s   Summary
===   =======


This document is concerned with high performance programming for the video
graphics array controller Trident 8900, equipped with 1 megabyte of memory.

The emphasis is on programming for high performance image manipulation and
presentation, principally using assembly language without use of a video bios.

A guide to the relevant chapters is given for those with various backgrounds,
motivations and interests.




2.    Orientation - the computer system
==    =================================


2.01  A computer system structure
====  ===========================


A computer system is a collection of many different component parts.  Some of
these are fixed and invariant in structure, whilst others are only partially
fixed in structure so may in practise have a variable structure.

We usually think of these two distinct properties as belonging to the hardware
components and software components, respectively, of a computer system.  These
two types of components make up an entire computer system, which consists only
of hardware components and software components.

The hardware components of a computer system represent the finite fixed means
available to enact a computation described in precise detail by the software
components of that computer system.

The software components of a computer system determine every detail of the
computation of that system, by means of a moment by moment selection of the
actual hardware capabilities brought into play, from the entire set of possible
capabilities available.  We talk about the entire collection of software
components associated with a computer system as the program for that computer
system.  Therefore a program is a complete collection of software components,
sufficient to fully direct the hardware which makes up a computer system.




2.02  Hardware of a computer system
====  =============================


The physical reality of the computer system hardware appears as a number of
fundamental units, interconnected with each other, but each of which is needed
in any general purpose digital computer system.  {We distinguish this class of
computer system in particular, since there are other classes of computer system
with which we will not concern ourselves.}  These units are as follows:

  1.  Input unit
  2.  Processing unit
  3.  Memory unit
  4.  Control unit
  5.  Output unit

Each of these units is physically constructed from a mix of components which
could be classed as mechanical, electro-mechanical, electro-optical or
electronic.  Other technologies may be used, but it is essential to understand
that the technology implementing hardware capability is not in itself crucial;
rather, it is the information processing capabilities provided by the hardware
units themselves which is important.

In some cases, only one class of component is used in the construction of a
particular type of unit.  For example, an input unit might use mechanical,
electro-mechanical and electronic components in its realisation.  This would
contrast with a processing unit which might use only electronic components in
its construction.  The construction is not as important as the fixed set of
capabilities supported by each unit, expressed in terms of information transfer
and modification abilities of a particular unit, as noted above.




2.03  Hardware: the input unit
====  ========================


The input unit has the fixed capability to obtain information from somewhere
outside the computer system and deliver it into the computer system in a timely
manner.  This is the only purpose for which the input unit is used.

The somewhere outside is usually referred to as the external environment within
which the computer system operates.




2.04  Hardware: the processing unit
====  =============================


The processing unit has a set of fixed capabilities for processing information,
that is, for changing information in a controlled manner.  Some of the ways in
which information may be changed are given below:

  1.  Reduction of information.

      This corresponds to removal of some of the information content of
      data, thereby classifying data into a set of predetermined groups.

      When one knows the classification of a data item, it is not then
      possible to say with certainty what exact data derived that class,
      since information loss has occured.  Therefore information loss is
      associated with a one way process which cannot then be reversed to
      obtain the original data.

  2.  Transformation of information.

      This does not change the information content of data, but merely
      changes the representation of that data, to make it suitable for
      use within a particular computational environment.

      It is in principle possible to reverse the transformation of data
      such that the transformed data could give rise to the original
      data, assuming sufficient computational resources are available to
      effect the inverse transformation.  {In fact, there may be reasons
      why the inverse transformation does not exist in practise, although
      this does not of itself deny the principle.}

  3.  Comparison of information.

      This actually creates information based upon the representation of
      existing information.  This newly created information is available
      for further processing just as any other information would be.

      By changing the representation of data, the result of comparing two
      data items can change.  The data representation is what determines
      the comparison result, not the information content of the data.

These are the only ways available for processing information, so all possible
computations are built up from these types of information manipulation.




2.05  Hardware: the memory unit
====  =========================


The memory unit has the fixed capability of accepting information at one moment
in time, and delivering that information at a later moment in time without any
change having occured to that information in the intervening time.  The amount
of time which passes between the presentation of information to the memory unit
and the later recovery of that unaltered information is not important for the
operation of the memory.  In that sense it is completely time independant.




2.06  Hardware: the control unit
====  ==========================


The control unit mediates between the instructions which comprise a program and
the operation of all the hardware units which comprise the computer hardware.
The control unit manages and directs all flows of information within the entire
computer system.  No computation can proceed without the involvement of the
control unit, which initiates input information flows, directs the output of
information, determines the processing of information and the presentation to
and recovery from memory of information.




2.07  Hardware: the output unit
====  =========================


The output unit is equipped with fixed capability to accept information from
within the computer system and present that information in timely manner to
somewhere outside the computer system.  This destination is referred to as the
external environment, which is also the source of input information, as noted
above.




2.08  Hardware: the external environment
====  ==================================


This means that a computer system takes its input from, and delivers output to,
its external environment.  In this view of things, the computer system itself
is completely separate from the external environment which contains information
to process and which in turn accepts processed information.  This observation
is important, since it is essential that the computer system be able to act in
a manner completely independant of the information environment with which it is
associated.  It is only when this is true that a program can be seen to be the
sole determinant of the activities of a computer system.




2.09  Hardware: control by program
====  ============================


All these activities are controlled by the program which controls the operation
of the control unit and thence the operation of the entire computer system.  So
the hardware component of the computer system represented by the control unit
is the fixed means by which the entire computer system fixed capabilities are
organised and controlled, but the moment by moment operation of this unit is in
turn controlled through the statements which comprise the program controlling
the computer system.  This program comprises the full collection of individual
software components which together with the hardware components make up the
complete computer system, thereby determining its entire behaviour.




2.s   Summary
===   =======


The structure of a computer system is described in terms of components which
appear as hardware and software.  The nature of the hardware components and
their function is examined.  In particular, the types of information processes
available to an information processing unit are discussed.  The program as the
ultimate arbiter of computer system operational control is seen as a collection
of all the software components of a computer system.




3.    Modelling using a computer system
==    =================================


3.01  Computer system operation
====  =========================


We have seen that a computer system comprises hardware units with fixed sets
of capabilities which interact under the direction of the control unit.  This
control unit is itself controlled by the software components which when taken
together comprise a program.

So now we know what a computer system comprises.  This does not directly help
to answer the question concerning what it is a computer system does.  Once we
know what a computer system does, we will understand the motivation for being
interested in a computer system.  This question is what we will now look at.




3.02  The original computer
====  =====================

We can look back in time to the days prior to the existence of electronic
computers, when the english language held that a computer was a person who by
dint of intelligence, knowledge and insight, performed calculations of interest
using just paper and pen.

This is the sort of activity we engage in when we ask how much we have spent
on the basket of shopping we have just bought.  But we can also ask questions
about the future, such as how much would it cost to buy all the food necessary
to entertain a group of friends each of whom has a different taste from each of
the others.

If we decide that the proposed evening would be too expensive, we can then ask
what would be the most economical way of entertaining half our friends, knowing
the range of meals which each would find acceptable.  This might involve making
a decision regarding who should attend, followed by a decision as to what each
guest should be given to eat.

Of course, this latter problem would quickly prove impractical to solve if we
had a large number of friends, each of who delighted in a wide range of special
dishes from around the world.  This introduces the notion of the tractability
of solving a particular problem, given the context of a particular method for
solving that problem.




3.03  Computation as modelling
====  ========================


All of these activities are completely characterised by the posing of some kind
of question and the discovery of an appropriate answer.  The connection between
the question and the answer is known as a model.  The model provides all the
information required in order to specify the context in which the question is
framed, and within which the answer must be interpreted.  Naturally then, if
the model changes, then so too will the associated questions and their answers.

The person whos job was that of computer was required to solve problems given
as questions, by providing answers given numerically.  This meant that usually
the problems posed were of a numerical nature, requiring for their solution
the application of numerical formulae.  These formulae and the knowledge needed
to manipulate them were provided by the computer as a skilled worker.

In some other situations, there was no directly applicable numerical model for
solving a problem.  This was so when deciding upon the invitations for half our
friends to an evening meal.  In this case, a structural model is required, and
this model must be developed by the expert computer, before being applied to
the solution of the given problem.




3.04  The essentials of computation
====  =============================


It is in principle, possible to look in detail at all the activities of such a
skilled computer, in order to discover the simplest steps taken during the
solution of any problem.  If this is done, it turns out that there are a very
small number of simplest such steps, which suffice for the solution of any
problem whatsoever, providing that the problem is indeed soluable.  {There are
some problems which appear to be insoluable by any currently known methods, but
this should not concern us since most of these types of problems are not too
relevant from a practical point of view.}

Realising this, we could then conjecture that we could build a machine in some
appropriate technology, capable of realising each one of these simplest steps.
The exact sequence of simplest steps actually used to solve any given problem,
could then be written out as a sequence of instructions, in a form suitable for
controlling the machine we have just defined.

If this is done, we can then recognise all the elements of a computer system.




3.05  Problem solving through model building
====  ======================================


It is now possible to see why a computer system is interesting and useful.  We
can solve any soluable problem for which it is possible to express a model by
applying a computer system to the expression of the problem within that model.

We usually talk of a program to solve a particular problem, or type of problem
which occurs frequently in practise.  The use of a program to control the
operation of a computer system comprises the execution of that program by the
computer system.  The activity of a computer system while executing a program
is said to be that of computation.  Computation solves a problem expressed in
the context of a given model, by supplying a solution to the problem expressed
in that same context.

The essential point is that we can represent some aspect of a reality by means
of an appropriate model, which can then be manipulated by a computer system.
In this way we can ask questions and obtain answers, without affecting the real
world reality.  The advantage of this is clear when one considers the actual
cost of answering some difficult types of question by means of an experiment.

For example, how many atomic bombs of a cetain size would it take to destroy
mankind?  Clearly, if we insist on obtaining an answer to this particular type
of question, we would benefit considerably by using a computer based model.




3.06  Types of models
====  ===============


Computation is effectively a modelling process, so we will consider the types
of modelling with which real world problems may be effectively expressed.  In
this manner we can conclude that there are really two types of models:

  1.  Numerical models
  2.  Structural models

Numerical models rely completely upon relations between numeric values given
by formulae which themselves represent the model.  The values describe certain
attributes which are applicable in the modelled situation.  Given sufficient
information, it is possible to use numerical methods to obtain values for some
unknown quantities represented by the model.  In this way, problems which are
concerned with discovering values for unknown quantites can be solved, given
that sufficient known quantities are available.

Structural models represent collections of attributes which cluster in groups
known as objects.  The structural composition of any given object may vary in
permitted ways which are themselves characteristic of the type of object.  That
is, the structure of an object may not be necessarily fixed.  An object belongs
to a class of objects, which represents a collection of object types each of
which possesses common characteristics. This enables objects to represent those
situations where the morphology is either unknown in advance or is determined
dynamically on a moment by moment basis.

In general, a structural model will employ embedded within it, many numerical
models, each for use in connection with particular situations or circumstances
arising in the model itself, or in connection with manipulation of the model.
For this reason, it is normally the case that structural models tend to be more
complex than numerical models, because they are usually larger than numerical
models.  However, special types of numerical models do occur which are very
complex indeed.  {Linear programming equations for optimising the output from
an oil refinary give just one example of such a case.}




3.07  Objects and structural models
====  =============================


Objects may theselves be composed of other objects, with variable structure, so
in principle, any structure can be modelled by means of a hierarchy of various
component objects of arbitrary complexity.  There is no restriction regarding
the use of network structures as objects, so strictly hierarchial arrangements
of objects may be used or ignored according to the modelling requirement.  This
provides complete modelling freedom.

The types of questions which we might ask in connection with structural models
are generally concerned with forming collections of objects so that some given
attribute is minimised or maximised over the group.  This type of question can
provide the answers to questions concerned with finding minimal cost routes for
travelling between a collection of cities, or the cheapest or perhaps most time
efficient synthesis route for a molecule, given certain precursor stock.

Notice that although we have identified that an object is just a collection of
attributes, we have not identified what we might mean by attribute.  Similarly
we have associated values with attributes, but have not considered what a value
might be, or what it might represent.




3.08  Attributes, values and value spaces
====  ===================================


An attribute is nothing more than the expression of one particular possibility
from a collection of such possibilities.  An attribute takes on a value, and
that value has the potential to change from moment to moment.  {Of course, for
a given model, an attribute may take a single constant value.}  In this way, an
attribute is associated with a set of potential values, which does not change
during the passage of time.  The values associated with an attribute determine
the type of the attribute, that is, the nature of the information imparted by,
or associated with the attribute.

An attribute will take on a single value at any particular moment.  We speak of
a single value chosen from a value space.  A value space is simply the complete
collection of all possible values of a related type.  Here related type implies
that all the values play an identical role in any model of which they may be a
part.

The association of an attribute with a value represents the minimum expression
of information possible.  Although a value represents minimal information, it
is usually the case that the value space containing that value possesses some
internal structure which permits more information to be associated with the
value than might at first appear possible.

Typically this will be so where other values within the same value space are
combined by means of information processing steps, such that new models result
which represent different interpretations of the original model.  The values
which are combined in this way may be attributes of objects, or purely numeric
quantities associated with numerical models.

In fact, for processing of values to take place at all, certain properties must
exist in the underlying value space.  {In general, very weak properties in the
value space are adequate to support computation.  However, in any practical
computation scheme, stronger properties are needed which have a significant
effect on the richness of available algorithms to solve any particular problem.
This richness manifests itself as a change from algorithmic intractability to
eminently practical algorithms, as the properties of the value space increase
in strength.}




3.09  Some properties of value spaces
====  ===============================


In any type of modelling scheme, certain underlying properties of the various
value spaces present are employed so frequently that they become indispensible
to any practical modelling construction.  These properties are identical to the
properties of some axiomatic number systems studied by mathematicians.  Some of
the more important properties for computational modelling are included below:

  1.  An attribute takes a single value from a finite set of similar values
      known as a value space for the particular attribute type.

  2.  There is a way of assessing the similarity or difference of any values
      from the same set of possible values.  This provides for the relations
      equal_to, not_equal_to, between any attributes of similar type.

  3.  There may be an ordering specified for the set of possible values.  In
      this case, it is possible to assess the similarity or difference of any
      values from the set, in terms of the relations less_than, greater_than,
      equal_to, not_equal_to.  It is also possible to arrange any group of
      values according to their position within the specified ordering.  It
      may be that there exists more than one possible ordering over any given
      value space.

  4.  Given two values from the same set of possible values, there is a way
      of describing their difference, which is a measure of how distant they
      are from each other assuming a special ordering of the value space made
      available for this particular purpose.  One difference can be produced
      for every pair of values in the value space.

  5.  A difference can potentially be either a signed difference or an unsigned
      difference.  A signed difference indicates a direction, and a magnitude,
      whereas an unsigned difference has a magnitude only.  Some value spaces
      do not have a signed difference defined for them.

  6.  The difference between two values from the value space is itself a value
      either of the same value space, or of another value space made available
      for the particular purpose of expressing differences.

  7.  Every value in a value space is associated with an ordinal number, which
      gives the position in the value space at which the value occurs, assuming
      the value space to be ordered according to an ordering made available for
      just this purpose.

  8.  Every value space is finite, and there is a value space which provides
      values capable of describing the size of all other value spaces.  There
      is a natural ordering specified for this size descriptive value space.

  9.  There is a value space which contains all other value spaces, over which
      a natural ordering is defined.  This natural ordering defines the natural
      ordering for every contained value space.

There are many other properties which may be required in the practical solution
of computational models, but these properties give the essential features of a
value space necessary to support useful modelling.  The essential point to see
is that values can be thought of as being associated with a continuum which
supports the notions of closeness and distance.  These notions are vital for
the construction of computational models as we will soon appreciate.




3.10  Simple values, collected values
====  ===============================


A computational model consists of a collection of attributes, each of which
associates with a single value at any given moment.  Attributes may collect
together as objects.  In turn, objects may be associated with other objects.

This provides the ability to model collections of real world objects each of
which has relations with other real world objects.  For the real world object,
there will typically be a set of characteristics which describe that object.

Each of the charateristics can usefully be modelled by an attribute of a type
appropriate to the values associated with that particular characteristic.  As
an example, consider a model of a real world gas pipeline.  The properties of
interest might be as follows:

  1.    [m]    Physical dimensions.
  2.    [s]    Maximum service pressure.
  3.    [m]    Chemical compatibility.
  4.    [m]    Maximum flow rate data.
  5.    [m]    Pressure drop / flow rate characteristics.
  6.    [s]    Coefficient of expansion of a pipe segment.
  7.    [m]    Optimum economic pressure drop.
  8.    [s]    Date of commissioning.
  9.    [s]    Major inspection interval.
  10.   [m]    Results of previous inspections.
  11.   [m]    Welding inspection certificate reference numbers.

These values are either simple values or a collection of a number of values.
For an example of simple values see (2,6,8,9) above.  The remaining attributes
collect together as multi-attributed objects which each describe what is in
effect, a single value of complex internal structure.

We can see that for models of practical interest, there must be a means for
collecting individual values together to represent multivalued aspects of the
modelled reality.  In similar fashion, it must be possible to collect together
objects into groups, which may collectively appear to behave as an object with
complex internal structure.

We have not yet considered how the representation of collections of attributes
might be possible in a computational setting.  To do this, we must consider an
aspect of computational modelling which we have so far ignored.

Until now, we have considered that processes are available for the manipulation
of information.  However, apart from suggesting that information is ultimately
represented as simple values selected from an appropriate value space, we have
not considered exactly how that information might be held in a computer system.




3.11  Models with memory
====  ==================


All models consist of constant components which never change in value, together
with variable components which do change in value, without which no model could
be used to support computational problem solving.  The fact that some values
always remain constant leads to the question of how it might be possible to
model constancy.  In fact we can conveniently manage this by means of the piece
of hardware described above as a memory unit.  A memory unit can store a value
without that value changing, no matter how much time has elapsed before the
request to retrieve the value is given.  Furthermore, no matter how many times
the value is retrieved, it does not change.  For this reason, a memory unit is
vitally important in any computational modelling activity.

Similarly, by using the properties of a memory unit in an appropriate manner,
we can make the memory preserve the value of attributes which themselves make
association with different values from moment to moment during the modelling
activity.  To see how this can be made to work, we must look in detail at the
manner in which a memory unit operates.




3.12  The memory store operation
====  ==========================


In order to get a memory unit to store a particular value, it is necessary to
provide a special value known as an address, which will be used by the memory
to give a unique identity to the value actually being stored.  So to store a
value, we first choose an address from the value space of addresses, then give
the memory an instruction to associate the address with the value to be stored.
The operation engaged in by the memory, in order to form this association, is
termed a store operation.  The instruction which causes the operation to be
carried out is termed a store instruction.

The association between an address value and the stored value during a store
operation is maintained for all time, until changed.  But before we consider
how such an association might be changed, we will see how a value stored by a
memory may be retrieved for further use outside the memory.




3.13  The memory load operation
====  =========================


A memory unit responds to two types of instruction.  We have seen above how the
store instruction can change the way an association is remembered by the memory
unit.  There is another instruction which is termed a load instruction.  This
results in the memory performing a load operation.  For a load operation to be
operate successfully, the memory unit must be presented with an address value
which must have been given at the time a store operation was made.  Given that
a store did actually take place using that address, the memory unit retrieves
the value.

This may not sound very useful, since it would appear that, in order to access
any stored information from a memory unit, a unique value must be associated
with every number stored.  In this way, it would seem that we would then have
to somehow remember the same number of address values as the number of values
stored in the memory.  This is of course a totally impractical situation.  We
will see shortly how a memory unit may be usefully employed without having to
remember endless quantities of address values.

We have seen how a store instruction provides the address and value association
which can then later be used to retrieve the value given the address.  We have
not seen how we might change an existing address and value association, so that
a model may be made of a value which changes from moment to moment during the
modelling process.




3.14  Modelling constants, variables
====  ==============================


If we fail to ever make an association between an address and a value, using a
store instruction, any load operation conducted using that address will return
a value whose nature is unpredictable.  A value is returned, but it will be of
a random nature.  If we perform a store operation, then retrieve the value by
using the same address in a load operation, the original stored value will be
returned.  If however, we perform two consecutive store operations to the same
address, using different values on each occasion, then perform a load using the
same address, the value returned will be the latest value stored.

In this way, a memory can be made to keep a value for as long as required, then
change it by means of a new store operation using the appropriate address.  In
this way, a memory unit can be made to model constancy and change.  The store
operation determines whether a load operation at a given address will retrieve
a constant value, or a variable value.  If only one store operation is made to
an address, then the value stored will always have the same value, so will be
constant.  Otherwise, the values stored to an address may be different from one
another, so any associated load operations will retrieve the changed value on
each occasion.




3.15  The problem of addresses
====  ========================


We noticed above that a memory unit would not be very practical if for each of
the stored values, it would be required to keep a note somewhere of the address
by means of which it might be retrieved.  We will now see why this difficulty
does not occur in practise.

A model is not something which remains static.  It is used to solve problems,
using computational activity to achieve a series of transformations of models
until a solution can be found.  The development of new interpretations of the
already available models is necessary to provide the information which will
ultimately solve the problem being addressed.

Implicit in all this is a set of instructions which dictate exactly how this
process of model refinement will take place.  These instructions can contain
constant values of direct or indirect use to the model.  An indirect use for
a constant value would be that of a memory address.  In this way, the question
of remembering addresses diminishes, since they can be included in the program
so long as they are constant in value.

In fact, we will not generally need the same number of address values as values
stored in a memory unit for other reasons which will soon become clear.  The
nature of information and therefore also of models, is that of natural grouping
into connected entities which we term objects.  Therefore, for any particular
aspect of a model, various values which are associated together, may easily be
stored close by each other in memory.  For this to work, we must have a notion
of closeness of two values.  Since an address is a value similar to any other
value, we will have the idea of closeness defined between two addresses.

In this way, we can choose a special address value representative of the close
grouping of addresses belonging to an associated group of values in memory.

This special address will be only a small distance away from any address values
assigned to values in the group.  Therefore we can apply a shorthand method of
accessing any of these related values.  This involves adding a small value to
the special address value, to yield the actual address in memory for any needed
value group member.  The special address value is generally known as a base
address, whilst the small value added to the base address is termed an offset.




3.16  Structures expressed by means of values
====  =======================================


We have seen that a memory is a vital component of any computational modelling
scheme, and that the representation of collections of values within a memory is
entirely natural.  We will now think about the way in which object collections
may be arranged into a grouping.

Any collection of values in memory will have a characteristic base address.  By
recognising that a base address is really just a value, it can be stored in a
memory just like any other value.  It is this possibility which permits groups
of objects to be formed with ease.  To form a group of objects, take the base
address of each individual component object, then store all the base addresses
as a collection of values making up a new compound object.  Given the base
address of the compound object, it becomes possible to access any value in any
of the member objects by means of judicious application of the relevant offset
values.

An important point to consider is that the number of objects sharing a given
internal structure (and thus set of associated characteristic offset values) is
usually large in a model of any complexity.  In this way, memory access using a
large base address value with a small offset value for each group member gives
a very compact representation for the final address of each value.  Since the
base addresses and offsets are stored with the instructions representing the
program, the program size is reduced as a consequence.




3.17  The program as a model
====  ======================


It should be clear by now that a program consists of instructions, and these
instructions may be closely associated in some way with constant values which
may be used in various ways.  One use for these values is as part of the model
which is being presented for solution of a problem.  Another, frequent use for
these constants is as representation of the base addresses and offset values
for accessing memory in order to retrieve constants and variable values which
represent the model proper.

Although we have not yet considered what may actually be necessary in order to
construct a program of instructions for solving a problem, we can now determine
some important properties of any program, no matter what the representation.

It should be clear that, whatever else a program is, it can only ultimately be
represented as a set of objects, each with any required internal structure, all
these objects being ultimately represented by a collection of single values.

This means that for any purposes, we can treat a program as an entity which can
itself be modelled in the same way that we build models of the real world.  The
reason that this is so important is that it enables a program to be stored in
the same type of memory unit that we use to store model values.  This means a
potential to build programs which take other programs as their data, using them
as models which can then be manipulated into forms and interpretations more
appropriate for solving certain proglems.  As an example of this type of model
manipulation, where the model is really a program, consider the translator for
a programming language.




3.18  The simplest operations for computation
====  =======================================


We will now look in some detail at the types of simplest operations necessary
to support meaningful computation.  These operations will have the capability
to process information by manipulating the basic information representations
that we use for modelling.

Using these manipulations, it is possible to make new interpretations of any
particular model, or indeed any particular aspect of a given model.  The new
interpretations are themselves models, but with a different information content
which may be either more specialised or more generalised than the source model
information.  In any event, it will be easier to obtain the answers to certain
questions when using the new model as compared with the original model.  This
fact provides the motivation for the creation and derivation of new models from
existing, but somehow deficient models, assuming a particular purpose has been
specified.

It is necessary to provide a model with new values from outside the model.  The
need for this is satisfied by an instruction which performs an input operation,
using the input unit described above.

In similar manner, an output instruction is made available, so that the output
unit may be commanded to deliver a new value to the computational environment.

We have already considered that store and load instructions are needed in order
to provide the memory unit with a means to function.

The processing of data requires a number of different instructions.  It must be
possible to introduce a new constant value into a computation.  Any given value
lies next to two nearest neighbouring values in the value space of which it is
a member.  Each of these nearest values must be easily and directly computable,
so that the notion of closeness may be directly used in modelling.  This can be
particularly important for the programmed manipulation of addresses, and in any
situation where counting is needed.  It should be possible to determine the
distance between two values; given a value and a difference, the value giving
the difference should be obtainable.  These operations correspond with addition
and subtraction.

Finally, it should be possible to control the proress of the computation.  This
means being able to take decisions dependant upon the values present from time
to time in the model.  In this way, the immediate progress of a computation may
be conditional upon situations detected in earlier parts of the computation.




3.s   Summary
===   =======


We have examined the operation of a computer system in order to find out what
it is that a computer actually does.  We have seen that computation can most
usefully be thought of as a modelling activity.  The motivation for modelling
is always as a means by which solutions can be found for what would otherwise
be difficult or impossible problems.

We have seen that there are essentially two types of models, and that the first
type is usually implicitly present in the second.  We have examined attributes
and their values, and means for combining attributes together to form objects.

The properties of values and their associated value spaces were described.  The
importance of the underlying structure of a value space was emphasised since it
is fundamentally important for supporting computation.

Memory units are seen to be the essential modelling vehicle for permitting the
simple expression of both constants and variables.  The concept of an address
value was introduced, with the consequent implications for representation of
programs and the modelling of objects.

We have seen that a program is itself a real world reality which may therefore
be modelled.  The resulting interesting properties of programs were described.

Finally, we examined the types of instruction which might be important for the
exppression of a program.  This concludes our overview of computation.




4.    Visual modelling
==    ================


4.01  Complexity control and abstraction
====  ==================================


In any modelling activity, there will be layers of structures built one upon
the next.  This is an important feature of modelling, since it implies that
certain details associated with a given object will be hidden from view as a
consequence of their presence within component objects of that object.  This
has the pleasant effect of enabling the component object properties to be
assumed present by abstraction, at the level of the given object.  In this way,
a complex model may be built up by combining simple component objects, or could
equally easily be built from the top down by assuming abstract properties for
needed components.

This proliferation of complexity within useful models does present certain
problems.  For example, there may be many possible ways of interpreting any
particular properties of a model.  This means that the ways we look at the
models we create must be flexible enough to accomodate the essential whilst
ommitting all unimportant detail.

Historically, when dealing with purely numeric models involving formulae which
relate different variable values together, it has been very useful for the good
understanding of such a model, to present graphs showing how under some assumed
constraints, two or more variables change with respect to each other.

It is easy to see that by visual means, a complex situation can be described
satisfactorily in terms of a two dimensional graph.  Sometimes, where an extra
dimension of change is involved, for example time, a sequence of graphs may be
the ideal representation.  Electronic engineers have embodied these principles
in devices such as the oscilloscope and logic analyser.




4.02  Human interaction with a computer system
====  ========================================


There are some special types of modelling situation where a drawing may include
multiple layers, each of which correspond to a level of design abstraction.  As
an example of this type of modelling system, one can consider the hierarchical
design systems with which silicon integrated circuits are designed.  In these
types of systems, much detail must be represented in a physically small screen
viewing area.  In addition, it must be possible to quickly change the scale at
which a design is presented, so that fine detail is clearly visible and more
importantly, manipulable.  This is an example of a direct visual model used to
represent a device which does not (yet) have any existance in the real world.

Typically, the user creating a drawing needs to be able to observe the existing
state of the drawing, and then must be able to select a portion of the drawing
and manipulate it.  It is necessary to be able to create new detail and to move
existing detail in the drawing.  For these types of operations which involve a
very precise spatial input from the user, as observed on the displayed image,
the mouse input device has proven very useful.  As an alternative to the mouse
device, a graphics tablet is also a powerful pointing device, with high useful
resolution and good positional accuracy.  Both these types of pointing device
provide for great sensitivity in pointing to a drawing feature, and therefore
enable modifications to be affected with ease.  The graphics tablet has a great
advantage over the mouse when input from an existing drawing is required.  The
tablet has excellent positional accuracy and repeatability, so can be readily
used to digitise an existing drawing into a computer system.  A mouse cannot
operate in this way, as it is a relative motion device with no capability for
absolute positional input.




4.03  Display quality issues
====  ======================


Usually, where a large amount of relevant detail must be shown on a drawing, it
it useful to inhibit the display of some detail, only enabling it to appear on
request.  In this respect, different colours used to highlight the significance
of important details can be advantageous in reducing any ambiguity in a crowded
drawing.  The number of possible colours available for display depends upon the
image generator and the display unit quality.  The image generator may generate
analogue signals with considerable colour information available, but unless the
display unit can accept this full colour bandwidth, the display colour palette
will remain limited.  This may result in some colours appearing to be identical
with each other, even though they are supposed to be different.

The ultimate capability of a displayed image is expressed in terms of the pixel
count in each screen dimension.  This depends on the image generation hardware
and the display unit.  The highest displayed spatial frequencies are limited by
the bandwidth of the output signal from the image generator and by the response
to that signal by the display unit.  In addition, there may be a physical limit
on image spatial resolution due to a shadow mask associated with the display.

When a view is changed by expanding the level of detail, or perhaps by changing
the scale at which it is displayed, it is important that the new image appear
without undue delay.  This is important to ensure continuity of concentration
for the person manipulating the design.  There is usually a trade-off between
the speed of update of an image and the level of detail actually displayed.  If
there is a great deal of image information, in general, update speeds will not
be as great as for a lower resolution image display.

In order to provide a display space which can be readily programmed to provide
high quality images within a range of different modelling requirements, it is
very important that the aspect ratio of individual display pixels be either
exactly 1:1 or very close indeed to this ideal ratio.  If aspect ratios other
than 1:1 are employed, it can be very difficult to obtain good visual results
when modelling fine detail, especially where curves must be presented.  In the
case of a circle, an aspect ratio of 1:2 will produce an effect not unlike that
of a broad nib fountain pen.  That is, the near vertical portions of the circle
will appear razor thin, whilst the near horizontals appear thick and blocklike.

The screen image must be absolutely rock steady, since any instability over a
prolonged period of time would be absolutely intolerable for someone engaged in
serious work.  This means that high quality design must be a prerequisite for
both the image generation hardware and the image display hardware.  In addition
the production and test procedures employed by the manufacturer have a vital
role to play in the production of a displayed image which is a pleasure to use.




4.04  Context representation
====  ======================


It is usually the case that when a change is contemplated to a visual model, it
must be considered in terms of at least two distinct views.  Often, it will be
necessary to consider many more than this number of separate views.  To see why
this is so, consider the common situation where a connection must be made from
one point on an image to a second, distinct point.  There are immediately two
regions of interest within the image.  If the displayed image is an uppermost
viewing level, then it may be prudent to take an enlargement about each of the
two points to be connected.  This means there will be three separate views of
the same image.

Practical considerations may mean that considerably more views are needed in
the performance of a particular manipulation.  Normally however, these views
are not needed concurrently.  As the manipulation proceeds (perhaps connecting
a line between points at different levels in a design hierarchy) the context
changes, so a previously necessary view can be relinquished, whilst a new view
is originated.  In this way, the visual presentation of the design is extremely
dynamic.  This need for multiple views can have an important impact on the way
a visual interface is designed to operate.  It must be easy and time efficient
to create and change multiple views into a design database.  One consequence of
displaying multiple views is the need to be able to place pairs of views one
upon another.  That is, it must be possible to choose the portion of one view
which is for the moment covered by a second view.  The implication is that any
view must be freely moveable within the display area.  In addition, it must be
possible to change the overlap order of views so that the obscured portions of
each view are exactly those parts that are visually unimportant.




4.05  Building blocks of a visual modelling scheme
====  ============================================


The building blocks of a visual modelling scheme are separable into two parts,
the visual context component, and the visual object component.

Visual context is concerned with the spaces available within a display screen
for presentation of a visual image which is bound to one aspect of the model
concerned.  When the visual context is changed, the displayed images change as
a consequence of overlap or of hiding, but the information which is visible in
any given context remains unchanged.  Visual context is concerned with the way
the display area of a screen is arranged so as to provide the maximum amount
of immediately visible, relevant information.

Within the display area associated with a given visual context, visual objects
will be made available for display.  {If any area of a context is not visible,
this will be as a consequence of the overlap of a number of contexts, with the
result that some are subjected to partial or complete hiding.}  These objects
will themselves be of two principle forms.   Geometric shapes comprise the main
element of visual modelling schemes, with text providing essential additional
information.

Geometric elements are provided for all the main families of geometric shape
which are likely to occur in real world objects.  Such shape families include
the square, the rectangle, the circle, the ellipse and the triangle.  Lines
are available for purposes of connecting any two points.

Text may be provided in various sizes, to suit the hierarchical level at which
the text associates with a design.  For example, in a silicon chip design, the
top level functional blocks will often employ large text with which to express
their names.  Details of interface lines between functional blocks will employ
a much smaller text, to emphasise the difference in overall importance of these
component parts.

In practise, there can be problems of representation for curves in any context
where an essentially rectilinear coordinate system is used, as is the case for
raster display systems.  The difficulty arises where line segment gradients
occur at angles antagonistic to accurate representation in a rectilinear system
of coordinates.  This happens at shallow angles to each major axis, and at the
angles which lie about one quarter of a right angle from the major axes.  These
critical angles result in jagged line segments, which are most disconcerting to
the eye.  There are means available to reduce problems of this nature, by using
an anti-aliasing technique.  This technique applies a small modification to the
displayed image by modifying the luminosity of pixels on or near the line being
processed.  The result deceives the eye into believing that a smooth gradient
is actually being displayed.  Under these conditions, the visual interpretation
becomes very close to the ideal shallow angle line segment.  However, to make
appropriate image adjustments is an extremely computationally intensive task.




4.s   Summary
====  =======


An introduction to visual modelling has been presented, showing the motivation
and historical background which preceeded computer based imaging systems.

The visual consequences of modelling with hierarchy are examined with a view to
understanding the design issues which must be addressed in ensuring that the
display system is capable of practical use in solving real problems.  Devices
available for closing the visual feedback loop by providing graphical input are
examined in terms of their comparative properties.

Some of the more important technical issues affecting displayed image quality
are reviewed.  This gives insight into motivations at work during the technical
design of a real display system.

The notion of visual context is introduced, with a discussion of the necessary
supporting manipulations required to enable control of visual context during
practical interaction with a visual modelling system.

Finally, the building blocks needed in order to construct a visual modelling
scheme are examined.  A discussion of some of the difficulties relating to use
of a rectilinear coordinate system in the representation of curves includes
mention of a technique for atonement of the problem.




5.    Display device characteristics
==    ==============================


5.01  Raster scan display systems
====  ===========================


There are a number of possible technologies used for producing high quality
visual images from computer produced data.  We are concerned with only one of
these technologies, raster scan display technology.  We will not mention any
of the other available systems, since we are concerned with video graphics
array controller chip programming, which implies using a raster scan display.

A raster scan display system is very simple in concept.  The generated visual
image is considered to be composed of a large number of lines of visual data,
with the orientation of each line being essentially horizontal.  One line is
displayed after another, so that successive lines are stacked vertically one
upon another, with minimal vertical separation.  In this way, a rectangular
image space is built up.  In order for this to work, the computer system must
provide data suitable for describing the visual content of each neighbouring
line, one after another, until each line has been described and the image is
complete.

We can think of a line as being composed of many individual picture elements,
each of which represent in some way, the smallest amount of information that it
is possible for a display to present.  A picture element is usually referred to
as a pixel, which is essentially a contraction of picture element, following
the fashion for contracting pictures to pics (or pix) and picture to pic.

A pixel has a number of useful properties.  It is entirely separate from any
other pixel, which means that any characteristics it possesses can be changed
independantly of the characteristics of any other pixel.  In this manner, we
can determine the resolving power of a display by means of a statement of how
many pixels the display can support during operation.  This is termed the
resolution of the display.  However, visual images are generated outside the
display itself, so the resolution of the image generator must be taken into
account when deciding the achievable resolution for the entire visual system.

The important physical properties of a pixel are those of size, aspect ratio
and colour capability.  A small pixel will pack more tightly into a given line
length therefore giving greater resolution for the presented image.  The aspect
ratio should ideally be 1:1 as noted above.  This gives best results using a
rectilinear coordinate system.  The colour capability of a pixel is expressed
as hue and luminosity.  Hue describes the mixture of the primary colours used
to generate a displayed colour, whilst luminosity is a measure of the strength
of the colour.




5.02  Raster scan image refresh
====  =========================


A pixel can be given exactly the properties required by means of descriptive
data sent to a display unit from a computer system.  However, a display unit
does not itself possess any memory for the characteristics given to a pixel in
this way.  That is, the display system can display a pixel according to data
describing that pixel, but that data is not remembered anywhere in the display
unit.  The effect is that a single image can be produced, which then starts to
fade away, until it becomes quite invisible.

Therefore, when building an image using a raster scan display system, we have
only to present the display device with an endless stream of data, composed of
the information we need to completely describe the characteristics of each and
every pixel, on a moment by moment basis.  The need to supply data to a display
on a continuous basis, arises because the display can only present a displayed
image for a small time before the image begins to fade.  However, if we make
the display data continuous, the image produced will not have time to begin to
fade, so will remain strong.  The fade time of an image determines the delay
before the image must be refreshed, this time decided by the chemicals used in
making the phosphor in the cathode ray tube.  {In fact, there is a short term
memory in a display unit, which is the result of a phosphor taking some time to
forget the information represented by the radiation of coloured light at some
particular intensity.  This short time permits the serial presentation of data
into a display device to result in a complete image over the entire screen.}

{Note: not all raster display systems use a cathode ray tube with its attendant
phosphor fade.  This was for many years the dominant technology, and is still
the principle display tchnology used today.  Other raster display technologies
use exactly the the same signals as would a cathode ray tube system, but do not
suffer from phosphor fade.  We mention the above simply to give an insight into
the original design motivation behind repeated data presentation into a raster
scan display device.  There are other consequences of the original technology
which will become apparent in later discussions.  Most of the timing issues in
raster scan image generation relate to the original technology.}




5.03  Signals for image generation
====  ============================


The sequential generation of an image requires that individual lines of visual
data be sent to a display device, one after another, until an entire image has
been constructed.  The whole process is then repeated indefinately.  The data
which represents the individual characteristics of each pixel must therefore be
synchronised in some way with the operation of the display device.  This must
be done in order to ensure that the data for each pixel actually changes the
same physical pixel on the screen, each time it is sent to the display unit.

The display unit operates to an extent without any knowledge of the data being
sent to it from the image generator.  Once an image has started, the display
alters each pixel in a display line simply by converting the colour information
arriving from the image generator into light of specified hue and luminosity.

The physical process used by the display unit involves scanning three separate
electron beams at a known and absolutely constant velocity across the pixels
making up the line to be displayed.  The colour information from the image
generator is used to change the intensity of each of the three electron beams.
The strength of an electron beam striking a phosphor determines the intensity
of the light emitted by the phosphor.  By making each pixel from three dots of
different coloured phosphors, and arranging that each electron beam focuses on
phosphor of a known colour, it is possible to completely control the colour at
each pixel position of the display.

The image generator has a way of telling the display unit that a complete new
image is about to be transmitted, and also a way of informing the display unit
that a new line of visual information is about to be sent.  Apart from these
two synchronisation signals, the displayed image positional stability depends
completely on the ability of the two units to maintain very accurate matched
timing in their operations.  The display scans each pixel in a line at a known
rate, so the image generator must supply pixel colour information at exactly
this same rate.  In this way, so long as the timing stays the same during the
period required to display one line, the image will be positionally stable.

The signals describing pixel characteristics provided by the image generator
represent intensities which are used by the display unit to modulate light from
each of the three phosphors which make up one complete display pixel.  These
phosphors generate the colours red, green and blue.  Using the emmision colour
mixing model, it is possible to represent any desired hue and luminance by
changing the absolute intensity value of each of these component colours.  In
this way an entire colour image is formed on the display screen.




5.04  Timing issues
====  =============


For practical generation of display image information suitable for presentation
into a raster scan display device, there must be provision for synchronisation
signals.  We will now examine some of the important timing characteristics of
these synchronisation signals by looking at the display unit operation in some
detail.  We will, as before, assume a cathode ray tube based display unit.

The most important aspect of timing information in a raster scan display based
on a cathode ray tube, is concerned with the finite energy required to move the
electron beams across the surface of the display tube.  This energy is used to
create a varying magnetic field, which permeates the display tube and results
in the deflection of the electrons passing through it.  This is the essential
mechanism by means of which the pixels in a display line are scanned.  However,
there are some important consequences of this use of a magnetic field and they
affect the timing signals presented by the image generator to the display unit.

The magnetic field which sweeps the beams of electrons across the display tube
is a strong magnetic field.  This means it possesses a large amount of energy.
That energy reaches a maximum at the extreme positions of a scan line.  So at
the start of a scan line the magnetic energy is at a maximum in one direction,
whilst at the end of a scan line the energy is a maximum in the very opposite
direction.  The implication is that between the extreme right position on one
scan line and the extreme left position of the following scan line, a large
amount of energy must be safely transferred.  This cannot happen without some
time being made available specially for the purpose.

Each time the display line is advanced from the top of the display tube towards
the bottom, a similar argument applies.  A magnetic field possessing energy is
used to direct the electron beams at right angles to those used for the pixel
scan along each line.  But the energy argument is just as valid in the vertical
direction.  Therefore in order to finish the last display line in the image it
is necessary to provide a time delay so that the magnetic field can be set up
ready for the first line in the display.  As before, considerable energy must
be transferred, which accounts for this requirement.

During the flyback period, which can be either line flyback or frame flyback,
the electron beams would normally re-traverse the screen, which would cause
difficulties with image interference.  This would be the result of any double
exposure of pixels to the electron beams.  In order to prevent this possibility
all the electron beams are inhibited during a flyback period.  This is termed
line blanking and frame blanking respectively.

The circuitry which controls the horizontal and vertical scanning uses a method
of improving the absolute positional accuracy of the electron beam deflection
called overscanning.  An overscan is the result of applying too much deflection
to the electron beams to the extent that they no longer strike the surface of
the screen.  Instead, they strike an interior portion of the display tube, and
do not generate any image as a consequence.  A difficulty arises when the beams
start to strike the display screen resulting in image generation.  The result
is an image which appears ragged, since the boundary between the non-displaying
and displaying part of the screen may not be well defined.  In addition, there
is the need to establish unambiguous synchronisation between the display unit
and the image generator.  This cannot be readily achieved by using the edge of
the screen as a guide to determining where each scan line should commence.

To combat this problem, horizontal blanking is used to switch off the electron
beams at the start and end of each horizontal scan line.  In this way some part
of the display screen remains unused, but the result is a much more stable and
accurately positioned display.  The horizontal synchronisation signal is used
to specify the exact timing characteristics of this special blanking.  It can
usefully be thought of as an extension of the line blanking due to flyback.

There is an identical extension to the vertical synchronisation signal for the
same reasons.




5.05  Image generation can be dangerous!
====  ==================================


The timing of the horizontal and vertical synchronisation signals is determined
completely by the image generator, but although this is so, these signals must
be interpreted correctly by the display unit if the intended image is ever to
be produced.  This means that there is potential for an image generator to send
visual signal information to a display unit, which that display unit cannot use
to produce an image.

It is important to see why this may be so, since if such signals are sent to a
display unit, one possible consequence is that permanent damage to the display
may result.  Obviously this situation is extremely undesirable, and likely to
be very costly if it does occur.  This is one of the rare situations where the
incorrect use of software can result in destruction of hardware.  {We refer to
industry standard systems only in making this remark.  There are large classes
of systems termed embedded systems where the coupling between hardware and the
software which controls it is so close, that this potential for destruction is
ever present.  Such systems are only programmed by experts as a result.}

A display unit has the important characteristic that it will correctly accept
synchronisation and image generation signals upto a certain maximum frequency.
This means that in a given time, only a certain quantity of information may be
accepted by the display unit from the image generator unit.  If this maximum
frequency is exceeded, the circuitry within the display unit will not function
correctly and may be damaged as a result.  This can happen because the quantity
of energy used in controlling the electron beam scanning is very high, making
it essential that electronic devices capable of withstanding high stress are
used in the circuitry.  Moreover, to improve display device reliability, energy
conservation circuits are introduced into the display unit.  This measure means
that the display circuits dissipate less heat and therefore operate at a lower
temperature than would otherwise be the case.  However, in order to for these
circuits to operate correctly, certain important assumptions must be made about
the frequency of operation.  This is in essence why it is possible to damage a
display device by feeding it with image information at too high a frequency.




5.06  Persistance in human vision
====  ===========================


The frequency of the image information presented to a display unit determines
the maximum image resolution of the resulting display, assuming an acceptable
match exists between the image generator and the display unit.  That is, the
greater the number of pixels to be displayed, the more information is required
for each single image displayed.  We term each of these images a frame.  More
information in a given amount of time results in a higher frequency.  We would
like to keep the image information frequency as low as possible, since this
helps to keep the display system quality high and the cost low.  This can only
be done by making a compromise.  We will now examine how this can be achieved.

We have seen above how it becomes necessary to repeat each frame at such a rate
that the resulting display image becomes constant.  We have seen how this can
be determined by the image persistance of the phosphors representing a pixel.
There is another important aspect of image persistance which we have not yet
considered.  The human eye itself has properties of image persistance.  So it
is possible for a human eye to provide an image for some time after the image
has vanished.  This is the important property which gives projected cinema film
the realism which makes cinema films possible.  In projecting a cinema film, a
single image is flashed onto the screen for a fraction of a second, then the
light illuminating the image is removed, the image is then replaced by the next
in sequence.  This whole process repeats many times per second.  Persistence of
vision is the means by which the cinema screen seems to give a steady portrayal
of stationary scenes and smooth representation of movement.

This same persistance is at least partly responsible for our ability to see the
image presented by a display unit as a single continuous image.  We know that a
phosphor also exibits persistance.  An interesting question therefore arises.
How many frames per second must we display in order to minimise the information
sent to a display unit, whilst still maintaining an acceptable displayed image?

This question is absolutely vital in determining the highest frequency that a
display unit must operate at, given a particular image resolution.  This whole
issue determines the cost of the display unit and the quality of the displayed
image.  It therefore also determines the characteristics of the image generator
which must produce the information for creating the image.  So it is a really
pivotal question for a visual display system.

A cinema projector usually operates at 24 frames per second, and at this frame
frequency a high quality image is perceived.  At lower frame frequencies, there
may be image flicker, which after some time can become very unpleasant.  It is
important to eliminate flicker so that a display system image can if necessary,
be observed for prolonged periods of time without creating undue stress.

A display unit frame is not directly comparable with a cinema film frame.  This
is so because a display unit produces an image by using scanned electron beams,
whilst the cinema film frame is a complete image in its own right.  This means
that in order to give the same freedom from perceived flicker, a display unit
must produce more frames per second than does a cinema projector.  In practise
a display unit will usually attempt to operate at a frame frequency of at least
40 frames per second.  Some display units operate at over 90 frames per second,
which results in an extremely stable, high quality image.  Of course, to run at
the higher frame rate means much more image information must be generated, so
the complete cost of the display system will be very much higher than a system
which uses a low frame rate.




5.07  Interlaced display
====  ==================


It is important to keep the frame rate of a display system as high as possible
in order to produce a good quality image which remains flicker free.  At the
same time, we wish to keep the information frequency as low as possible so as
to minimise the cost of the display system.  We will now examine an interesting
compromise which attempts to obtain the best of both situations by using what
really amounts to a clever visual trick.  This trick just happens to be simple
to implement using raster scan display technology, hence is of practical merit
in some types of display systems.

The trick is based on the observation that apparent flicker can be reduced when
two almost identical images are displayed one after another, but in a special
physical relationship with each other on the display screen.  All single images
are composed of a certain number of raster scan lines.  It is possible to take
a single image and make two separate images from it, by taking alternate scan
lines from the full image.  This places all even numbered scan lines in one of
the derived images, with all the odd numbered scan lines making up the second
image.  These derived images are then each composed of approximately half the
number of scan lines appearing in the original image.  In this way each derived
image is represented by approximately half the visual information needed in the
original image frame.  {We say approximately half, since we did not specify the
number of scan lines in the original image, which may not be divisible into two
identical parts.}

We can then display these two derived image frames alternately, which means the
visual information frequency is roughly halved, whilst the frame rate remains
constant.  Alternatively, the visual informatin frequency can remain constant,
whilst the frame rate is doubled.  To do this, the display unit interlaces the
two images, which means that physically, on the screen, the original image is
reconstituted exactly as it was prior to being dismembered.  Obviously in order
for this to work, the display unit positional error must be very low.  However,
this is a requirement of any display system, so does not present tremendous
difficulty.  In this way, flicker is reduced, whilst a reasonable quality image
is produced by the display system.  As a result the apparent display resolution
can be increased by a factor of two, without too much increase to the cost.

For the very highest quality display presentation, it is better not to use this
technique, since the ability of the display unit to correctly reconstitute the
image will leave something to be desired.  However in some situations interlace
can be useful.




5.08  Screen border display
====  =====================


It may prove useful to display an image which is substantially smaller than the
resolution of the display unit being used.  This might be the case where some
software assumes such a smaller image area when creating a visual image.  So it
can be displayed on the higher resolution display system, some of the pixels on
the display must be effectively removed from the true image area.  In this way,
the actual image display will appear smaller than the true available image area
on the display screen.

A convenient way to manage this reduction in display image size, is to create a
border surrounding the true active display area.  In this way, those pixels not
required in the image are set to some predetermined colour, which is termed the
border colour.  We mention this possibility since later, we will see that this
capability is supported by a video graphics array controller chip.




5.09  Cursor generation
====  =================


An image display system is an output component in a feedback loop incorporating
the computer system and the person using that system.  Within a displayed image
there is one point with which the user is presently concerned.  This point will
be subject to any manipulation deemed necessary by the user.  As the resolution
of the display system increases, the quantity of visual data becomes large, so
the user requires a means of determining where the active point is situated.

The movement of an input device can be related to a cursor which specifies the
exact position of the hot spot within the image.  This cursor will be easy to
distinguish from the image proper, and for this purpose will normally blink on
and off at a rate designed to be easily seen amongst a mass of visual detail.

Since the generation of a blinking cursor by software is a very high overhead
operation, it is beneficial for the image generation hardware to provide some
facilities for cursor generation and positional control.




5.10  Multi-synch monitors
====  ====================


There is some advantage in designing a display unit (also termed a monitor, or
sometimes video monitor) so that it will accept image information at different
frequencies.  The advantage is that the full display area is used, rather than
producing a small image with an unused border as discussed above.  The display
accepts lower frequencies of image information and, as a direct consequence of
this, the apparent physical width of a pixel changes.  The result is a reduced
resolution display, but one which takes up the full display area.

For this concept to work, there are certain frequencies assumed to be in use by
the display system, so that signals from the image generator can be analysed to
determine their timing properties, and hence determine the correct operation of
the display unit.  Since the signals which give image timing are synchronising
signals, the name of such devices is multi-synch monitors.  At any moment, only
one of the possible display unit operating frequencies is matched by the timing
of the horizontal and vertical synchronising signals.  If this timing should be
changed, then the monitor adopts the new frequency after a short period.  For a
short time during the change over period, the image produced by the monitor may
be dimensionally and visually unstable.  This is quite normal with commercially
available multi-synch monitors.  However, this should not be surprising, as the
operation of the monitor is affected so fundamentally by the change from one
input frequency to another.




5.s   Summary
====  =======


The concepts associated with raster scan display systems are introduced with
the special emphasis on the use of cathode ray tubes for the display unit of
such systems.

The pixel is identified as the fundamental unit for image presentation and also
display image resolution.  Properties of pixels are explored.

The properties of a cathode ray tube based display unit are seen to embrace the
need for image refresh.  This is seen to be a consequence of the absence of any
image data memory in a display unit.

The need for synchronisation between an image generator and a display unit is
identified and related to the physical processes employed by the display unit
for image presentation.  The concept of multi-phosphor pixels is introduced,
with consequences for the data encoding of colour information.

The need for periods of inactivity between the display of neighbouring scan
lines is outlined in terms of flyback energy, with similar requirements for
the frame flyback period.  The use of special linearising circuitry for both
line scanning and frame scanning is seen to have important implications for
the horizontal and vertical synchronisation signals respectively.

The properties of display units which make them suceptible to damage by image
generators are carefully examined.

Consequences for display system design deriving from human visual persistance
are examined.  These are seen to be of seminal importance.

The interlace technique is seen as a trade off between ultimate image quality
and image information frequency, with implications for display system cost.

The use of a border area is examined as a means for using low resolution images
with a high resolution display unit.

The advantage of an image generator supported cursor is reviewed.

Multi-synch monitor are described in relation to their frequency agility with
implications for display of images at a lower resolution than that supported
naturally by the display device.




6.    Trident 8900 VGA controller: Computer interface
==    ===============================================


6.01  Memory interface
====  ================


The video graphics array controller must repeatedly transmit image information
to the display device.  Since the display device does not possess an image data
memory, that memory must be provided by the image generator.  Image generation
is intimately managed by the controller chip, so the image memory can only be
accessed through the controller chip.  In this way, we do not have to concern
ourselves with the complicated hardware details of memory access, as the memory
interface provided by the controller chip suffices.   This interface will now
be given in broad outline, but important details will be omitted for clarity.

The Intel 80x86 processor family uses a segmented memory architecture.  In the
original 8086 processor, for which most current software is targetted, the size
of a segment is limited to a maximum of length of 64 kilo-bytes.  This quantity
of memory is therefore immediately accessible without the need for changes to a
segment register value.  For this reason, the memory access interface provided
by the VGA controller requires that the processor generate addresses inside the
64 kilo-byte span of a segment.  The motivation is speed of image access.

The image generator typically controls much more memory than 64 kilo-bytes, so
that high resolution colour images can be generated.  A usual configuration at
the time of writing would be 1024 kilo-bytes of image memory.  Clearly, so that
the processor be able to read and write such a large image memory using only 64
kilo-bytes of addressing, some type of access extension mechanism is needed.

We can think of the 64K {shorthand: 64 kilo-bytes} addressing range recognised
by the VGA controller as being a window into the much larger image memory.  If
the controller is reappraised of the alignment of this window within the entire
image memory range, it is possible to read and write to the full image memory.

Of course, for this scheme to work, we would periodically have to send special
information to the controller chip, which adjusts the positioning of the memory
window, so gaining access to memory outside the 64K furnished by the currently
defined window.

In order to specify where within the full image memory span the current access
window will be situated, the concept of a page is introduced.  A page contains
two segments, each of which is 64K.  So a page represents a memory unit of 128K
bytes of image memory.  Further, two pages combine to form a bank with 256K of
image memory.  Finally, one of four possible banks can be selected, giving full
access to one megabyte of image memory.  It is important to note that the image
memory is only accessible via the VGA controller chip.  It is not possible to
directly access this memory from the processor, except insofar that the memory
interface provided by the VGA controller permits.  This is equivalent to saying
that any read or write access to the 64K window provided by the VGA controller
has an effect in video memory determined by a pre-established context which has
to be explicitly programmed for the purpose at hand.  The memory interface must
be managed by the programmer, so nothing can be taken for granted.

In fact, there are a number of complications with this scheme, which we should
expect in a subsystem as powerful as the VGA controller.  This means that later
we will encounter additional VGA controller capabilities which affect the image
memory addresses which are generated by the processor.




6.02  Input, output, port interface
====  =============================


The VGA controller is a collection of mutually supporting logic blocks, which
interact to produce the full functionality required of the controller.  Each of
the individual logic blocks can sometimes be conveniently programmed as though
it were completely isolated from all the remaining blocks, although that is not
always the case.  For reasons related to ease of chip design, each block has an
interface provided which gives input output port access to a set of internal
control registers.  These registers determine the detailed operation for each
logic block so can be used to give fine control of image generation as required
in a sophisticated image display system.

The access to large numbers of internal programmable registers by a processor
provides a problem for the hardware designer.  The idea is to provide as much
functionality as possible, without using too many hardware resources providing
access to the large number of programmable registers needed for control.

To ease this hardware design problem, which is effectively an attempt to reduce
the device complexity and cost from the hardware point of view, a trade-off is
made with respect to ease of programmability.  This trade-off is the reason why
VGA controller chips are a little strange to program.  {People who think every
means possible should be employed to make every device easier to program should
reflect that even with contemporary technology, adherance to this philosophy is
not economically possible, from the hardware design and development viewpoint
and also because of manufacturing and marketing considerations.  The truth of
this is especially visible where commodity market chips are concerned.}

We now see the typical input output port interface provided to give access to
the programmable registers within one logic block of the VGA controller chip.
Each interface uses just two input output port addresses.  This simplifies the
decoder logic overhead within the logic block.

If the logic block we are going to program is the Sequencer, the two ports we
will access lie at the following addresses:

  1.  Sequencer Address Register  {  Port 3c4 hex for Read, Write }
  2.  Sequencer access port       {  Port 3c5 hex for Read, Write }

The correct programming sequence for accessing an internal register depends on
each of the registers being associated with an index number.  Programmers can
think of the internal registers being arranged in an array for which an index
must be provided in order to obtain access to an individual register.  Once the
index number for the register of interest is known, that index number is output
to the Sequencer Address Register.  The sequencer will then set itself up so an
access to the Sequencer access port actually performs input or output to the
required internal sequencer programmable register.

A code fragment to perform a write to the Character Map Select Register within
the sequencer, and then to read that value back is given below.


           ; start example 1

           ; Set up Sequencer Address Register ...
           ; ... for access to Character Map Select Register

           mov     dx,3c4h         ; Sequencer Address Register port
           mov     al,03h          ; Character Map Select Register index
           out     dx,al           ; select the Character Map Select Register

           ; Write the Character Map Select Register

           mov     dx,3c5h         ; Sequencer access port
           mov     al,write_data   ; collect the data to write
           out     dx,al           ; write the Character Map Select Register

           ; Read the Character Map Select Register

           mov     dx,3c5h         ; Sequencer access port
           in      al,dx           ; read the Character Map Select Register

           ; end example 1


Whilst this example does not appear to be particularly onerous, we will see in
later examples that the number of registers which must be programmed in concert
may lead to long sequences of code which do nothing else but select and access
VGA controller registers, prior to actually performing image manipulation.  It
would be misleading to pretend that the writing of such sequences is anything
other than tedious;  however, if excellent results (or indeed any results!) are
to be had, we must face this prospect.

There is a fortunate aspect of the Intel 80x86 input output port architecture
which can help to ease the programming burden associated with VGA registers.
When a word output is performed to a particular port number, two bytes are in
fact transferred.   The first is sent to the port mentioned and the second is
sent to that port number plus one.  This has the happy consequence that it is
possible using word output, to effect the index selection with the first port,
followed by data output to the just selected register.  This can help to ease
the amount of code to be written, and is of course much faster to execute.


           ; start example 2

           ; Set up Sequencer Address Register ...
           ; ... for access to Character Map Select Register

           mov     dx,3c4h         ; Sequencer Address Register port
           mov     al,03h          ; Character Map Select Register index

           ; Write the Character Map Select Register

           mov     ah,write_data   ; collect the data to write
           out     dx,ax           ; write the Character Map Select Register

           ; Read the Character Map Select Register

           mov     dx,3c5h         ; Sequencer access port
           in      al,dx           ; read the Character Map Select Register

           ; end example 2


In this way, it is possible to omit one output port instruction and one address
load instruction, making a saving of 2 instructions per 6 original.  This is a
very useful saving.  Useful execution speedup is also obtained in consequence.




6.03  Complete input, output port accessible register list
====  ====================================================


The registers are listed with a document reference number which is numeric only
or preceeded by an X.  The numeric only register reference numbers describe the
standard VGA registers.  Those beginning with an X, describe extended registers
which may be specific to a particular implementation, in this case, the Trident
8900 video graphics controller chip.

The port address is some instances contains a ? indicating that an alternative
port address can be made available under program control.  This choice will be
between the hex digit 'b' for monochrome emulation or 'd' for colour emulation.
The port address shown as 3?5h would be either 3b5h or 3d5h depending upon the
value of the status bit <0> in the Miscellaneous Output Register.

In some instances, the access definition for a particular register will change
for read and write.  Sometimes, for example, a different port is used depending
on whether a value is being written to, or being read from, the register.  This
difference will be highlighted by the appearance of two descriptive lines, with
the suffixes a,b indicating a closely related definition.

Note that not all port addresses are used.  This is also true of the register
index numbers used to access the internal arrays of registers.  In most cases
the hardware defines some internal datapath for these unused register indexes.
They are used only for testing purposes, if at all.  They are not significant
with respect to programmable functionality, so should not be accessed.  Where
a break in contiguous index numbers occurs, this is emphasised by means of a
dummy line, which breaks the pattern of smoothly increasing index numbers.


Document Reference
===---------------

       Index Port Address
===    ====--------------

               Access Port Address
===    ====    ====---------------

                       Index Number
===    ====    ====    ===---------

                              Read/Write Access
===    ====    ====    ===    ===--------------

                                     Register Description
===    ====    ====    ===    ===    ====================


  1    3c4h    ----    ---    R/W    Sequencer Address Register
  2    3c4h    3c5h    00h    R/W    Reset Register
  3    3c4h    3c5h    01h    R/W    Clocking Mode Register
  4    3c4h    3c5h    02h    R/W    Map Mask Register
  5    3c4h    3c5h    03h    R/W    Character Map Select Register
  6    3c4h    3c5h    04h    R/W    Sequencer Memory Mode Register
       ----    ----    ---    ---
X 1    3c4h    3c5h    0bh    R--    Hardware Version Register {new definition}
X 2    3c4h    3c5h    0bh    --W    Version Selector Register {old definition}
       ----    ----    ---    ---
X 3    3c4h    3c5h    0ch    R/W    Configuration Port Register 1
X 4    3c4h    3c5h    0dh    R/W    Mode Control Register 2
X 5    3c4h    3c5h    0eh    R/W    Mode Control Register 1
X 6    3c4h    3c5h    0fh    R/W    Power-up Mode Register 2


  7a   3b4h    ----    ---    R/W    CRT Controller Address Register
   b   3d4h    ----    ---    R/W    CRT Controller Address Register
  8    3?4h    3?5h    00h    R/W    Horizontal Total Register
  9    3?4h    3?5h    01h    R/W    Horizontal Display Enable End Register
 10    3?4h    3?5h    02h    R/W    Start Horizontal Blanking Register
 11    3?4h    3?5h    03h    R/W    End Horizontal Blanking Register
 12    3?4h    3?5h    04h    R/W    Start Horizontal Retrace Pulse Register
 13    3?4h    3?5h    05h    R/W    End Horizontal Retrace Register
 14    3?4h    3?5h    06h    R/W    Vertical Total Register
 15    3?4h    3?5h    07h    R/W    CRT Controller Overfow Register
 16    3?4h    3?5h    08h    R/W    Preset Row Scan Register
 17    3?4h    3?5h    09h    R/W    Maximum Scan Line Register
 18    3?4h    3?5h    0ah    R/W    Cursor Start Register
 19    3?4h    3?5h    0bh    R/W    Cursor End Register
 20    3?4h    3?5h    0ch    R/W    Start Address High Register
 21    3?4h    3?5h    0dh    R/W    Start Address Low Register
 22    3?4h    3?5h    0eh    R/W    Cursor Location High Register
 23    3?4h    3?5h    0fh    R/W    Cursor Location Low Register
 24    3?4h    3?5h    10h    R/W    Vertical Retrace Start Register
 25    3?4h    3?5h    11h    R/W    Vertical Retrace End Register
 26    3?4h    3?5h    12h    R/W    Vertical Display Enable End Register
 27    3?4h    3?5h    13h    R/W    Offset Register
 28    3?4h    3?5h    14h    R/W    Underline Location Register
 29    3?4h    3?5h    15h    R/W    Start Vertical Blanking Register
 30    3?4h    3?5h    16h    R/W    End Vertical Blanking Register
 31    3?4h    3?5h    17h    R/W    CRTC Mode Control Register
 32    3?4h    3?5h    18h    R/W    Line Compare Register
       ----    ----    ---    ---
X 7    3?4h    3?5h    1eh    R/W    CRTC Module Testing Register
X 8    3?4h    3?5h    1fh    R/W    Software Programming Register
       ----    ----    ---    ---
X 9    3?4h    3?5h    22h    R--    CPU Latch Read Back Register
       ----    ----    ---    ---
X10    3?4h    3?5h    24h    R--    Attribute State Read Back Register
       ----    ----    ---    ---
X11    3?4h    3?5h    26h    R--    Attribute Index Read Back Register


 33    3ceh    ----    ---    R/W    Graphics Address Register
 34    3ceh    3cfh    00h    R/W    Set/Reset Register
 35    3ceh    3cfh    01h    R/W    Enable Set/Reset Register
 36    3ceh    3cfh    02h    R/W    Colour Compare Register
 37    3ceh    3cfh    03h    R/W    Data Rotate Register
 38    3ceh    3cfh    04h    R/W    Read Map Select Register
 39    3ceh    3cfh    05h    R/W    Graphics Mode Register
 40    3ceh    3cfh    06h    R/W    Miscellaneous Register
 41    3ceh    3cfh    07h    R/W    Colour Don't Care Register
 42    3ceh    3cfh    08h    R/W    Bit Mask Register
       ----    ----    ---    ---
X12    3ceh    3cfh    0eh    R/W    Source Address Register
X13    3ceh    3cfh    0fh    R/W    Source Address Enable Register


 43    3c0h    ----    ---    R/W    Attribute Address Register
 44a   3c0h    3c0h    00h    --W    Palette Register 00
   b   3c0h    3c1h    00h    R--    Palette Register 00
 45a   3c0h    3c0h    01h    --W    Palette Register 01
   b   3c0h    3c1h    01h    R--    Palette Register 01
 46a   3c0h    3c0h    02h    --W    Palette Register 02
   b   3c0h    3c1h    02h    R--    Palette Register 02
 47a   3c0h    3c0h    03h    --W    Palette Register 03
   b   3c0h    3c1h    03h    R--    Palette Register 03
 48a   3c0h    3c0h    04h    --W    Palette Register 04
   b   3c0h    3c1h    04h    R--    Palette Register 04
 49a   3c0h    3c0h    05h    --W    Palette Register 05
   b   3c0h    3c1h    05h    R--    Palette Register 05
 50a   3c0h    3c0h    06h    --W    Palette Register 06
   b   3c0h    3c1h    06h    R--    Palette Register 06
 51a   3c0h    3c0h    07h    --W    Palette Register 07
   b   3c0h    3c1h    07h    R--    Palette Register 07
 52a   3c0h    3c0h    08h    --W    Palette Register 08
   b   3c0h    3c1h    08h    R--    Palette Register 08
 53a   3c0h    3c0h    09h    --W    Palette Register 09
   b   3c0h    3c1h    09h    R--    Palette Register 09
 54a   3c0h    3c0h    0ah    --W    Palette Register 10
   b   3c0h    3c1h    0ah    R--    Palette Register 10
 55a   3c0h    3c0h    0bh    --W    Palette Register 11
   b   3c0h    3c1h    0bh    R--    Palette Register 11
 56a   3c0h    3c0h    0ch    --W    Palette Register 12
   b   3c0h    3c1h    0ch    R--    Palette Register 12
 57a   3c0h    3c0h    0dh    --W    Palette Register 13
   b   3c0h    3c1h    0dh    R--    Palette Register 13
 58a   3c0h    3c0h    0eh    --W    Palette Register 14
   b   3c0h    3c1h    0eh    R--    Palette Register 14
 59a   3c0h    3c0h    0fh    --W    Palette Register 15
   b   3c0h    3c1h    0fh    R--    Palette Register 15
 60a   3c0h    3c0h    10h    --W    Attribute Mode Control Register
   b   3c0h    3c1h    10h    R--    Attribute Mode Control Register
 61a   3c0h    3c0h    11h    --W    Overscan Colour Register
   b   3c0h    3c1h    11h    R--    Overscan Colour Register
 62a   3c0h    3c0h    12h    --W    Colour Plane Enable Register
   b   3c0h    3c1h    12h    R--    Colour Plane Enable Register
 63a   3c0h    3c0h    13h    --W    Horizontal PEL Panning Register
   b   3c0h    3c1h    13h    R--    Horizontal PEL Panning Register
 64a   3c0h    3c0h    14h    --W    Colour Select Register
   b   3c0h    3c1h    14h    R--    Colour Select Register


 65a   3c2h    ----    ---    W--    Miscellaneous Output Register
   b   3cch    ----    ---    --R    Miscellaneous Output Register
 66    3c2h    ----    ---    R--    Input Status Register Zero
 67    3?ah    ----    ---    R--    Input Status Register One


 68    3c3h    ----    ---    R/W    Video Subsystem Enable Register
 69    46e8h   ----    ---    R/W    Display Adapter Enable Register


 70    3c6h    ----    ---    R/W    DAC Pixel Mask Register
 71    3c7h    ----    ---    R--    DAC Status Register
 72    3c7h    ----    ---    W--    DAC Read Data Address Register
 73    3c8h    ----    ---    R/W    DAC Write Data Address Register
 74    3c9h    ----    ---    R/W    DAC Data Register


This concludes the list of programmable registers for the VGA controller chip.




6.04  Register specifications: Sequencer
====  ==================================


6.04.01  Sequencer Address Register      { 3c4h    ---    R/W }
=======  ======================================================


<3..0>   Sequencer Register Address
         --------------------------

         Port 3c5h accesses the register pointed to by the index number in this
         bit field.  Index number zero is represented by <=0000>.

         This register is cleared to zero by hardware RESET.


<7..4>   Reserved. Always <=0000>.
         -------------------------




6.04.02  Reset Register                  { 3c5h    00h    R/W }
=======  ======================================================


Cross reference with {6.04.03} Clocking Mode Register.


This register provides capability to stop the sequencer operation.  This must
be done before changing the highly critical mode selections which govern all
the timing signal generation for the VGA controller.  Changes to the critical
Clocking Mode Register must be preceeded by a reset to the sequencer and then
followed by a sequencer restart.


<0>      Fast Reset Command
         ------------------

         <=0>  Apply an immediate reset to the sequencer.  This can result in
               a loss of data from the image memory.  If this loss cannot be
               tolerated, the safe reset command should be used.  This image
               memory loss occurs because the sequencer action maintains the
               memory refresh necessary to preserve memory data during normal
               operation.  If the sequencer suddenly stops, the memory chips
               cannot receive their refresh cycles resulting in lost data.
               At the hardware level, all sequencer outputs go tristate when
               this option is selected.

         <=1>  No immediate reset condition requested.  This condition is not
               sufficient to guarantee that the sequencer will run, since it
               must occur in conjunction with an absence of Safe Reset.


<1>      Safe Reset Command
         ------------------

         <=0>  Apply a safe reset to the sequencer.  The sequencer maintains
               correct image memory signal operation during the reset period.
               This reset should be used whenever the image memory must be
               preserved across the reset.  Note that this reset cannot last
               longer than a few tens of microseconds without the possibility
               of image memory corruption due to lack of refresh activity.
               The sequencer outputs do not go tristate for this setting.

         <=1>  No safe reset condition requested.  This condition is not
               sufficient to guarantee that the sequencer will run, since
               it must occur in conjunction with an absence of Fast Reset.


<7..2>   Reserved. Always <=000000>.
         ---------------------------




6.04.03  Clocking Mode Register          { 3c5h    01h    R/W }
=======  ======================================================


Cross reference with {6.04.02} Reset Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.03} Horizontal Display Enable End Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.06} Start Horizontal Retrace Pulse Register.
Cross reference with {6.05.07} End Horizontal Retrace Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.07.21} Horizontal PEL Panning Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.04} Mode Control Register 2.


<0>      Character Dot Clock Select
         --------------------------

         <=0>  Generate character clocks using 9 dot clocks.  This provides for
               separation between each character in a line of text by insertion
               of one extra pixel between characters in a horizontal direction.
               This pixel is normally given the background colour, so that the
               apparent width of each character is increased.  In this way, the
               character fonts can use the full 8 pixels width, without having
               to allow for separation between neighbouring characters.

               However, a problem can arise with the automatic insertion of an
               extra pixel, since some characters are used for giving graphics
               effects even though text mode is in use.  A graphics character
               is normally used for drawing boxes around text, such that lines
               representing the box are unbroken.  This does not work when the
               hardware inserts one extra pixel for every eight actually in the
               character font.  To overcome this problem, a special control bit
               can be set to ensure that any character in the ascii range from
               hex 'c0' to hex 'df' is treated so that the 8th pixel is copied
               into the 9th pixel, thereby creating continuous line graphics.

               See {6.07.18} Attribute Mode Control Register.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.

         <=1>  Generate character clocks using 8 dot clocks.  This results in
               all text mode generated characters being 8 dot clocks width. On
               the display, 8 pixels are available to represent the character,
               in each scan line belonging to the character.  When designing a
               character font for use with 8 pixel character width, it should
               be remembered that character separation will only occur if the
               font uses 7 of the 8 available pixels.  The remaining pixel is
               used to provide background colour to prevent characters merging.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.

         Packed pixel 256 colour mode halves the dot clock frequency through a
         rearrangement of the shift register structure, which shifts 4 bits at
         each clock using 2 dot clocks per 8 bit unit to represent 256 colours
         for display.

         See {6.06.07} Graphics Mode Register.


<1>      Reserved.  Always <=0>.
         -----------------------


<2>      Shift Load Two Control
         ----------------------

         <=0>  Reload the video shift registers on each character clock.  This
               assumes that the video memory can respond fast enough to permit
               safe operation at the frequency of the character clock.  With a
               contemporary design, this is not a problem.  This is the normal
               value for the bit.

               The ability to load more than one byte per character clock can
               assist with display image memory address extension schemes, by
               making certain of the low order address bits redundant.

               See {6.05.25} CRTC Mode Control Register.

               The loading of more than one shift register per character clock
               also has implications for shift register interconnection.  This
               is discussed elsewhere.

               See {6.06.07} Graphics Mode Register.

               Note this setting can be over-ridden by the setting of the Shift
               Load Four Control bit to <=1>.  See below.

         <=1>  Reload the video shift registers on every second character clock
               permitting use of slow image memory chips.  The reload accesses
               two memory locations in parallel;  the length of the video shift
               register is doubled.  This permits using a slower video memory
               than would otherwise be possible.

               The ability to load more than one byte per character clock can
               assist with display image memory address extension schemes, by
               making certain of the low order address bits redundant.

               See {6.05.25} CRTC Mode Control Register.

               The loading of more than one shift register per character clock
               also has implications for shift register interconnection.  This
               is discussed elsewhere.

               See {6.06.07} Graphics Mode Register.

               Note this setting can be over-ridden by the setting of the Shift
               Load Four Control bit to <=1>.  See below.


<3>      Dot Clock Divide by Two Enable
         ------------------------------

         <=0>  The normal dot clock frequency is available.  This means that a
               single pixel will be displayed for each dot clock period.  This
               is the normal setting for this bit.  It provides maximum image
               resolution on the display unit.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.

         <=1>  The dot clock frequency is divided by two.  In this manner, the
               quantity of image data available is reduced by two.  This means
               that the data from what would have been originally one pixel is
               now used to specify two pixels.  The result is a reduction in
               the image resolution to one half of the original value.  At the
               same time, any image will extend to twice the original size.
               Commonly used for low resolution text displays at 40 characters
               per line.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.


<4>      Shift Load Four Control
         -----------------------

         <=0>  Reload the video shift registers on each character clock.  This
               assumes that the video memory can respond fast enough to permit
               safe operation at the frequency of the character clock.  With a
               contemporary design, this is not a problem.  This is the normal
               value for the bit.

               The ability to load more than one byte per character clock can
               assist with display image memory address extension schemes, by
               making certain of the low order address bits redundant.

               See {6.05.25} CRTC Mode Control Register.

               The loading of more than one shift register per character clock
               also has implications for shift register interconnection.  This
               is discussed elsewhere.

               See {6.06.07} Graphics Mode Register.

               Note this setting can be over-ridden by the setting of the Shift
               Load Two Control bit to <=1>.  See above.

         <=1>  Reload the video shift registers on every fourth character clock
               permitting use of slow image memory chips.  The reload accesses
               four memory locations in parallel;  the width of the video shift
               register is quadrupled.  This permits a much slower video memory
               to be used than would otherwise be possible.  This feature does
               not find any use in contemporary designs unless used for address
               extension schemes.

               The ability to load more than one byte per character clock can
               assist with display image memory address extension schemes, by
               making certain of the low order address bits redundant.

               See {6.05.25} CRTC Mode Control Register.

               The loading of more than one shift register per character clock
               also has implications for shift register interconnection.  This
               is discussed elsewhere.

               See {6.06.07} Graphics Mode Register.

               Note this setting is dominant over the setting of the Shift Load
               Two Control bit.  See above.


<5>      Screen Inhibit
         --------------

         <=0>  The display screen operates normally.  The contents of the image
               memory are displayed as usual, depending on the specified modes
               of the VGA controller chip.

         <=1>  The display screen is blanked.  The image memory is not accessed
               for purposes of maintaining the display.  This means that there
               is full memory bandwidth available for processor access to image
               memory.  During this period, the display screen remains blanked.
               However the display remains synchronised with the VGA controller
               so that the display can be re-enabled at any time.

               This facility is sometimes used to update a complex image such
               that the update itself cannot be viewed as it occurs.  When the
               update is complete, the screen is re-enabled for normal use.
               Since image memory access is much faster than normal, an update
               made in this way can be completed in significantly less time.


<7..6>   Reserved.  Always <=00>.
         ------------------------


         Prior to any change to the Clocking Mode Register, the sequencer must
         be temporarily shut down.  This avoids corrupted timing generation in
         the VGA controller.

         See {6.04.02} Reset Register.

         The display generation mode is either text mode or graphic mode.

         See {6.06.08} Miscellaneous Register.




6.04.04  Map Mask Register               { 3c5h    02h    R/W }
=======  ======================================================


Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.06.02} Set/Reset Register.


<0>      Map Plane 0 Write Enable Control
         --------------------------------

         <=0>  Disable memory plane 0.  This prevents data being written to the
               image plane 0 by any processor write operation to image memory.
               Using this facility, plane 0 contents can be preserved across a
               write operation which updates some of the other memory planes.

         <=1>  Enable memory plane 0.  A processor write operation will be able
               to modify data stored in the image memory plane 0.  Unless there
               is at least one memory plane enabled, processor writes will not
               affect image memory in any way.

               Note when operating in Packed Pixel mode, all memory planes must
               be enabled.  See {6.04.06} Sequencer Memory Mode Register.


<1>      Map Plane 1 Write Enable Control
         --------------------------------

         <=0>  Disable memory plane 1.  This prevents data being written to the
               image plane 1 by any processor write operation to image memory.
               Using this facility, plane 1 contents can be preserved across a
               write operation which updates some of the other memory planes.

         <=1>  Enable memory plane 1.  A processor write operation will be able
               to modify data stored in the image memory plane 1.  Unless there
               is at least one memory plane enabled, processor writes will not
               affect image memory in any way.

               Note when operating in Packed Pixel mode, all memory planes must
               be enabled.  See {6.04.06} Sequencer Memory Mode Register.


<2>      Map Plane 2 Write Enable Control
         --------------------------------

         <=0>  Disable memory plane 2.  This prevents data being written to the
               image plane 2 by any processor write operation to image memory.
               Using this facility, plane 2 contents can be preserved across a
               write operation which updates some of the other memory planes.

         <=1>  Enable memory plane 2.  A processor write operation will be able
               to modify data stored in the image memory plane 2.  Unless there
               is at least one memory plane enabled, processor writes will not
               affect image memory in any way.

               Note when operating in Packed Pixel mode, all memory planes must
               be enabled.  See {6.04.06} Sequencer Memory Mode Register.


<3>      Map Plane 3 Write Enable Control
         --------------------------------

         <=0>  Disable memory plane 3.  This prevents data being written to the
               image plane 3 by any processor write operation to image memory.
               Using this facility, plane 3 contents can be preserved across a
               write operation which updates some of the other memory planes.

         <=1>  Enable memory plane 3.  A processor write operation will be able
               to modify data stored in the image memory plane 3.  Unless there
               is at least one memory plane enabled, processor writes will not
               affect image memory in any way.

               Note when operating in Packed Pixel mode, all memory planes must
               be enabled.  See {6.04.06} Sequencer Memory Mode Register.



<7..4>   Reserved.  Always <=0000>.




6.04.05  Character Map Select Register   { 3c5h    03h    R/W }
=======  ======================================================


Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.10.04} Mode Control Register 2.


<0>      Character Font Memory Map 'B' Partial Offset 16K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 16K byte


<1>      Character Font Memory Map 'B' Partial Offset 32K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 32K byte


<2>      Character Font Memory Map 'A' Partial Offset 16K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 16K byte


<3>      Character Font Memory Map 'A' Partial Offset 32K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 32K byte


<4>      Character Font Memory Map 'B' Partial Offset 08K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 08K byte


<5>      Character Font Memory Map 'A' Partial Offset 08K byte
         -----------------------------------------------------

         <=0>  Character Font Memory Map partial offset set to 00K byte
         <=1>  Character Font Memory Map partial offset set to 08K byte


<7..6>   Reserved.  Always <=00>.
         ------------------------


         Text mode results in character generation through hardware capability
         with the character fonts being brought into use.

         See {6.06.08} Miscellaneous Register.

         This register only becomes active when the Memory Size Specification
         indicates that more than 64K of image memory is present.

         See {6.04.06} Sequencer Memory Mode Register.

         When the fonts selected by the A and B maps are identical, there is a
         change made to the text mode attribute byte bit 3 interpretation.  In
         this situation, bit 3 specifies the foreground intensity.

         See {6.05.22} Underline Location Register.

         When the fonts are distinct, text mode attribute byte bit 3 selects
         which of the character fonts to use, either A, or B.  When the value
         of bit 3 is zero, font A is used.  Otherwise, font B is selected.

         See {6.05.22} Underline Location Register.

         There is the possibility to extend the character set selection with
         an extension to the addressing capability for a character font base
         address.

         See {6.10.04} Mode Control Register 2.

         For convenience, the bit patterns associated with the different font
         memory offsets are specified below.  They are identical for both A,B
         maps, but are shown in different sorted orders below for ease of use.

         Note that the hardware requires all character font data to reside in
         image memory plane 2.  This cannot be circumvented by software unless
         the hardware character generator is not used.  This situation results
         in a much slower text display than that obtainable with the hardware,
         but is essential for generation of text in graphics display modes.


<5|3|2>  Character Map Select A
         ----------------------

         <=000>  Select Character Map Memory offset 00K
         <=100>  Select Character Map Memory offset 08K
         <=001>  Select Character Map Memory offset 16K
         <=101>  Select Character Map Memory offset 24K
         <=010>  Select Character Map Memory offset 32K
         <=110>  Select Character Map Memory offset 40K
         <=011>  Select Character Map Memory offset 48K
         <=111>  Select Character Map Memory offset 56K


<4|1|0>  Character Map Select B
         ----------------------

         <=000>  Select Character Map Memory offset 00K
         <=001>  Select Character Map Memory offset 16K
         <=010>  Select Character Map Memory offset 32K
         <=011>  Select Character Map Memory offset 48K
         <=100>  Select Character Map Memory offset 08K
         <=101>  Select Character Map Memory offset 24K
         <=110>  Select Character Map Memory offset 40K
         <=111>  Select Character Map Memory offset 56K




6.04.06  Sequencer Memory Mode Register  { 3c5h    04h    R/W }
=======  ======================================================


Cross reference with {6.04.04} Map Mask Register.
Cross reference with {6.04.05} Character Map Select Register.
Cross reference with {6.06.02} Set/Reset Register.
Cross reference with {6.06.06} Read Map Select Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.05} Mode Control Register 1.


<0>      Reserved.  Always <=0>.
         -----------------------


<1>      Memory Size Specification
         -------------------------

         <=0>  Specifies that the total image memory installed is 64K bytes.
               This feature was used historically when image memory was very
               much more expensive than contemporary pricing.  The option is
               not used today.  When this setting is active, feature support
               for multiple character sets is inhibited.  In consequence the
               Character Map Select Register is disabled.

               See {6.04.05} Character Map Select Register.

         <=1>  Specifies that more than 64K bytes of image memory is available.
               This used to be 256K bytes in earlier design implementations but
               this value is likely to be too small now.  It is usual for image
               memory sizing to be 1024K bytes at the time of writing.  This is
               is the standard setting in use today.  With this setting active,
               the Character Map Select Register features become operative.  In
               addition, the display memory address counter higher order output
               bits become active, permitting use of a larger addressing range.

               See {6.04.05} Character Map Select Register.


<2>      Processor Image Memory Access Mode Select
         -----------------------------------------

         <=0>  Text Memory Access Mode.  This affects a data transfer from the
               processor to the image memory such that it is suitable for text
               mode operations.  The processor transfers 16 bits per access to
               image memory in text mode.  The data consists of a character in
               the current character set together with an attribute byte which
               exterts control over the character presentation on the display.

               For text mode display character codes occupy image memory plane
               zero with attribute data occupying plane one.  The image memory
               planes are paired (0,1) and (2,3).  The Text Memory Access Mode
               directs even address accesses to planes (0,2), with odd address
               accesses directed to planes (1,3).  In this way maximum ease of
               access is provided for textual data update.  This is sometimes
               termed odd/even mode.

               To use this mode effectively it is usual to disable writes to a
               pair of planes so permitting update to a two plane pair.

               See {6.04.04} Map Mask Register.

               Only processor writes to image memory are affected by this mode.
               That is, image memory organisation continues to be multiplane in
               all respects except as described above during write addressing.

               Processor Image Memory Access Mapping Select must be set to zero
               for this setting to be effective.  See below.

         <=1>  Graphics Memory Access Mode.  In graphics mode the image memory
               planes respond to addresses from the processor in parallel.  In
               this way, all four memory planes can be read or written using a
               single access.  The processor data transfer supports only 8 bit
               transfers, so various mechanisms are employed to map the 8 bits
               to each of the four bytes actually accessed.  In some cases, it
               is not necessary to perform any mapping of this type at all, as
               the processor is used only to generate an address which is then
               used internally for image manipulation.

               The manipulation is specified in advance and all that is needed
               is a stream of processor generated addresses to put the process
               into operation.  This type of operation is very fast to execute.
               It is discussed during the description of write mode 1.

               See {6.06.02} Set/Reset Register.

               Processor Image Memory Access Mapping Select must be set to zero
               for this setting to be effective.  See below.

               See {6.06.07} Graphics Mode Register.

         This is rather similar to the Memory Plane Pairing Control.
         See {6.06.08} Miscellaneous Register.


<3>      Processor Image Memory Access Mapping Select
         --------------------------------------------

         <=0>  The processor accesses all four image memory planes using a
               single access.  The access for write is modified for each of
               the memory planes by means of the Map Mask Register.  This
               permits multiple plane writes to take place, which is useful
               when graphics mode multi-plane operation is in effect.  Each
               memory plane contains all the information of a given colour.
               Using multi-plane writes gives the capability to selectively
               change more than one colour plane for each of eight pixels,
               using one memory access.  This makes for high speed updates.

               See the {6.04.04} Map Mask Register.

               The processor write accesses can be further determined with
               the Processor Image Memory Access Mode Select, when this is
               the selected setting.  See above.

               See {6.06.06} Read Map Select Register.

         <=1>  The processor accesses a single image memory plane during a
               single access.  This memory plane is identified by the two
               least significant bits of the memory address.  This provides
               a convenient means for access to image memory when packed
               pixel operation is in use.  Packed pixel images do not use
               multiple memory planes for colour definition.  Instead, each
               memory plane is accessed in turn, and the byte specifies the
               colour directly.  For this type of image, the processor need
               is for single byte access to successive image planes as this
               setting provides.  Of course only 16K bytes of each plane is
               accessible without changing the memory mapping in this mode.
               {Four planes with a 64K processor access window.}

               See {6.10.05} Mode Control Register 1.

               All effects of Processor Image Memory Access Mode Select, as
               specified above, are made null when this setting is active.

               See {6.06.06} Read Map Select Register.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




         A Synopsis of Display Image Memory Access Control
         =================================================


         Processor Image Memory Access Mapping Select
         =-------------------------------------------

              Processor Image Memory Access Mode Select
         =    =----------------------------------------

                   Processor Display Memory Addressing
         =    =    ===================================------------------


         0    0    Text access; odd/even mode; the low order address bit
                   selects the pair of planes to access.  Even addresses
                   select the pair (0,2) and odd addresses (1,3).

                   In all other respects the memory organisation remains
                   multiplane.

                   Data transfers are by word from the processor in this
                   memory mode, with a character code and attribute byte
                   sent together.  Memory planes 2,3 are write inhibited
                   to preserve the character font data in plane 2.

                   The Read Map Select field bit 0 is not used for this
                   memory mode.  The remaining bit 1 selects a plane in
                   the pair of planes determined by the access address,
                   for read mode 0.

                   See {6.06.06} Read Map Select Register.

         0    1    Multiplane access; the planes are written by using a
                   write mode and read using a read mode.  The plane is
                   selected by means of special registers used by these
                   read and write modes.  This organisation supports 16
                   colours, with 8 pixels per byte across 4 planes at a
                   single image memory byte address.

                   Data transfers are single byte from the processor in
                   this memory mode.

                   The Read Map Select field denotes the plane number to
                   be read by a read mode 0 access, in this memory mode.
                   Planes 0 through 3 are therefore accessible.

                   See {6.06.06} Read Map Select Register.


         1    0    The two low order address bits are the plane address;
                   the remaining address bits are shifted down to become
                   a byte address into multiplane memory.  This supports
                   256 colour packed pixel mode, where a byte represents
                   the colour data for a single pixel.

                   Data transfers are single byte from the processor in
                   this memory mode.

                   All two bits of the Read Map Select field are ignored
                   in this memory mode, for read mode 0 access.

                   See {6.06.06} Read Map Select Register.


         1    1    The two low order address bits are the plane address;
                   the remaining address bits are shifted down to become
                   a byte address into multiplane memory.  This supports
                   256 colour packed pixel mode, where a byte represents
                   the colour data for a single pixel.

                   Data transfers are single byte from the processor in
                   this memory mode, for read mode 0 access.

                   All two bits of the Read Map Select field are ignored
                   in this memory mode.

                   See {6.06.06} Read Map Select Register.


         ---------------------------------------------------------------




6.04.07  ................................{ 3c5h    07h    R/W }
6.04.07  Horizontal Character Counter Reset Register...........
=======  ======================================================


         This existance of this register is not formally recognised.
         It has only been discovered through reverse engineering the
         original VGA controller design.  For this reason, it cannot
         be guaranteed to exist in all clone chips.  The origin of
         this information is the Chips 82C456 chip documentation.


<7..0>   Horizontal Character Counter Reset
         ----------------------------------

         When any write operation occurs to this register, with data of any
         value, a special state is entered.  This state holds the horizontal
         character counter in a permanent reset, making it hold the value 0.

         A write to any sequencer register in the index range 0..6 will make
         the special reset state terminate.  Then the horizontal character
         counter is free to respond to character clocks as usual.

         The character row counter which counts all active display scan lines
         is clocked using a horizontal character counter derived signal.  If
         the character counter reset state is entered during the vertical
         retrace period, then releasing the reset state will permit display
         operation to recommence in a synchronised manner.

         The motivation for this functionality is that of synchronisation to
         an external event.  This affords the possibility of a display being
         synchronised to some event of interest, which might be the case for
         a system which photographs a display screen for example.  Since the
         functionality has never been officially documented, the use is made
         unsafe from a portability point of view across many VGA chips.




6.05  Register specifications: CRT Controller
====  =======================================


6.05.01  CRT Controller Address Register          { 3?4h    ---    R/W }
=======  ===============================================================


Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.09} CPU Latch Read Back Register.


<5..0>   CRT Controller Register Address
         -------------------------------

         Port 3?5h accesses the register pointed to by the index number in this
         bit field.  Index number zero is represented by <=000000>.

         The value of the hexadecimal digit '?' used in defining input output
         port addresses is either hex 'b' or hex 'd' depending upon the setting
         of the Miscellaneous Output Register Input Output Address Select bit.

         See {6.09.01} Miscellaneous Output Register.

         Note that bit <5> is normally set to zero, but can be used for access
         to registers normally used for manufacturing test.  These are special
         registers which are specific to the Trident 8900 chip.

         See {6.10.09} CPU Latch Read Back Register.


<7..6>   Reserved.  Always <=00>.
         ------------------------




6.05.02  Horizontal Total Register                { 3?5h    00h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.03} Horizontal Display Enable End Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.06} Start Horizontal Retrace Pulse Register.
Cross reference with {6.05.07} End Horizontal Retrace Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Horizontal Total
         ----------------

         This register specifies the total time required to enable a scan line
         to complete, and the next scan line to start, such that the positions
         are identical on successive scan lines.  This is equivalent to seeing
         scan line generation as a repetitive operation, and allowing a fixed
         amount of time for the production of a full scan line followed by the
         full retrace interval.  This register provides the means to tell when
         a new scan line period is about to start.  Character periods are the
         unit of measurement.

         Note that this is not the same as determining when a new scan line is
         about to start.  See below for details.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.
         See {6.04.03} Clocking Mode Register.

         Because the hardware is pipelined, the number actually appearing in
         this register is the total time in character periods, minus five.

         When the number actually actually appearing in this register matches
         the contents of the horizontal character counter, the preparations
         needed for reset of the latter register are put into effect.  After
         five more character clock periods, the reset takes place.  For this
         reason, the horizontal character counter will continue to count past
         the value determined in the Horizontal Total Register.  This implies
         that further value matches are possible before the counter is reset.
         In practice, the End Horizontal Blanking Register matches during the
         five character clock over-run period.  See below for details.

         Prior to the reset, border colour generation should have recommenced
         with the completion of the display blanking period.

         See {6.05.05} End Horizontal Blanking Register.
         See {6.07.19} Overscan Colour Register.

         The effect of the reset is that border colour generation is finished,
         and the display unit begins to display actual image data.



         Overview of relationship with other registers
         =============================================

         This register is used with the horizontal character counter, which is
         the master timing reference.  The values of this counter begin at zero
         and increase successively through the scan line.  When the counter is
         equal to the Horizontal Total, preparations are made for the counter
         to be reset back to zero.  After five further character clock periods
         this reset actually takes place.  All the horizontal timing is derived
         from values which match this counter as it increases from zero to the
         maximum value.  A scan line is commenced just before the counter is
         reset to zero, so there is a small offset between the display physical
         scan line position and the value of the horizontal character counter.

         By convention, when the horizontal character counter is reset to zero,
         the scan line begins to generate the display using image data.  Prior
         to that moment, border colour will be generated, without use of image
         data.  The display image will commence part way through the scan line
         so that there is an offset between actual counter values and the real
         position of the electron beam(s) forming the (colour) display image.

         To make this point clear, we give a value map which relates the value
         in the horizontal character counter to the activity of the display.

         The actual values given in hex are taken from the settings used by the
         bios, when video mode 10h is in effect.  These values are illustrative
         of the conceptual approach required when formulating register values.

         Please note that these values may have to be encoded before actually
         being used.  For example, some registers do not fully specify all the
         eight bits of the horizontal character counter.  Sometimes, a setting
         is split across two different registers.  The values given here are
         the functional values which do not take these coding conventions into
         account.  We mention this point to avoid possible confusion between
         functional values and their coded representation in registers.

         See {6.05.02} Horizontal Total Register. {This.}
         See {6.05.03} Horizontal Display Enable End Register.
         See {6.05.04} Start Horizontal Blanking Register.
         See {6.05.05} End Horizontal Blanking Register.
         See {6.05.06} Start Horizontal Retrace Pulse Register.
         See {6.05.07} End Horizontal Retrace Register.




 Hex     Register name     Corresponding Display Activity
 ===     =============     ==============================


 00      [Zero]

         ------------>     Horizontal Character Counter start.................
         ------------>     Border Colour end...............................  |
         ------------>     Image display start..............              |  |
                                                           |              |  |
                                                           |              |  |
 4f      {6.05.03} Horizontal Display Enable End Register  |              |  |
                                                           |              |  |
         ------------>     Image display end...............|              |  |
         ------------>     Border Colour start.................           |  |
                                                              |           |  |
                                                              |           |  |
 50      {6.05.04} Start Horizontal Blanking Register         |           |  |
                                                              |           |  |
         ------------>     Border Colour end..................|           |  |                                            |
         ------------>     Display blanked start........................  |  |
                                                                       |  |  |
                                                                       |  |  |
 54      {6.05.06} Start Horizontal Retrace Pulse Register             |  |  |
                                                                       |  |  |
         ------------>     Scan line end.............................  |  |  |
         ------------>     Horizontal Retrace start...............  |  |  |  |
                                                                 |  |  |  |  |
                                                                 |  |  |  |  |
 5f      {6.05.02} Horizontal Total Register - {A}               |  |  |  |  |
                                                                 |  |  |  |  |
         ------------>     Horizontal character                  |  |  |  |  |
         ------------>     counter prepared for                  |  |  |  |  |
         ------------>     reset to zero                         |  |  |  |  |
                                                                 |  |  |  |  |
                                                                 |  |  |  |  |
 61      {6.05.07} End Horizontal Retrace Register               |  |  |  |  |
                                                                 |  |  |  |  |
         ------------>     Horizontal Retrace end................|  |  |  |  |
         ------------>     Scan line start..........................|  |  |  |
                                                                       |  |  |
                                                                       |  |  |
 62      {6.05.05} End Horizontal Blanking Register                    |  |  |
                                                                       |  |  |
         ------------>     Display blanked end.........................|  |  |
         ------------>     Border Colour start............................|  |
                                                                             |
                                                                             |
         {6.05.02} Horizontal Total Register - {B}                           |
                                                                             |
 64      ------------>     Horizontal character                              |
         ------------>     counter is actually                               |
                           reset to zero.....................................|




6.05.03  Horizontal Display Enable End Register   { 3?5h    01h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Horizontal Display Enable
         -------------------------

         This register specifies the total time during which a single scan line
         will actually display image data. The character period is the unit for
         measurement.  This determines the length of a scan line in character
         periods.  This measure is independant of the means by which the image
         is generated.  It is therefore valid for text mode or graphics mode.
         See {6.05.02} Horizontal Total Register.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.
         See {6.04.03} Clocking Mode Register.

         Because the hardware represents this period by means of the horizontal
         character counter which starts the active display period with a value
         of zero, at the end of the active display period the counter will have
         a value equal to the display time in character periods, minus one.  It
         is that period value minus one which is programmed into this register.

         This register specifies the start of border colour generation.
         See {6.05.04} Start Horizontal Blanking Register.
         See {6.07.19} Overscan Colour Register.




6.05.04  Start Horizontal Blanking Register       { 3?5h    02h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.03} Horizontal Display Enable End Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Start Horizontal Blanking
         -------------------------

         This register specifies the value of the horizontal character counter
         when display blanking begins.  This measure is independant of the way
         in which the image is generated.  It is therefore valid for text mode
         or graphics mode.

         See {6.05.02} Horizontal Total Register.

         Before this point, border colour generation will have been started.

         See {6.05.03} Horizontal Display Enable End Register.
         See {6.07.19} Overscan Colour Register.

         This point determines the end of the border colour generation.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.

         See {6.04.03} Clocking Mode Register.




6.05.05  End Horizontal Blanking Register         { 3?5h    03h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.07} End Horizontal Retrace Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<4..0>   End Horizontal Blanking
         -----------------------

         This register specifies the value of the horizontal character counter
         when blanking finishes.  This measure is independant of the means by
         which the image is generated.  It is therefore valid for text mode or
         graphics mode.   The full register width is six bits, with the higher
         order bit stored elsewhere.

         See {6.05.07} End Horizontal Retrace Register.

         A discussion of vertical timing generation is available.

         See {6.05.02} Horizontal Total Register.

         This determines the start of the border colour generation.

         See {6.07.19} Overscan Colour Register.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.

         See {6.04.03} Clocking Mode Register.


<6..5>   Display Enable Skew
         -------------------

         <=00>  0 character clock delay
         <=01>  1 character clock delay
         <=10>  2 character clock delay
         <=11>  3 character clock delay

         This setting permits compensation for internal delays in the data path
         of the VGA controller, due to pipelining.


<7>      Light Pen Register Enable
         -------------------------

         This bit is Reserved for the Trident 8900 chip.
         This bit is used for test with the UM587 chip.
         The following is valid for the Chips 82C456 chip.

         <=0>  Enable Lightpen Registers
               -------------------------

               The CRTC Registers at indexes 10h, 11h, function as light pen
               location registers.  In this mode, the register assignments
               are as follows:

               10h:  Lightpen High Register.
                     -----------------------

                     Read only register representing the character position at
                     which the lightpen became active.  This portion specifies
                     the 8 high order bits.

                     Effective only in MDA/Hercules modes, or when enabled as
                     described above.  This facility is not used much today,
                     essentially because of unfavourable results which do not
                     compare well with other pointing devices.

                     See {6.05.18} Vertical Retrace Start Register.
                     See {6.10.04} Mode Control Register 2.

               11h:  Lightpen Low Register.
                     ----------------------

                     Read only register representing the character position at
                     which the lightpen became active.  This portion specifies
                     the 8 low order bits.

                     Effective only in MDA/Hercules modes, or when enabled as
                     described above.  This facility is not used much today,
                     essentially because of unfavourable results which do not
                     compare well with other pointing devices.

                     See {6.05.19} Vertical Retrace End Register.
                     See {6.10.04} Mode Control Register 2.

         <=1>  Normal Operation
               ----------------

               The CRTC Registers at indexes 10h, 11h, function as normal.

               See {6.05.18} Vertical Retrace Start Register.
               See {6.05.19} Vertical Retrace End Register.




6.05.06  Start Horizontal Retrace Pulse Register  { 3?5h    04h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.07} End Horizontal Retrace Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Start Horizontal Retrace Pulse
         ------------------------------

         This register specifies the value of the horizontal character counter
         when the horizontal retrace pulse starts.  This measure is independant
         of the means by which the image is generated.  It is therefore valid
         for text mode or graphics mode.

         This point determines where the scan line will end.  The display will
         have been blanked from a time before the horizontal retrace pulse was
         started, until some time after the horizontal retrace pulse finished.

         See {6.05.02} Horizontal Total Register.
         See {6.05.04} Start Horizontal Blanking Register.
         See {6.05.05} End Horizontal Blanking Register.
         See {6.05.07} End Horizontal Retrace Register.

         This register permits control of display screen horizontal centering.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.

         See {6.04.03} Clocking Mode Register.




6.05.07  End Horizontal Retrace Register          { 3?5h    05h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.06} Start Horizontal Retrace Pulse Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<4..0>   End Horizontal Retrace
         ----------------------

         This register specifies the value of the horizontal character counter
         when the horizontal retrace pulse ends.  This measure is independant
         of the means by which the image is generated.  It is therefore valid
         for text mode or graphics mode.

         This point determines when the scan line will start.  The display is
         blanked from a time before the horizontal retrace pulse was started,
         until some time after the horizontal retrace pulse was finished.

         See {6.05.02} Horizontal Total Register.
         See {6.05.04} Start Horizontal Blanking Register.
         See {6.05.05} End Horizontal Blanking Register.
         See {6.05.06} Start Horizontal Retrace Pulse Register.

         Note that the width of a character in text mode can be changed from
         8 pixels to 9 pixels which would change the apparent scan line time.

         See {6.04.03} Clocking Mode Register.


<6..5>   Horizontal Retrace Skew
         -----------------------

         <=00>  0 character clock delay
         <=01>  1 character clock delay
         <=10>  2 character clock delay
         <=11>  3 character clock delay

         This setting permits compensation for internal delays in the data path
         of the VGA controller, due to pipelining.


<7>      End Horizontal Blanking Bit 5
         -----------------------------

         This bit provides the most significant bit for this 6 bit register.

         See {6.05.05} End Horizontal Blanking Register.




6.05.08  Vertical Total Register                  { 3?5h    06h    R/W }
=======  ===============================================================


Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.20} Vertical Display Enable End Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.07} CRTC Module Testing Register.
Cross reference with {6.10.12} Clear Vertical Display Enable Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Vertical Total
         --------------

         This register specifies the lower eight bits of the ten bits effective
         width register, used to specify the total number of display image scan
         lines.  The two remaining high order bits are located elsewhere.

         See {6.05.09} CRT Controller Overflow Register.

         Because the hardware is pipelined, the number appearing in the ten bit
         wide register is the total scan line count minus two.

         When the number actually actually appearing in this extended register
         matches the contents of the character row counter, the preparations
         needed for reset of the latter register are put into effect.  After a
         further two scan line periods, the reset takes place.  For this reason
         the character row counter will continue to count past the value given
         by the extended Vertical Total Register.  This is pipelining at work.

         This register is used in conjunction with the character row counter.
         The character row counter is a principle timing reference, which gives
         control over all operations which are determined by the number of the
         current scan line being generated.  The character row counter changes
         at the end of each scan line which generates an active image display,
         to reflect the number of each scan line created.  This count operation
         can be changed on option, to count pairs of scan lines.  This option
         has the important property of changing the timing resolution of every
         aspect of vertical timing generation.

         See {6.05.25} CRTC Mode Control Register.




         Overview of relationship with other registers
         =============================================

         This register is used in conjunction with the character row counter,
         which is a principle timing reference.  This counter starts at zero
         and steadily increases as the display develops each new scan line.
         By convention, the value zero corresponds with the first scan line
         which actually develops displayable data for the frame.

         When the content of the Vertical Total register matches the character
         row counter, preparations are put into effect to reset the latter, to
         begin counting scan lines for a new frame.  Two scan lines later, the
         reset actually takes place.

         All the vertical timing is derived from values which match the counter
         as it increases from zero to the maximum value.  The value zero is by
         convention associated with the very first display image scan line in a
         frame.  This is not the same as the first scan line in a frame.  Prior
         to the display of this first image scan line the vertical retrace will
         have returned the notional position of the electron beams to the upper
         left of the display screen.

         Since this traversal across the screen would damage any image display
         if the electron beams were switched on, the vertical blanking period
         starts some time before, and extends to some time after, the vertical
         retrace period.  In this manner the electron beams are inhibited, so
         preserving the display with complete integrity.

         The character row counter controls the vertical blanking and retrace,
         before being reset to begin counting active image scan lines.  This is
         the reason why the physical display unit scan line does not correspond
         directly with the scan line in the character row counter.  There is a
         small offset between the two, such that when the character row counter
         is reset to zero, the display unit has already displayed some overscan
         lines immediately following the vertical retrace period.

         The active image display extends from scan line zero upto the maximum
         scan line specified by the Vertical Display Enable End Register.  The
         overscan colour is generated from this point onwards, until the onset
         of the vertical blanking period.  The vertical retrace period activity
         then takes place during vertical blanking.  When the vertical blanking
         period finishes, overscan colour is again produced, but this occurs at
         the top of the display, since retrace has occured.

         To make these points clear we give a value map which relates the value
         in the character row counter to the activity of the display.

         The actual values given in hex are taken from the settings used by the
         bios, when video mode 10h is in effect.  These values are illustrative
         of the conceptual approach required when formulating register values.

         Please note that these values may have to be encoded before actually
         being used.  For example some registers do not fully specify all the
         ten bits of the character row counter.  Sometimes, a setting appears
         split across two different registers.  The values here are functional
         values which do not take these coding conventions into account.  This
         point is mentioned to avoid possible confusion between the functional
         values and their coded representation in registers.

         See {6.05.08} Vertical Total Register. {This.}
         See {6.05.18} Vertical Retrace Start Register.
         See {6.05.19} Vertical Retrace End Register.
         See {6.05.20} Vertical Display Enable End Register.
         See {6.05.23} Start Vertical Blanking Register.
         See {6.05.24} End Vertical Blanking Register.
         See {6.05.26} Line Compare Register.




 Hex     Register name     Corresponding Display Activity
 ===     =============     ==============================


 00      [Zero]

         ------------>     Character Row Counter start........................
         ------------>     Overscan Colour end.............................  |
         ------------>     First image scan line start......              |  |
                                                           |              |  |
                                                           |              |  |
 ??      {6.05.26} Line Compare Register                   |              |  |
                                                           |              |  |
         ------------>     Start address of display        |              |  |
         ------------>     is reset to zero.  Makes        |              |  |
         ------------>     a new window in which it        |              |  |
         ------------>     is possible to completely       |              |  |
         ------------>     inhibit display panning.        |              |  |
                                                           |              |  |
                                                           |              |  |
15d      {6.05.20} Vertical Display Enable End Register    |              |  |
                                                           |              |  |
         ------------>     Last image scan line end........|              |  |
         ------------>     Overscan Colour start...............           |  |
                                                              |           |  |
                                                              |           |  |
163      {6.05.23} Start Vertical Blanking Register           |           |  |
                                                              |           |  |
         ------------>     Overscan Colour end................|           |  |                                            |
         ------------>     Display blanked start.....................     |  |
                                                                    |     |  |
                                                                    |     |  |
183      {6.05.18} Vertical Retrace Start Register                  |     |  |
                                                                    |     |  |
         ------------>     Vertical Retrace start.................  |     |  |
                                                                 |  |     |  |
                                                                 |  |     |  |
185      {6.05.19} Vertical Retrace End Register                 |  |     |  |
                                                                 |  |     |  |
         ------------>     Vertical Retrace end..................|  |     |  |
                                                                    |     |  |
                                                                    |     |  |
1ba      {6.05.24} End Vertical Blanking Register                   |     |  |
                                                                    |     |  |
         ------------>     Display blanked end......................|     |  |
         ------------>     Overscan Colour start..........................|  |
                                                                             |
                                                                             |
1bf      {6.05.08} Vertical Total Register - {A}                             |
                                                                             |
         ------------>     Character row counter                             |
         ------------>     prepared for reset to                             |
         ------------>     zero                                              |
                                                                             |
                                                                             |
         {6.05.08} Vertical Total Register - {B}                             |
                                                                             |
1c1      ------------>     Character row counter is                          |
         ------------>     actually reset to zero............................|




6.05.09  CRT Controller Overflow Register         { 3?5h    07h    R/W }
=======  ===============================================================


Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.20} Vertical Display Enable End Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register provides for the high order bits needed to complete some
         wide internal registers of greater than eight bits total width.  This
         is necessary since the processor input output port transfer capability
         supports only eight bit transfers.

         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<0>      Vertical Total Bit 8
         --------------------
         See {6.05.08} Vertical Total Register.


<1>      Vertical Display Enable End Bit 8
         ---------------------------------
         See {6.05.20} Vertical Display Enable End Register.


<2>      Vertical Retrace Start Bit 8
         ----------------------------
         See {6.05.18} Vertical Retrace Start Register.


<3>      Start Vertical Blank Bit 8
         --------------------------
         See {6.05.23} Start Vertical Blanking Register.

         The highest bit of the ten bit Start Vertical Blank Register is found
         in the Maximum Scan Line Register.

         See {6.05.11} Maximum Scan Line Register.


<4>      Line Compare Bit 8
         ------------------
         See {6.05.26} Line Compare Register.

         The highest bit of the ten bit Line Compare Register is located in the
         Maximum Scan Line Register.

         See {6.05.11} Maximum Scan Line Register.


<5>      Vertical Total Bit 9
         --------------------
         See {6.05.08} Vertical Total Register.


<6>      Vertical Display Enable End Bit 9
         ---------------------------------
         See {6.05.20} Vertical Display Enable End Register.


<7>      Vertical Retrace Start Bit 9
         ----------------------------
         See {6.05.18} Vertical Retrace Start Register.




6.05.10  Preset Row Scan Register                 { 3?5h    08h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.21} Offset Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.07.21} Horizontal PEL Panning Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


<4..0>   Preset Row Scan
         ---------------

         This binary value determines the notional scan line within a character
         font, immediately after a vertical retrace has arrived at the display.
         When the display is operating in text mode, this value is used to give
         the correct position on the display for the first line of text.  Later
         lines of text have their position on the display controlled relative
         to the preceeding lines, using the controls provided for this purpose.

         See {6.05.11} Maximum Scan Line Register.

         This capability provides for the smooth vertical scrolling of lines of
         text.  During the generation of the first line of text on the display,
         some of the uppermost scan lines of a character font can be inhibited
         by use of this facility.  When successively more of the first line of
         text is ommitted in this manner, the result will give the visual idea
         that the whole screen of text is slowly being scrolled upwards.

         To make this situation more concrete, we will look at how a character
         display is generated by the VGA controller when text mode is in use.

         A character font contains 256 characters, each of which is 8 pixels in
         width, with 32 scan lines depth.  This means that 32 bytes, each of 8
         bits, will represent one character completely.  However most character
         fonts do not require the full 32 pixel by 8 pixel format.  In order to
         display all the 32 rows of 8 pixels, it is necessary to arrange that a
         conversion of each character code in a line of text takes place using
         the appropriate 8 consecutive pixels during each scan line.  This scan
         line indexing into the 32 byte array of pixel data representing a font
         can be performed by means of a special scan line counter reserved just
         for character generation purposes.

         If this is done, it is then necessary to decide how to initialise the
         scan line counter after a vertical retrace occurs.  During character
         generation, we must know the maximum value of scan line which is part
         of the character font in current use.  This permits any depth of font
         to be used even though the storage format provided by the hardware is
         standardised at 32 rows by 8 columns.  The maximum scan line used for
         text font generation is specified by the Maximum Scan Line Register.

         See {6.05.11} Maximum Scan Line Register.


<6..5>   Byte Panning Control
         --------------------

         The value of this bit field determines byte panning in text mode.  The
         effect is to shift the displayed image left by the specified number of
         eight or nine pixel groups.  The selection of eight or nine dot clocks
         is performed by the Clocking Mode Register, which directly determines
         the maximum number of pixels controlled for panning purposes.  The pan
         takes effect by shifting the screen image successively to the left of
         the screen, with increasing binary panning control values.

         See {6.04.03} Clocking Mode Register.

         This panning capability is fully complementary with the pixel panning
         control available using the Horizontal PEL Panning Register.

         See {6.07.21} Horizontal PEL Panning Register.

         Note that in graphics modes employing 256 colour packed pixel format,
         the Byte Panning Control and the Horizontal PEL Panning Register must
         not be used.  Instead, use the image start address to obtain a single
         pixel pan effect.  Where this technique is used the screen width must
         be increased by use of the Offset Register, so that panning does not
         cause the data from a scan line to become part of the following scan
         line.  This is the same as saying that panning can only modify a view
         to the extent that the view remains within a displayable image stored
         within the video memory.  See below for discussion.

         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.
         See {6.05.21} Offset Register.
         See {6.10.07} CRTC Module Testing Register.




         Essential Display Panning Concepts
         ==================================

         In order to understand panning, it is necessary to understand the big
         difference in display image generation when in text mode as opposed to
         graphics mode.  This difference is absolutely fundamental, and arises
         because of the distinctions between the ways in which the information
         which comprises the displayed image is stored in image memory.

         In text mode, the image memory holds character codes and attributes,
         which, when combined together with font definitions for a character
         set, enable the VGA controller to generate characters to the display.

         Each character is represented by either 8 or 9 pixels in each of the
         scan lines in which it appears, depending upon the specified dot clock
         selection made by the Clocking Mode Register.

         See {6.04.03} Clocking Mode Register.

         If the pixels appearing at the extreme left of the display are removed
         from the display, then the result gives the impression of the complete
         screen image having been panned left.  This function is controlled by
         the Horizontal PEL Panning Register, which takes values dependant upon
         the maximum pan required, either 8 or 9 pixels:

             1.  8 pixel pan, binary value specifies left pan movement, with
                 number zero representing a pan of left zero positions.  The
                 pan magnitude is taken modulo 8 as in:

                 left_pan = (number_field + 0) mod 8

                 The pan range is therefore 0 .. 7 pixels.

             2.  9 pixel pan, binary value specifies a left pan movement of the
                 value plus one, with number 8 representing a left pan movement
                 of zero positions.  The pan magnitude is taken modulo 9 with
                 an offset of one as in:

                 left_pan = (number_field + 1) mod 9

                 The pan range is therefore 0 .. 8 pixels.

         Once the limit of pixel panning is reached, it is necessary to change
         the data used to generate the display.  This is where byte panning is
         used.  To achieve a smooth panning effect, the pixel panning register
         is gradually increased to the maximum, then changed to zero, whilst
         simultaneously increasing byte panning.  This enables panning to take
         place smoothly across large portions of the displayed image.

         In graphics mode there are two separate image generation methods used.

         Multi-plane graphics images are produced by reading the image memory
         planes using a single address, which yields four parallel bytes, one
         each from each memory plane.  These bytes together represent eight of
         the pixels for display.  By interpreting the same numbered bit in all
         these four bytes at the same time, it is possible to produce a coding
         for 16 separate colours.  In this way, the four bytes are shifted out
         to the display in parallel, so defining the colour of each successive
         pixel in the display image as one of a possible 16 distinct colours.

         For this type of image, the Horizontal PEL Panning Register operates
         exactly as described above, except that there is no 9 dot clock used.
         {This is only for use in text modes.}

         In packed pixel mode, graphics images are produced in a different way.
         There are actually three different types of packed pixel mode.  These
         are:

             1.  Colour 2 Packed Pixel Mode.    {Uses 1 bit per pixel.}
             2.  Colour 4 Packed Pixel Mode.    {Uses 2 bits per pixel.}
             3.  Colour 256 Packed Pixel Mode.  {Uses 8 bits per pixel.}

         For the Colour 2 Packed Pixel Mode, the image consists of individual
         pixels represented directly by the bits in a byte, thus the high order
         bit represents the leftmost pixel colour, foreground or background.

         This type of image is easily panned, exactly as described above for
         the 8 dot clock selection.

         The Colour 256 Packed Pixel Mode represents a single pixel colour in
         one complete byte of image memory.  In this case the bit shifting of
         the Horizontal PEL Panning Register is superfluous together with the
         Byte Panning Control.  Instead, the starting address of the display
         should be used to give pixel panning in both the horizontal and the
         vertical directions.

         Colour 4 Packed Pixel Mode uses the image memory planes in a modified
         multi-plane mode, which uses two of the four planes to specify one of
         four possible colour selections for each pixel.  Neighbouring memory
         planes are used, either planes (0,1) or (2,3).  In this situation the
         full Horizontal PEL Panning Register capability is used.  Only the 8
         dot clock selection is applicable.

         A facility is available which affords the possibility of creating two
         separate windows within a single screen display.  This has an impact
         on some aspects of pixel panning.

         The two windows are distinguished in that the first always specifies
         a non-zero starting address into the image memory, and is subject to
         panning control.  The second window always begins at a display image
         memory address of zero, and may either be panned in the same manner
         as the first window, or alternatively may be made immune to panning,
         as determined by option setting.

         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.
         See {6.07.18} Attribute Mode Control Register.

         The scan line where the first window ends and where the second lower
         window starts is determined by the Line Compare Register.

         See {6.05.26} Line Compare Register.

         The control governing the second window which determines whether it
         responds to panning specified for the first upper window is applied
         by the Attribute Mode Control Register.

         See {6.07.18} Attribute Mode Control Register.

         A discussion of pixel panning is available.

         See {6.07.21} Horizontal PEL Panning Register.


<7>      Reserved.  Always <=0>.
         -----------------------




6.05.11  Maximum Scan Line Register               { 3?5h    09h    R/W }
=======  ===============================================================


Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         A single bit <7> only is affected.  {Double Scan Line Display.}

         See {6.10.07} CRTC Module Testing Register.


<4..0>   Maximum Scan Lines
         ------------------

         The binary value of this field determines the highest scan line to be
         used in generating characters from any currently selected font.  This
         binary value matches an internal scan line counter which commences at
         zero, so to permit generation of characters with 14 scan lines, the
         value 13 would be programmed into this field.  This internal counter
         keeps track of the scan line for character generation, so is separate
         from the character row counter that counts scan lines in the display.
         The internal counter is reset to zero when it has a value equal to the
         Maximum Scan Lines field.  It therefore continually cycles through all
         values from zero to the maximum.

         The effect of this field is to decide when it is necessary to commence
         reading the data in image memory associated with the following line of
         text.  Until that time, each line of text is repeatedly read and sent
         to the character generator logic, once for each scan line in the font
         being used.  In this manner, all the scan lines are built up and sent
         to the display to represent the image of one complete line of text.


<5>      Start Vertical Blank Bit 9
         --------------------------

         This bit represents bit 9 of the 10 bit wide representation for the
         Start Vertical Blank value.

         See {6.05.09} CRT Controller Overflow Register.
         See {6.05.23} Start Vertical Blanking Register.


<6>      Line Compare Bit 9
         ------------------

         This bit represents bit 9 of the 10 bit wide representation for the
         Line Compare Register value.

         See {6.05.09} CRT Controller Overflow Register.
         See {6.05.26} Line Compare Register.


<7>      Double Scan Line Display
         ------------------------

         <=0>  Each scan line is displayed once only.  This represents the
               normal operational value.

         <=1>  Each scan line is displayed twice so increasing the depth of the
               display by a factor of two despite using the same amount of data
               needed to specify only half the number of scan lines. This is a
               compatibility feature used for low resolution display emulation.

               The pixel aspect ratio doubles when using this setting.

               This capability advances the display memory address counter to
               the next scan line in image memory only every second scan line,
               so data is repeated exactly twice during successive scan lines.
               This means the display memory address counter is actually reset
               after the first scan line of every pair, so that the same data
               can be output during the second scan line of the pair.

               Warning: do not confuse this capability with that provided by
               the Horizontal Retrace Divisor.

               See {6.05.25} CRTC Mode Control Register.




6.05.12  Cursor Start Register                    { 3?5h    0ah    R/W }
=======  ===============================================================


Cross reference with {6.05.13} Cursor End Register.
Cross reference with {6.05.16} Cursor Location High Register.
Cross reference with {6.05.17} Cursor Location Low Register.


<4..0>   Cursor Row Scan Start
         ---------------------

         This binary field represents the first scan line used to present the
         cursor when in text mode.  The very first scan line is numbered zero,
         corresponding with the first scan line in the character font used to
         produce the text.  It is therefore not a scan line relative to the
         start of the frame being displayed.

         The displayed cursor will extend from this value, through to the value
         specified in the Cursor Row Scan End field.

         The hardware generated cursor is only active in text mode.

         See {6.05.13} Cursor End Register.
         See {6.05.16} Cursor Location High Register.
         See {6.05.17} Cursor Location Low Register.


<5>      Cursor Enable
         -------------

         <=0>  Text mode hardware cursor is displayed.  Cursor on.
         <=1>  Text mode hardware cursor is inhibited.  Cursor off.


<7..6>   Reserved.  Always <=00>.
         ------------------------




6.05.13  Cursor End Register                      { 3?5h    0bh    R/W }
=======  ===============================================================


Cross reference with {6.05.12} Cursor Start Register.
Cross reference with {6.05.16} Cursor Location High Register.
Cross reference with {6.05.17} Cursor Location Low Register.


<4..0>   Cursor Row Scan End
         -------------------

         This binary field represents the first scan line used to present the
         cursor when in text mode.  The very first scan line is numbered zero,
         corresponding with the first scan line in the character font used to
         produce the text.  It is therefore not a scan line relative to the
         start of the frame being displayed.

         The displayed cursor will extend from the value specified in the field
         Cursor Row Scan End, through to this value, inclusive.

         The hardware generated cursor is only active in text mode.

         See {6.05.12} Cursor Start Register.
         See {6.05.16} Cursor Location High Register.
         See {6.05.17} Cursor Location Low Register.


<6..5>   Cursor Skew Control
         -------------------

         This binary field specifies the amount of right skew applied to the
         cursor, when it is visible.  In this way, it is possible to displace
         the cursor to the right of the character where it would normally be
         produced.  This feature can sometimes be of benefit when very small
         characters are produced during high resolution screen operation.

         It should be used with care, however, since visual disorientation
         can result from over-use of the higher displacement values.

         The main motivation for this control is to compensate for internal
         pipeline delays in the VGA controller.

         See {6.05.16} Cursor Location High Register.
         See {6.05.17} Cursor Location Low Register.


<7>      Reserved.  Always <=0>.
         -----------------------




6.05.14  Start Address High Register              { 3?5h    0ch    R/W }
=======  ===============================================================


Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.21} Offset Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.05} Mode Control Register 1.
Cross reference with {6.10.07} CRTC Module Testing Register.


<7..0>   Start Address High
         ------------------

         This binary value represents 8 of the possible 16 to 17 display start
         address bits.  The display generation uses this address to determine
         where to commence reading image memory.  This address corresponds to
         the upper left of the display screen.

         In the following display modes, addresses wrap as indicated:
         Colour Graphics Adapter    ==>   16K or 14 bits wide addressing.
         Monochrome Display Adapter ==>   32K or 15 bits wide addressing.
         Hercules mode              ==>   64K or 16 bits wide addressing.

         See {6.10.04} Mode Control Register 2.

         There may be some address alignment implications, depending upon the
         way in which memory addresses are used during the display generation
         process.

         See {6.05.22} Underline Location Register.
         See {6.05.25} CRTC Mode Control Register.

         The lower bits <7..0> are found in the Start Address Low Register.

         See {6.05.15} Start Address Low Register.

         The upper bit <16> is a switchable option.  Assume a maximum image
         size of 1024K arranged in four planes of 256K; it is possible with
         17 bits of start address to specify upto 128K of offset into image
         memory.  This is adequate to support two separate display pages.

         See {6.10.07} CRTC Module Testing Register.

         There is also a start address bit <19> available for configurations
         with more than 512K of image memory.  This bit defines which memory
         bank is to be used for display purposes, so is quite distinct from
         that accessible to the processor.  The display hardware is not able
         to address images larger than 512K unless 1024x768 256 colour mode
         is used.  For display images smaller than 512K, bit <19> is useful.

         See {6.10.05} Mode Control Register 1.

         During display operation, there is potential to reset the display
         image current address to zero, coincidently with the commencement
         of a new display scan line.  This facility is useful for providing
         two separate window areas on the display screen.  The first window
         possesses a start address which is greater than zero, and displays
         for the required number of scan lines.  Then, at a scan line given
         by the Line Compare Register, the current display address is reset
         to zero, thereby displaying the second window.

         See {6.05.26} Line Compare Register.

         This second window has the useful property that it can be protected
         from panning.  This means that during panning operations affecting
         the upper window, the lower window will either pan in the same way,
         or remain completely unchanged depending upon an option bit setting.

         See {6.07.18} Attribute Mode Control Register.




6.05.15  Start Address Low Register               { 3?5h    0dh    R/W }
=======  ===============================================================


Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.21} Offset Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.05} Mode Control Register 1.
Cross reference with {6.10.07} CRTC Module Testing Register.


<7..0>   Start Address Low
         -----------------

         This binary value represents 8 of the possible 16 to 17 display start
         address bits.  The display generation uses this address to determine
         where to commence reading image memory.  This address corresponds to
         the upper left of the display screen.

         In the following display modes, addresses wrap as indicated:
         Colour Graphics Adapter    ==>   16K or 14 bits wide addressing.
         Monochrome Display Adapter ==>   32K or 15 bits wide addressing.
         Hercules mode              ==>   64K or 16 bits wide addressing.

         See {6.10.04} Mode Control Register 2.

         There may be some address alignment implications, depending upon the
         way in which memory addresses are used during the display generation
         process.

         See {6.05.22} Underline Location Register.
         See {6.05.25} CRTC Mode Control Register.

         The upper bits <15..8> are found in the Start Address High Register.

         See {6.05.14} Start Address High Register.

         The upper bit <16> is a switchable option.  Assume a maximum image
         size of 1024K arranged in four planes of 256K; it is possible with
         17 bits of start address to specify upto 128K of offset into image
         memory.  This is adequate to support two separate display pages.

         See {6.10.07} CRTC Module Testing Register.

         There is also a start address bit <17> available for configurations
         with more than 512K of image memory.  This bit defines which memory
         bank is to be used for display purposes, so is quite distinct from
         that accessible to the processor.  The display hardware is not able
         to address images larger than 512K unless 1024x768 256 colour mode
         is used.  For display images smaller than 512K, bit <17> is useful.

         See {6.10.05} Mode Control Register 1.

         During display operation, there is potential to reset the display
         image current address to zero, coincidently with the commencement
         of a new display scan line.  This facility is useful for providing
         two separate window areas on the display screen.  The first window
         possesses a start address which is greater than zero, and displays
         for the required number of scan lines.  Then, at a scan line given
         by the Line Compare Register, the current display address is reset
         to zero, thereby displaying the second window.

         See {6.05.26} Line Compare Register.

         This second window has the useful property that it can be protected
         from panning.  This means that during panning operations affecting
         the upper window, the lower window will either pan in the same way,
         or remain completely unchanged depending upon an option bit setting.

         See {6.07.18} Attribute Mode Control Register.




6.05.16  Cursor Location High Register            { 3?5h    0eh    R/W }
=======  ===============================================================


Cross reference with {6.05.12} Cursor Start Register.
Cross reference with {6.05.13} Cursor End Register.
Cross reference with {6.05.17} Cursor Location Low Register.
Cross reference with {6.10.04} Mode Control Register 2.


<7..0>   Cursor Location High
         --------------------

         This binary value represents an image memory address.  As the display
         is created, image data is read from image memory.  When this address
         is accessed in order to create the display, the cursor will be placed
         to coincide with the corresponding character position on the screen,
         subject only to any applied cursor right skew.

         A hardware cursor is only generated in text mode.

         See {6.05.12} Cursor Start Register.
         See {6.05.13} Cursor End Register.
         See {6.05.17} Cursor Location Low Register.

         In the following display modes, addresses wrap as indicated:
         Colour Graphics Adapter    ==>   16K or 14 bits wide addressing.
         Monochrome Display Adapter ==>   32K or 15 bits wide addressing.
         Hercules mode              ==>   64K or 16 bits wide addressing.

         See {6.10.04} Mode Control Register 2.




6.05.17  Cursor Location Low Register             { 3?5h    0fh    R/W }
=======  ===============================================================


Cross reference with {6.05.12} Cursor Start Register.
Cross reference with {6.05.13} Cursor End Register.
Cross reference with {6.05.16} Cursor Location High Register.
Cross reference with {6.10.04} Mode Control Register 2.


<7..0>   Cursor Location Low
         -------------------

         This binary value represents an image memory address.  As the display
         is created, image data is read from image memory.  When this address
         is accessed in order to create the display, the cursor will be placed
         to coincide with the corresponding character position on the screen,
         subject only to any applied cursor right skew.

         A hardware cursor is only generated in text mode.

         See {6.05.12} Cursor Start Register.
         See {6.05.13} Cursor End Register.
         See {6.05.16} Cursor Location High Register.

         In the following display modes, addresses wrap as indicated:
         Colour Graphics Adapter    ==>   16K or 14 bits wide addressing.
         Monochrome Display Adapter ==>   32K or 15 bits wide addressing.
         Hercules mode              ==>   64K or 16 bits wide addressing.

         See {6.10.04} Mode Control Register 2.




6.05.18  Vertical Retrace Start Register          { 3?5h    10h    R/W }
=======  ===============================================================


Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Vertical Retrace Start
         ----------------------

         This binary value represents the 8 lower bits of the 10 bit wide
         Vertical Retrace Start Register.  This register is compared with
         the character row counter which therefore matches when a certain
         scan line is displayed.  The upper bits are stored elsewhere.

         See {6.05.09} CRT Controller Overflow Register.

         When the match occurs, the vertical retrace period begins.  This
         generates the vertical retrace signal to the display unit, which
         then commences the return of the electron beam scanning position
         to the upper left of the display screen.  The vertical retrace
         period continues until the character row counter is of identical
         value with that in the Vertical Retrace End Register.

         See {6.05.19} Vertical Retrace End Register.

         At the time the vertical retrace commences, the vertical blanking
         period will already have begun.  This is so that the retrace will
         not disturb the image present on the screen.  Vertical blanking
         continues until after the vertical retrace period has ended.

         See {6.05.23} Start Vertical Blanking Register.
         See {6.05.24} End Vertical Blanking Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.

         A detailed discussion of vertical timing issues is available with
         a timing diagram.

         See {6.05.08} Vertical Total Register.

         The following is not true for the Trident 8900 chip.
         The following is valid for the Chips 82C456 chip.

         The Vertical Retrace Start Register can be made invisible at this
         index address, when the Lightpen High Register is placed at this
         same register index.
         For details see the Light Pen Register Enable description.

         See {6.05.05} End Horizontal Blanking Register.




6.05.19  Vertical Retrace End Register            { 3?5h    11h    R/W }
=======  ===============================================================


Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.09.03} Input Status Register Zero.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<3..0>   Vertical Retrace End
         --------------------

         This binary value represents the 4 lower bits of the 10 bit wide
         character row counter.  The character row counter determines the
         current scan line being generated for the display.  When a match
         occurs in these lower four bits, the vertical retrace period end
         is signalled.  The comparison between these low bits only starts
         when the vertical retrace period has commenced, consequently the
         possibility of an ambiguous match cannot occur.  This coding has
         the property of limiting the maximum period to 15 scan lines.

         See {6.05.18} Vertical Retrace Start Register.

         At the time the vertical retrace commences, the vertical blanking
         period will already have begun.  This is so that the retrace will
         not disturb the image present on the screen.  Vertical blanking
         continues until after the vertical retrace period has ended.

         See {6.05.23} Start Vertical Blanking Register.
         See {6.05.24} End Vertical Blanking Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.

         A detailed discussion of vertical timing issues is available with
         a timing diagram.

         See {6.05.08} Vertical Total Register.


<4>      Clear Vertical Interrupt
         ------------------------

         This bit is cleared by hardware RESET.

         <=0>  Clear the vertical interrupt state.
         <=1>  Normal vertical interrupt state operation.

         This interrupt status is obtainable from a status bit provided for
         just this purpose.  It can be useful when interrupts are inhibited
         yet it is still necessary to obtain vertical timing information.

         See {6.09.03} Input Status Register Zero.


<5>      Enable Vertical Interrupt
         -------------------------

         This bit is cleared by hardware RESET.

         <=0>  Enable the vertical interrupt {assigned by hardware to IRQ2}.
               This will only occur if the programmable interrupt controller
               8259 was initialised appropriately, since all interrupts must
               first be routed through this chip before being serviced by an
               interrupt program in the processor.

         <=1>  Disable the vertical interrupt.

         This interrupt status is obtainable from a status bit provided for
         just this purpose.  It can be useful when interrupts are inhibited
         yet it is still necessary to obtain vertical timing information.

         See {6.09.03} Input Status Register Zero.


<6>      Refresh Bandwidth Select
         ------------------------

         <=0>  Generate 3 image memory refresh cycles per horizontal scan
               line.  These refresh cycles prevent data stored in dynamic
               RAM {random access memory} chips from being lost.

         <=1>  Generate 5 image memory refresh cycles per horizontal scan
               line.  If more refresh cycles are needed to keep the image
               memory intact, less time is available for processor access.

         This field is sometimes termed CPU Bandwidth Select, for reasons
         which will become apparent below.

         Small image memories require lower numbers of refresh periods than
         do larger memories with more data to refresh.

         The greater the refresh activity, the less opportunity there is to
         access the memory for processor reads and writes.  With high image
         resolution displays the issue of processor access to image memory
         can become critical in determining the display update speed.

         The processor can make a request to access image memory, which then
         cannot be granted immediately as all display activity has priority.
         A relatively long access delay can then ensue until the access is
         finally granted.  Although the delay is measured in microseconds,
         this still represents a significant delay for fast processors which
         could have executed possibly many instructions during this period.

         A memory can be either read, written or refreshed at any one time.
         The sequencer determines the moment by moment activity for all the
         image display RAM chips, thereby ensuring that the maximum use is
         made of image memory capability at all times.

         Bandwidth is a hardware term which is concerned with describing a
         rate at which information is transferred, or at which an activity
         is, or can be, performed.  Typically, bandwidth is measured using
         a number which represents the count of things taking place over a
         fixed time period, usually one second.  Because this measure is
         identical with the measure of frequency, the unit of bandwidth is
         the Hertz, or Hz.  Display memory bandwidth therefore describes
         the number of units of data which can be transferred into or out
         of the display memory, in one second.  It provides a broad measure
         of display unit capability.  However, like all broad measures, it
         should not be taken too seriously.


<7>      CRTC Register Protect
         ---------------------

         This bit is cleared by hardware RESET.

         <=0>  Enable writes to CRTC Registers at indexes 0 .. 7.
         <=1>  Disable writes to CRTC Registers at indexes 0 .. 7.


         The ability to protect certain important register groups can assist
         with emulation, by preventing programs from changing critical data.

         Typical use allows direct register writes from software, by keeping
         registers which cannot be changed intact, whilst permitting others
         to be modified.  This is an emulation issue only, so is of little
         importance for new software architecture implementations.


         See {6.05.02} Horizontal Total Register.                 {0}
         See {6.05.03} Horizontal Display Enable End Register.    {1}
         See {6.05.04} Start Horizontal Blanking Register.        {2}
         See {6.05.05} End Horizontal Blanking Register.          {3}
         See {6.05.06} Start Horizontal Retrace Pulse Register.   {4}
         See {6.05.07} End Horizontal Retrace Register.           {5}
         See {6.05.08} Vertical Total Register.                   {6}
         See {6.05.09} CRT Controller Overflow Register.          {7}


         The following is not true for the Trident 8900 chip.
         The following is valid for the Chips 82C456 chip.

         The Vertical Retrace End Register can be made invisible at this
         index address, when the Lightpen Low Register is placed at this
         same register index.
         For details see the Light Pen Register Enable description.

         See {6.05.05} End Horizontal Blanking Register.




6.05.20  Vertical Display Enable End Register     { 3?5h    12h    R/W }
=======  ===============================================================


Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.07.19} Overscan Colour Register.
Cross reference with {6.10.12} Clear Vertical Display Enable Register.


<7..0>   Vertical Display Enable End
         ---------------------------

         This binary value represents the eight lower order bits of a ten bit
         width Vertical Display Enable End value.  This ten bit value is used
         in conjunction with the character row counter.  When a match between
         these two values occurs, the active portion of the display finishes.

         This happens when the current display scan line runs into the first
         non-display scan line.   At that time, the display unit produces the
         colour specified by the Overscan Colour Register.  Typically several
         scan lines, termed overscan lines, are produced both at a frame end
         and at a frame start.  The two high order bits are stored elsewhere.

         See {6.05.09} CRT Controller Overflow Register.
         See {6.07.19} Overscan Colour Register.

         The active part of the display image is produced from the time when
         the character row counter has the value zero, representing the first
         scan line of the image proper, through to the value in this register.

         The only time this is not true is when the vertical display enable
         state is cleared asynchronously by special command.

         See {6.10.12} Clear Vertical Display Enable Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.

         A discussion of vertical timing and image generation is available,
         with a timing diagram.

         See {6.05.08} Vertical Total Register.




6.05.21  Offset Register                          { 3?5h    13h    R/W }
=======  ===============================================================


Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.05.25} CRTC Mode Control Register.


<7..0>   Display Image Offset
         --------------------

         The value of this field defines the image width for the complete image
         retained in the image memory.  This width is typically the same width
         as that of the image display, or possibly a greater width.

         This value employs a memory addressing unit of variable size according
         to the units of address employed by the display memory address counter
         determined by option settings:


         Display Memory Address Unit 2
         See {6.05.25} CRTC Mode Control Register.

         Display Memory Address Unit 4
         See {6.05.22} Underline Location Register.


         Display Memory Address Unit 4
         =----------------------------

              Display Memory Address Unit 2
         =    =----------------------------

                   Unit of display addressing
         =    =    ==========================--------------------


         0    0    Word mode addressing          { 2 byte units }

         0    1    Byte mode addressing          { 1 byte units }

         1    0    Double word mode addressing   { 4 byte units }

         1    1    Double word mode addressing   { 4 byte units }


         --------------------------------------------------------


         Whenever a new display scan line commences the current display address
         is adjusted to point to the data representing the new scan line.  This
         might involve skipping some of the data lying within the previous scan
         line.  This capability is provided so that an image much too large for
         display in a single screen can be maintained and manipulated easily in
         image memory.

         The screen can be made to display different portions of a much larger
         image by means of panning, in both the horizontal and vertical planes.
         In fact, for panning to work effectively, there must be a larger image
         present in image memory than that which can actually be displayed.

         See {6.05.10} Preset Row Scan Register.

         There is a circumstance where the value of the current display address
         register is not dependant upon the Display Image Offset value.  There
         is a facility which can be used to provide two windows within a single
         display screen.  The lower window can be made immune from panning.  In
         this situation, the display address is reset to zero.

         See {6.05.10} Preset Row Scan Register.

         Note that the display memory address counter is initialised with
         the value of the Start Address Register, which automatically has
         a value expressed in the same addressing units.

         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.




6.05.22  Underline Location Register              { 3?5h    14h    R/W }
=======  ===============================================================


Cross reference with {6.04.05} Character Map Select Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.21} Offset Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.10.04} Mode Control Register 2.


<4..0>   Underline Location
         ------------------

         This field specifies which character font relative scan line will be
         used to display an underline invoked by a character attribute in the
         Monochrome Graphics Adapter, Colour Graphics Adapter or the Hercules
         modes.  The first scan line in a font is numbered zero.  The feature
         operates only in text mode.

         See {6.06.08} Miscellaneous Register.

         The underline attribute appears as follows in these modes.

         See {6.10.04} Mode Control Register 2.


         Character Attribute Byte, Monochrome Emulation Mode
         ===================================================

         For monochrome emulation mode, set the Display Generation Mode.
         See {6.07.18} Attribute Mode Control Register.


         <2..0>  Foreground
                 ----------

                 <=000>  Black
                 <=001>  Underline
                 <=111>  White


         <3>     Intensity
                 ---------

                 <=0>  Normal
                 <=1>  High Intensity {alternatively character set select}

                  See {6.04.05} Character Map Select Register.


         <6..4>  Background
                 ----------

                 <=000>  Black
                 <=111>  White


         <7>     Blink
                 -----

                 <=0>  Normal
                 <=1>  Blink {alternatively high intensity select}

                 See {6.07.18} Attribute Mode Control Register.


         Character Attribute Byte, Colour Emulation Mode
         ===============================================

         For colour emulation mode, set the Display Generation Mode.
         See {6.07.18} Attribute Mode Control Register.


         <0>     Foreground Blue
                 ---------------

                 <=0>  No blue colour
                 <=1>  Output blue colour


         <1>     Foreground Green
                 ----------------

                 <=0>  No green colour
                 <=1>  Output green colour


         <2>     Foreground Red
                 --------------

                 <=0>  No red colour
                 <=1>  Output red colour


         <3>     Intensity
                 ---------

                 <=0>  Normal
                 <=1>  High Intensity {alternatively character set select}

                  See {6.04.05} Character Map Select Register.


         <4>     Background Blue
                 ---------------

                 <=0>  No blue colour
                 <=1>  Output blue colour


         <5>     Background Green
                 ----------------

                 <=0>  No green colour
                 <=1>  Output green colour


         <6>     Background Red
                 --------------

                 <=0>  No red colour
                 <=1>  Output red colour


         <7>     Blink
                 -----

                 <=0>  Normal
                 <=1>  Blink {alternatively high intensity select}

                 See {6.07.18} Attribute Mode Control Register.


<5>      Display Address Dwell Count 4
         -----------------------------

         The display memory address counter increments the memory address at a
         rate dependant upon the character clock frequency.  It is possible to
         increment the display memory address every character clock, or permit
         a number of character clock periods to elapse before the increment is
         put into effect.  When the display address does not change with every
         change of character clock, the display address experiences dwell.  It
         is possible to change the dwell through option settings:

         Display Address Dwell Count 4  {This.}

         Display Address Dwell Count 2

         See {6.05.25} CRTC Mode Control Register.


         Display Address Dwell Count 4  {This.}
         =----------------------------

              Display Address Dwell Count 2
         =    =----------------------------

                   Unit of display address dwell
         =    =    =============================----------------------


         0    0    Dwell = 1    { 1 character clocking per increment }

         0    1    Dwell = 2    { 2 character clocking per increment }

         1    0    Dwell = 4    { 4 character clocking per increment }

         1    1    Dwell = 2    { 2 character clocking per increment }


         -------------------------------------------------------------


         <=0>  Provide a single display address increment after each character
               clock period.  This provides a new image memory address for all
               new character clock periods.

               If the image memory is arranged in multiplane format, this will
               permit all four planes to be read at the beginning of every new
               character period.  This is the usual way to access image memory
               in 16 colour multiplane format.  It does not waste image space.

               The alternative facilities provided elsewhere are dominant over
               this option setting.  See the table above.

               See {6.05.25} CRTC Mode Control Register.

         <=1>  Specifies that four character clock periods must elapse before
               the display address increment takes place.  Therefore a single
               image memory address is issued with four consecutive character
               clocks.

               This is useful where the first character clock loaded four data
               planes using the new address and it is simply required that any
               new address generated be generated four character clocks later.
               In this case the intention is that the first clock of the group
               will load data whilst the remaining three clocks remain unused.

               This would be the case where the unit of addressing of the image
               memory has been changed, so permitting a much larger image to be
               displayed, without needing a display memory address counter with
               an increased number of bits.

               See Display Memory Address Unit 4, immediately below.

               Alternatively, all image planes could be loaded at an identical
               image memory address on each new character clock, providing for
               repeated presentation of image data.  The image produced depends
               upon the image format, either multiplane or packed pixel.  Each
               situation would be examined individually for appropriate merit.

               The alternative facilities provided elsewhere are dominant over
               this option setting.  See the table above.

               See {6.05.25} CRTC Mode Control Register.


<6>      Display Memory Address Unit 4
         -----------------------------

         The display memory address counter employs a memory addressing
         unit of variable size according to option settings:

         Display Memory Address Unit 4  {This.}

         Display Memory Address Unit 2
         See {6.05.25} CRTC Mode Control Register.


         Display Memory Address Unit 4  {This.}
         =----------------------------

              Display Memory Address Unit 2
         =    =----------------------------

                   Unit of display addressing
         =    =    ==========================--------------------


         0    0    Word mode addressing          { 2 byte units }

         0    1    Byte mode addressing          { 1 byte units }

         1    0    Double word mode addressing   { 4 byte units }

         1    1    Double word mode addressing   { 4 byte units }


         --------------------------------------------------------


         <=0>  Provide no bit shift between the display memory address counter
               and the image memory address lines.  This means that an address
               is generated into the display memory with granularity specified
               by Display Memory Address Unit 2.  See the table above.

               See {6.05.25} CRTC Mode Control Register.

               With this option selected the bit width of the display memory
               address counter determines the maximum number of bytes in the
               display image.  No further bytes can contribute to the image,
               since the image address space is fixed by this finite counter
               width.  This can represent a problem with large images, using
               packed pixel display format with 256 colours, since each byte
               represents one pixel.  With 18 bits of address counter, image
               size is restricted to 256K/512K which may not be adequate.

               When the display generation employs multiplane mode, the 256K
               address capability is sufficient to give full access to every
               pixel that can be stored in the image memory.  This is because
               with 1024K of image memory, arranged in four parallel planes,
               256K of address capacity covers the entire address space.

               Note that the display memory address counter is initialised with
               the value of the Start Address Register, which automatically has
               a value expressed in the same addressing units.

               See {6.05.14} Start Address High Register.
               See {6.05.15} Start Address Low Register.

         <=1>  Left shift the display memory address counter by 2 bits before
               using the resulting address to access display memory.  In this
               way, each address is multiplied by four, so becoming a double
               word address.  This provides an effective increase of two bits
               in the addressing capability of the memory address counter.

               This option increases the maximum display image size to four
               times the original limit, which enables larger packed pixel
               images to be displayed at high resolution in 256 colours.

               Since the display memory address counter is 18 bits width, the
               adoption of two additional bits of addressing span provide for
               20 bits of total addressing capability.  This gives sufficient
               capacity to address a full 1024K display memory.

               A side effect of this greater memory addressing span is that it
               becomes impossible to address image data in a unit smaller than
               a group consisting of 4 bytes.  As a direct consequence of this
               the display hardware must always use load a single 4 byte group
               at each new display memory address counter value.  Only if this
               is done can the full image memory capacity be realised. In fact
               this method of addressing is ideally suited to packed pixel 256
               colour mode.

               Note that the display memory address counter is initialised with
               the value of the Start Address Register, which automatically has
               a value expressed in the same addressing units.

               See {6.05.14} Start Address High Register.
               See {6.05.15} Start Address Low Register.

               The alternative facilities provided elsewhere are inhibited with
               this option setting.  See the table above.

               See {6.05.25} CRTC Mode Control Register.


<7>      Reserved.  Always <=0>.
         -----------------------




6.05.23  Start Vertical Blanking Register         { 3?5h    15h    R/W }
=======  ===============================================================


Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   Start Vertical Blanking
         -----------------------

         This binary field specifies the lower order 8 bits of the 10 bit width
         value representing the scan line at which vertical blanking commences.
         The two remaining bits are stored elsewhere.

         See {6.05.11} Maximum Scan Line Register.
         See {6.05.09} CRT Controller Overflow Register.

         The 10 bit value is compared with the character row counter until the
         values match.  The character row counter counts all active scan lines
         in the frame, commencing at zero, which is the first scan line to use
         image data in the display.

         When the match occurs the vertical blanking period begins.  During the
         blanking period the display electron beams which illuminate the screen
         are temporarily inhibited, for the entire period of vertical retrace.

         See {6.05.18} Vertical Retrace Start Register.
         See {6.05.19} Vertical Retrace End Register.

         The vertical retrace sends the notional position of the electron beams
         to the top left of the screen.  As this would damage the display image
         if the electron beams were operational, blanking prevents any problems
         of image quality by inhibiting the electron beams during retrace.

         The length of the blanking period is determined using a terminal value
         to indicate that blanking should finish.

         See {6.05.24} End Vertical Blanking Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.

         A discussion of vertical display timing is available together with a
         timing diagram.

         See {6.05.08} Vertical Total Register.




6.05.24  End Vertical Blanking Register           { 3?5h    16h    R/W }
=======  ===============================================================


Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.


<7..0>   End Vertical Blanking
         ---------------------

         This specifies a compare value for use with the character row counter
         giving the display scan line at which the vertical blanking period is
         deemed to be complete.  During the vertical blanking period, vertical
         retrace will have fully taken place.

         See {6.05.18} Vertical Retrace Start Register.
         See {6.05.19} Vertical Retrace End Register.

         The character row counter is actually of 10 bits width but the compare
         does not take place until after the vertical blanking period has begun
         so there is no ambiguity in operation.  Therefore the 8 value bits are
         sufficient under these circumstances to specify upto 255 scan lines of
         vertical blanking period.  This is such a large number it would never
         be used in practise.

         See {6.05.23} Start Vertical Blanking Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.

         A discussion of vertical display timing is available together with a
         timing diagram.

         See {6.05.08} Vertical Total Register.




6.05.25  CRTC Mode Control Register               { 3?5h    17h    R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.20} Vertical Display Enable End Register.
Cross reference with {6.05.21} Offset Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         A single bit <2> only is affected.  {Horizontal Retrace Divisor.}

         See {6.10.07} CRTC Module Testing Register.


<0>      Display Address 13 Remap Row 0
         ------------------------------

         <=0>  Replace the display memory address counter bit 13 with the
               character row counter bit 0.  This means that for even row
               scan line generation, image data addresses are not offset.
               Odd row scan lines incur an address offset with equivalent
               value of 8K bytes.  In this way there is an 8K offset with
               each alternate scan line display.  This facility provides
               an emulation capability for Colour Graphics Adapter image
               memory layout.  It is of little interest for construction
               of new software which aims for high execution speeds.

               See also Display Address 14 Remap Row 1, below.

         <=1>  No modification to display memory address counter bit 13
               takes place.  This is the normal setting for this option.


<1>      Display Address 14 Remap Row 1
         ------------------------------

         <=0>  Replace the display memory address counter bit 14 with the
               character row counter bit 1.  In this way, the pair number
               of the scan line being displayed changes the image memory
               address being used to generate the display.  On each pair
               change, an equivalent memory offset of 16K is introduced.

               This option is usually employed in conjunction with that
               of Display Address 13 Remap Row 0, in order to provide a
               four bank image memory layout.  This is usually used for
               Hercules adapter emulation.  It is of little interest in
               terms of new software aiming for high speed operation.

         <=1>  No modification to display memory address counter bit 14
               takes place.  This is the normal setting for this option.


<2>      Horizontal Retrace Divisor
         --------------------------

         <=0>  This option selects horizontal retrace as the source of the
               decision to increment the character row counter which keeps
               track of the scan line being generated for display.  Normal
               operation of the generation process takes place using this
               option setting.  The character row counter increments after
               every scan line of the active image is completed.

         <=1>  This option counts two horizontal retrace events before the
               increment of the character row counter takes place.  After
               two scan lines have completed, the character row counter is
               incremented by only one scan line.  In this way, the timing
               period for all vertical timing is increased to double the
               usual period.  At the same time, the maximum number of scan
               lines resolvable in the 10 bits width character row counter
               increases from 1024 to 2048.  This can be used to create a
               display with much higher vertical resolution.

               See {6.05.08} Vertical Total Register.
               See {6.05.18} Vertical Retrace Start Register.
               See {6.05.19} Vertical Retrace End Register.
               See {6.05.20} Vertical Display Enable End Register.
               See {6.05.23} Start Vertical Blanking Register.
               See {6.05.24} End Vertical Blanking Register.
               See {6.05.26} Line Compare Register.

               While this mode is operational, the display memory address
               counter operation is unaffected and so behaves as normal.
               This means that the image data is always read from display
               memory with continually increasing addresses.  Every scan
               line is built using image data unique to that scan line.

               Warning: do not confuse this capability with that provided
               by the Double Scan Line Display.

               See {6.05.11} Maximum Scan Line Register.




<3>      Display Address Dwell Count 2
         -----------------------------

         The display memory address counter increments the memory address at a
         rate dependant upon the character clock frequency.  It is possible to
         increment the display memory address every character clock, or permit
         a number of character clock periods to elapse before the increment is
         put into effect.  When the display address does not change with every
         change of character clock, the display address experiences dwell.  It
         is possible to change the dwell through option settings:

         Display Address Dwell Count 4
         See {6.05.22} Underline Location Register.

         Display Address Dwell Count 2  {This.}


         Display Address Dwell Count 4
         =----------------------------

              Display Address Dwell Count 2  {This.}
         =    =----------------------------

                   Unit of display address dwell
         =    =    =============================----------------------


         0    0    Dwell = 1    { 1 character clocking per increment }

         0    1    Dwell = 2    { 2 character clocking per increment }

         1    0    Dwell = 4    { 4 character clocking per increment }

         1    1    Dwell = 2    { 2 character clocking per increment }


         -------------------------------------------------------------


         <=0>  Provide a single display address increment after each character
               clock period.  This provides a new image memory address for all
               new character clock periods.

               If the image memory is arranged in multiplane format, this will
               permit all four planes to be read at the beginning of every new
               character period.  This is the usual way to access image memory
               in 16 colour multiplane format.  It does not waste image space.

               The alternative facilities provided elsewhere are available with
               this option setting.  See table above.

               See {6.05.22} Underline Location Register.

         <=1>  Specifies that two character clock periods must elapse before a
               new display memory address is produced by increment.  Thus just
               one new display memory address is produced each two consecutive
               character clocks.

               This is useful where the first character clock loaded two data
               planes using the new address and it is simply required that any
               new address generated be generated two character clocks later.
               In this case the intention is that the first clock of the group
               will load data while the remaining clock period remains unused.

               This would be the case where the unit of addressing of the image
               memory has been changed, so permitting a much larger image to be
               displayed, without needing a display memory address counter with
               an increased number of bits.

               See Display Memory Address Unit 2, below.

               The alternative facilities provided elsewhere are dominated by
               this option setting.  See table above.

               See {6.05.22} Underline Location Register.


<4>      Reserved.  Always <=0>.
         -----------------------


<5>      Display Address Unit 2 Remap
         ----------------------------

         <=0>  When option Display Memory Address Unit 2 {see below} is active,
               this selection specifies that the display memory address counter
               bit 0 will take on the value of memory address counter bit 13.
               Address counter bit 13 measures addresses in terms of 8K units.
               One 8K unit is sometimes termed a bank.

               The effect is to double the address span which can be achieved,
               by using bit 0 to specify which memory bank to select.  In word
               address mode, bit 0 is never used for address generation since
               byte addresses are always incremented by 2.  Therefore bit 0 is
               always left unchanged.

               When display image memory is organised as multiple planes, each
               of the four planes shares an identical, parallel address space.
               In this situation, each word address accesses all the planes in
               parallel, by using what amounts to an even byte address.  When
               the increment occurs the odd byte address situated between the
               two even addresses is skipped, so remaining inaccessible.

               This has the effect of wasting half the address space.  To avoid
               such waste, the display memory address counter bit 0 is used to
               differentiate between even and odd numbered byte addresses.  The
               display unit will only access even byte addresses initially, but
               after reading half an 8K bank, will proceed to read that bank by
               accessing only odd byte addresses.  In this way, the bank space
               is effectively doubled.

               The option of selecting bit 13 is decided by the maximum amount
               of image memory present.  Were only 64K bytes available, there
               would be 16K of multiplane memory address space present with 4
               bytes at each memory address.  In this situation 14 effective
               memory address counter bits <13..0> would provide 16K units of
               addressing.  With this option selected, that enables the whole
               of the image memory to be used for image generation.

               This option simply changes the significance and manner of use of
               the display memory address counter bits.  It should be used only
               for emulation purposes.  Note that use of this option cannot be
               entirely avoided when the Display Memory Address Unit 2 option
               is active.

         <=1>  When option Display Memory Address Unit 2 {see below} is active,
               this selection specifies that the display memory address counter
               bit 0 will take on the value of memory address counter bit 15.
               Address counter bit 15 measures addresses in terms of 32K units.
               One 32K unit is sometimes termed a bank.

               The effect is to double the address span which can be achieved,
               by using bit 0 to specify which memory bank to select.  In word
               address mode, bit 0 is never used for address generation since
               byte addresses are always incremented by 2.  Therefore bit 0 is
               always left unchanged.

               When display image memory is organised as multiple planes, each
               of the four planes shares an identical, parallel address space.
               In this situation, each word address accesses all the planes in
               parallel, by using what amounts to an even byte address.  When
               the increment occurs the odd byte address situated between the
               two even addresses is skipped, so remaining inaccessible.

               This has the effect of wasting half the address space.  To avoid
               such waste, the display memory address counter bit 0 is used to
               differentiate between even and odd numbered byte addresses.  The
               display unit will only access even byte addresses initially, but
               after reading half a 32K bank, will proceed to read that bank by
               accessing only odd byte addresses.  In this way, the bank space
               is effectively doubled.

               The option of selecting bit 15 is decided by the maximum amount
               of image memory present.  Where 256K bytes is available, there
               would be 64K of multiplane memory address space present with 4
               bytes at each memory address.  In this situation 16 effective
               memory address counter bits <15..0> would provide 64K units of
               addressing.  With this option selected, that enables the whole
               of the image memory to be used for image generation.

               This option simply changes the significance and manner of use of
               the display memory address counter bits.  It should be used only
               for emulation purposes.  Note that use of this option cannot be
               entirely avoided when the Display Memory Address Unit 2 option
               is active.


<6>      Display Memory Address Unit 2
         -----------------------------

         The display memory address counter employs a memory addressing
         unit of variable size according to option settings:

         Display Memory Address Unit 2  {This.}

         Display Memory Address Unit 4
         See {6.05.22} Underline Location Register.


         Display Memory Address Unit 4
         =----------------------------

              Display Memory Address Unit 2  {This.}
         =    =----------------------------

                   Unit of display addressing
         =    =    ==========================--------------------


         0    0    Word mode addressing          { 2 byte units }

         0    1    Byte mode addressing          { 1 byte units }

         1    0    Double word mode addressing   { 4 byte units }

         1    1    Double word mode addressing   { 4 byte units }


         --------------------------------------------------------


         <=0>  Left shift the display memory address counter by 1 bit, before
               using the resulting address to access display memory.  In this
               way, each address is multiplied by two, thus becoming a double
               byte address.  This provides an apparent effective increase of
               one bit in the memory address counter addressing capability.

               However, it also fails to use bit 0 of the resulting effective
               memory address, which would decrease the size of the resulting
               address space.  There is automatic capability to use the extra
               bit 0 to increase the size of the address space.  Note that it
               has the effect of returning the address space size to the same
               size it was before Display Memory Address Unit 2 became active.

               Thus this option simply changes the interpretation attributed
               to the display memory address counter, and does not increase
               the address range generated.  However, the organisation of the
               address space is changed.  Use this facility with due caution,
               probably only for emulation purposes.

               See Display Address Unit 2 Remap, immediately above.

               This option is often termed word address mode, since two bytes
               make up one single word.

               Note that the display memory address counter is initialised with
               the value of the Start Address Register, which automatically has
               a value expressed in the same addressing units.

               See {6.05.14} Start Address High Register.
               See {6.05.15} Start Address Low Register.

               The alternative facilities provided elsewhere are dominant over
               this option setting.  This is shown clearly in the table above.

               See {6.05.22} Underline Location Register.


         <=1>  Provide no bit shift between the display memory address counter
               and the image memory address lines.  This means that an address
               is generated into the display memory with a granularity of one
               single byte.  This option is often termed byte address mode.

               With this option selected the bit width of the display memory
               address counter determines the maximum number of bytes in the
               display image.  No further bytes can contribute to the image,
               since the image address space is fixed by this finite counter
               width.  This can represent a problem with large images, using
               packed pixel display format with 256 colours, since each byte
               represents one pixel.  With 18 bits of address counter, image
               size is restricted to 256K.

               Note that the display memory address counter is initialised with
               the value of the Start Address Register, which automatically has
               a value expressed in the same addressing units.

               See {6.05.14} Start Address High Register.
               See {6.05.15} Start Address Low Register.

               The alternative facilities provided elsewhere are dominant over
               this option setting.  This is shown clearly in the table above.

               See {6.05.22} Underline Location Register.


<7>      Horizontal/Vertical Retrace Reset
         ---------------------------------

         <=0>  Reset the horizontal and vertical retrace signals to the
               display unit.

         <=1>  Generate horizontal and vertical retrace signals to the
               display unit.  This is the usual setting for the option.




         A note on addresses produced by the display memory address counter
         ==================================================================


         Addresses are generated by the display memory address counter, but
         these addresses are then mapped to the actual memory address lines
         before being used.  The table shown below gives the detail of this
         mapping.




         Physical memory address used for display generation
         ====-----------------------------------------------


                 Display Memory Address Counter Bit
         ====    -------------------------------------------------
                                         |           |           |
                                         |           |           |
                 Byte Mode Addressing    |           |           |
         ====    ====---------------------           |           |
                                                     |           |
                                                     |           |
                         Word Mode Addressing        |           |
         ====    ====    ====-------------------------           |
                                                                 |
                                                                 |
                                 Double Word Mode Addressing     |
         ====    ====    ====    ====-----------------------------


                                         Comments
         ====    ====    ====    ====    ------------------------------------


         PA00    MA00     [1]     [2]    [1] is defined by the option
                                         Display Address Unit 2 Remap
         PA01    MA01    MA00     [3]    see above <5>.  This is only
                                         valid in word address mode.
         PA02    MA02    MA01    MA00

         PA03    MA03    MA02    MA01
                                         [2] is defined by the display
         PA04    MA04    MA03    MA02    mode in use.

         PA05    MA05    MA04    MA03    See Shift Load Two Control
                                             {6.04.03} Clocking Mode Register
         PA06    MA06    MA05    MA04    See Shift Load Four Control
                                             {6.04.03} Clocking Mode Register
         PA07    MA07    MA06    MA05

         PA08    MA08    MA07    MA06
                                         [3] is defined by the display
         PA09    MA09    MA08    MA07    mode in use.

         PA10    MA10    MA09    MA08    See Shift Load Two Control
                                             {6.04.03} Clocking Mode Register
         PA11    MA11    MA10    MA09    See Shift Load Four Control
                                             {6.04.03} Clocking Mode Register
         PA12    MA12    MA11    MA10

         PA13    MA13    MA12    MA11

         PA14    MA14    MA13    MA12

         PA15    MA15    MA14    MA13

         PA16    MA16    MA15    MA14

         PA17    MA17    MA16    MA15

         PA18    ----    MA17    MA16

         PA19    ----    ----    MA17


         --------------------------------------------------------------------




6.05.26  Line Compare Register                    { 3?5h    18h    R/W }
=======  ===============================================================


Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.07.21} Horizontal PEL Panning Register.


<7..0>   Line Compare
         ------------

         This binary field represents the lower eight bits of the full 10 bit
         wide value of the Line Compare Register.  The 10 bit value specifies
         the scan line registered by the character row counter when a change
         should be made to a second display window in the two window screen.
         The higher order bits are held elsewhere.

         See {6.05.09} CRT Controller Overflow Register.
         See {6.05.11} Maximum Scan Line Register.

         The two windows are distinguished in that the first always specifies
         a non-zero starting address into the image memory, and is subject to
         panning control.  The second window always begins at a display image
         memory address of zero, and may either be panned in the same manner
         as the first window, or alternatively may be made immune to panning,
         as determined by option setting.

         When the match occurs with the character row counter, the display
         memory address counter is reset to zero, ready for display of the
         second, lower window.  Simultaneously, any panning controls which
         were in operation for the upper window are optionally cancelled,
         until the next frame display commences.

         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.
         See {6.07.18} Attribute Mode Control Register.

         A discussion of pixel panning is available.
         See {6.05.10} Preset Row Scan Register.
         See {6.07.21} Horizontal PEL Panning Register.

         A discussion of vertical display timing generation is available with
         a timing diagram.

         See {6.05.08} Vertical Total Register.

         The units in which vertical timing is measured can be changed by a
         factor of two upon option setting.

         See {6.05.25} CRTC Mode Control Register.




6.06  Register specifications: Graphics Controller
====  ============================================


6.06.01  Graphics Address Register    { 3ceh    ---    R/W }
=======  ===================================================


<3..0>   Graphics Register Address
         -------------------------

         Port 3cfh accesses the register pointed to by the index number in this
         bit field.  Index number zero is represented by <=0000>.


<7..4>   Reserved. Always <=0000>.
         -------------------------




6.06.02  Set/Reset Register           { 3cfh    00h    R/W }
=======  ===================================================


Cross reference with {6.04.04} Map Mask Register.
Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.06.03} Enable Set/Reset Register.
Cross reference with {6.06.05} Data Rotate Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.10} Bit Mask Register.
Cross reference with {6.10.09} CPU Latch Read Back Register.


<0>      Set/Reset Data Image Plane 0
         ----------------------------

         During multiplane image memory write access operation by the processor
         this bit helps to determine the value written to the byte lying within
         display memory image plane 0.

         <=0>  The data value 0 is selected for image plane zero, so long as
               the plane is suitably enabled for this operation.

               See {6.06.03} Enable Set/Reset Register.

         <=1>  The data value 1 is selected for image plane zero, so long as
               the plane is suitably enabled for this operation.

               See {6.06.03} Enable Set/Reset Register.

         The precise effect of this bit is determined by the write mode used to
         perform the update operation.  There are four different write modes as
         follows:


         Write Mode 0
         ============

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         Processor data for write arrive as an 8 bit wide value.  These bits
         are rotated.  The rotated bits are copied in parallel to data paths
         8 bits wide associated with each of the four image memory planes.

         Where Set/Reset Enable Image Plane 0 is set <=1>, all eight data path
         bits associated with image plane 0 are set to just one value given by
         the single bit Set/Reset Data Image Plane 0.  All other memory planes
         are processed in an identical manner.  Four output data paths result,
         each of eight bits width, making a total of 32 bits.

         These result data paths are then operated upon by a logic unit with
         capability to perform combining operations with corresponding eight
         bit contents of four read latches, one each per image memory plane.
         The read latches must be well defined for this processing to be of
         any value.  The combining operations are NO_OP, AND, OR, XOR.  The
         NO_OP passes the data through unchanged, ignoring read latch data,
         but the read latches are updated with the data as a consequence.

         Thereafter, each plane in parallel has the result of the previously
         described processing combined with the contents of the read latches
         (which must previously have been defined using a read operation).

         This combining operation selects for each image plane data path, and
         for each of eight bits in one data path, the value of the processing
         path bit or the value of the read latch bit, in identical position.
         The selection is based on all eight bits of a bit mask register used
         specially for just this purpose.  Any given bit position in the mask
         register will select either the process data path or the read latch
         output path, in identical manner, for the corresponding bit position
         in each of the four image planes.

         The output from this operation is another 32 bit wide data path, made
         up of four eight bit wide paths, one for each of four image planes.
         This final output data is written in a single write operation to each
         corresponding image plane in parallel, subject to plane write inhibit
         state.  Each plane can be write inhibited in complete independance of
         any other plane.  A write inhibit state prevents any write operations
         from modifying data within the corresponding image plane.

         Write mode 3 processes for relative colour.  By contrast, write mode
         0 should be seen as processing in terms of absolute colour.

         The use of the Set/Reset Enable and Set/Reset Data input is to specify
         a four bit colour value across a single bit position within all planes
         of the image memory, in parallel.  In this way, the processor supplied
         data is either used unchanged, is modified partially, or is completely
         ignored when deciding how to process for update.  The resulting output
         is used by the logic unit together with the read latch contents.  This
         provides extremely powerful colour processing capability when properly
         used.  This write mode is probably the most generally used write mode.

         See {6.06.07} Graphics Mode Register.




         Schematic Overview of Data Path for Write Mode 0
         ================================================
         ================================================




 Processor Data
 ===========---
 <7654.3210>
      |
 [All Planes]
      |
      |
      |
      |             Multiplane
      |             Rotation
      |             Select
      |             ==========-
      |             <7654.3210>
      |                  |
     .|             [All planes]
     |                   |
     |                   |
     | ..................|
     | |
     | |
     | |
 Data Rotation
 ===========--
 <7654.3210>
      |
 [All Planes]
      |
      |
      |
      | Copy all data into four identical data paths
      |.........................................................
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
 .....|             .....|             .....|             .....|
 |                  |                  |                  |
 |                  |                  |                  |
 |                  |                  |                  |
 |  Force Value     |  Force Value     |  Force Value     |  Force Value
 |  Enable bit      |  Enable bit      |  Enable bit      |  Enable bit
 |  ===========     |  ===========     |  ===========     |  ===========
 |       |          |       |          |       |          |       |
 |   [Plane 0]      |   [Plane 1]      |   [Plane 2]      |   [Plane 3]
 |       |          |       |          |       |          |       |
 |       |          |       |          |       |          |       |
 | ......|          | ......|          | ......|          | ......|
 | |                | |                | |                | |
 | |                | |                | |                | |
 | |                | |                | |                | |
 | |  Force Value   | |  Force Value   | |  Force Value   | |  Force Value
 | |  Data bit      | |  Data bit      | |  Data bit      | |  Data bit
 | |  ===========   | |  ===========   | |  ===========   | |  ===========
 | |       |        | |       |        | |       |        | |       |
 | |   [Plane 0]    | |   [Plane 1]    | |   [Plane 2]    | |   [Plane 3]
 | |       |        | |       |        | |       |        | |       |
 | |       |        | |       |        | |       |        | |       |
 | |...    |        | |...    |        | |...    |        | |...    |
 |    |    |        |    |    |        |    |    |        |    |    |
 |    |    |        |    |    |        |    |    |        |    |    |
 |... | ...|        |... | ...|        |... | ...|        |... | ...|
    | | |              | | |              | | |              | | |
    | | |              | | |              | | |              | | |
    | | |              | | |              | | |              | | |
 Force Value        Force Value        Force Value        Force Value
 of each bit        of each bit        of each bit        of each bit
 to the same        to the same        to the same        to the same
 equal value        equal value        equal value        equal value
 ===========        ===========        ===========        ===========
 <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
   ...|               ...|               ...|               ...|
   |                  |                  |                  |
   |                  |                  |                  |
   |                  |                  |                  |
   |   Read Latch 0   |   Read Latch 1   |   Read Latch 2   |   Read Latch 3
   |   ===========-   |   ===========-   |   ===========-   |   ===========-
   |   <7654.3210>    |   <7654.3210>    |   <7654.3210>    |   <7654.3210>
   |        |         |        |         |        |         |        |
   |    [Plane 0]     |    [Plane 1]     |    [Plane 2]     |    [Plane 3]
   |        |         |        |         |        |         |        |
   |        |         |        |         |        |         |        |
   |.. .....|         |.. .....|         |.. .....|         |.. .....|
     | |                | |                | |                | |
     | |                | |                | |                | |
     | |                | |                | |                | |
     | |  Multiplane    | |  Multiplane    | |  Multiplane    | |  Multiplane
     | |  Function      | |  Function      | |  Function      | |  Function
     | |  Select        | |  Select        | |  Select        | |  Select
     | |  ===========   | |  ===========   | |  ===========   | |  ===========
     | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>
     | |       |        | |       |        | |       |        | |       |
     | |  [All planes]  | |  [All planes]  | |  [All planes]  | |  [All planes]
     | |       |        | |       |        | |       |        | |       |
     | |       |        | |       |        | |       |        | |       |
     | |       |        | |       |        | |       |        | |       |
     | | ......|        | | ......|        | | ......|        | | ......|
     | | |              | | |              | | |              | | |
     | | |              | | |              | | |              | | |
     | | |              | | |              | | |              | | |
     Logic Block        Logic Block        Logic Block        Logic Block
     ...NO_OP...        ...NO_OP...        ...NO_OP...        ...NO_OP...
     ...AND.....        ...AND.....        ...AND.....        ...AND.....
     ...OR......        ...OR......        ...OR......        ...OR......
     ...XOR.....        ...XOR.....        ...XOR.....        ...XOR.....
     ===========        ===========        ===========        ===========
     <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
          |                  |                  |                  |
      [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
          |                  |                  |                  |
          |                  |                  |                  |
   .......|           .......|           .......|           .......|
   |                  |                  |                  |
   |                  |                  |                  |
   |                  |                  |                  |
   |   Read Latch 0   |   Read Latch 1   |   Read Latch 2   |   Read Latch 3
   |   ===========-   |   ===========-   |   ===========-   |   ===========-
   |   <7654.3210>    |   <7654.3210>    |   <7654.3210>    |   <7654.3210>
   |        |         |        |         |        |         |        |
   |    [Plane 0]     |    [Plane 1]     |    [Plane 2]     |    [Plane 3]
   |        |         |        |         |        |         |        |
   |        |         |        |         |        |         |        |
   | .......|         | .......|         | .......|         | .......|
   | |                | |                | |                | |
   | |                | |                | |                | |
   | |                | |                | |                | |
   | |  Multiplane    | |  Multiplane    | |  Multiplane    | |  Multiplane
   | |  Select Bit    | |  Select Bit    | |  Select Bit    | |  Select Bit
   | |  Definition    | |  Definition    | |  Definition    | |  Definition
   | |  ===========   | |  ===========   | |  ===========   | |  ===========
   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>
   | |       |        | |       |        | |       |        | |       |
   | |  [All Planes]  | |  [All Planes]  | |  [All Planes]  | |  [All Planes]
   | |       |        | |       |        | |       |        | |       |
   | |       |        | |       |        | |       |        | |       |
   | | ......|        | | ......|        | | ......|        | | ......|
   | | |              | | |              | | |              | | |
   | | |              | | |              | | |              | | |
   | | |              | | |              | | |              | | |
 Every output       Every output       Every output       Every output
 bit selected       bit selected       bit selected       bit selected
 using choice       using choice       using choice       using choice
 for that bit       for that bit       for that bit       for that bit
 ===========-       ===========-       ===========-       ===========-
 <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
      |                  |                  |                  |
      |  Plane 0         |  Plane 1         |  Plane 2         |  Plane 3
      |  Inhibit         |  Inhibit         |  Inhibit         |  Inhibit
      |   Write          |   Write          |   Write          |   Write
      |  =======         |  =======         |  =======         |  =======
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
     -----------        -----------        -----------        -----------
     Write Logic        Write Logic        Write Logic        Write Logic
     for Plane 0        for Plane 1        for Plane 2        for Plane 3
       Memory             Memory             Memory             Memory
     -----------        -----------        -----------        -----------




         Key to schematic for Write Mode 0
         =================================


         --------------------------
         Multiplane Rotation Select
         --------------------------

             See {6.06.05} Data Rotate Register.


         ----------------------
         Force Value Enable bit
         ----------------------

             See {6.06.03} Enable Set/Reset Register.


         --------------------
         Force Value Data bit
         --------------------

             See {6.06.02} Set/Reset Register.  {This.}


         --------------------------
         Multiplane Function Select
         --------------------------

             See {6.06.05} Data Rotate Register.


         --------------------------------
         Multiplane Select Bit Definition
         --------------------------------

             See {6.06.10} Bit Mask Register.


         -----------------------
         Plane 'N' Inhibit Write
         -----------------------

             See {6.04.04} Map Mask Register.




         Write Mode 1
         ============

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         There is no processor data involved in using write mode 1, however the
         processor must generate a read memory or write memory operation to the
         image memory space. This provides the control input required to effect
         the data transfers which are provided by this mode.

         Write mode 1 provides for a very fast multiplane image data movement
         between one region of image memory to another region within the same
         image memory.

         This copy capability is very flexible.  It can be used to perform an
         image copy, or an initialisation operation using constant image data
         to specify the value for the complete image.  In both cases, 32 bits,
         that is four bytes, one each per image plane are transferred, unless
         writes are inhibited to a particular plane.  Any individual plane is
         subject to write inhibit control, independantly of all other planes.

         To perform a true copy, a read address is generated to the multiplane
         image.  This will have the effect of loading four read latches with
         data from each of the four image planes.

         Then a write operation is generated onto the multiplane image.  This
         gives the effect of writing each of four image planes using the read
         latch data associated with each plane, in parallel.  In this way, a
         single write is able to transfer 32 bits of data simultaneously.

         This accounts for the large image transfer bandwidth available from
         this write mode.

         In order to initialise an image, it is necessary to load the four read
         latches once and then to repeatedly write them into the required image
         addresses.  This provides for very fast image initialisation.

         There is no use made of the Set/Reset Enable and Set/Reset Data during
         operations in write mode 1.

         Write mode 1 is mentioned in connection with Graphics Memory Access
         Mode and Processor Image Memory Access Mode Select.

         See {6.04.06} Sequencer Memory Mode Register.




         Schematic Overview of Data Path for Write Mode 1
         ================================================
         ================================================




 Read Latch 0       Read Latch 1       Read Latch 2       Read Latch 3
 ===========-       ===========-       ===========-       ===========-
 <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
      |                  |                  |                  |
      |  Plane 0         |  Plane 1         |  Plane 2         |  Plane 3
      |  Inhibit         |  Inhibit         |  Inhibit         |  Inhibit
      |   Write          |   Write          |   Write          |   Write
      |  =======         |  =======         |  =======         |  =======
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
     -----------        -----------        -----------        -----------
     Write Logic        Write Logic        Write Logic        Write Logic
     for Plane 0        for Plane 1        for Plane 2        for Plane 3
       Memory             Memory             Memory             Memory
     -----------        -----------        -----------        -----------




         Key to schematic for Write Mode 1
         =================================



         -----------------------
         Plane 'N' Inhibit Write
         -----------------------

             See {6.04.04} Map Mask Register.




         Write Mode 2
         ============

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         Processor data for write arrive as a 4 bit wide value.  Each of the
         bits are associated with a corresponding image plane, so bit 0 will
         provide data for use in conjunction with image plane 0, and so on.

         Each bit is copied into a data path of eight bits with each of these
         eight bits taking on the same value as the original bit.  The result
         is four data paths of eight bits, one data path for each of the four
         image planes.  Within a data path all eight bits are the same value,
         determined by the corresponding bit in the four bit processor data.

         These result data paths are then operated upon by a logic unit with
         capability to perform combining operations with corresponding eight
         bit contents of four read latches, one each per image memory plane.
         The read latches must be well defined for this processing to be of
         any value.  The combining operations are NO_OP, AND, OR, XOR.  The
         NO_OP passes the data through unchanged, ignoring read latch data.

         Thereafter, each plane in parallel has the result of the previously
         described processing combined with the contents of the read latches
         (which must previously have been defined using a read operation).

         This combining operation selects for each image plane data path, and
         for each of eight bits in one data path, the value of the processing
         path bit or the value of the read latch bit, in identical position.
         The selection is based on all eight bits of a bit mask register used
         specially for just this purpose.  Any given bit position in the mask
         register will select either the process data path or the read latch
         output path, in identical manner, for the corresponding bit position
         in each of the four image planes.

         The output from this operation is another 32 bit wide data path, made
         up of four eight bit wide paths, one for each of four image planes.
         This final output data is written in a single write operation to each
         corresponding image plane in parallel, subject to plane write inhibit
         state.  Each plane can be write inhibited in complete independance of
         any other plane.  A write inhibit state prevents any write operations
         from modifying data within the corresponding image plane.

         There is no use made of the Set/Reset Enable and Set/Reset Data during
         operations in write mode 2.

         See {6.06.07} Graphics Mode Register.




         Schematic Overview of Data Path for Write Mode 2
         ================================================
         ================================================




 Processor Data
 ===========---
 <----.3210>
       ||||
       ||||......................................................
       |||                                                      |
       |||....................................                  |
       ||                                    |                  |
       ||..................                  |                  |
       |                  |                  |                  |
       |                  |                  |                  |
       |                  |                  |                  |
  Repeat bit         Repeat bit         Repeat bit         Repeat bit
  value over         value over         value over         value over
  all 8 bits         all 8 bits         all 8 bits         all 8 bits
  ==========-        ==========-        ==========-        ==========-
  <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
       |                  |                  |                  |
   [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
       |                  |                  |                  |
       |                  |                  |                  |
   ....|              ....|              ....|              ....|
   |                  |                  |                  |
   |                  |                  |                  |
   |                  |                  |                  |
   |   Read Latch 0   |   Read Latch 1   |   Read Latch 2   |   Read Latch 3
   |   ===========-   |   ===========-   |   ===========-   |   ===========-
   |   <7654.3210>    |   <7654.3210>    |   <7654.3210>    |   <7654.3210>
   |        |         |        |         |        |         |        |
   |    [Plane 0]     |    [Plane 1]     |    [Plane 2]     |    [Plane 3]
   |        |         |        |         |        |         |        |
   |        |         |        |         |        |         |        |
   |.. .....|         |.. .....|         |.. .....|         |.. .....|
     | |                | |                | |                | |
     | |                | |                | |                | |
     | |                | |                | |                | |
     | |  Multiplane    | |  Multiplane    | |  Multiplane    | |  Multiplane
     | |  Function      | |  Function      | |  Function      | |  Function
     | |  Select        | |  Select        | |  Select        | |  Select
     | |  ===========   | |  ===========   | |  ===========   | |  ===========
     | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>
     | |       |        | |       |        | |       |        | |       |
     | |  [All planes]  | |  [All planes]  | |  [All planes]  | |  [All planes]
     | |       |        | |       |        | |       |        | |       |
     | |       |        | |       |        | |       |        | |       |
     | |       |        | |       |        | |       |        | |       |
     | | ......|        | | ......|        | | ......|        | | ......|
     | | |              | | |              | | |              | | |
     | | |              | | |              | | |              | | |
     | | |              | | |              | | |              | | |
     Logic Block        Logic Block        Logic Block        Logic Block
     ...NO_OP...        ...NO_OP...        ...NO_OP...        ...NO_OP...
     ...AND.....        ...AND.....        ...AND.....        ...AND.....
     ...OR......        ...OR......        ...OR......        ...OR......
     ...XOR.....        ...XOR.....        ...XOR.....        ...XOR.....
     ===========        ===========        ===========        ===========
     <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
          |                  |                  |                  |
      [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
          |                  |                  |                  |
          |                  |                  |                  |
   .......|           .......|           .......|           .......|
   |                  |                  |                  |
   |                  |                  |                  |
   |                  |                  |                  |
   |   Read Latch 0   |   Read Latch 1   |   Read Latch 2   |   Read Latch 3
   |   ===========-   |   ===========-   |   ===========-   |   ===========-
   |   <7654.3210>    |   <7654.3210>    |   <7654.3210>    |   <7654.3210>
   |        |         |        |         |        |         |        |
   |    [Plane 0]     |    [Plane 1]     |    [Plane 2]     |    [Plane 3]
   |        |         |        |         |        |         |        |
   |        |         |        |         |        |         |        |
   | .......|         | .......|         | .......|         | .......|
   | |                | |                | |                | |
   | |                | |                | |                | |
   | |                | |                | |                | |
   | |  Multiplane    | |  Multiplane    | |  Multiplane    | |  Multiplane
   | |  Select Bit    | |  Select Bit    | |  Select Bit    | |  Select Bit
   | |  Definition    | |  Definition    | |  Definition    | |  Definition
   | |  ===========   | |  ===========   | |  ===========   | |  ===========
   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>   | |  <7654.3210>
   | |       |        | |       |        | |       |        | |       |
   | |  [All Planes]  | |  [All Planes]  | |  [All Planes]  | |  [All Planes]
   | |       |        | |       |        | |       |        | |       |
   | |       |        | |       |        | |       |        | |       |
   | | ......|        | | ......|        | | ......|        | | ......|
   | | |              | | |              | | |              | | |
   | | |              | | |              | | |              | | |
   | | |              | | |              | | |              | | |
 Every output       Every output       Every output       Every output
 bit selected       bit selected       bit selected       bit selected
 using choice       using choice       using choice       using choice
 for that bit       for that bit       for that bit       for that bit
 ===========-       ===========-       ===========-       ===========-
 <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
      |                  |                  |                  |
      |  Plane 0         |  Plane 1         |  Plane 2         |  Plane 3
      |  Inhibit         |  Inhibit         |  Inhibit         |  Inhibit
      |   Write          |   Write          |   Write          |   Write
      |  =======         |  =======         |  =======         |  =======
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
     -----------        -----------        -----------        -----------
     Write Logic        Write Logic        Write Logic        Write Logic
     for Plane 0        for Plane 1        for Plane 2        for Plane 3
       Memory             Memory             Memory             Memory
     -----------        -----------        -----------        -----------




         Key to schematic for Write Mode 2
         =================================


         --------------------------
         Multiplane Function Select
         --------------------------

             See {6.06.05} Data Rotate Register.


         --------------------------------
         Multiplane Select Bit Definition
         --------------------------------

             See {6.06.10} Bit Mask Register.


         -----------------------
         Plane 'N' Inhibit Write
         -----------------------

             See {6.04.04} Map Mask Register.




         Write Mode 3
         ============

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         Processor write data is not used directly to determine image data in
         this mode.  Instead the eight bit data written from the processor is
         interpreted as a bit map with each bit corresponding to one pixel in
         multiplane image memory.  The value of the bit determines the result
         of a computation which ultimately provides the new pixel value to be
         associated with the bit.

         This computation permits a pixel to take on the value for background
         colour or the value for foreground colour depending upon the written
         bit value from the processor associated with the pixel.  This allows
         for modifying selected portions of an image by means of relative use
         of colour.  That is, the image can be modified such that the changes
         are visible no matter what the previous underlying image colours. In
         this way, important data can be written without fear of occlusion.

         Write mode 3 processes for relative colour.  By contrast, write mode
         0 should be seen as processing in terms of absolute colour.

         Processor data for write arrive as an 8 bit wide value.  These 8 bits
         are rotated.  The rotated bits are logically ANDed with eight bits of
         a register specially provided for purposes of specifying which pixels
         are to be modified, at a given image memory address.  The result then
         provides pixel modify permission for 8 pixels as an 8 bit wide value.
         This modify permission value is used later.

         The four eight bit read latch outputs associated with the four image
         memory planes are formed into four data paths, one per memory plane.
         These data paths are used as input to a logic unit, described later.

         Each of four bits in a specially provided register are used to define
         the value of all eight bits of a data path associated with one memory
         plane.  In this way, four bits define four data paths, and every data
         path consists of eight bits, all of which share the same value. There
         is a data path associated with each of the four memory image planes.

         These result data paths are then operated upon by a logic unit with
         capability to perform combining operations with corresponding eight
         bit contents of four read latches, one each per image memory plane.
         The read latches must be well defined for this processing to be of
         any value.  The combining operations are NO_OP, AND, OR, XOR.  The
         NO_OP passes the data through unchanged, ignoring read latch data.

         Thereafter, each plane in parallel has the result of the previously
         described processing combined with the contents of the read latches
         according to the pixel modify permission bits derived above.  These
         determine whether a pixel is preserved, or changed.  {We assume the
         read latches were loaded from the same pixel group currently being
         modifed.  Since the read latch data need not be defined this way it
         is prudent to point out the assumption.}

         This combining operation selects for each image plane data path, and
         for each of eight bits in one data path, the value of the processing
         path bit or the value of the read latch bit, in identical position.
         The selection is based on all eight bits of a permission value used
         specially for just this purpose.  This permission applies to all the
         memory image planes, but affects only the corresponding bit position
         in each plane.  Therefore each permission bit applies to four bits,
         each of identical bit number in each image memory plane.  These four
         bits will all take their value from the same data path chosen by the
         common permission bit.  Note that a data path is associated with one
         memory plane only.  This means that despite sharing a permission bit
         the resulting bits in each plane will be of distinct value.  This is
         a direct result of maintaining each data path in strict association
         with one single memory plane at all times.

         The output from this operation is another 32 bit wide data path, made
         up of four eight bit wide paths, one for each of four image planes.
         This final output data is written in a single write operation to each
         corresponding image plane in parallel, subject to plane write inhibit
         state.  Each plane can be write inhibited in complete independance of
         any other plane.  A write inhibit state prevents any write operations
         from modifying data within the corresponding image plane.

         Write mode 3 processes for relative colour.  By contrast, write mode
         0 should be seen as processing in terms of absolute colour.

         There is no use made of the Set/Reset Enable during operations in
         write mode 3.  However, despite this, the Set/Reset Data register
         provides the value for Data Source in the write mode 3 schematic.
         This value has the dimensions of a colour value but it is used in
         a potentially complex manner.  See schematic below.

         See {6.06.07} Graphics Mode Register.

         See Set/Reset Enable Image Plane 0, below.




         Schematic Overview of Data Path for Write Mode 3
         ================================================
         ================================================




 Processor Data
 ===========---
 <7654.3210>
      |
 [Permission]
      |
      |
      |
      |             Permission
      |             Rotation
      |             Select
      |             ==========-
      |             <7654.3210>
      |                  |
      |             [Permission]
      |                  |
      |                  |
      | .................|
      | |
      | |
      | |
  Data Rotation                            Applicable
  ===========--                            Permission
  <7654.3210>                              Selector
       |                                   ===========
  [Permission]                             <7654.3210>
       |                                        |
       |                                   [Permission]
       |                                        |
       |                                        |
       |...................    .................|
                          |    |
                          |    |
                          |    |
                        Permission
                        Resolution
                        ...AND....
                        ==========
                        <7654.3210>
                             |
                        [Permission]
                             |
                             |
                             |
                             |...............................................
                                                                            |
                                                                            |
  Multiplane                                                                |          |
  Data Source                                                               |            |
  ===========                                                               |            |
  <----.3210>                                                               |            |
        ||||                                                                |
        ||||                                                                |
        ||||......................................................          |
        |||                                                      |          |
        |||                                                      |          |
        |||....................................                  |          |
        ||                                    |                  |          |
        ||                                    |                  |          |
        ||..................                  |                  |          |
        |                  |                  |                  |          |
        |                  |                  |                  |          |
        |                  |                  |                  |          |
    [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]      |
        |                  |                  |                  |          |
        |                  |                  |                  |          |
        |                  |                  |                  |          |
   Repeat bit         Repeat bit         Repeat bit         Repeat bit      |
   value over         value over         value over         value over      |
   all 8 bits         all 8 bits         all 8 bits         all 8 bits      |
   ==========-        ==========         ==========         ==========      |
   <7654.3210>        <7654.3210         <7654.3210         <7654.3210      |
        |                  |                  |                  |          |
    [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]      |
        |                  |                  |                  |          |
        |                  |                  |                  |          |
 .......|           .......|           .......|           .......|          |
 |                  |                  |                  |                 |
 |                  |                  |                  |                 |
 |                  |                  |                  |                 |
 |                  |                  |                  |                 |
 |   Read Latch 0   |   Read Latch 1   |   Read Latch 2   |   Read Latch 3  |
 |   ===========-   |   ===========-   |   ===========-   |   ===========-  |
 |   <7654.3210>    |   <7654.3210>    |   <7654.3210>    |   <7654.3210>   |
 |        |         |        |         |        |         |        |        |
 |    [Plane 0]     |    [Plane 1]     |    [Plane 2]     |    [Plane 3]    |
 |        |         |        |         |        |         |        |        |
 |        |         |        |         |        |         |        |        |
 | .......|         | .......|         | .......|         | .......|        |
 | |                | |                | |                | |               |
 | |                | |                | |                | |               |
 | |                | |                | |                | |               |
 | | Multiplane     | | Multiplane     | | Multiplane     | | Multiplane    |
 | | Function       | | Function       | | Function       | | Function      |
 | | Select         | | Select         | | Select         | | Select        |
 | | ===========    | | ===========    | | ===========    | | ===========   |
 | | <7654.3210>    | | <7654.3210>    | | <7654.3210>    | | <7654.3210>   |
 | |      |         | |      |         | |      |         | |      |        |
 | | [All planes]   | | [All planes]   | | [All planes]   | | [All planes]  |
 | |      |         | |      |         | |      |         | |      |        |
 | |      |         | |      |         | |      |         | |      |        |
 | |      |         | |      |         | |      |         | |      |        |
 | |....  |         | |....  |         | |....  |         | |....  |        |
 |      | |         |      | |         |      | |         |      | |        |
 |      | |         |      | |         |      | |         |      | |        |
 |      | |         |      | |         |      | |         |      | |        |
 |..... | |         |..... | |         |..... | |         |..... | |        |
      | | |              | | |              | | |              | | |        |
      | | |              | | |              | | |              | | |        |
      | | |              | | |              | | |              | | |        |
   Logic Block        Logic Block        Logic Block        Logic Block     |
   ...NO_OP...        ...NO_OP...        ...NO_OP...        ...NO_OP...     |
   ...AND.....        ...AND.....        ...AND.....        ...AND.....     |
   ...OR......        ...OR......        ...OR......        ...OR......     |
   ...XOR.....        ...XOR.....        ...XOR.....        ...XOR.....     |
   ===========        ===========        ===========        ===========     |
   <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>     |
        |                  |                  |                  |          |
    [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]      |
       |                  |                  |                  |           |
       |                  |                  |                  |           |
  .....|             .....|             .....|             .....|           |
  |                  |                  |                  |                |
  |                  |                  |                  |                |
  |                  |                  |                  |                |
  |  Read Latch 0    |  Read Latch 1    |  Read Latch 2    |  Read Latch 3  |
  |  ===========-    |  ===========-    |  ===========-    |  ===========-  |
  |  <7654.3210>     |  <7654.3210>     |  <7654.3210>     |  <7654.3210>   |
  |       |          |       |          |       |          |       |        |
  |   [Plane 0]      |   [Plane 1]      |   [Plane 2]      |   [Plane 3]    |
  |       |          |       |          |       |          |       |        |
  |       |          |       |          |       |          |       |        |
  | ......|          | ......|          | ......|          | ......|        |
  | |                | |                | |                | |              |
  | |                | |                | |                | |              |
  | |                | |                | |                | |              |
  | |      ......... | | .............. | | .............. | | .............P
  | |      |         | |      |         | |      |         | |      |
  | |      |         | |      |         | |      |         | |      |
  | |      P         | |      P         | |      P         | |      P
 Every output       Every output       Every output       Every output
 bit selected       bit selected       bit selected       bit selected
 using choice       using choice       using choice       using choice
 for that bit       for that bit       for that bit       for that bit
 ===========-       ===========-       ===========-       ===========-
 <7654.3210>        <7654.3210>        <7654.3210>        <7654.3210>
      |                  |                  |                  |
  [Plane 0]          [Plane 1]          [Plane 2]          [Plane 3]
      |                  |                  |                  |
      |                  |                  |                  |
      |                  |                  |                  |
      |  Plane 0         |  Plane 1         |  Plane 2         |  Plane 3
      |  Inhibit         |  Inhibit         |  Inhibit         |  Inhibit
      |   Write          |   Write          |   Write          |   Write
      |  =======         |  =======         |  =======         |  =======
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
      |     |            |     |            |     |            |     |
    -----------        -----------        -----------        -----------
    Write Logic        Write Logic        Write Logic        Write Logic
    for Plane 0        for Plane 1        for Plane 2        for Plane 3
      Memory             Memory             Memory             Memory
    -----------        -----------        -----------        -----------




         Key to schematic for Write Mode 3
         =================================


         --------------------------
         Permission Rotation Select
         --------------------------

             See {6.06.05} Data Rotate Register.


         ------------------------------
         Applicable Permission Selector
         ------------------------------

             See {6.06.10} Bit Mask Register.


         ----------------------
         Multiplane Data Source
         ----------------------

             See {6.06.02} Set/Reset Register.



         --------------------------
         Multiplane Function Select
         --------------------------

             See {6.06.05} Data Rotate Register.


         -----------------------
         Plane 'N' Inhibit Write
         -----------------------

             See {6.04.04} Map Mask Register.




<1>      Set/Reset Data Image Plane 1
         ----------------------------

         As for Set/Reset Image Plane 0, immediately above.

         See Set/Reset Enable Image Plane 1, below.


<2>      Set/Reset Data Image Plane 2
         ----------------------------

         As for Set/Reset Image Plane 0, immediately above.

         See Set/Reset Enable Image Plane 2, below.


<3>      Set/Reset Data Image Plane 3
         ----------------------------

         As for Set/Reset Image Plane 0, immediately above.

         See Set/Reset Enable Image Plane 3, below.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.06.03  Enable Set/Reset Register    { 3cfh    01h    R/W }
=======  ===================================================


Cross reference with {6.06.02} Set/Reset Register.


<0>      Set/Reset Enable Image Plane 0
         ------------------------------

         During multiplane image memory write access operation by the processor
         this bit helps to determine the value written to the byte lying within
         display memory image plane 0.

         <=0>  Image plane zero is disabled from accepting any set/reset data,
               so long as the plane is able to support this operation.

               See {6.06.02} Set/Reset Register.

         <=1>  Image plane zero is enabled to accept set/reset data, so long as
               the plane is able to support this operation.

               See {6.06.02} Set/Reset Register.


         The precise effect of this bit is determined by the write mode used to
         perform the update operation.  There are four different write modes as
         follows:


         Write Mode 0
         ============

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         Where Set/Reset Enable Image Plane 0 is set <=1>, all eight data path
         bits associated with image plane 0 are set to just one value given by
         the single bit Set/Reset Data Image Plane 0.  All other memory planes
         are processed in an identical manner.  Four output data paths result,
         each of eight bits width, making a total of 32 bits.  These data path
         outputs are then subjected to further processing, before any data are
         actually stored in image memory.

         The use of the Set/Reset Enable and Set/Reset Data input is to specify
         a four bit colour value across a single bit position within all planes
         of the image memory, in parallel.  In this way, the processor supplied
         data is either used unchanged, is modified partially, or is completely
         ignored when deciding how to process for update.  The resulting output
         is used by the logic unit together with the read latch contents.  This
         provides extremely powerful colour processing capability when properly
         used.  This write mode is probably the most generally used write mode.

         A schematic for write mode 0 is available.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


         Write Mode 1
         ============

         There is no use made of this bit value for write mode 1 operations.

         A schematic for write mode 1 is available.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


         Write Mode 2
         ============

         There is no use made of this bit value for write mode 2 operations.

         A schematic for write mode 2 is available.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


         Write Mode 3
         ============

         There is no use made of this bit value for write mode 3 operations.

         A schematic for write mode 3 is available.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


<1>      Set/Reset Enable Image Plane 1
         ------------------------------

         As for Set/Reset Enable Image Plane 0, immediately above.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


<2>      Set/Reset Enable Image Plane 2
         ------------------------------

         As for Set/Reset Enable Image Plane 0, immediately above.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.



<3>      Set/Reset Enable Image Plane 3
         ------------------------------

         As for Set/Reset Enable Image Plane 0, immediately above.

         See {6.06.02} Set/Reset Register.
         See {6.06.07} Graphics Mode Register.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.06.04  Colour Compare Register      { 3cfh    02h    R/W }
=======  ===================================================


Cross reference with {6.06.06} Read Map Select Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.09} Colour Don't Care Register.


<0>      Colour Compare Plane 0
         ----------------------

         During multiplane image memory read access operation by the processor,
         this bit can determine the value of the byte representing the result
         returned to the processor.

         <=0>  Image plane zero is compared with the data value 0, so long as
               the plane is enabled to support this operation.

               See {6.06.09} Colour Don't Care Register.

         <=0>  Image plane zero is compared with the data value 1, so long as
               the plane is enabled to support this operation.

               See {6.06.09} Colour Don't Care Register.

         The effect of this bit is determined by the read mode used to perform
         the image memory read access operation.  Two different read modes are
         provided as follows:


         Read Mode 0
         ===========

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         When read mode 0 is active, a read operation by the processor returns
         a single byte, which is associated with one of the four image planes.  The plan
         The particular image plane is selected by means of a special register
         provided specifically for this purpose.

         See {6.06.06} Read Map Select Register.
         See {6.06.07} Graphics Mode Register.

         In read mode 0, the Colour Compare Register plays no active role in
         processor read operation so the value of the Colour Compare Plane 0
         bit is irrelevant.


         Read Mode 1
         ===========

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         It is often required to determine where the border pixels of an area
         are situated, perhaps in order to provide a colour fill function for
         a graphics software package.  Usually in such a situation, either of
         the colours associated with the foreground or background are a known
         constant.  The business of discovering the border pixels becomes one
         of tracing a region consisting of pixels with a known colour.

         There is a way of doing this, using read mode 0 to recover the four
         bytes of colour plane data at a given image memory address.  But it
         would then be necessary to change those four bytes into eight pixels
         each of 4 bits.  Whilst this is computationally simple, it is a very
         time consuming operation to perform, especially with large images.

         This is where read mode 1 can provide assistance.  Read mode 1 uses
         a colour match specification to inspect an eight pixel image memory
         address in parallel, producing a colour match bit for each pixel in
         the result byte.  A matching colour produces a set bit result.

         The match value for any plane can be made irrelevant by using a mask
         value for the plane indicating a colour match don't care.  Any don't
         care planes are considered to match under all circumstances.  So for
         some colour ranges it is possible to obtain sensible match behaviour
         even though the match result is expressed in a single bit.

         See {6.06.07} Graphics Mode Register.
         See {6.06.09} Colour Don't Care Register.


<1>      Colour Compare Plane 1
         ----------------------

         As for Colour Compare Plane 0, immediately above.

         See {6.06.06} Read Map Select Register.
         See {6.06.09} Colour Don't Care Register.


<2>      Colour Compare Plane 2
         ----------------------

         As for Colour Compare Plane 0, immediately above.

         See {6.06.06} Read Map Select Register.
         See {6.06.09} Colour Don't Care Register.


<3>      Colour Compare Plane 3
         ----------------------

         As for Colour Compare Plane 0, immediately above.

         See {6.06.06} Read Map Select Register.
         See {6.06.09} Colour Don't Care Register.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.06.05  Data Rotate Register         { 3cfh    03h    R/W }
=======  ===================================================


Cross reference with {6.06.02} Set/Reset Register.


<2..0>   Data Rotate
         -----------

         This binary value specifies the data rotate count for the following
         write modes {0,3}.  The rotation is to the right.

         There is a description of these modes available with a schematic of
         the data flow.

         See {6.06.02} Set/Reset Register.


<4..3>   Logic Unit Function Code
         ------------------------

         This binary field specifies the logic unit function code.  There are
         two data path inputs to the logic unit, each of which contains image
         memory plane data for each of the four memory planes.  One plane has
         eight data bits associated with it, making 32 bits total for each of
         two input data paths.  So the logic unit combines 64 input bits with
         a corresponding output of 32 result bits.

         The logic function always takes one input data path to be the memory
         read latches, with the other input depending on the particular write
         mode selected.

         The logic unit functions are effective in the following write modes
         {0,2,3} and are assigned as follows:

         <=00>  NO_OP.  No operation, the data passes straight through.  No use
                        is made of the read latch data input to the logic unit,
                        but THE READ LATCHES ARE UPDATED WITH THE DATA.

         <=01>  AND.    Logical AND, bit position for bit position between the
                        input data path and the read latch data path.

         <=10>  OR.     Logical OR, bit position for bit position between the
                        input data path and the read latch data path.

         <=11>  XOR.    Logical XOR, bit position for bit position between the
                        input data path and the read latch data path.

         See {6.06.02} Set/Reset Register.


<7..5>   Reserved.  Always <=000>.
         -------------------------




6.06.06  Read Map Select Register     { 3cfh    04h    R/W }
=======  ===================================================


Cross reference with {6.06.04} Colour Compare Register.
Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.10.09} CPU Latch Read Back Register.



<1..0>   Read Map Select
         ---------------

         The binary value of this field represents the multiplane image memory
         plane from which the processor will read a byte of pixel data when in
         read mode 0.  The actual effect depends upon the display image memory
         organisation as follows:


         Processor Image Memory Access Mapping Select
         =-------------------------------------------

              Processor Image Memory Access Mode Select
         =    =----------------------------------------

                   Processor Display Memory Addressing
         =    =    ===================================------------------


         0    0    Text access; odd/even mode; the low order address bit
                   selects the pair of planes to access.  Even addresses
                   select the pair (0,2) and odd addresses (1,3).

                   In all other respects the memory organisation remains
                   multiplane.

                   Data transfers are by word from the processor in this
                   memory mode, with a character code and attribute byte
                   sent together.  Memory planes 2,3 are write inhibited
                   to preserve the character font data in plane 2.

                   The Read Map Select field bit 0 is not used for this
                   memory mode.  The remaining bit 1 selects a plane in
                   the pair of planes determined by the access address,
                   for read mode 0.


         0    1    Multiplane access; the planes are written by using a
                   write mode and read using a read mode.  The plane is
                   selected by means of special registers used by these
                   read and write modes.  This organisation supports 16
                   colours, with 8 pixels per byte across 4 planes at a
                   single image memory byte address.

                   Data transfers are single byte from the processor in
                   this memory mode.

                   The Read Map Select field denotes the plane number to
                   be read by a read mode 0 access, in this memory mode.
                   Planes 0 through 3 are therefore accessible.


         1    0    The two low order address bits are the plane address;
                   the remaining address bits are shifted down to become
                   a byte address into multiplane memory.  This supports
                   256 colour packed pixel mode, where a byte represents
                   the colour data for a single pixel.

                   Data transfers are single byte from the processor in
                   this memory mode.

                   All two bits of the Read Map Select field are ignored
                   in this memory mode, for read mode 0 access.


         1    1    The two low order address bits are the plane address;
                   the remaining address bits are shifted down to become
                   a byte address into multiplane memory.  This supports
                   256 colour packed pixel mode, where a byte represents
                   the colour data for a single pixel.

                   Data transfers are single byte from the processor in
                   this memory mode, for read mode 0 access.

                   All two bits of the Read Map Select field are ignored
                   in this memory mode.


         ---------------------------------------------------------------


         See {6.04.06} Sequencer Memory Mode Register.
         See {6.06.07} Graphics Mode Register.

         This field decides which cpu data latch to access during a cpu latch
         read back operation.  Each cpu data latch is associated with an image
         memory plane.

         See {6.10.09} CPU Latch Read Back Register.

         This field does not have any influence over processor read operations
         in read mode 1.  These are colour compare read operations.

         See {6.06.04} Colour Compare Register.
         See {6.06.07} Graphics Mode Register.


<7..2>   Reserved.  Always <=000000>.
         ----------------------------




6.06.07  Graphics Mode Register       { 3cfh    05h    R/W }
=======  ===================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.04.04} Map Mask Register.
Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.06.02} Set/Reset Register.
Cross reference with {6.06.03} Enable Set/Reset Register.
Cross reference with {6.06.04} Colour Compare Register.
Cross reference with {6.06.05} Data Rotate Register.
Cross reference with {6.06.06} Read Map Select Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.06.09} Colour Don't Care Register.
Cross reference with {6.06.10} Bit Mask Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.07.20} Colour Plane Enable Register.
Cross reference with {6.07.21} Horizontal PEL Panning Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.09} CPU Latch Read Back Register.


<1..0>   Processor Write Mode
         --------------------

         The display may be used in either text mode or graphics mode.
         See {6.06.08} Miscellaneous Register.

         There is capability provided to read back the data written to
         the display image memory data latches by the processor.

         See {6.10.09} CPU Latch Read Back Register.


         <=00>  Write Mode 0
                ------------

                This write mode is used to process absolute colour values, when
                image memory is in multiplane format.  There are many possible
                types of image processing operations which can be achieved with
                this write mode, which permits processor modification of any of
                one through eight pixels per single access.  The data might be
                stored in any of one to four image memory planes some or all of
                which may be modified simultaneously as the result of one write
                operation by the processor.  This write mode is the most often
                used, because of the great flexibility it provides.  It is most
                suitable for writing text whilst in graphics mode, which is one
                of the most demanding operations the processor can perform with
                a multiplane image.  In this write mode the read latch contents
                have a very important role in either preserving existing memory
                background image content, or in establishing a new background.

                However, because there are so many processing operations which
                are carried out in parallel, sometimes considerable thought is
                required to produce the best results from this mode.  Otherwise
                it is easy to program simply by ignoring most of the available
                processing power.  If this approach is adopted, it is possible
                to implement improved graphics algorithms as they are developed
                provided always that simple functional interfaces are used with
                the graphics software components.

                This is an absolute colour processing update operation, whereas
                write mode 3 provides for relative colour update operation.

                There is a discussion of write mode 0 available, together with
                a schematic of the data flow invlved.

                See {6.06.02} Set/Reset Register.

                A discussion of graphics shift register configuration with data
                flow schematics is available.

                See {6.04.03} Clocking Mode Register.
                See table below.
                See schematic diagrams below.

                The registers used in this mode are as follows.

                See {6.04.04} Map Mask Register.
                See {6.06.02} Set/Reset Register.
                See {6.06.03} Enable Set/Reset Register.
                See {6.06.05} Data Rotate Register.
                See {6.06.10} Bit Mask Register.


         <=01>  Write Mode 1
                ------------

                Write mode 1 provides the facilities for fast multiplane memory
                image movement and initialisation.  This write mode ignores all
                data written by the processor.  Instead it uses the associated
                addresses generated by the processor, together with the type of
                memory access (read, write) to control the internal processing
                carried out by the VGA controller.  In this manner, great speed
                of processing is achieved, since all internal data paths are 32
                bits wide.

                The processing ability possessed by this mode is minimal which
                means that in practise, it is very easy to set up for use.  In
                this way, it is a practical mode for use in high speed program
                operation, with important application where large images must
                be updated using predefined image components.  Such components
                are generally held in a library, which is located within a part
                of the display image memory which is not displayed directly.

                The fast copy ability of this mode can replicate such standard
                image parts wherever they are needed, with low overhead.

                There is a discussion of write mode 1 available, together with
                a schematic of the data flow invlved.

                See {6.06.02} Set/Reset Register.

                The registers used in this mode are as follows.

                See {6.04.04} Map Mask Register.


         <=10>  Write Mode 2
                ------------

                This mode can write from one upto eight pixels with a processor
                specified colour, when in multiplane image memory format.  This
                enables complex colour change image updates to take place where
                the processor must determine colour according to possibly quite
                sophisticated criteria.  The read latch contents are important
                in this mode for specifying the image for regions which are not
                directly being modified.  The read latches may either be given
                a single value, which is then subsequently used for many write
                operations, or may be initialised immediately prior to a write
                in order to preserve existing image data.

                This mode can be used in line drawing where the colour of the
                line must be changed frequently.  It can also be used to fill
                an area with colour.  As logic operations can be performed in
                this mode, it can find application in image animation.

                There is a discussion of write mode 2 available, together with
                a schematic of the data flow invlved.

                See {6.06.02} Set/Reset Register.

                A discussion of graphics shift register configuration with data
                flow schematics is available.

                See {6.04.03} Clocking Mode Register.
                See table below.
                See schematic diagrams below.

                The registers used in this mode are as follows.

                See {6.04.04} Map Mask Register.
                See {6.06.05} Data Rotate Register.
                See {6.06.10} Bit Mask Register.


         <=11>  Write Mode 3
                ------------

                Write mode 3 provides the capability for processing an image
                according to the current colour data existing in that image.

                The colour value for each pixel is processed by the logic unit
                and the processor supplied data is then used to determine what
                data source to use for the new pixel colour value.  The effect
                is to selectively preserve or update the current pixel colour.

                This type of processing is useful for update operations which
                must guarantee that all new image data written must be visible
                no matter what the colour distribution in the existing image.

                This is a relative colour processing update operation, whereas
                write mode 0 provides for absolute colour update operation.

                There is a discussion of write mode 3 available, together with
                a schematic of the data flow invlved.

                See {6.06.02} Set/Reset Register.

                A discussion of graphics shift register configuration with data
                flow schematics is available.

                See {6.04.03} Clocking Mode Register.
                See table below.
                See schematic diagrams below.

                The registers used in this mode are as follows.

                See {6.04.04} Map Mask Register.
                See {6.06.02} Set/Reset Register.
                See {6.06.05} Data Rotate Register.
                See {6.06.10} Bit Mask Register.


<2>      Reserved.  Always <=0>.
         -----------------------


<3>      Processor Read Mode
         -------------------

         <=0>  Read Mode 0
               -----------

               This read mode returns a byte of pixel data from one of the four
               image memory planes in multiplane image format.  Each plane has
               responsibility for storing one bit of colour data for each pixel
               so a byte gives the setting of one colour bit over eight pixels.

               Sometimes it is useful to read data from just one of the planes,
               so that functionality is provided by read mode 0.  Any read will
               load the read latches from each of the four image memory planes
               when read mode 0 is operational.  This happens despite the fact
               that only one plane will deliver data to the processor.  Latches
               are selected for processor read using a special register.

               See {6.06.06} Read Map Select Register.

               When the logic unit is used during a write mode, it is possible
               to arrange for the read latches to be updated as a result of a
               NO_OP function code.

               See {6.06.02} Set/Reset Register.

               There is another discussion of read mode 0 available.

               See {6.06.04} Colour Compare Register.


         <=1>  Read Mode 1
               -----------

               This read mode provides for deciding on the colour value for a
               group of eight neighbouring pixels.  The four colour bits that
               make up each pixel are compared with a predetermined colour.

               The result of the comparison process over eight pixels is given
               as an eight bit byte, indicating whether or not the colour was
               present for each pixel.

               There are provisions for indicating that certain image planes
               are to be ignored for comparison purposes, and this read mode
               gives a considerable speed advantage for some operations such
               as colour fill.  Without read mode 1, colour boundary search
               operations would be extremely slow to execute.

               See {6.06.09} Colour Don't Care Register.

               Note that the image memory organisation must be multiplane if
               read mode 1 is to function.  A processor read using read mode
               1 will load all four read latches identically with the colour
               compare result.  This provides a way of initialising the read
               latches within a single processor instruction.

               If the colour don't care register is set to zero, the colour
               compare is guaranteed to succeed, independantly of the pixel
               data.  This will generate a full byte result where every bit
               is set to one.  In addition the all bits set pattern appears
               in all four read latches.  This can be very useful when used
               with a processor instruction which performs an image address
               read access, then performs a corresponding write access.  An
               example of this could be:

                   ;
                   ; Demonstrate multiple access to image memory when using
                   ; read mode 1 in order to initialise the read latches to
                   ; a value of all ones.
                   ;

                   and      [bx],al

                   ;
                   ; End example
                   ;

               In this example, the logical operation uses the image memory
               addressed through register 'bx' for both read and write.  In
               reading the image memory, the read latches are filled with 1
               bits, since the colour don't care register is set to zeros.

               The processor then combines this all bits set value with the
               value of register 'al', producing no change from that value.
               This value is then sent to the VGA controller using whatever
               write mode is in force which then stores the image memory at
               the same address previously accessed for read.

               It is also possible to arrange loading the read latches with 0
               bits, by using a colour don't care register value of all ones.
               It is also necessary to set the colour compare register to one
               particular colour value which is never used.  Then all compare
               operations will fail resulting in each read latch being set to
               all zero bits.

               Note that there are other ways of initialising the read latch
               registers.  It can be useful to write into image memory those
               initial values which will commonly be used.  These values can
               then be read prior to any image manipulation.  Until the read
               latches are modified by another processor read operation, the
               value they possess remains unchanged.  This property provides
               for writing fast executing software, since the problem with a
               separate initialisation on each write is the overhead of data
               bus speed (which is relatively low).

               When the logic unit is used during a write mode, it is possible
               to arrange for the read latches to be updated as a result of a
               NO_OP function code.

               See {6.06.02} Set/Reset Register.

               There is another discussion of read mode 1 available.

               See {6.06.04} Colour Compare Register.


<4>      Graphics Memory Access Mode
         ---------------------------

         <=0>  Graphics Memory Access Mode.  In graphics mode the image memory
               planes respond to addresses from the processor in parallel.  In
               this way, all four memory planes can be read or written using a
               single access.  The processor data transfer supports only 8 bit
               transfers, so various mechanisms are employed to map the 8 bits
               to each of the four bytes actually accessed.  In some cases, it
               is not necessary to perform any mapping of this type at all, as
               the processor is used only to generate an address which is then
               used internally for image manipulation.

               The manipulation is specified in advance and all that is needed
               is a stream of processor generated addresses to put the process
               into operation.  This type of operation is very fast to execute.
               It is discussed during the description of write mode 1.

               See {6.06.02} Set/Reset Register.

               Processor Image Memory Access Mapping Select must be set to zero
               for this setting to be effective.  See below.

               See {6.06.07} Graphics Mode Register.

         <=1>  Text Memory Access Mode.  This affects a data transfer from the
               processor to the image memory such that it is suitable for text
               mode operations.  The processor transfers 16 bits per access to
               image memory in text mode.  The data consists of a character in
               the current character set together with an attribute byte which
               exterts control over the character presentation on the display.

               For text mode display character codes occupy image memory plane
               zero with attribute data occupying plane one.  The image memory
               planes are paired (0,1) and (2,3).  The Text Memory Access Mode
               directs even address accesses to planes (0,2), with odd address
               accesses directed to planes (1,3).  In this way maximum ease of
               access is provided for textual data update.  This is sometimes
               termed odd/even mode.

               To use this mode effectively it is usual to disable writes to a
               pair of planes so permitting update to a two plane pair.

               See {6.04.04} Map Mask Register.

               Only processor writes to image memory are affected by this mode.
               That is, image memory organisation continues to be multiplane in
               all respects except as described above during write addressing.


         This option setting should be reflected in the setting applied within
         the sequencer, Processor Image Memory Access Mode Select.  Note these
         bits are of opposite sense.

         See {6.04.06} Sequencer Memory Mode Register.


<5>      Graphics Shift Register Mode
         ----------------------------

         <=0>  Normal shift register operation.  This is only available when
               the Graphics 256 Colour Control is set <=0>.  See table below
               for full details.

               A number of shift registers can be loaded together at one time
               which affords powerful possibilities.  The shift registers can
               change their interconnection when this occurs so as to support
               a number of different types of image generation.  See below.

               See {6.04.03} Clocking Mode Register.

         <=1>  The shift registers support 4 colour packed pixel mode.  This
               is only available when the Graphics 256 Colour Control is set
               <=0>.  See table below for full details.

               A number of shift registers can be loaded together at one time
               which affords powerful possibilities.  The shift registers can
               change their interconnection when this occurs so as to support
               a number of different types of image generation.  See below.

               See {6.04.03} Clocking Mode Register.


<6>      Graphics 256 Colour Control
         ---------------------------

         <=0>  The Graphics Shift Register Mode, above, controls the operation
               of the shift registers.  See table below for full details.

               A number of shift registers can be loaded together at one time
               which affords powerful possibilities.  The shift registers can
               change their interconnection when this occurs so as to support
               a number of different types of image generation.  See below.

               See {6.04.03} Clocking Mode Register.

         <=1>  The shift registers support the 256 colour packed pixel mode so
               the Graphics Shift Register Mode, above, performs no function.

               This option connects the shift registers so that 4 bits are sent
               together to a special register, then another 4 bits are received
               by that register, making 8 bits in total.  These 8 bits give the
               full colour code needed to represent 256 colours.  Since these 8
               bits are assembled from two 4 bit fields, it takes twice as long
               to create each 8 bit colour value as it would take to issue each
               4 bit colour value.  For this reason, the effective frequency of
               the dot clock is halved in this mode.  To produce a display with
               equivalent high resolution to a 16 colour multiplane display the
               dot clock frequency must be doubled.

               See {6.04.03} Clocking Mode Register.
               See table below for full details.

               The internal pixel palette is bypassed in this mode, due to two
               bits being transmitted in sequence from each of the four planes
               output lines.  This multiplexing prohibits the possibility that
               the internal colour palette could exert any colour control over
               the display.  However each of the shift register outputs should
               be enabled, so that the two bits can be safely transmitted into
               the shift register assembly latches.

               See {6.07.20} Colour Plane Enable Register.
               See table below.
               See schematic diagrams below.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.

               A number of shift registers can be loaded together at one time
               which affords powerful possibilities.  The shift registers can
               change their interconnection when this occurs so as to support
               a number of different types of image generation.  See below.

               See {6.04.03} Clocking Mode Register.


<7>      Reserved.  Always <=0>.
         -----------------------




         Shift Register Mode Control Summary
         ===================================


         Graphics 256 Colour Control
         =--------------------------


              Graphics Shift Register Mode
         =    =---------------------------


                   Colour Output Bit Plane Number
         =    =    =-----------------------------


                        Shift Register Operation Specification
         =    =    =    ======================================----------------


         =    =    =    shift direction    ------------------>    [output bit]


                        Bit 0         Bit 2         Bit 4         Bit 6
         =    =    =    ====-         ====-         ====-         ====-

                               Bit 1         Bit 3         Bit 5         Bit 7
         =    =    =           ====-         ====-         ====-         ====-


         =    =    =    ====   ====   ====   ====   ====   ====   ====   ====


         -------------------- multiplane 16 colour mode ---------------------

         0    0    0    p0b0   p0b1   p0b2   p0b3   p0b4   p0b5   p0b6   p0b7

                   1    p1b0   p1b1   p1b2   p1b3   p1b4   p1b5   p1b6   p1b7

                   2    p2b0   p2b1   p2b2   p2b3   p2b4   p2b5   p2b6   p2b7

                   3    p3b0   p3b1   p3b2   p3b3   p3b4   p3b5   p3b6   p3b7


         -------------------- packed pixel 4 colour mode --------------------

         0    1    0    p1b0   p1b2   p1b4   p1b6   p0b0   p0b2   p0b4   p0b6

                   1    p1b1   p1b3   p1b5   p1b7   p0b1   p0b3   p0b5   p0b7

                   2    p3b0   p3b2   p3b4   p3b6   p2b0   p2b2   p2b4   p2b6

                   3    p3b1   p3b3   p3b5   p3b7   p2b1   p2b3   p2b5   p2b7


         -------------------- packed pixel 256 colour mode ------------------

         1    0    0    p3b0   p3b4   p2b0   p2b4   p1b0   p1b4   p0b0   p0b4

                   1    p3b1   p3b5   p2b1   p2b5   p1b1   p1b5   p0b1   p0b5

                   2    p3b2   p3b6   p2b2   p2b6   p1b2   p1b6   p0b2   p0b6

                   3    p3b3   p3b7   p2b3   p2b7   p1b3   p1b7   p0b3   p0b7


         -------------------- packed pixel 256 colour mode ------------------

         1    1    0    p3b0   p3b4   p2b0   p2b4   p1b0   p1b4   p0b0   p0b4

                   1    p3b1   p3b5   p2b1   p2b5   p1b1   p1b5   p0b1   p0b5

                   2    p3b2   p3b6   p2b2   p2b6   p1b2   p1b6   p0b2   p0b6

                   3    p3b3   p3b7   p2b3   p2b7   p1b3   p1b7   p0b3   p0b7


         ------------------------------------------------------------------


         When the shift registers are not loaded every character clock, they
         are chained together such that the output from the preceeding shift
         register becomes the input to that of the following shift register.

         See {6.04.03} Clocking Mode Register.

         This organisation changes depending upon the shift register mode, so
         that monochrome bit map, 4 colour packed pixel and 256 colour packed
         pixel displays may be supported.  This organisation change takes the
         individual shift register bits and changes their interconnections so
         that the different functionality required can be supported.

         There are some important consequences of changes to the organisation
         of the shift register bits.  From the diagrams below it will be seen
         that in the rearranged modes, various output bits are not used.  The
         deselection of these bits is under control of a special register for
         just this purpose.  A deselected bit becomes a constant zero output,
         which is necessary to ensure stable indexing into the colour tables.

         See {6.07.20} Colour Plane Enable Register.

         The various organisations are detailed below, in diagramatic form.




         Individual Shift Register Connection, Multiplane 16 colour mode
         ===============================================================




         [Display Address]
         |
         |
         |
         |  [Load Clock]      --  derived from character clock
         |  |
         |  |
         |  |
         |  |  [Shift Clock]  --  dot clock
         |  |  |
         |  |  |
         |  |  |
         |  |  sc..........................................
         |  |  |                                          |       _______
         |  |  |                   Memory Plane 3         |...>...Shift 3
         |  lc...................>.| [plane 3, bit 7]...........>.| [7]
         |  |  |                   | [plane 3, bit 6].........>...| [6]
         |  |  |                   | [plane 3, bit 5]...........>.| [5]
         da......................>.| [plane 3, bit 4].........>...| [4]
         |  |  |                   | [plane 3, bit 3]...........>.| [3]
         |  |  |                   | [plane 3, bit 2].........>...| [2]
         |  |  |                   | [plane 3, bit 1]...........>.| [1]
         |  |  |                   | [plane 3, bit 0].........>...| [0]
         |  |  |                                                     |
         |  |  |                                                     |
         |  |  sc....................................                |
         |  |  |                                    |       _______  |
         |  |  |             Memory Plane 2         |...>...Shift 2  |
         |  lc.............>.| [plane 2, bit 7]...........>.| [7]    |
         |  |  |             | [plane 2, bit 6].........>...| [6]    |
         |  |  |             | [plane 2, bit 5]...........>.| [5]    |
         da................>.| [plane 2, bit 4].........>...| [4]    |
         |  |  |             | [plane 2, bit 3]...........>.| [3]    |
         |  |  |             | [plane 2, bit 2].........>...| [2]    |
         |  |  |             | [plane 2, bit 1]...........>.| [1]    |
         |  |  |             | [plane 2, bit 0].........>...| [0]    |
         |  |  |                                               |     |
         |  |  |                                               |     |
         |  |  sc..............................                |     |
         |  |  |                              |       _______  |     |
         |  |  |       Memory Plane 1         |...>...Shift 1  |     |
         |  lc.......>.| [plane 1, bit 7]...........>.| [7]    |     |
         |  |  |       | [plane 1, bit 6].........>...| [6]    |     |
         |  |  |       | [plane 1, bit 5]...........>.| [5]    |     |
         da..........>.| [plane 1, bit 4].........>...| [4]    |     |
         |  |  |       | [plane 1, bit 3]...........>.| [3]    |     |
         |  |  |       | [plane 1, bit 2].........>...| [2]    |     |
         |  |  |       | [plane 1, bit 1]...........>.| [1]    |     |
         |  |  |       | [plane 1, bit 0].........>...| [0]    |     |
         |  |  |                                         |     |     |
         |  |  |                                         |     |     |
         |  |  sc........................                |     |     |
         |  |                           |       _______  |     |     |
         |  |    Memory Plane 0         |...>...Shift 0  |     |     |
         |  lc.>.| [plane 0, bit 7]...........>.| [7]    |     |     |
         |       | [plane 0, bit 6].........>...| [6]    |     |     |
         |       | [plane 0, bit 5]...........>.| [5]    |     |     |
         da....>.| [plane 0, bit 4].........>...| [4]    |     |     |
                 | [plane 0, bit 3]...........>.| [3]    |     |     |
                 | [plane 0, bit 2].........>...| [2]    |     |     |
                 | [plane 0, bit 1]...........>.| [1]    |     |     |
                 | [plane 0, bit 0].........>...| [0]    |     |     |
                                                   |     |     |     |
                                                   |     |     |     |
                                                   |     |     |     |
                                                   |   Plane   |   Plane
                                                   |   1 Out   |   3 Out
                                                   |           |
                                                 Plane       Plane
                                                 0 Out       2 Out

                                               ===========================

                                                    16 colour output
                                                    delivered at full
                                                    dot clock frequency

                                               ===========================


         Note each of the output bits are associated with a particular image
         plane and each of these shift register output bits can individually
         be enabled or disabled.  This control is exerted by means of a zero
         bit substitution for the data bit that would normally be output.  A
         specially appointed control register is provided for this purpose.

         See {6.07.20} Colour Plane Enable Register.


         -------------------------------------------------------------------




         Individual Shift Register Connection, Packed Pixel 2 colour mode
         ================================================================




         [Display Address]
         |
         |
         |
         |  [Load Clock]      --  derived from character clock
         |  |
         |  |
         |  |
         |  |  [Shift Clock]  --  dot clock
         |  |  |
         |  |  |
         |  |  |
         |  |  sc..........................................
         |  |  |                                          |       ________
         |  |  |                   Memory Plane 3         |...>...Shift 3
         |  lc...................>.| [plane 3, bit 7]...........>.| [7]
         |  |  |                   | [plane 3, bit 6].........>...| [6]
         |  |  |                   | [plane 3, bit 5]...........>.| [5]
         da......................>.| [plane 3, bit 4].........>...| [4]
         |  |  |                   | [plane 3, bit 3]...........>.| [3]
         |  |  |                   | [plane 3, bit 2].........>...| [2]
         |  |  |                   | [plane 3, bit 1]...........>.| [1]
         |  |  |                   | [plane 3, bit 0].........>...| [0]
         |  |  |                                                     |
         |  |  |                                                     |
         |  |  |                                               ......|
         |  |  sc....................................          |     |
         |  |  |                                    |       ___|____ |
         |  |  |             Memory Plane 2         |...>...Shift 2  |
         |  lc.............>.| [plane 2, bit 7]...........>.| [7]    |
         |  |  |             | [plane 2, bit 6].........>...| [6]    |
         |  |  |             | [plane 2, bit 5]...........>.| [5]    |
         da................>.| [plane 2, bit 4].........>...| [4]    |
         |  |  |             | [plane 2, bit 3]...........>.| [3]    |
         |  |  |             | [plane 2, bit 2].........>...| [2]    |
         |  |  |             | [plane 2, bit 1]...........>.| [1]    |
         |  |  |             | [plane 2, bit 0].........>...| [0]    |
         |  |  |                                               |     |
         |  |  |                                               |     |
         |  |  |                                         ......|     |
         |  |  sc..............................          |     |     |
         |  |  |                              |       ___|____ |     |
         |  |  |       Memory Plane 1         |...>...Shift 1  |     |
         |  lc.......>.| [plane 1, bit 7]...........>.| [7]    |     |
         |  |  |       | [plane 1, bit 6].........>...| [6]    |     |
         |  |  |       | [plane 1, bit 5]...........>.| [5]    |     |
         da..........>.| [plane 1, bit 4].........>...| [4]    |     |
         |  |  |       | [plane 1, bit 3]...........>.| [3]    |     |
         |  |  |       | [plane 1, bit 2].........>...| [2]    |     |
         |  |  |       | [plane 1, bit 1]...........>.| [1]    |     |
         |  |  |       | [plane 1, bit 0].........>...| [0]    |     |
         |  |  |                                         |     |     |
         |  |  |                                         |     |     |
         |  |  |                                   ......|     |     |
         |  |  sc........................          |     |     |     |
         |  |                           |       ___|____ |     |     |
         |  |    Memory Plane 0         |...>...Shift 0  |     |     |
         |  lc.>.| [plane 0, bit 7]...........>.| [7]    |     |     |
         |       | [plane 0, bit 6].........>...| [6]    |     |     |
         |       | [plane 0, bit 5]...........>.| [5]    |     |     |
         da....>.| [plane 0, bit 4].........>...| [4]    |     |     |
                 | [plane 0, bit 3]...........>.| [3]    |     |     |
                 | [plane 0, bit 2].........>...| [2]    |     |     |
                 | [plane 0, bit 1]...........>.| [1]    |     |     |
                 | [plane 0, bit 0].........>...| [0]    |     |     |
                                                   |     |     |     |
                                                   |     |     |     |
                                                   |     |     |     |
                                                   |   Plane   |   Plane
                                                   |   1 Out   |   3 Out
                                                   |   [Not ]  |   [Not ]
                                                   |   [Used]  |   [Used]
                                                   |           |
                                                   |         Plane
                                                   |         2 Out
                                                   |         [Not ]
                                                   |         [Used]
                                                   |
                                                 Plane
                                                 0 Out

                                       ==========================

                                           Monochrome Output
                                           delivered at full
                                           dot clock frequency

                                       ==========================


         Note each of the output bits are associated with a particular image
         plane and each of these shift register output bits can individually
         be enabled or disabled.  This control is exerted by means of a zero
         bit substitution for the data bit that would normally be output.  A
         specially appointed control register is provided for this purpose.

         See {6.07.20} Colour Plane Enable Register.


         -------------------------------------------------------------------




         Individual Shift Register Connection, Packed Pixel 4 colour mode
         ================================================================




         [Display Address]
         |
         |
         |
         |  [Load Clock]      --  derived from character clock
         |  |
         |  |
         |  |
         |  |  [Shift Clock]  --  dot clock
         |  |  |
         |  |  |
         |  |  |
         |  |  sc..........................................
         |  |  |                                          |       ________
         |  |  |                   Memory Plane 3         |...>...Shift 3
         |  lc...................>.| [plane 3, bit 7]...........>.|    [7]
         |  |  |                   | [plane 3, bit 6].........>...| [6] |
         |  |  |                   | [plane 3, bit 5]...........>.|  | [5]
         da......................>.| [plane 3, bit 4].........>...| [4] |
         |  |  |                   | [plane 3, bit 3]...........>.|  | [3]
         |  |  |                   | [plane 3, bit 2].........>...| [2] |
         |  |  |                   | [plane 3, bit 1]...........>.|  | [1]
         |  |  |                   | [plane 3, bit 0].........>...| [0] |
         |  |  |                                                     |  |
         |  |  |                                                     |  |
         |  |  |                                               ......|  |
         |  |  |                                               |        |
         |  |  |                                               |  ......|
         |  |  |                                               |  |
         |  |  sc....................................          |  |
         |  |  |                                    |       ___|__|_
         |  |  |             Memory Plane 2         |...>...Shift 2
         |  lc.............>.| [plane 2, bit 7]...........>.|  | [7]
         |  |  |             | [plane 2, bit 6].........>...| [6] |
         |  |  |             | [plane 2, bit 5]...........>.|  | [5]
         da................>.| [plane 2, bit 4].........>...| [4] |
         |  |  |             | [plane 2, bit 3]...........>.|  | [3]
         |  |  |             | [plane 2, bit 2].........>...| [2] |
         |  |  |             | [plane 2, bit 1]...........>.|  | [1]
         |  |  |             | [plane 2, bit 0].........>...| [0] |
         |  |  |                                               |  |
         |  |  |                                               |  |
         |  |  |                                               |  |
         |  |  |                                         ......e  |
         |  |  |                                         |     |  |
         |  |  |                                         |     |  |
         |  |  |                                         |     e  |
         |  |  |                                         |  ......o...
         |  |  |                                         |  |  e     |
         |  |  |                                         |  |  |     |
         |  |  sc..............................          |  |  |     |
         |  |  |                              |       ___|__|_ |     |
         |  |  |       Memory Plane 1         |...>...Shift 1  |     |
         |  lc.......>.| [plane 1, bit 7]...........>.|  | [7] |     |
         |  |  |       | [plane 1, bit 6].........>...| [6] |  |     |
         |  |  |       | [plane 1, bit 5]...........>.|  | [5] |     |
         da..........>.| [plane 1, bit 4].........>...| [4] |  |     |
         |  |  |       | [plane 1, bit 3]...........>.|  | [3] |     |
         |  |  |       | [plane 1, bit 2].........>...| [2] |  |     |
         |  |  |       | [plane 1, bit 1]...........>.|  | [1] |     |
         |  |  |       | [plane 1, bit 0].........>...| [0] |  |     |
         |  |  |                                         |  |  |     |
         |  |  |                                         |  |  |     |
         |  |  |                                   ......|  |  |     |
         |  |  |                                   |        |  |     |
         |  |  |                                   |  ......|  |     |
         |  |  |                                   |  |        |     |
         |  |  sc........................          |  |        |     |
         |  |                           |       ___|__|_       |     |
         |  |    Memory Plane 0         |...>...Shift 0        |     |
         |  lc.>.| [plane 0, bit 7]...........>.|  | [7]       |     |
         |       | [plane 0, bit 6].........>...| [6] |        |     |
         |       | [plane 0, bit 5]...........>.|  | [5]       |     |
         da....>.| [plane 0, bit 4].........>...| [4] |        |     |
                 | [plane 0, bit 3]...........>.|  | [3]       |     |
                 | [plane 0, bit 2].........>...| [2] |        |     |
                 | [plane 0, bit 1]...........>.|  | [1]       |     |
                 | [plane 0, bit 0].........>...| [0] |        |     |
                                                   |  |        |     |
                                                   |  |        |     |
                         ..........................|  |        |     |
                         |                            |        |     |
                         |                ............|        |   Plane
                         |                |                    |   3 Out
                         |                |                    |   2 Out
                         |                |                    |   ODD
                         |                |                    |   [Not ]
                         |                |                    |   [Used]
                         |                |                    |
                         |                |                   Plane
                         |                |                   3 Out
                         |                |                   2 Out
                         |                |                   EVEN
                         |                |                   [Not ]
                         |                |                   [Used]
                         |                |
                       Plane            Plane
                       1 Out            1 Out
                       0 Out            0 Out
                       EVEN             ODD


                     ==========================

                         4 colour output
                         delivered at full
                         dot clock frequency

                     ==========================


         Note each of the output bits are associated with a particular image
         plane and each of these shift register output bits can individually
         be enabled or disabled.  This control is exerted by means of a zero
         bit substitution for the data bit that would normally be output.  A
         specially appointed control register is provided for this purpose.

         See {6.07.20} Colour Plane Enable Register.


         -------------------------------------------------------------------




         Individual Shift Register Connection, Packed Pixel 256 colour mode
         ==================================================================




         [Display Address]
         |
         |
         |
         |  [Load Clock]      --  derived from character clock
         |  |
         |  |
         |  |
         |  |  [Shift Clock]  --  dot clock
         |  |  |
         |  |  |
         |  |  |
         |  |  sc..........................
         |  |  |                          |       ______________
         |  |  |   Memory Plane 3         |...>...Shift 3
         |  lc...>.| [plane 3, bit 0]...........>.|..........[0]
         |  |  |   | [plane 3, bit 1].........>...|.......[1] |
         |  |  |   | [plane 3, bit 2]...........>.|....[2] |  |
         da......>.| [plane 3, bit 3].........>...|.[3] |  |  |
         |  |  |   | [plane 3, bit 4]...........>.|..|..|..|.[4]
         |  |  |   | [plane 3, bit 5].........>...|..|..|.[5] |
         |  |  |   | [plane 3, bit 6]...........>.|..|.[6] |  |
         |  |  |   | [plane 3, bit 7].........>...|.[7] |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  sc..........................          |  |  |  |
         |  |  |                          |       ___|__|__|__|_
         |  |  |   Memory Plane 2         |...>...Shift 2  |  |
         |  lc...>.| [plane 2, bit 0]...........>.|..|..|..|.[0]
         |  |  |   | [plane 2, bit 1].........>...|..|..|.[1] |
         |  |  |   | [plane 2, bit 2]...........>.|..|.[2] |  |
         da......>.| [plane 2, bit 3].........>...|.[3] |  |  |
         |  |  |   | [plane 2, bit 4]...........>.|..|..|..|.[4]
         |  |  |   | [plane 2, bit 5].........>...|..|..|.[5] |
         |  |  |   | [plane 2, bit 6]...........>.|..|.[6] |  |
         |  |  |   | [plane 2, bit 7].........>...|.[7] |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  sc..........................          |  |  |  |
         |  |  |                          |       ___|__|__|__|_
         |  |  |   Memory Plane 1         |...>...Shift 1  |  |
         |  lc...>.| [plane 1, bit 0]...........>.|..|..|..|.[0]
         |  |  |   | [plane 1, bit 1].........>...|..|..|.[1] |
         |  |  |   | [plane 1, bit 2]...........>.|..|.[2] |  |
         da......>.| [plane 1, bit 3].........>...|.[3] |  |  |
         |  |  |   | [plane 1, bit 4]...........>.|..|..|..|.[4]
         |  |  |   | [plane 1, bit 5].........>...|..|..|.[5] |
         |  |  |   | [plane 1, bit 6]...........>.|..|.[6] |  |
         |  |  |   | [plane 1, bit 7].........>...|.[7] |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  |                                     |  |  |  |
         |  |  sc..........................          |  |  |  |
         |  |  |                          |       ___|__|__|__|_
         |  |  |   Memory Plane 0         |...>...Shift 0  |  |
         |  lc...>.| [plane 0, bit 0]...........>.|..|..|..|.[0]
         |     |   | [plane 0, bit 1].........>...|..|..|.[1] |
         |     |   | [plane 0, bit 2]...........>.|..|.[2] |  |
         da......>.| [plane 0, bit 3].........>...|.[3] |  |  |
               |   | [plane 0, bit 4]...........>.|..|..|..|.[4]
               |   | [plane 0, bit 5].........>...|..|..|.[5] |
               |   | [plane 0, bit 6]...........>.|..|.[6] |  |
               |   | [plane 0, bit 7].........>...|.[7] |  |  |
               |                                     |  |  |  |
               |                                     |  |  |  |
               |                                     |  |  |  |
               |                                     |  |  |  |
               |                                ___________________
               |
               |                                 these are the 4
               |                                 plane output bits
               |                                 which have little
               |                                 significance for
               |                                 256 colour mode
               |                                 (see note below)
               |                                ___________________
               |                                     |  |  |  |
               |                                     |  |  |  |
               |                                     |  |  |  |
               |                                     |  |  |  |
           ____|______                               |  |  |  |
           Divide by 2                               |  |  |  |
           | ODD.....|..........................     |  |  |  |
           | EVEN....|.....                    |     |  |  |  |
                          |                    |     |  |  |  |
                          |                    |     |  |  |  |
                          |     ...............|.....a  |  |  |
                          |     |  ............|.....|..b  |  |
                          |     |  |  .........|.....|..|..c  |
                          |     |  |  |  ......|.....|..|..|..d
                          |     |  |  |  |     |     |  |  |  |
                          |     |  |  |  |     |     |  |  |  |
                          |     |  |  |  |     |     |  |  |  |
                          |     |  |  |  |     |     |  |  |  |
                          |    _|__|__|__|_    |    _|__|__|__|_
                          |   |Latch 4 bits    |   |Latch 4 bits
                          |.>.|making 8 bit    |.>.|making 8 bit
                              |256 colours         |256 colours
                               <7><6><5><4>         <3><2><1><0>
                                |  |  |  |           |  |  |  |
                                |  |  |  |           |  |  |  |
                                |  |  |  |           |  |  |  |
                                |  |  |  |           |  |  |  |

                               =================================

                                     256 colour output
                                     delivered at only half
                                     the dot clock frequency

                               =================================




         Important note: the concept of output bits corresponding with each
         display memory image plane is redundant in 256 colour packed pixel
         mode.  Two distinct colour bits flow from each of four output bits
         during the two dot clock period necessary to build an 8 bit colour
         value.  For this reason, the internal colour palette cannot effect
         any colour control for 256 colour packed pixel modes. So that each
         of the four shift register output bits can deliver two colour bits
         making a total of 8 bits per pixel the colour plane outputs should
         all be enabled during 256 colour modes.

         See {6.07.20} Colour Plane Enable Register.


         -------------------------------------------------------------------




6.06.08  Miscellaneous Register       { 3cfh    06h    R/W }
=======  ===================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.04.05} Character Map Select Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.05} Mode Control Register 1.


<0>      Display Generation Mode
         -----------------------

         <=0>  Text Mode
               ---------

               Hardware character generation is invoked for display generation.
               There is no capability to generate graphics in the usual manner
               but a software technique can be used, giving a limited graphics
               capability.  The technique depends upon assigning characters to
               a display area, then re-writing the character fonts assigned to
               those characters.  In this manner a limited graphics capability
               can be supported within a relatively small area of the display.

               The text mode display stores character codes in memory plane 0,
               with their associated attribute bytes in plane 1.  The hardware
               expects character font data to be stored at specified addresses
               in plane 2.  Memory plane 3 is unused in this display mode.

               The main characteristics of this mode are high speed operation,
               with very low associated host processor overhead.  A number of
               separate pages of text can be maintained, and switched between
               at high speed.  This is the ideal mode to employ where no true
               graphics capability is required, other than that provided with
               the specially reserved graphics drawing characters.  Two fonts
               can be used within one display screen, each font consisting of
               256 characters in total.  User defined fonts can be used, when
               occasion demands.

               See {6.04.03} Clocking Mode Register.
               See {6.04.05} Character Map Select Register.
               See {6.05.22} Underline Location Register.

         <=1>  Graphics Mode
               -------------

               The display will be generated with reference to an image memory,
               organised as a collection of pixel data.  There is no capability
               for the support of hardware text generation, but software can be
               written to support multiple character fonts and any size of font
               necessary for the application.

               Display image memory organisation is dependant upon the range of
               colours available for definition of a pixel.  The principle mode
               options include:


                   1.    Multiplane 16 Colour
                         --------------------

                         The display memory is arranged as four parallel planes
                         each of which holds data for eight pixels by splitting
                         four colour bits across four planes.  Each plane gives
                         access to a single byte when presented with an address
                         so with parallel address spaces, each access returns 4
                         bytes.  The 32 bits specify 4 bits of colour data, for
                         each of eight pixels.

                         See {6.06.07} Graphics Mode Register.

                   2.    Packed pixel Monochrome
                         -----------------------

                         The display memory is arranged as a linear array which
                         is addressed in a manner corresponding directly to the
                         screen pixel display.  One bit per pixel specifies any
                         colour required, from a large available palette.  This
                         choice is normally restricted by making black the fore
                         ground colour.  The display image is easily managed as
                         it is of small size.  A large number of distinct pages
                         can be maintained and quickly switched for one another
                         which is very useful for hierarchical design systems.

                         See {6.06.07} Graphics Mode Register.

                   3.    Packed Pixel 4 Colour
                         ---------------------

                         This display mode requires double the amount of memory
                         compared with monochrome mode, but provides 4 colours,
                         which can be much more flexible in some applications.

                         Each pixel is represented by two neighbouring bits, so
                         four pixels are collected together in one byte.  There
                         are special hardware capabilities available, to decode
                         this special colour representation.

                         Since images are still very compact large displays can
                         be manipulated without great memory overhead; a number
                         of distinct pages can be held in memory and swapped at
                         high speed.

                         See {6.06.07} Graphics Mode Register.

                   4.    Packed Pixel 256 Colour
                         -----------------------

                         This display mode ensures the highest image resolution
                         and complexity.  As a result the display memory needed
                         is larger than with any other mode.  This can mean the
                         quantity of data accessed when changing an image is an
                         important determinant of processing speed.  A pixel is
                         represented by a single byte of data.  In this way, it
                         is the simplest mode, from the point of view of memory
                         organisation.

                         See {6.06.07} Graphics Mode Register.


<1>      Memory Plane Pairing Control
         ----------------------------

         <=0>  No plane pairing.  Address bit 0 is not replaced.

         <=1>  Memory planes are paired.  The processor address bit 0 gives the
               plane pair to access.  Even addresses access planes (0,2) whilst
               odd addresses access planes (1,3).  Address bit 0 is replaced by
               a higher order address bit.

         This is similar to Processor Image Memory Access Mode Select.
         See {6.04.06} Sequencer Memory Mode Register.


<3..2>   Memory Map Mode
         ---------------

         This field specifies the mapping of the display image memory into the
         processor memory address space.  This changes the range of processor
         addresses which are recognised as being display memory references.

         <=00>  Host processor address range is {a0000h .. bffffh}.

         <=01>  Host processor address range is {a0000h .. affffh}.

                High resolution graphics controls require this processor map
                for correct operation {Trident 8900 only}.

                See {6.10.05} Mode Control Register 1.

         <=10>  Host processor address range is {b0000h .. b7fffh}.

         <=11>  Host processor address range is {b8000h .. bffffh}.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.06.09  Colour Don't Care Register   { 3cfh    07h    R/W }
=======  ===================================================


Cross reference with {6.06.04} Colour Compare Register.
Cross reference with {6.06.06} Read Map Select Register.
Cross reference with {6.06.07} Graphics Mode Register.


<0>      Colour Don't Care Plane 0
         -------------------------

         During multiplane image memory read access operation by the processor,
         this bit can determine the value of the byte representing the result
         returned to the processor.

         <=0>  Image plane zero data is not actively used for colour comparison
               rather it is considered to have generated an unconditional match
               with the colour data value specified, assuming read mode 1.

               See {6.06.04} Colour Compare Register.

         <=1>  Image plane zero is actively compared with the colour data value
               specified.  The result depends directly on data from this plane,
               assuming read mode 1.

               See {6.06.04} Colour Compare Register.

         The effect of this bit is determined by the read mode used to perform
         the image memory read access operation.  Two different read modes are
         provided as follows:


         Read Mode 0
         ===========

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         When read mode 0 is active, a read operation by the processor returns
         a single byte, which is associated with one of the four image planes.  The plan
         The particular image plane is selected by means of a special register
         provided specifically for this purpose.

         See {6.06.06} Read Map Select Register.
         See {6.06.07} Graphics Mode Register.

         In read mode 0, the Colour Compare Register plays no active role in
         processor read operation so the value of the Colour Compare Plane 0
         bit and the Colour Don't Care Plane 0 bit is irrelevant.


         Read Mode 1
         ===========

         At any single address, each image plane stores one eight bit byte so
         providing for 32 bits total storage spread across four planes.  Each
         bit position on each of the four planes provides a four bit value so
         that 16 colours can be represented.  In this way, eight neighbouring
         pixels are completely described by the 32 bits at a single address.
         This convention for image memory organisation is termed multiplane.

         It is often required to determine where the border pixels of an area
         are situated, perhaps in order to provide a colour fill function for
         a graphics software package.  Usually in such a situation, either of
         the colours associated with the foreground or background are a known
         constant.  The business of discovering the border pixels becomes one
         of tracing a region consisting of pixels with a known colour.

         There is a way of doing this, using read mode 0 to recover the four
         bytes of colour plane data at a given image memory address.  But it
         would then be necessary to change those four bytes into eight pixels
         each of 4 bits.  Whilst this is computationally simple, it is a very
         time consuming operation to perform, especially with large images.

         This is where read mode 1 can provide assistance.  Read mode 1 uses
         a colour match specification to inspect an eight pixel image memory
         address in parallel, producing a colour match bit for each pixel in
         the result byte.  A matching colour produces a set bit result.

         The match value for any plane can be made irrelevant by using a mask
         value for the plane indicating a colour match don't care.  Any don't
         care planes are considered to match under all circumstances.  So for
         some colour ranges it is possible to obtain sensible match behaviour
         even though the match result is expressed in a single bit.

         See {6.06.04} Colour Compare Register.
         See {6.06.07} Graphics Mode Register.


<1>      Colour Don't Care Plane 1
         -------------------------

         As for Colour Don't Care Plane 0, immediately above.

         See {6.06.04} Colour Compare Register.
         See {6.06.07} Graphics Mode Register.


<2>      Colour Don't Care Plane 2
         -------------------------

         As for Colour Don't Care Plane 0, immediately above.

         See {6.06.04} Colour Compare Register.
         See {6.06.07} Graphics Mode Register.


<3>      Colour Don't Care Plane 3
         -------------------------

         As for Colour Don't Care Plane 0, immediately above.

         See {6.06.04} Colour Compare Register.
         See {6.06.07} Graphics Mode Register.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.06.10  Bit Mask Register            { 3cfh    08h    R/W }
=======  ===================================================


Cross reference with {6.06.02} Set/Reset Register.


<0>   Update Value Source Bit 0
      -------------------------

      <=0>  This bit position in all write enabled planes will be sourced from
            the current read latch contents associated with those planes.  The
            interpretation of this bit can be simplified when the read latches
            have been loaded with the original image data.  In that case, this
            option signifies that this pixel number will be write inhibited in
            all four image memory planes.

            This bit is used in write modes (0, 2, 3).

            See {6.06.02} Set/Reset Register.

      <=1>  This bit position in all write enabled planes will be sourced from
            the logic unit output data path associated with those planes.  The
            interpretation of this bit can be simplified when the read latches
            have been loaded with the original image data.  In that case, this
            option signifies that this pixel number will be enabled for write,
            across all the four image memory planes.

            This bit is used in write modes (0, 2, 3).

            See {6.06.02} Set/Reset Register.


<1>   Update Value Source Bit 1
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<2>   Update Value Source Bit 2
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<3>   Update Value Source Bit 3
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<4>   Update Value Source Bit 4
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<5>   Update Value Source Bit 5
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<6>   Update Value Source Bit 6
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.


<7>   Update Value Source Bit 7
      -------------------------

            This bit is used in write modes (0, 2, 3).

            See Update Value Source Bit 0, immediately above.
            See {6.06.02} Set/Reset Register.




6.07  Register specifications: Attribute Controller
====  =============================================


6.07.01  Attribute Address Register       { 3c0h/I/W  3c0h/R  ---  R/W }
=======  ===================================================================


Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.09.04} Input Status Register One.
Cross reference with {6.10.10} Attribute State Read Back Register.
Cross reference with {6.10.11} Attribute Index Read Back Register.


<4..0>   Attribute Address
         -----------------

         The attribute controller address register defines the index number of
         the register in the internal register array.  All reads and writes to
         the attribute controller are made to this selected register.

         Port 3c0h is used for writes to both the Attribute Address Register,
         and to the selected register array index.  Port 3c0h is also used to
         read the Attribute Address Register.  The selected internal register
         index can always be read using port 3c1h.

         In this scheme, port 3c0h is used for writing the index value for the
         internal register access control, and also for writing the value into
         the selected register.  Obviously there must be a means for resolving
         this ambiguity of write access.

         There is an internal state which chooses whether to write the index
         value, or the register being indexed.  This state can be reset with
         a read to port 3?ah {where ? represents either hex 'b' or hex 'd'},
         so that the next write is to the Attribute Address Register rather
         than to an indexed internal register.

         See {6.09.01} Miscellaneous Output Register.
         See {6.09.04} Input Status Register One.

         Having written the Attribute Address (that is, the register index),
         successive writes are to the indexed register, then to the value of
         the index, and so on, alternately.  This is very useful when a word
         is written to port 3c0h, since the first byte controls the index of
         the register, which is then written into by the second byte.

         The internal register index value can be obtained, as can the state
         which determines index access or register access for write purposes.

         See {6.10.10} Attribute State Read Back Register.
         See {6.10.11} Attribute Index Read Back Register.

         Note that no official documentation describes the existance of this
         decode of port 3c1h for such write purposes.  However, the hardware
         does respond correctly in this manner.  This is a standard feature.


<5>      Palette Control
         ---------------

         <=0>  Disable the generation of a video signal, permitting processor
               access to the attribute controller colour registers.  Note the
               display will become unstable, should this option be set whilst
               the active image is being generated.  For this reason vertical
               retrace should be active for the duration of this setting.

         <=1>  Enable video signal generation and prevent processor access to
               the attribute controller colour registers.


<7..6>   Reserved.  Always <=00>.
         ------------------------




6.07.02  Palette Register 00              { 3c0h/I/W  3c1h/R  00h  R/W }
=======  ===================================================================


Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.07.03} Palette Register 01.
Cross reference with {6.07.04} Palette Register 02.
Cross reference with {6.07.05} Palette Register 03.
Cross reference with {6.07.06} Palette Register 04.
Cross reference with {6.07.07} Palette Register 05.
Cross reference with {6.07.08} Palette Register 06.
Cross reference with {6.07.09} Palette Register 07.
Cross reference with {6.07.10} Palette Register 08.
Cross reference with {6.07.11} Palette Register 09.
Cross reference with {6.07.12} Palette Register 10.
Cross reference with {6.07.13} Palette Register 11.
Cross reference with {6.07.14} Palette Register 12.
Cross reference with {6.07.15} Palette Register 13.
Cross reference with {6.07.16} Palette Register 14.
Cross reference with {6.07.17} Palette Register 15.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.07.20} Colour Plane Enable Register.
Cross reference with {6.07.22} Colour Select Register.
Cross reference with {6.08.01} DAC Pixel Mask Register.
Cross reference with {6.08.05} DAC Data Register.


<5..0>   Colour Value
         ------------

         This binary field expresses the value of an index into the DAC colour
         table.  {DAC is an acronym for Digital to Analogue Converter.}  A DAC
         converts eight bit digital colour information to analogue red, green,
         blue information from which all required colours can be mixed.  There
         is a great deal of context surrounding colour generation, which needs
         to be understood before the palette operation can become clear.

         The manner in which pixel colour is converted into display colour is
         actually non-trivial, offering powerful control facilities which are
         suitable for high speed animation.  We now describe all the features
         for colour control of an image working forewards from the pixel data
         and backwards from the displayed colours.

         The size of a pixel in bits determines the range of colours which can
         be generated within any displayed image.  However, the actual colours
         displayed can be composed from a very wide range of possible colours.

         To see how this can be, we look at the DACs which generate colour out
         to the display unit.  Each DAC accepts 8 bits of digital code thereby
         producing 8 bits of analogue signal into one of the three colour guns
         in the display tube.  So all combinations of three 8 bit colours will
         give a colour spectrum of 24 bits resolution. This gives a full range
         of 16_777_216 colours in total.

         The three DAC units accept 8 bit digital colour code from a specially
         designed memory unit, which stores for each of 256 addresses, 24 bits
         of colour data.  Each 24 bit block contains three groups of eight bit
         colour data, associated respectively with the red green and blue DAC.
         The 256 addresses can be fully determined with an 8 bit digital code.

         The 256 colour memory unit is termed an external colour palette.  It
         is this palette which governs the true colours actually sent into the
         display unit.  Since the external colour palette converts 8 bit codes
         into displayed colours, it is clear that no display can use more than
         256 distinct colours.

         See {6.08.05} DAC Data Register.

         There is another colour palette memory unit, which provides for just
         16 separate addresses.  This colour palette is the internal palette,
         which is located within the VGA controller.  It is distinguished from
         the external colour palette by being termed simply the colour palette.
         It stores 6 bits of colour data for each of the 16 addresses.  Only 4
         bits of digital code are needed to completely represent 16 addresses.

         Display image memory is split into four separately accessible planes,
         each of which is associated with a shift register, which presents bit
         data to an output bit corresponding with the same plane.  In this way
         data from image memory is converted into a serial data stream so that
         parallel bits in the stream specify a colour to display.

         See {6.06.07} Graphics Mode Register.

         These parallel bits are used to index the colour palette, which gives
         the 4 bits of address needed to completely range over every entry the
         colour palette contains.  As a result of this, the colour palette can
         deliver a 6 bit code output.  This 6 bit code is combined with 2 bits
         from a special register to make the 8 bit code needed by the external
         colour palette to generate real colour signals into the display unit.

         See {6.07.22} Colour Select Register.

         Note that the number of displayed colours is now constrained to 4 bit
         colour specified by pixel representation, rather than the 8 bits used
         as input to the external colour palette.

         That is the overview.  In practise, things can be more involved.

         In multiplane 16 colour mode, the situation is altered slightly by
         virtue of there being a choice of formation of the 8 bit code sent
         into the external colour palette.  The shift register outputs sent
         to the internal colour palette can be individually inhibited.  The
         effect of this is to reduce the number of displayed colours whilst
         increasing the quantity of image information available.  Therefore
         each of the four image memory planes, can be individually selected
         for display.  This display will be monochrome, but 4 images can be
         defined, maintained and rapidly switched between.

         See {6.07.20} Colour Plane Enable Register.

         We will assume for the moment that all 4 colour bits are operational
         so the display will be in 16 colours. There are two separate methods
         for determining how the pixel data becomes display colour.

         The first method mixes just 2 additional bits with the 6 bits output
         from the colour palette.  This provides a three way control for each
         displayed colour.  The two additional bits provide instant selection
         between 4 distinct colour maps, so by modifying these 2 bits, colour
         modification of the entire image will instantly take place.  Also it
         is possible to change the contents of the colour palette so that the
         colours generated change.  External colour palette data changes will
         also alter the displayed image colour at any time but the larger the
         palette, the longer it takes to modify.

         See {6.07.18} Attribute Mode Control Register.
         See {6.07.22} Colour Select Register.

         The second code formation method mixes 4 additional bits with the
         lowest 4 bits from the colour palette output.  This provides more
         capability to instantly change the colour mapping between upto 16
         separate colour assignments, each of a full 16 colours.

         See {6.07.18} Attribute Mode Control Register.
         See {6.07.22} Colour Select Register.

         When the display is generated in 256 colour packed pixel mode the
         shift register outputs become completely divorced from notions of
         image plane association.  Instead, the colour palette is ignored,
         with the shift register outputs driving the 8 bit external colour
         palette inputs directly.  In this case, only by changing the data
         held in the external colour palette can the display colour change
         be effected.  However, there is potential to reduce the number of
         displayed colours, which results in greater ability to change the
         actual colour set displayed.  This happens by means of inhibition
         of some of the 8 bits input to the external colour palette.  When
         only 7 bits are actually in use, changing the bit 7 for bit 8 can
         radically alter the colour display.  If more bits are kept out of
         immediate use, the greater the potential for rapid changes in the
         display colour set.

         See {6.08.01} DAC Pixel Mask Register.


<7..6>   Reserved.  Always <=00>.
         ------------------------




         Schematic Data Flow From Shift Register Outputs to Display Colours
         ==================================================================

         Scheme A:  Colour Select Register provides 2 additional bits.
         =============================================================

         See {6.07.22} Colour Select Register.




         Colour Select
         ===========--
         <----.32-->
               ||
               ||
               ||
               ||            Multiplane
               ||            Shift Register
               ||            Colour Outputs
               ||            ===========---
               ||            <----.3210>
               ||                  ||||
               ||                  ||||
               ||                  ||||
               ||                  ||||
               ||                  ||||          [Internal]
               ||                  ||||          Colour
               ||                  ||||          Palette
               ||                  ||||          ===========
               ||                  ||||     <0>  | 00
               ||                  ||||........>.| 01
               ||                  |||.......>...| 02
               ||                  ||..........>.|  .
               ||                  |.........>...|  .
               ||                           <3>  |  .
               ||                                |  .
               ||                                | 13
               ||                                | 14
               ||                                | 15
               ||                                ===========
               ||                                <--54.3210>
               ||                                   || ||||
               ||                                   || ||||
               ||                                   || ||||
               ||...................................|| ||||
               |...................................||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         DAC Pixel Mask                           |||| ||||
         ===========---                           |||| ||||
         <7654.3210>                              |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                             -------------
          |||| ||||.........................>...| mask bit0 |
          |||| |||........................>.....| mask bit1 |
          |||| ||...........................>...| mask bit2 |
          |||| |..........................>.....| mask bit3 |
          ||||..............................>...| mask bit4 |
          |||.............................>.....| mask bit5 |
          ||................................>...| mask bit6 |
          |...............................>.....| mask bit7 |
                                                -------------
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                [256 Colours]
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         .........................................|||| ||||
         |.........................................||| ||||
         ||.........................................|| ||||
         |||.........................................| ||||
         |||| .........................................||||
         |||| |.........................................|||
         |||| ||.........................................||
         |||| |||.........................................|
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||           External Colour Palette
         |||| ||||           RED        GREEN      BLUE
         |||| ||||      <0>  =================================
         |||| ||||.........>.| 000      | 000      | 000
         |||| |||........>...| 001      | 001      | 001
         |||| ||...........>.| 002      | 002      | 002
         |||| |..........>...|  .       |  .       |  .
         ||||..............>.|  .       |  .       |  .
         |||.............>...|  .       |  .       |  .
         ||................>.|  .       |  .       |  .
         |...............>...| 253      | 253      | 253
                        <7>  | 254      | 254      | 254
                             | 255      | 255      | 255
                             =================================
                             <7654.3210><7654.3210><7654.3210>
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  ==========
                              |||| ||||  |||| ||||  BLUE DAC |
                              |||| ||||  |||| ||||  inputs   |..>......
                              |||| ||||  |||| ||||  ==========        |
                              |||| ||||  ===========                  |
                              |||| ||||  GREEN DAC |                  |
                              |||| ||||  inputs    |..>.........>.... |
                              |||| ||||  ===========                | |
                              =========                             | |
                              RED DAC |                             | |
                              inputs  |..>............>.........>.. | |
                              =========                           | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                 ========
                                                                 Analogue
                                                                  Output
                                                                 ========




         See {6.06.07} Graphics Mode Register.
         See {6.07.22} Colour Select Register.
         See {6.08.01} DAC Pixel Mask Register.




         -------------------------------------------------------------------




         Schematic Data Flow From Shift Register Outputs to Display Colours
         ==================================================================

         Scheme B:  Colour Select Register provides 4 additional bits.
         =============================================================

         See {6.07.22} Colour Select Register.




         Colour Select
         ===========--
         <----.3210>
               ||||
               ||||
               ||||
               ||||          Multiplane
               ||||          Shift Register
               ||||          Colour Outputs
               ||||          ===========---
               ||||          <----.3210>
               ||||                ||||
               ||||                ||||
               ||||                ||||
               ||||                ||||
               ||||                ||||          [Internal]
               ||||                ||||          Colour
               ||||                ||||          Palette
               ||||                ||||          ===========
               ||||                ||||     <0>  | 00
               ||||                ||||........>.| 01
               ||||                |||.......>...| 02
               ||||                ||..........>.|  .
               ||||                |.........>...|  .
               ||||                         <3>  |  .
               ||||                              |  .
               ||||                              | 13
               ||||                              | 14
               ||||                              | 15
               ||||                              ===========
               ||||                              <----.3210>
               ||||                                    ||||
               ||||                                    ||||
               ||||................................... ||||
               |||...................................| ||||
               ||...................................|| ||||
               |...................................||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         DAC Pixel Mask                           |||| ||||
         ===========---                           |||| ||||
         <7654.3210>                              |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                             -------------
          |||| ||||.........................>...| mask bit0 |
          |||| |||........................>.....| mask bit1 |
          |||| ||...........................>...| mask bit2 |
          |||| |..........................>.....| mask bit3 |
          ||||..............................>...| mask bit4 |
          |||.............................>.....| mask bit5 |
          ||................................>...| mask bit6 |
          |...............................>.....| mask bit7 |
                                                -------------
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                [256 Colours]
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         .........................................|||| ||||
         |.........................................||| ||||
         ||.........................................|| ||||
         |||.........................................| ||||
         |||| .........................................||||
         |||| |.........................................|||
         |||| ||.........................................||
         |||| |||.........................................|
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||           External Colour Palette
         |||| ||||           RED        GREEN      BLUE
         |||| ||||      <0>  =================================
         |||| ||||.........>.| 000      | 000      | 000
         |||| |||........>...| 001      | 001      | 001
         |||| ||...........>.| 002      | 002      | 002
         |||| |..........>...|  .       |  .       |  .
         ||||..............>.|  .       |  .       |  .
         |||.............>...|  .       |  .       |  .
         ||................>.|  .       |  .       |  .
         |...............>...| 253      | 253      | 253
                        <7>  | 254      | 254      | 254
                             | 255      | 255      | 255
                             =================================
                             <7654.3210><7654.3210><7654.3210>
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  ==========
                              |||| ||||  |||| ||||  BLUE DAC |
                              |||| ||||  |||| ||||  inputs   |..>......
                              |||| ||||  |||| ||||  ==========        |
                              |||| ||||  ===========                  |
                              |||| ||||  GREEN DAC |                  |
                              |||| ||||  inputs    |..>.........>.... |
                              |||| ||||  ===========                | |
                              =========                             | |
                              RED DAC |                             | |
                              inputs  |..>............>.........>.. | |
                              =========                           | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                 ========
                                                                 Analogue
                                                                  Output
                                                                 ========




         See {6.06.07} Graphics Mode Register.
         See {6.07.22} Colour Select Register.
         See {6.08.01} DAC Pixel Mask Register.




         -------------------------------------------------------------------




         Schematic Data Flow From Shift Register Outputs to Display Colours
         ==================================================================

         Scheme C:  Packed Pixel 256 Colour Format
         =========================================




                                                 Packed Pixel
                                                 Shift Register
                                                 Assembly Latch
                                                 Colour Outputs
                                                 ===========
                                                 <7654.3210>
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         DAC Pixel Mask                           |||| ||||
         ===========---                           |||| ||||
         <7654.3210>                              |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                               |||| ||||
          |||| ||||                             -------------
          |||| ||||.........................>...| mask bit0 |
          |||| |||........................>.....| mask bit1 |
          |||| ||...........................>...| mask bit2 |
          |||| |..........................>.....| mask bit3 |
          ||||..............................>...| mask bit4 |
          |||.............................>.....| mask bit5 |
          ||................................>...| mask bit6 |
          |...............................>.....| mask bit7 |
                                                -------------
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                [256 Colours]
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
                                                  |||| ||||
         .........................................|||| ||||
         |.........................................||| ||||
         ||.........................................|| ||||
         |||.........................................| ||||
         |||| .........................................||||
         |||| |.........................................|||
         |||| ||.........................................||
         |||| |||.........................................|
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||
         |||| ||||           External Colour Palette
         |||| ||||           RED        GREEN      BLUE
         |||| ||||      <0>  =================================
         |||| ||||.........>.| 000      | 000      | 000
         |||| |||........>...| 001      | 001      | 001
         |||| ||...........>.| 002      | 002      | 002
         |||| |..........>...|  .       |  .       |  .
         ||||..............>.|  .       |  .       |  .
         |||.............>...|  .       |  .       |  .
         ||................>.|  .       |  .       |  .
         |...............>...| 253      | 253      | 253
                        <7>  | 254      | 254      | 254
                             | 255      | 255      | 255
                             =================================
                             <7654.3210><7654.3210><7654.3210>
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  |||| ||||
                              |||| ||||  |||| ||||  ==========
                              |||| ||||  |||| ||||  BLUE DAC |
                              |||| ||||  |||| ||||  inputs   |..>......
                              |||| ||||  |||| ||||  ==========        |
                              |||| ||||  ===========                  |
                              |||| ||||  GREEN DAC |                  |
                              |||| ||||  inputs    |..>.........>.... |
                              |||| ||||  ===========                | |
                              =========                             | |
                              RED DAC |                             | |
                              inputs  |..>............>.........>.. | |
                              =========                           | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                  | | |
                                                                 ========
                                                                 Analogue
                                                                  Output
                                                                 ========




         See {6.06.07} Graphics Mode Register.
         See {6.08.01} DAC Pixel Mask Register.




         -------------------------------------------------------------------




6.07.03  Palette Register 01              { 3c0h/I/W  3c1h/R  01h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.04  Palette Register 02              { 3c0h/I/W  3c1h/R  02h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.05  Palette Register 03              { 3c0h/I/W  3c1h/R  03h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.06  Palette Register 04              { 3c0h/I/W  3c1h/R  04h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.07  Palette Register 05              { 3c0h/I/W  3c1h/R  05h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.08  Palette Register 06              { 3c0h/I/W  3c1h/R  06h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.09  Palette Register 07              { 3c0h/I/W  3c1h/R  07h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.10  Palette Register 08              { 3c0h/I/W  3c1h/R  08h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.11  Palette Register 09              { 3c0h/I/W  3c1h/R  09h  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.12  Palette Register 10              { 3c0h/I/W  3c1h/R  0ah  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.13  Palette Register 11              { 3c0h/I/W  3c1h/R  0bh  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.14  Palette Register 12              { 3c0h/I/W  3c1h/R  0ch  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.15  Palette Register 13              { 3c0h/I/W  3c1h/R  0dh  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.16  Palette Register 14              { 3c0h/I/W  3c1h/R  0eh  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.17  Palette Register 15              { 3c0h/I/W  3c1h/R  0fh  R/W }
=======  ===================================================================


Cross reference with {6.07.02} Palette Register 00.


         See {6.07.02} Palette Register 00.




6.07.18  Attribute Mode Control Register  { 3c0h/I/W  3c1h/R  10h  R/W }
=======  ==================================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.04.05} Character Map Select Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.07.02} Palette Register 00.
Cross reference with {6.07.21} Horizontal PEL Panning Register.
Cross reference with {6.07.22} Colour Select Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.04} Mode Control Register 2.


<0>      Display Generation Mode
         -----------------------

         See {6.06.08} Miscellaneous Register.

         <=0>  Text Mode
               ---------

               Hardware character generation is invoked for display generation.
               There is no capability to generate graphics in the usual manner
               but a software technique can be used, giving a limited graphics
               capability.  The technique depends upon assigning characters to
               a display area, then re-writing the character fonts assigned to
               those characters.  In this manner a limited graphics capability
               can be supported within a relatively small area of the display.

               The text mode display stores character codes in memory plane 0,
               with their associated attribute bytes in plane 1.  The hardware
               expects character font data to be stored at specified addresses
               in plane 2.  Memory plane 3 is unused in this display mode.

               The main characteristics of this mode are high speed operation,
               with very low associated host processor overhead.  A number of
               separate pages of text can be maintained, and switched between
               at high speed.  This is the ideal mode to employ where no true
               graphics capability is required, other than that provided with
               the specially reserved graphics drawing characters.  Two fonts
               can be used within one display screen, each font consisting of
               256 characters in total.  User defined fonts can be used, when
               occasion demands.

               See {6.04.03} Clocking Mode Register.
               See {6.04.05} Character Map Select Register.
               See {6.05.22} Underline Location Register.

         <=1>  Graphics Mode
               -------------

               The display will be generated with reference to an image memory,
               organised as a collection of pixel data.  There is no capability
               for the support of hardware text generation, but software can be
               written to support multiple character fonts and any size of font
               necessary for the application.

               Display image memory organisation is dependant upon the range of
               colours available for definition of a pixel.  The principle mode
               options include:


                   1.    Multiplane 16 Colour
                         --------------------

                         The display memory is arranged as four parallel planes
                         each of which holds data for eight pixels by splitting
                         four colour bits across four planes.  Each plane gives
                         access to a single byte when presented with an address
                         so with parallel address spaces, each access returns 4
                         bytes.  The 32 bits specify 4 bits of colour data, for
                         each of eight pixels.

                         See {6.06.07} Graphics Mode Register.

                   2.    Packed pixel Monochrome
                         -----------------------

                         The display memory is arranged as a linear array which
                         is addressed in a manner corresponding directly to the
                         screen pixel display.  One bit per pixel specifies any
                         colour required, from a large available palette.  This
                         choice is normally restricted by making black the fore
                         ground colour.  The display image is easily managed as
                         it is of small size.  A large number of distinct pages
                         can be maintained and quickly switched for one another
                         which is very useful for hierarchical design systems.

                         See {6.06.07} Graphics Mode Register.

                   3.    Packed Pixel 4 Colour
                         ---------------------

                         This display mode requires double the amount of memory
                         compared with monochrome mode, but provides 4 colours,
                         which can be much more flexible in some applications.

                         Each pixel is represented by two neighbouring bits, so
                         four pixels are collected together in one byte.  There
                         are special hardware capabilities available, to decode
                         this special colour representation.

                         Since images are still very compact large displays can
                         be manipulated without great memory overhead; a number
                         of distinct pages can be held in memory and swapped at
                         high speed.

                         See {6.06.07} Graphics Mode Register.

                   4.    Packed Pixel 256 Colour
                         -----------------------

                         This display mode ensures the highest image resolution
                         and complexity.  As a result the display memory needed
                         is larger than with any other mode.  This can mean the
                         quantity of data accessed when changing an image is an
                         important determinant of processing speed.  A pixel is
                         represented by a single byte of data.  In this way, it
                         is the simplest mode, from the point of view of memory
                         organisation.

                         See {6.06.07} Graphics Mode Register.


<1>      Display Generation Mode
         -----------------------

         <=0>  Select colour display attribute definitions for supporting
               colour emulation mode.

         <=1>  Select monochrome display attribute definitions for supporting
               monochrome emulation mode.

         This selection governs the treatment of attribute byte decoding, in
         text mode.  Differences exist in expressive capability of attributes
         depending upon whether monochrome or colour emulation is active.

         To see these differences, consult the specification of the attribute
         byte under both emulation schemes.

         See {6.05.22} Underline Location Register.


<2>      Line Graphics Character Code Control
         ------------------------------------

         <=0>  When using 9 dot character clocks, this option specifies that
               the ninth dot will always be set to the background colour for
               character generation in text mode.  This setting implies that
               there are no special continuous line graphics characters used
               in the character font.

               See {6.04.03} Clocking Mode Register.

         <=1>  When using 9 dot character clocks, and a graphics character is
               to be generated in text mode with a code value between hex 'c0'
               and hex 'df' inclusive the ninth dot will be displayed exactly
               as was the eighth dot.  This provides for character fonts with
               the full eight pixels width, without any problems of merging.

               Where continuous line graphics are used, however, merging must
               occur selectively for all the graphics character codes.  These
               graphic codes are not always present in all character sets, so
               there must be a means to disable them selectively.

               See {6.04.03} Clocking Mode Register.


<3>      Text Mode Attribute Select
         --------------------------

         <=0>  The text mode attribute byte associated with each character for
               display defines bit <7> in one of two different ways: with this
               option selection, bit <7> specifies background intensity.  When
               the intensity bit is set a high background colour luminosity is
               displayed, drawing attention to the foreground text display.

               See {6.05.22} Underline Location Register.

         <=1>  The text mode attribute byte associated with each character for
               display defines bit <7> in one of two different ways: with this
               option selection, bit <7> specifies background blink.  When the
               blink bit is set, the background switches on and off, driven by
               the vertical retrace signal.  In this manner attention is drawn
               to the text display in the foreground.

               See {6.05.22} Underline Location Register.


<4>      Reserved.  Always <=0>.
         -----------------------


<5>      Split Screen Panning Control
         ----------------------------

         <=0>  Scroll both screens horizontally {this is panning} in the same
               manner, as defined by the various control registers.  This has
               utility only when a split screen display is operational.

         <=1>  Scroll only the upper screen {that is upper window} of a split
               screen display in the horizontal direction, leaving the screen
               in the lower position intact.  This only has significance when
               a split screen display creates an upper and lower window.

         See {6.05.10} Preset Row Scan Register.
         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.
         See {6.05.26} Line Compare Register.
         See {6.07.21} Horizontal PEL Panning Register.


<6>      Shift Register 256 Colour Assembly Latch
         ----------------------------------------

         <=0>  The 4 bit shift register output bits are sent for translation
               into the internal 16 address colour palette, producing 6 bits
               of colour output.  These bits are increased to 8 bits through
               various options, and the resulting 8 bit code is presented to
               the external colour palette, which drives the display unit.

               See External Colour Palette Input Select, immediately below.

               This setting should be used for 2 colour, 4 colour, 16 colour
               displays, in either graphics mode or text mode.

               See {6.06.07} Graphics Mode Register.
               See {6.06.08} Miscellaneous Register.

         <=1>  The 4 bit shift register output bits do not go to the internal
               colour palette for translation.  Instead, using two successive
               dot clock periods 4 bits of shift register output are combined
               together to produce one 8 bit pixel colour value.  Every other
               dot clock produces a new 256 colour pixel which is sent direct
               to the external colour palette and thence the display unit.

               This setting should only ever be used to produce packed pixel
               displays supporting 256 colours.  There are implications for
               the dot clock frequency when this mode is employed.

               See {6.06.07} Graphics Mode Register.

               There are controls available to select dot clock frequency and
               dot clock division ratios.

               See {6.09.01} Miscellaneous Output Register.
               See {6.10.04} Mode Control Register 2.


<7>      External Colour Palette Input Select
         ------------------------------------

         <=0>  For all display modes other than 256 colour packed pixel mode,
               this option selects the source of bits <5..4> which are output
               to the external colour palette for driving the display unit.

               With this option, these bits are sourced from the internal
               colour palette output bits <5..4>.  In this case there are
               two bits provided by a register to make up these 6 bits to
               the 8 bits required to drive the external colour palette.

               See {6.07.22} Colour Select Register.

         <=1>  For all display modes other than 256 colour packed pixel mode,
               this option selects the source of bits <5..4> which are output
               to the external colour palette for driving the display unit.

               For this option setting, these bits are sourced from a special
               register provided for the purpose.  This register normally has
               responsibility for providing two additional bits to make the 8
               bit group needed for input to the external colour palette.  In
               this case, the register provides the original two bits with an
               extra two bits, making four in total.  Under this circumstance
               the internal colour palette output is restricted to four bits,
               instead of the usual six bits.  These four bits are the lowest
               significance bits.

               See {6.07.22} Colour Select Register.

         Note that the Shift Register 256 Colour Assembly Latch must be <=0>
         if this option is to have any effect.  See immediately above.

         See Shift Register 256 Colour Assembly Latch, immediately above.
         See {6.06.07} Graphics Mode Register.




6.07.19  Overscan Colour Register         { 3c0h/I/W  3c1h/R  11h  R/W }
=======  ===================================================================


Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.03} Horizontal Display Enable End Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.20} Vertical Display Enable End Register.


<7..0>   Overscan Colour
         ---------------

         At times when the active image is not being produced, and yet there
         is no blanking in progress the external colour palette must produce
         some displayable colour.  The selection of this colour is performed
         by the binary field in this register.

         A discussion of horizontal image scan line generation is available.
         This is appropriate to border colour generation on the boundaries
         of each active image scan line.

         See {6.05.02} Horizontal Total Register.
         See {6.05.03} Horizontal Display Enable End Register.
         See {6.05.04} Start Horizontal Blanking Register.
         See {6.05.05} End Horizontal Blanking Register.
         See {6.05.20} Vertical Display Enable End Register.

         A discussion of vertical timing generation is available.  This is
         useful to appreciate border colour generation during non-active
         image scan line generation.

         See {6.05.08} Vertical Total Register.




6.07.20  Colour Plane Enable Register     { 3c0h/I/W  3c1h/R  12h  R/W }
=======  ===============================================================


Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.07.02} Palette Register 00.
Cross reference with {6.09.04} Input Status Register One.


<0>      Colour Plane Enable 0
         ---------------------

         <=0>  Disable all output from a shift register(s) associated with this
               image memory plane.  The output is set to be a constant zero bit
               to provide a stable input to the colour tables.

         <=1>  Enable shift register(s) output associated with this image plane
               so the data shifted out will provide input to the colour tables.

         There is discussion of shift register operation together with diagrams
         showing shift register data paths and output data paths.

         See {6.06.07} Graphics Mode Register.


<1>      Colour Plane Enable 1
         ---------------------

         <=0>  Disable all output from a shift register(s) associated with this
               image memory plane.  The output is set to be a constant zero bit
               to provide a stable input to the colour tables.

         <=1>  Enable shift register(s) output associated with this image plane
               so the data shifted out will provide input to the colour tables.

         There is discussion of shift register operation together with diagrams
         showing shift register data paths and output data paths.

         See {6.06.07} Graphics Mode Register.


<2>      Colour Plane Enable 2
         ---------------------

         <=0>  Disable all output from a shift register(s) associated with this
               image memory plane.  The output is set to be a constant zero bit
               to provide a stable input to the colour tables.

         <=1>  Enable shift register(s) output associated with this image plane
               so the data shifted out will provide input to the colour tables.

         There is discussion of shift register operation together with diagrams
         showing shift register data paths and output data paths.

         See {6.06.07} Graphics Mode Register.


<3>      Colour Plane Enable 3
         ---------------------

         <=0>  Disable all output from a shift register(s) associated with this
               image memory plane.  The output is set to be a constant zero bit
               to provide a stable input to the colour palette.

         <=1>  Enable shift register(s) output associated with this image plane
               so the data shifted out will provide input to the colour tables.

         There is discussion of shift register operation together with diagrams
         showing shift register data paths and output data paths.

         See {6.06.07} Graphics Mode Register.


<5..4>   Display Status Select
         ---------------------

         This binary field selects two of the eight colour select output bits
         to be read back using the register reserved for this use.  Which are
         selected are detailed by the table below.

         See {6.09.04} Input Status Register One.


         Display Status Select
         =====----------------

                        Input Status Register One, bit 5
         =====          ==------------------------------

                                    Input Status Register One, bit 4
         =====          ==          ==------------------------------


         <=00>          c2          c0

         <=01>          c5          c4

         <=10>          c3          c1

         <=11>          c7          c6


         ------------------------------------------------------------


<7..6>   Reserved.  Always <=00>.
         ------------------------




6.07.21  Horizontal PEL Panning Register  { 3c0h/I/W  3c1h/R  13h  R/W }
=======  ===============================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.26} Line Compare Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.07.18} Attribute Mode Control Register.


<3..0>   Horizontal PEL Panning
         ----------------------

         PEL panning {Picture ELement panning} operates in both graphics mode
         and text mode displays, so it is always operational.  Panning shifts
         the entire display image to the left of the screen loosing pixels on
         the left and introducing new pixels to the right.  It is implemented
         in hardware by missing out pixels at the beginning of a scan line so
         that the scan line active display starts at a point after the actual
         start of image data for the scan line.  This means of course, that a
         scan line to be panned in this way must be wider than the screen, so
         that there is always some data which cannot be displayed.  It is the
         hidden data which is brought into view by the panning process.

         There is a discussion of panning elsewhere, which is concerned with
         byte panning controls which can be used with pixel panning controls
         to achieve continuous, smooth horizontal panning.

         See {6.05.10} Preset Row Scan Register.

         The value provided in order to control pixel panning varies depending
         upon the way the display is generated.  In particular, there may be 8
         or 9 dot clock periods per character clock period.  This reflects the
         fact that in text mode displays, there is a choice for interpretation
         of a character font.  When the full 8 pixel width of a font expresses
         a true 8 pixel width character shape, then an extra pixel must be put
         into the display after each character position, so that characters do
         not merge with each other.  This is the motivation for providing nine
         dot clock periods per character clock.  When a character font ignores
         the 8th pixel, setting it always to the background colour there is no
         need to provide for character separation by hardware.  In this case 8
         dot clock periods per character clock period are all that is required.

         See {6.04.03} Clocking Mode Register.

         The type of graphics display generation scheme also affects the value
         used to control pixel panning operation.  This arises because panning
         is implemented in hardware by means of special shift registers, which
         use the structure of a serial data stream to shift the image.  In the
         most commonly used display mode, 16 colour multiplane mode each pixel
         is represented by one position in the panning shift registers.  Where
         a pixel occupies more than one panning shift register position, shift
         values must change accordingly.  This affects the behaviour of images
         built using 9 dot clocks, and those using packed pixel modes with the
         pixel represented by more than one bit.




         Control Value for Horizontal Pixel Panning
         ===---------------------------------------


                Actual panned distance, in pixels, on screen
         ===    ===============================================================


                Text Mode, 8 dot clock character period
         ===    ===------------------------------------


                       Text Mode, 9 dot clock character period
         ===    ===    ===------------------------------------


                              Multiplane 16 colour mode
         ===    ===    ===    ===----------------------


                                     Packed Pixel 2 colour mode
         ===    ===    ===    ===    ===-----------------------


                                            Packed Pixel 4 colour mode
         ===    ===    ===    ===    ===    ===-----------------------


                                                   Packed Pixel 256 colour mode
         ===    ===    ===    ===    ===    ===    ===-------------------------


          0      0      1 !    0      0      0      0 !

          1      1      2 !    1      1      1      * !

          2      2      3 !    2      2      2      1 !

          3      3      4 !    3      3      3      * !

          4      4      5 !    4      4      4      2 !

          5      5      6 !    5      5      5      * !

          6      6      7 !    6      6      6      3 !

          7      7      8 !    7      7      7      * !

          8      0      0 !    0      0      0      * !


         Notes:
         ======


         !  specifies that this entry is different from the majority of entries
            and that special attention should be given to the entry as a result
            of this.


         *  specifies that the entry is 'not applicable'.  This arises because
            of the way packed pixel 256 colour mode uses two dot clock periods
            to construct an 8 bit colour code.  Each dot clock makes the shift
            registers deliver one packet of 4 bits of colour code.  After each
            two consecutive dot clocks, two four bit packets are combined with
            the required 8 bit colour code as a result.  Therefore a two place
            shift is required per pixel in 256 colour packed pixel mode.  This
            'not applicable' entry should be avoided since it will not produce
            the expected results.

            See {6.06.07} Graphics Mode Register.


         Formulae concerned with 8 dot clock character periods and 9 dot clock
         character periods are as follows:

            left_pan = (number_field + 0) mod 8
            left_pan = (number_field + 1) mod 9

            See {6.04.03} Clocking Mode Register.


         ----------------------------------------------------------------------


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.07.22  Colour Select Register           { 3c0h/I/W  3c1h/R  14h  R/W }
=======  ===============================================================


Cross reference with {6.07.02} Palette Register 00.
Cross reference with {6.07.18} Attribute Mode Control Register.


         The Colour Select Register provides additional colour definition bits
         which are used to increase the either 4 or 6 bits output, produced by
         the internal colour palette, to the 8 colour bits as required for the
         external colour palette input.

         The number of bits produced by the internal colour palette is selected
         by means of a control bit, which also governs the number of bits taken
         from the Colour Select Register.  This is arranged so that there are 8
         bits of resulting colour code, under all circumstances.  This control
         is provided by the bit External Colour Palette Input Select.

         See {6.07.18} Attribute Mode Control Register.

         However, when the packed pixel 256 colour mode is in use, there is no
         need to provide any additional colour data as all 8 bits required for
         input to the external colour palette come directly from display image
         memory.  Then there is no use for the Colour Select Register.  Option
         control is governed by the Shift Register 256 Colour Assembly Latch.

         See {6.07.18} Attribute Mode Control Register.

         A detailed discussion with schematics is available for the data flow
         between the memory image plane shift register outputs and the display
         unit analogue colour inputs.

         See {6.07.02} Palette Register 00.


<1..0>   External colour palette bits <5..4>
         -----------------------------------

         In all display generation modes except packed pixel 256 colour mode,
         these bits are always available for optional use, controlled by the
         Attribute Mode Control Register.  When selected for use, these bits
         replace the internal colour palette output bits <5..4> becoming the
         bits <5..4> input to the external colour palette.

         See {6.07.18} Attribute Mode Control Register.


<3..2>   External colour palette bits <7..6>
         -----------------------------------

         In all display generation modes except packed pixel 256 colour mode,
         these bits are always available for unconditional use.  They become
         bits <7..6> input to the external colour palette.

         See {6.07.02} Palette Register 00.


<7..4>   Reserved.  Always <=0000>.
         --------------------------




6.08  Register specifications: DAC Support Logic
====  ==========================================


6.08.01  DAC Pixel Mask Register          { 3c6h   R/W }
=======  ===============================================


Cross reference with {6.07.02} Palette Register 00.
Cross reference with {6.08.02} DAC Status Register.


<0>      DAC Pixel Mask 0 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         The shift registers produce an output stream of width dependant upon
         the display generation mode in use.  No matter what this data output
         width actually is, ultimately it will be expanded into the 8 bits of
         colour data required as input by the external colour palette.  Where
         it is required that a reduction in addressing into this 256 location
         memory be put into effect, it is possible to substitute zero bits in
         place of specified colour input bits.  The substitution is permitted
         or disabled by means of this DAC Pixel Mask Register, with a bit for
         bit control correspondance.

         <=0>  Send zero into the external colour palette at this input bit
               position.

         <=1>  Permit colour data at this input bit position to flow freely
               into the external colour palette.

         A detailed discussion of colour generation is available, with data
         flow schematics.

         See {6.07.02} Palette Register 00.

         By selectively enabling and disabling individual colour select bits,
         an image can be manipulated for different colour sets very rapidly.
         Also, multiple images can be associated with different colour data,
         and combined in different ways using this masking control technique.

         Note that if the external colour palette is correctly initialised it
         is possible to associate multiple images with identical colour sets,
         thereby making multiple image animation sequences possible.  This is
         possible only by using identical colour definitions, repeated across
         many distinct addresses.

         For operational purposes it should be noted that accesses to the
         DAC Pixel Mask Register are not relevant for DAC Status Register
         purposes.

         See {6.08.02} DAC Status Register.


<1>      DAC Pixel Mask 1 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<2>      DAC Pixel Mask 2 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<3>      DAC Pixel Mask 3 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<4>      DAC Pixel Mask 4 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<5>      DAC Pixel Mask 5 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<6>      DAC Pixel Mask 6 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.


<7>      DAC Pixel Mask 7 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------------------

         As for DAC Pixel Mask 0 above.




6.08.02  DAC Status Register              { 3c7h   R-- }
=======  ===============================================


Cross reference with {6.08.01} DAC Pixel Mask Register.
Cross reference with {6.08.03} DAC Read Data Address Register.
Cross reference with {6.08.04} DAC Write Data Address Register.
Cross reference with {6.08.05} DAC Data Register.


<1..0>   DAC Status
         ----------

         <=00>  The last access to the DAC Data Register was a processor write
                access.

         <=01>  This value significance is not assigned.

         <=10>  This value significance is not assigned.

         <=11>  The last access to the DAC Data Register was a processor read
                access.

         This binary field indicates the type of transaction last performed by
         the processor on the DAC Data Register.  This information can be used
         in a situation when an interrupt routine periodically writes into the
         external colour palette, to modify the colour data held there.  After
         such a write sequence has been completed in the interrupt routine, it
         is important that any read or write activity which was in progress at
         the time of the interrupt is restored transparently.  In practise, an
         interrupt routine might well need to read and write colour data; this
         situation is taken care of equally well by the DAC Status Register if
         it is correctly used.

         See {6.08.05} DAC Data Register.

         An interrupt routine executes without synchronisation to main program
         code.  This program could read from or write to the DAC Data Register
         at any time, so when the interrupt occurs, the transaction state with
         the DAC Data Register is effectively unknown.  Despite this, any such
         trnsaction must be permitted to continue undisturbed, after interrupt
         program execution is complete.

         It is this problem which the DAC Status Register is designed to give
         the solution to.

         When the interrupt program gains control, there could be either of a
         read transaction or a write transaction in progress from the program
         which was executing immediately prior to the interrupt.  Whilst this
         program would typically be the main program it could also be another
         interrupt program, assigned to a different, lower interrupt level.

         The first job the newly entered interrupt program must perform is to
         secure the status of that program which has just had control wrested
         from it.  This involves determining which type of transaction was in
         progress at the time of interrupt.  By using the DAC Status Register
         an indication is given as to the type of transaction, which was last
         in progress.  This transaction might well be complete or it could be
         still in progress.  This point is unknown but does not matter if the
         object is only to preserve the status of the DAC Data Register.

         Any read or write sequence involving the DAC Data Register begins by
         means of a write from the processor into either of the two registers
         DAC Read Data Address Register, or DAC Write Data Address Register.
         This write to a particular address register is used to associate the
         DAC Data Register with the appropriate transaction type, either read
         or write.  It is also used to specify which of the address registers
         should be associated with the autoincrement capability that provides
         for long transfers of one type without need to update the addressing
         register for that transaction type.

         The read address is initialised prior to any read sequence, with the
         write address set prior to any write sequence.  During that sequence
         the relevant address register is updated automatically, so that long
         data transfers in either direction can occur without the overhead of
         resetting the address register.  This makes for fast program running
         times and eases programming overheads.

         However, after any other transaction type is used, the autoincrement
         feature is switched off.  This means that writing a value to another
         address register or performing a transaction of the opposite type is
         sufficient to switch off autoincrement to the address register being
         presently used.  This has the effect of freezing an address register
         which in turn provides for recovering the present contents and later
         reinstating them, for example, after an interrupt has completed.

         It should now be clear that for an interrupt program to preserve any
         existing read or write sequence on the DAC Data Register it is quite
         enough to determine the last transaction type, and then to read from
         the associated address register the current read or write address in
         use by the previously executing program.  After the interrupt, there
         is no difficulty in restoring the DAC Data Register program state by
         using the preserved value from interrupt entry time.

         See {6.08.03} DAC Read Data Address Register.
         See {6.08.04} DAC Write Data Address Register.

         For operational purposes it should be noted that accesses to the
         DAC Pixel Mask Register are not relevant for DAC Status Register
         purposes.

         See {6.08.01} DAC Pixel Mask Register.


<7..2>   Reserved.  Always <=000000>.
         ----------------------------




6.08.03  DAC Read Data Address Register   { 3c7h   W-- }
=======  ===============================================


Cross reference with {6.08.02} DAC Status Register.
Cross reference with {6.08.04} DAC Write Data Address Register.
Cross reference with {6.08.05} DAC Data Register.


<7..0>   DAC Read Data Address
         ---------------------

         This binary field determines the initial value for the address index
         into the external colour palette, at which processor reads will take
         place.  The external colour palette contains 256 distinct addresses,
         each of which holds three colour values of up to 8 bits each for the
         colours read, green and blue.  Typically either 6 bits or 8 bits for
         each colour intensity are provided, depending upon the hardware.

         Setting a new DAC Read Data Address value has the effect of freezing
         the current value of the DAC Write Data Address, and also associates
         the address autoincrement operation with the read transaction on the
         DAC Data Register.

         See {6.08.04} DAC Write Data Address Register.
         See {6.08.05} DAC Data Register.

         At this point, the processor can perform three read transactions on
         the DAC Data Register, after which an automatic increment will make
         the address point to the next group of three intensity values.  The
         possibility of an interrupt occuring during this 3 consecutive read
         sequence must be taken into account as the hardware state cannot be
         interrogated to discover which of the three colours was the last to
         be transferred.  In practise, most programs adopt a policy eshewing
         use of interrupts during the three colour data transfer.  This will
         effectively prevent such a transfer from being interrupted, and the
         problems of an unknown hardware transfer state simply disappear.

         The current read address can be discovered at any time, by virtue of
         a read on the DAC Write Data Address Register.  This is necessary to
         recover the hardware state at time of entry to an interrupt routine.

         See {6.08.04} DAC Write Data Address Register.

         The address register in use {either read or write} can also be found
         by using a special status register.

         See {6.08.02} DAC Status Register.




6.08.04  DAC Write Data Address Register  { 3c8h   R/W }
=======  ===============================================


Cross reference with {6.08.02} DAC Status Register.
Cross reference with {6.08.03} DAC Read Data Address Register.
Cross reference with {6.08.05} DAC Data Register.


<7..0>   DAC Write Data Address
         ----------------------

         This binary field determines the initial value for the address index
         into the external colour palette at which processor writes will take
         place.  The external colour palette contains 256 distinct addresses,
         each of which holds three colour values of up to 8 bits each for the
         colours read, green and blue.  Typically either 6 bits or 8 bits for
         each colour intensity are provided, depending upon the hardware.

         Updating the DAC Write Data Address value has the effect of freezing
         the current value of the DAC Read Data Address which also associates
         the address autoincrement feature with any write transaction, to the
         DAC Data Register.

         See {6.08.03} DAC Read Data Address Register.
         See {6.08.05} DAC Data Register.

         At this point the processor can perform three write transactions on
         the DAC Data Register, after which an automatic increment will make
         the address point to the next group of three intensity values.  The
         possibility of an interrupt occuring during these three consecutive
         writes must be carefully considered as the hardware state cannot be
         interrogated to discover which of the three colours was the last to
         be transferred.  In practise, most programs adopt a policy eshewing
         use of interrupts during the three colour data transfer.  This will
         effectively prevent such a transfer from being interrupted, and the
         problems of an unknown hardware transfer state simply disappear.

         The current write address can be discovered at any time by virtue of
         a read on the DAC Write Data Address Register.  This is necessary to
         recover the hardware state at time of entry to an interrupt routine.

         See {6.08.04} DAC Write Data Address Register.

         The address register in use {either read or write} can also be found
         by using a special status register.

         See {6.08.02} DAC Status Register.




6.08.05  DAC Data Register                { 3c9h   R/W }
=======  ===============================================


Cross reference with {6.07.02} Palette Register 00.
Cross reference with {6.08.02} DAC Status Register.
Cross reference with {6.08.03} DAC Read Data Address Register.
Cross reference with {6.08.04} DAC Write Data Address Register.


<7..0>   DAC Data
         --------

         All processor read and write operations which transfer colour values
         to and from the external colour palette are implemented using access
         to this register.  The actual read or write address accessed is that
         specified in the address register for either read or write functions.

         See {6.08.03} DAC Read Data Address Register.
         See {6.08.04} DAC Write Data Address Register.

         The external colour palette accepts an 8 bit value which ranges over
         256 separate addresses.  Each address stores three colour values for
         red, green and blue intensities, respectively.  Since each colour is
         of either 6 or 8 bits width to completely access all the colour data
         at any given address, 3 byte sized transfers are used, in the strict
         order red, green, blue.  The processor must issue 3 consecutive read
         or write transactions to complete the access to the data at a single
         address.  This can mean in practise that during the 3 byte transfer,
         interrupts remain inhibited so that no indeterminate length accesses
         can occur, so avoiding the hardware entering an unknown state.

         To prevent the hardware entering an unknown state, all transactions
         must first determine the current transaction type and address, then
         initialise the relevent read or write address register fro the type
         of intended transaction, before proceeding.

         The current access address can be discovered at any time by means of
         a read on the DAC Write Data Address Register.  This is necessary to
         recover the hardware state at time of entry to an interrupt routine.

         See {6.08.04} DAC Write Data Address Register.

         The address register in use {either read or write} can also be found
         by using a special status register.  This is sometimes necessary for
         purposes of determining the hardware state at the time of activation
         of an interrupt routine.

         See {6.08.02} DAC Status Register.

         A discussion of the role of the external colour palette is available
         elsewhere.

         See {6.07.02} Palette Register 00.




6.09  Register specifications: General Registers
====  ==========================================


6.09.01  Miscellaneous Output Register  { 3c2h  W-- }
=======  ============================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.05.01} CRT Controller Address Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.07.01} Attribute Address Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.09.02} Miscellaneous Output Register.
Cross reference with {6.09.04} Input Status Register One.
Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register is subject to write protection through option setting.
         The whole register is affected.

         See {6.10.07} CRTC Module Testing Register.

         This register can be read back using a different input output port
         address provided specially for this purpose.

         See {6.09.02} Miscellaneous Output Register.


<0>      Input Output Address Select
         ---------------------------

         <=0>  Select the CRT Controller input/output port address to be
               hex '3b?', where '?' is some hex digit.

               See {6.05.01} CRT Controller Address Register.

               Also select the Input Status Register One port address to
               hex '3ba'.

               See {6.09.04} Input Status Register One.

         <=1>  Select the CRT Controller input/output port address to be
               hex '3d?', where '?' is some hex digit.

               See {6.05.01} CRT Controller Address Register.

               Also select the Input Status Register One port address to
               hex '3da'.

               See {6.09.04} Input Status Register One.


<1>      Display Memory Access Enable
         ----------------------------

         This control can be used to prevent image memory from responding
         to processor generated addresses, in circumstances where another
         device is (temporarily) enabled for the same address span.

         <=0>  Disable processor access to display image memory.

         <=1>  Enable processor access to display image memory.

         There are controls available to select the address range employed
         for processor access to display image memory.

         See {6.06.08} Miscellaneous Register.


<3..2>   Dot Clock Frequency Select
         --------------------------

         Dot clock selection controls horizontal pixel resolution and also
         character clock generation.  The clock frequency control modifies
         the dot clock period in conjunction with a programmable dot clock
         division ratio select.  This resulting dot clock is then used for
         character clock definition.  The character clock specifies a scan
         line period, which in turn determines the frame period for a full
         image display to be produced.  This frame period then decides the
         display refresh rate.  The dot clock is a master timing reference.

         <=00>  Clock select 25.175 MHz clock for
                640 total Horizontal Pixels.

         <=01>  Clock select 28.322 MHz clock for
                720 total Horizontal Pixels.

         <=10>  Clock select external user clock
                up to a maximum of 65.000 MHz.

         <=11>  Clock select external user clock
                up to a maximum of 65.000 MHz.

         See {6.04.03} Clocking Mode Register
         See {6.05.02} Horizontal Total Register.
         See {6.05.08} Vertical Total Register.
         See {6.06.07} Graphics Mode Register.
         See {6.10.04} Mode Control Register 2.


<4>      Reserved.  Always <=0>.
         -----------------------


<5>      Address Extension Bit
         ---------------------

         <=0>  Select the low 64K page.

         <=1>  Select the high 64K page.

         This bit is the 64K page bit for the Text Memory Access Mode.  For
         more details consult Processor Image Memory Access Mode Select.

         See {6.04.06} Sequencer Memory Mode Register.

         This option controls processor access to display image memory, and
         offers a larger number of possible display pages in text mode.  It
         is only used in conjunction with text mode displays.

         See {6.06.08} Miscellaneous Register.


<6>      Horizontal Synchronisation Signal Polarity
         ------------------------------------------

         This polarity with Vertical Synchronisation Signal Polarity, below,
         encodes the vertical scan line count for the display unit.  This is
         an aid to the display unit, in helping to select the vertical frame
         rate.  See table below.

         <=0>  Positive horizontal retrace signal select.

         <=1>  Negative horizontal retrace signal select.


<7>      Vertical Synchronisation Signal Polarity
         ----------------------------------------

         This polarity with Horizontal Synchronisation Signal Polarity below
         encodes the vertical scan line count for the display unit.  This is
         an aid to the display unit, in helping to select the vertical frame
         rate.  See table below.

         <=0>  Positive vertical retrace signal select.

         <=1>  Negative vertical retrace signal select.




         Encoding of Vertical Scan Line Count for Display Unit
         =====================================================


         Vertical Synchronisation Signal Polarity
         =---------------------------------------

              Horizontal Synchronisation Signal Polarity
         =    =-----------------------------------------

                   Vertical Display Size
         =    =    ===----------------------------------------


         0    0    reserved, not used at present

         0    1    400 scan lines

         1    0    350 scan lines

         1    1    480 scan lines


         -----------------------------------------------------




6.09.02  Miscellaneous Output Register  { 3cch  --R }
=======  ============================================


Cross reference with {6.09.01} Miscellaneous Output Register.


<7..0>   Miscellaneous Output
         --------------------

         This is a read only register, provided for use with the write
         only Miscellaneous Output Register.

         The value in this register can be written using the different
         input output port address provided for this purpose.

         See {6.09.01} Miscellaneous Output Register.




6.09.03  Input Status Register Zero     { 3c2h  R-- }
=======  ============================================


Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.09.04} Input Status Register One.
Cross reference with {10.02}   Monitor auto-detection operation.


<3..0>   Reserved.  Always <=0000>.
         --------------------------


<4>      Monitor Detect Status Bit
         -------------------------

         <=0>  There is a high video signal current flowing at this time.  This
               is a real-time scan line status, which comes directly from video
               DAC output measurement.

         <=1>  There is a low video signal current flowing at this time.  This
               is a real-time scan line status which comes directly from video
               DAC output measurement.

         This read only bit provides an indication of the video signal current
         flow into a display unit during active video signal generation.  This
         provides information to determine which of a monochrome display unit,
         or a colour display unit is connected to the image generator.  Use of
         this bit is in practise non-trivial, as is described elsewhere.  This
         is a facility which must only be used when the original documentation
         from the VGA subsystem manufacturer is available.

         See {10.02} Monitor auto-detection operation.


<6..5>   Reserved.  Always <=00>.
         ------------------------


<7>      CRT Controller Interrupt State
         ------------------------------

         <=0>  There is no current vertical retrace interrupt active, which is
               because there really is no vertical retrace at present, or this
               status is itself permanently inactive through option selection.

               See {6.05.19} Vertical Retrace End Register.

         <=1>  A vertical retrace interrupt is pending.  This interrupt can be
               received by the processor only where 8259 interrupt hardware is
               correctly initialised.  This status can always be accessed by a
               continuous polling operation by software, providing always that
               this status is itself enabled by option selection.

               See {6.05.19} Vertical Retrace End Register.

         This status bit can be used to synchronise software operation with the
         display unit frame production.  In this manner, certain critical types
         of operation can be made to occur during frame flyback time.  This has
         the effect of preventing any visual disturbance to the display screen,
         which is psychologically far better for the user of the display unit.

         See {6.09.04} Input Status Register One.
         See {10.02}   Monitor auto-detection operation.




6.09.04  Input Status Register One      { 3?ah  R-- }
=======  ============================================


Cross reference with {6.07.01} Attribute Address Register.
Cross reference with {6.07.20} Colour Plane Enable Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.09.03} Input Status Register Zero.
Cross reference with {10.02}   Monitor auto-detection operation.


         The input/output port address of this register can be modified under
         program control by unsing the Input Output Address Select option bit
         in the Miscellaneous Output Register.  The selectable port addresses
         are either hex '3ba' or alternatively, hex '3da'.

         See {6.09.01} Miscellaneous Output Register.

         A read of this register resets the write state associated with the
         attribute controller write port 3c0h.  This ensures that the first
         write to port 3c0h will select the Attribute Address Register thus
         permitting specification of the index for the internal register to
         be accessed next.

         See {6.07.01} Attribute Address Register.


<0>      Inverted Display Enable Status
         ------------------------------

         <=0>  This represents the active image scan line display time, where
               the display is not blanked.  This status is set dynamically in
               real-time, so can be used by software to synchronise operation
               with display activity.

         <=1>  The display is in a blanking period.  This might be either of
               horizontal or vertical blanking.  It is possible to decide on
               the basis of the vertical interrupt state, or by using timing
               information to make the deduction.

               See Vertical Retrace State, below.
               See {6.09.03} Input Status Register Zero.


<1>      Reserved.  Always <=0>.
         -----------------------


<2>      Reserved.  Always <=0>.  {Trident 8900 <=1>.}
         -----------------------


<3>      Vertical Retrace State
         ----------------------

         <=0>  The display is in an active state, which might in practise mean
               that information is being displayed, or a horizontal retrace is
               in progress.  However, there is no vertical retrace active.

         <=1>  The display is in a vertical retrace period.  The exact time at
               which the display entered this state can be determined by means
               of software continuously inspecting this state, until the start
               of vertical retrace is detected.  If the software maintains all
               operations in approximate synchronism thereafter, a synchronise
               becomes possible in a comparatively short time after each frame
               is completed.


<5..4>   Video Sampling State
         --------------------

         <=00>  Sampled digital video data as selected by option.
         <=01>  Sampled digital video data as selected by option.
         <=10>  Sampled digital video data as selected by option.
         <=11>  Sampled digital video data as selected by option.

         These two bits have a significance determined by an option setting.
         They are provided for diagnotic use, and can be used to sample the
         bits sent out from the attribute controller to the external colour
         palette.  There are 8 bits sent in total so there must be means to
         select those to be sampled.

         See {6.07.20} Colour Plane Enable Register.


<7..6>   Reserved.  Always <=00>.
         ------------------------




6.10  Register specifications: Special Registers
====  ==========================================
      Trident 8900 only
====  ==========================================
      standard register officially undocumented
====  ==========================================


6.10.01  Hardware Version Register {new definition}  { 3c5h    0bh    R-- }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.05} Mode Control Register 1.


         Note that reading this register has a special side effect for Trident
         8900 VGA controller chips.

         The definitions for the two mode control registers are transformed to
         their new definitions.

         See {6.10.04} Mode Control Register 2.
         See {6.10.05} Mode Control Register 1.


<3..0>   Chip version identification   {Trident}
         ---------------------------

         <=0000>  Unassigned.
         <=0001>  Unassigned.
         <=0010>  Trident 8800CS
         <=0011>  Trident 8900B
         <=0100>  Trident 8900C
         <=0101>  Unassigned.
         <=0110>  Unassigned.
         <=0111>  Unassigned.
         <=1000>  Unassigned.
         <=1001>  Unassigned.
         <=1010>  Unassigned.
         <=1011>  Unassigned.
         <=1100>  Unassigned.
         <=1101>  Unassigned.
         <=1110>  Unassigned.
         <=1111>  Unassigned.


<7..4>   Reserved.
         ---------




6.10.02  Version Selector Register {old definition}  { 3c5h    0bh    --W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.04} Mode Control Register 2.
Cross reference with {6.10.05} Mode Control Register 1.


         Note that writing this register has a special side effect for Trident
         8900 VGA controller chips.

         The definitions for the two mode control registers are transformed to
         their old definitions.  The data written is irrelevant, as it will be
         ignored.  It is the write operation which indicates the definition is
         to be changed.

         See {6.10.04} Mode Control Register 2.
         See {6.10.05} Mode Control Register 1.




6.10.03  Configuration Port Register 1               { 3c5h    0ch    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.05} Mode Control Register 1. {Old definition.}
Cross reference with {6.10.05} Mode Control Register 1. {New definition.}


         This register is read/write only for Trident 8900.
         This register can be write protected by option setting.

         See {6.10.05} Mode Control Register 1.  {New definition.}

         There are two separate definitions for this register, as
         determined by the NMI state option setting.

         See {6.10.05} Mode Control Register 1.  {Old definition.}


-----------------------------------------------------------------------------
         Definition {only when NMI disabled}
-----------------------------------------------------------------------------


<0>      Address Decode Source
         ---------------------

         <=0>  Employ latched system address for A16 decode.
         <=1>  Employ unlatched A19..A17 system address for A16 decode.


<1>      ROM Chip Count Specify
         ----------------------

         <=0>  Two BIOS ROM chips present.
         <=1>  One BIOS ROM chip present.


<2>      Reserved.
         ---------


<3>      ROM Address Span Specify
         ------------------------

         <=0>  Decode 24K ROM BIOS address space.
         <=1>  Decode 32K ROM BIOS address space.


<4>      VGA Control Port Specify
         ------------------------

         <=0>  Select hex '46e8' as VGA Control Port.
               This is a standard plug-in board control port address.

         <=1>  Select hex '3c3' as VGA Control Port.
               This is a standard motherboard control port address.


<6..5>   DRAM Configuration
         ------------------

         <=00>  64K  by 4 bits {either 8 or 16 chips}.
         <=01>  256K by 4 bits {2 chips}.
         <=10>  256K by 4 bits {4 chips}.
         <=11>  256K by 4 bits {8 chips}.


<7>      DRAM Access Width
         -----------------

         <=0>  8 bit memory access.
         <=1>  16 bit memory access.


-----------------------------------------------------------------------------




-----------------------------------------------------------------------------
         Definition {only when NMI enabled}
-----------------------------------------------------------------------------


<0>      Software Status
         ---------------

         Read and write to this bit by software to store a binary status flag.


<1>      NMI State {Non Maskable Interrupt State}
         ----------------------------------------

         This state has influence over the interpretation of this register.
         This interpretation only exists when the NMI state is set <=1>.
         Therefore the NMI state can only be turned off here.

         <=0>  NMI Disable.
               Remove this interpretation of the register.

         <=1>  NMI Enable.
               Consistent with this register interpretation.


<3..2>   Testing Bits
         ------------

         <=00>  Manufacturing test.
         <=01>  Manufacturing test.
         <=10>  Manufacturing test.
         <=11>  Normal operation.


<7..4>   NMI Vector Enable
         -----------------

         <=0000>  No NMI vector specified.
         <=0001>  NMI vector is specifed as hex '3x8'.
         <=0010>  NMI vector is specifed as hex '3d9'.
         <=0011>  Illegal value.
         <=0100>  NMI vector is specifed as hex '3dd'.
         <=0101>  Illegal value.
         <=0110>  Illegal value.
         <=0111>  Illegal value.
         <=1000>  NMI vector is specifed as hex '3bf'.
         <=1001>  Illegal value.
         <=1010>  Illegal value.
         <=1011>  Illegal value.
         <=1100>  Illegal value.
         <=1101>  Illegal value.
         <=1110>  Illegal value.
         <=1111>  Illegal value.


-----------------------------------------------------------------------------




6.10.04  Mode Control Register 2                     { 3c5h    0dh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.04.03} Clocking Mode Register.
Cross reference with {6.04.05} Character Map Select Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.16} Cursor Location High Register.
Cross reference with {6.05.17} Cursor Location Low Register.
Cross reference with {6.05.22} Underline Location Register.
Cross reference with {6.06.07} Graphics Mode Register.
Cross reference with {6.07.18} Attribute Mode Control Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.01} Hardware Version Register {new definition}.
Cross reference with {6.10.02} Version Selector Register {old definition}.
Cross reference with {6.10.07} CRTC Module Testing Register.


         This register has two different interpretations depending upon the
         last transaction to either of the following registers:

         See {6.10.01} Hardware Version Register {new definition}.
         See {6.10.02} Version Selector Register {old definition}.


-----------------------------------------------------------------------------
         New Definition
-----------------------------------------------------------------------------
         See {6.10.01} Hardware Version Register {new definition}.


<0>      Dot Clock Extended Select
         -------------------------

         This bit extends the clock frequency select bits already available
         elsewhere from 2 bits to 3 bits.  This bit is the high order bit.

         See {6.09.01} Miscellaneous Output Register.

         <=0>  Select normal clocks.
         <=1>  Select extended clocks.


<2..1>   Dot Clock Division Ratio Select
         -------------------------------

         The dot clock frequency can be selectively divided to provide other
         useful frequencies without need for additional oscillators.

         <=00>  No division.
         <=01>  Division ratio is 2.0
         <=10>  Division ratio is 4.0
         <=11>  Division ratio is 1.5

         See {6.04.03} Clocking Mode Register.


<3>      Software Status
         ---------------

         Read and write to this bit by software to store a binary status flag.


<5..4>   Software Status
         ---------------

         Read and write to these bits by software to store a pair of binary
         status flags.


<7..6>   General Purpose Outputs
         -----------------------

         No documented function.  There are two VGA controller chip outputs
         which can be used to control aspects of a subsystem as the designer
         wishes.  These bits control the logic levels on these two hardware
         lines.  Their use is therefore totally design specific.  These are
         Trident 8900 outputs only.


-----------------------------------------------------------------------------




-----------------------------------------------------------------------------
         Old Definition
-----------------------------------------------------------------------------
         See {6.10.02} Version Selector Register {old definition}.


<2..0>   Video Generation Mode Select
         ----------------------------

         <=000>  VGA mode {with analogue monitor} select.
         <=001>  Not used.
         <=010>  EGA mode {with analogue monitor} select.
         <=011>  EGA mode {with TTL monitor} select.
         <=100>  CGA, MDA, Hercules modes {with analogue monitor} select.
         <=101>  CGA, MDA, Hercules modes {with TTL monitor} select.
         <=110>  Not used.
         <=111>  Not used.

         These options can alter the significance of an option bit in
         another register.  {Multipurpose Select bit.}

         See {6.10.07} CRTC Module Testing Register.


<3>      Processor Bandwidth during Blanking
         -----------------------------------

         <=0>  Normal access.
         <=1>  Provide full bandwidth during blanking.


<4>      Memory Plane Architecture Select
         --------------------------------

         <=0>  Planes 0 .. 3 active.
         <=1>  Planes 0 .. 7 active.


<5>      DRAM Clock Control

         <=0>  Enable  DRAM clock.
         <=1>  Inhibit DRAM clock.


<7..6>   Character Set Select High Extend
         --------------------------------

         These bits are used to select the character set base address in the
         display image memory plane 2.  hey provide two high order bits such
         that 4 times the number of character fonts can be selected over the
         basic VGA architecture.

         See {6.04.05} Character Map Select Register.


-----------------------------------------------------------------------------




6.10.05  Mode Control Register 1                     { 3c5h    0eh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================

Cross reference with {6.04.06} Sequencer Memory Mode Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.06.08} Miscellaneous Register.
Cross reference with {6.10.01} Hardware Version Register {new definition}.
Cross reference with {6.10.02} Version Selector Register {old definition}.
Cross reference with {6.10.03} Configuration Port Register 1.
Cross reference with {6.10.06} Power-up Mode Register 2.
Cross reference with {6.10.13} Source Address Register.
Cross reference with {6.10.14} Source Address Enable Register.


         This register has two different interpretations depending upon the
         last transaction to either of the following registers:

         See {6.10.01} Hardware Version Register {new definition}.
         See {6.10.02} Version Selector Register {old definition}.

         The interpretations and layout of the Source Address Register match
         exactly those for this register, provided the facility is enabled.

         See {6.10.13} Source Address Register.
         See {6.10.14} Source Address Enable Register.


-----------------------------------------------------------------------------
         New Definition
-----------------------------------------------------------------------------
         See {6.10.01} Hardware Version Register {new definition}.


         This new definition is suitable for high resolution graphics use.
         To use the features correctly, the processor display image memory
         must be set to hex 'a0000' for 64K bytes length.

         See {6.06.08} Miscellaneous Register.


<0>      Segment Selector
         ----------------

         <=0>  Select lower 64K of 128K page.
         <=1>  Select upper 64K of 128K page.


<1>      Page Selector
         -------------

         Caution!  These bits are WRITTEN with opposite polarity to that which
         is actually required.

         READ SENSE !
         <=0>  Selected bank is LOWER 128K of 256K bank.
         <=1>  Selected bank is upper 128K of 256K bank.

         WRITE SENSE !
         <=0>  Select UPPER 128K of 256K bank.
         <=1>  Select lower 128K of 256K bank.


<3..2>   Bank Selector
         -------------

         <=00>  Select 256K bank 0.  {Power on default, lowest memory bank}
         <=01>  Select 256K bank 1.
         <=10>  Select 256K bank 2.
         <=11>  Select 256K bank 3.  {Highest memory bank}


<6..4>   Software Status
         ---------------

         Read and write to these bits by software to store a triple of binary
         status flags.

         These bits can be made subject to write protection by the option
         Write Protection State, immediately below.


<7>      Write Protection State
         ----------------------

         This state controls write protection for Software Status, immediately
         above, in addition to some other registers.

         See {6.10.03} Configuration Port Register 1.
         See {6.10.06} Power-up Mode Register 2.

         <=0>  Write Protect.  {Default}
         <=1>  Write Permit.


-----------------------------------------------------------------------------




-----------------------------------------------------------------------------
         Old Definition
-----------------------------------------------------------------------------
         See {6.10.02} Version Selector Register {old definition}.


<0>      Display Access Bank Selector
         ----------------------------

         This bit controls addresses for display generation only,
         not for display image memory processor access.

         <=0>  Select lower 512K bank.  {Default}
         <=1>  Select upper 512K bank.


<2..1>   Processor Access Bank Selector
         ------------------------------

         This bit controls addresses for processor access only,
         not for display generation.

         <=00>  Select 256K bank 0.  {Power on default, lowest memory bank}
         <=01>  Select 256K bank 1.
         <=10>  Select 256K bank 2.
         <=11>  Select 256K bank 3.  {Highest memory bank}


<3>      DRAM Access Width
         -----------------

         <=0>  8 bit memory access.
         <=1>  16 bit memory access.


<4>      Reserved for Dot Clock Extended Select
         --------------------------------------

         Not implemented at present {Trident 8900}.


<5>      NMI State {Non Maskable Interrupt State}
         ----------------------------------------

         This state has influence over the interpretation of other registers.

         See {6.10.03} Configuration Port Register 1.

         <=0>  NMI Enable.
         <=1>  NMI Disable.


<6>      Interrupt Request Polarity Select
         ---------------------------------

         <=0>  Positive logic polarity.
         <=1>  Negative logic polarity.


<7>      Clock Pins Function Select
         --------------------------

         There are two clock pins available for the Trident 8900, which can be
         used either to select an external oscillator, or to accept oscillator
         outputs.  They are denoted CLK2, CLK3.

         When used to select an external oscillator these pins output from the
         VGA controller to the external environment.

         When accepting external oscillator generated clock signals, the pins
         act as input pins.

         <=0>  Select INPUT operation for CLK2, CLK3 pins.
         <=1>  Select OUTPUT operation for CLK2, CLK3 pins.


-----------------------------------------------------------------------------




6.10.06  Power-up Mode Register 2                    { 3c5h    0fh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.05} Mode Control Register 1. {New Definition}



<3..0>   DIP Switch Image
         ----------------

         These bits are a copy of the configuration DIP switch settings.
         Note the inverted polarity!

         <=0>  DIP switch is ON.
         <=1>  DIP switch is OFF.


<4>      Bus Protocol Select
         -------------------

         <=0>  Micro channel bus protocol is selected.
         <=1>  ISA PC/AT bus protocol is selected.


<5>      Input Output Address Map Select
         -------------------------------

         <=0>  Select alternate input output address map at hex '2xx'.
         <=1>  Select ISA input output address map at hex '3xx'.


<6>      ROM BIOS Address Decode Enable
         ------------------------------

         <=0>  ROM address decode is disabled.
         <=1>  ROM address decode is enabled.


<7>      ROM BIOS Data Path Width
         ------------------------

         <=0>  8 bit wide BIOS ROM.
         <=1>  16 bit BIOS ROM.




6.10.07  CRTC Module Testing Register                { 3?5h    1eh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.05.01} CRT Controller Address Register.
Cross reference with {6.05.02} Horizontal Total Register.
Cross reference with {6.05.03} Horizontal Display Enable End Register.
Cross reference with {6.05.04} Start Horizontal Blanking Register.
Cross reference with {6.05.05} End Horizontal Blanking Register.
Cross reference with {6.05.06} Start Horizontal Retrace Pulse Register.
Cross reference with {6.05.07} End Horizontal Retrace Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.09} CRT Controller Overflow Register.
Cross reference with {6.05.10} Preset Row Scan Register.
Cross reference with {6.05.11} Maximum Scan Line Register.
Cross reference with {6.05.14} Start Address High Register.
Cross reference with {6.05.15} Start Address Low Register.
Cross reference with {6.05.18} Vertical Retrace Start Register.
Cross reference with {6.05.19} Vertical Retrace End Register.
Cross reference with {6.05.23} Start Vertical Blanking Register.
Cross reference with {6.05.24} End Vertical Blanking Register.
Cross reference with {6.05.25} CRTC Mode Control Register.
Cross reference with {6.09.01} Miscellaneous Output Register.
Cross reference with {6.10.04} Mode Control Register 2. {Old Definition}


<0>      Horizontal Clock Select
         -----------------------

         <=0>  Normal operation.  {Power on default}
         <=1>  Manufacturing test.


<1>      Character Clock Select
         ----------------------

         <=0>  Normal operation.  {Power on default}
         <=1>  Manufacturing test.


<2>      Interlace Enable
         ----------------

         <=0>  Non-interlace display generation mode.  {Power on default}
         <=1>  Interlace display generation mode.


<3>      Multipurpose Select
         -------------------

         --------------------------------------------------------------------

         Vertical Retrace Clock Edge Select
         ==================================

         This operates only in CGA, MDA modes.

         See {6.10.04} Mode Control Register 2. {Old Definition}

         <=0>  Vertical retrace on rising clock edge.  {Power on default}
         <=1>  Vertical retrace on falling clock edge.

         --------------------------------------------------------------------

         Font Load Address Select
         ========================

         This operates only in EGA, VGA modes.

         See {6.10.04} Mode Control Register 2. {Old Definition}

         <=0>  Load from low address.
         <=1>  Load from high address.

         --------------------------------------------------------------------


<4>      CRT Controller Register Protection State
         ----------------------------------------

         <=0>  No protection.  {Power on default}
         <=1>  Protection applied.


         The following register indexes are protected:


         Register Index
         ===-----------

                Bit Numbers
         ===    ===--------

                       Register Description and Bit Description
         ===    ===    ========================================----------------

         00h    0-7    {6.05.02} Horizontal Total Register.

         01h    0-7    {6.05.03} Horizontal Display Enable End Register.

         02h    0-7    {6.05.04} Start Horizontal Blanking Register.

         03h    0-7    {6.05.05} End Horizontal Blanking Register.

         04h    0-7    {6.05.06} Start Horizontal Retrace Pulse Register.

         05h    0-7    {6.05.07} End Horizontal Retrace Register.

         06h    0-7    {6.05.08} Vertical Total Register.

         07h    0-7    {6.05.09} CRT Controller Overflow Register.

         09h     7     {6.05.11} Maximum Scan Line Register.
                         bit --> Double Scan Line Display.

         10h    0-7    {6.05.18} Vertical Retrace Start Register.

         11h    0-7    {6.05.19} Vertical Retrace End Register.

         15h    0-7    {6.05.23} Start Vertical Blanking Register.

         16h    0-7    {6.05.24} End Vertical Blanking Register.

         17h     2     {6.05.25} CRTC Mode Control Register.
                         bit --> Horizontal Retrace Divisor.

         ----------------------------------------------------------------------


<5>      Start Address Extension Bit 16
         ------------------------------

         This feature must be enabled.  See Start Address Extension Enable,
         almost immediately below.

         See {6.05.14} Start Address High Register.
         See {6.05.15} Start Address Low Register.


<6>      Miscellaneous Output Register Protect State
         -------------------------------------------

         <=0>  No protection.  {Power on default}
         <=1>  Protection applied.

         See {6.09.01} Miscellaneous Output Register.



<7>      Start Address Extension Enable
         ------------------------------

         This feature is not an ISA feature, so must be specially enabled by
         means of this option setting, before use.

         <=0>  Disable start address extension bit 16.
         <=1>  Enable start address extension bit 16.




6.10.08  Software Programming Register               { 3?5h    1fh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.05.01} CRT Controller Address Register.


         This register provides means for storage and retrieval of software
         status associated, typically, with BIOS operation.


<1..0>   Reserved for BIOS use.
         ----------------------

         <=00>  Memory size is 256K bytes.
         <=01>  Memory size is 512K bytes.
         <=10>  Memory size is 768K bytes.
         <=11>  Memory size is 1024K bytes.


<3..2>   Software Status Bits
         --------------------

         Used for software defined purposes.


<7..4>   Reserved for BIOS use.  Do NOT disturb.
         ---------------------------------------




6.10.09  CPU Latch Read Back Register                { 3?5h    22h    R-- }
=======  ==================================================================
         standard register officially undocumented
=======  ==================================================================


Cross reference with {6.06.02} Set/Reset Register.
Cross reference with {6.06.06} Read Map Select Register.
Cross reference with {6.06.07} Graphics Mode Register.


         This is a standard VGA controller register which was never
         officially documented.


<7..0>   CPU Latch Read Back
         -------------------

         This register provides access to the four data latches used in the
         data path between the processor and the display image memory.  The
         latch number directly associates with the image memory plane which
         receives data from the latch during memory writes by the processor
         so this plane is specified by the Read Map Select Register.

         See {6.06.02} Set/Reset Register.
         See {6.06.06} Read Map Select Register.
         See {6.06.07} Graphics Mode Register.




6.10.10  Attribute State Read Back Register          { 3?5h    24h    R-- }
=======  ==================================================================
         standard register officially undocumented
=======  ==================================================================


Cross reference with {6.07.01} Attribute Address Register.
Cross reference with {6.10.11} Attribute Index Read Back Register.


         This is a standard VGA controller register which was never
         officially documented.


-------------------------------------------------------------------------------
         standard register officially undocumented
-------------------------------------------------------------------------------


<4..0>   Attribute Controller Index
         --------------------------

         This provides the index value which selects an attribute controller
         register so that the processor can obtain access.  This value is
         defined by writing to the attribute controller address register and
         the appropriate internal associated state must be defined.

         See {6.07.01} Attribute Address Register.


<5>      Colour Palette Address Source {Internal palette}
         -----------------------------

         <=0>  Colour palette is accessed only by the processor, no video can
               be generated.

         <=1>  Colour palette generates video, processor access is denied.


<6>      Reserved.
         ---------


<7>      Attribute State Read Back
         -------------------------

         <=0>  This specifies that the Attribute controller is set to point to
               the attribute controller address register.  This permits a new
               attribute controller register index value to be specified.

         <=1>  This specifies that the Attribute controller is set to point to
               one particular internal attribute controller register.  This is
               specified by the index value in the address register, and it is
               this indexed register which will be accessed by the processor.


-------------------------------------------------------------------------------




-------------------------------------------------------------------------------
         Trident 8900 only
-------------------------------------------------------------------------------
         See {6.10.11} Attribute Index Read Back Register.


<6..0>   Reserved.  Undefined.
         ---------------------


<7>      Attribute State Read Back
         -------------------------

         <=0>  This specifies that the Attribute controller is set to point to
               the attribute controller address register.  This permits a new
               attribute controller register index value to be specified.

         <=1>  This specifies that the Attribute controller is set to point to
               one particular internal attribute controller register.  This is
               specified by the index value in the address register, and it is
               this indexed register which will be accessed by the processor.


-------------------------------------------------------------------------------




6.10.11  Attribute Index Read Back Register          { 3?5h    26h    R-- }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.07.01} Attribute Address Register.
Cross reference with {6.10.10} Attribute State Read Back Register.


<4..0>   Attribute Index
         ---------------

         This binary field indicates the index value which determines which of
         the internal registers will be accessed by the processor assuming the
         correct required internal state is present.

         See {6.07.01} Attribute Address Register.

         An alternative ISA register may be available on non-Trident hardware,
         which may provide a slightly more standard way to obtain this data.

         See {6.10.10} Attribute State Read Back Register.


<7..5>   Reserved.
         ---------




6.10.12  Clear Vertical Display Enable Register      { 3?5h    3nh    W-- }
=======  ==================================================================
         standard register officially undocumented
=======  ==================================================================


Note: the index address 'n' indicates any value, that is, a don't care value.


Cross reference with {6.05.01} CRT Controller Address Register.
Cross reference with {6.05.08} Vertical Total Register.
Cross reference with {6.05.20} Vertical Display Enable End Register.


         This is a standard VGA controller register which was never
         officially documented.


<0>      Clear Vertical Display Enable
         -----------------------------

         <=0>  Do not clear the vertical display enable state.

               See {6.05.08} Vertical Total Register.
               See {6.05.20} Vertical Display Enable End Register.

         <=1>  Clear the vertical display enable state.  This has the effect
               of immediately blanking the screen and causes the generation
               of display data to terminate.  The sequencer then changes the
               image memory timing so permitting greater bandwidth access by
               the processor.  The display will be subject to disturbance if
               appropriate synchronisation is not provided.  In any case the
               use of this facility will produce some flicker.

               The character row counter achievement of the vertical total in
               the usual manner will set the vertical display enable state so
               permitting normal production of the following display frame.

               See {6.05.08} Vertical Total Register.
               See {6.05.20} Vertical Display Enable End Register.

               This might be used to temporarily increase the processor speed
               of image update at the expense of display disturbance.



<7..1>   Unused.  Any value can be present.
         ----------------------------------




6.10.13  Source Address Register                     { 3cfh    0eh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.05} Mode Control Register 1.
Cross reference with {6.10.14} Source Address Enable Register.


         There is a difficulty of low speed when manipulating large graphics
         images across memory bank boundaries.  This arises when an image is
         located in a number of display memory banks, only one of which will
         be accessible to the processor at any given moment.

         In this situation, it is often required to copy a part of the image
         from one bank into another.  This entails performing a read, then a
         change of processor mapping into the display memory following which
         a corresponding processor write can take place.

         Needless to say, this whole operation is cumbersome in the extreme.

         For this reason, it is possible to specify a source and destination
         bank selection invoked by processor read write access respectively.
         In this way any processor read is directed to the source address in
         the source bank while a write access is directed to the destination
         bank in similar manner.

         This Source Address Register specifies the details of the source
         address, while the Mode Control Register 1 specifies all details
         for the destination address.

         See {6.10.05} Mode Control Register 1.

         This facility must be enabled appropriately before use, since it is
         not a standard VGA controller capability.

         See {6.10.14} Source Address Enable Register.




6.10.14  Source Address Enable Register              { 3cfh    0fh    R/W }
=======  ==================================================================
         Trident 8900 only
=======  ==================================================================


Cross reference with {6.10.05} Mode Control Register 1.
Cross reference with {6.10.13} Source Address Register.


         This register controls the apparent existance of a very useful feature
         which can greatly speed up graphics programming image manipulations if
         correctly used.

         See {6.10.05} Mode Control Register 1.
         See {6.10.13} Source Address Register.


<0>      Source Address Enable
         ---------------------

         <=0>  Disable the Source Address Register.
         <=1>  Enable the  Source Address Register.


<7..1>   Reserved.  Always <=0000000>.
         -----------------------------




6.s   Summary
====  =======

Details have been given of some special registers which provide for the most
part, proprietary features concerned with VGA architecture extension.  These
proprietary details relate in this case to the Trident 8900 chip.

There are however, certain features described here which are standard in that
the ISA contains these features, yet they remain officially undocumented.  It
has only been possible to decide on their existance, by means of a program of
reverse engineering.  This analyses a semiconductor chip in order to obtain a
complete logic schematic from the circuit physical structure.

Using these undocumented yet standard features may cause difficulty because
companies which design their compatible products on the basis of documented
interfaces may not have performed the reverse engineering necessary to make
a fully hardware compatible product.

The simple fact is with a device as complex as the VGA controller, it is very
important to obtain original technical material before starting any serious
programming work.  Most importantly, before purchase of a VGA controller, is
the possibility for review of such technical material as may be available in
order to assess it for quality.




7.    VGA controller: architecture
====  ============================


7.01  Controller timing generator:  { Sequencer }
====  ===========================================


The video graphics array controller is a complex collection of distinct logic
blocks each of which has various connections to other such blocks.  Since the
notion of time used by each logic block must agree with that used by associated
blocks a special set of timing, that is, clock pulses is distributed throughout
the device.  Each clock pulse keeps all the logic which uses it in common step,
so that all the events which must be maintained in lock-step remain so at all
times.  This is the purpose of a clock pulse.  It regulates the changing flow
of events within a logic circuit.

There will be more than one clock pulse needed by such a complex device as the
VGA controller chip, so it becomes important for each clock pulse to maintain
a particular relationship with all other clock pulses.  This is so as to permit
the reliable and timely flow of information between circuitry which determines
events using distinct time scales.  These time scales are naturally represented
by the different periods associated with each of the separate clock pulses.  As
an example of just two distinct time scales we will be interested in using, we
can think of the horizontal and vertical synchronisation pulses that the image
generator regularly sends to a display unit.  In this way, we can see that the
synchronisation signals are really just special clock pulses sent by the image
generator to the display unit in order to keep the display unit in lock-step,
therefore ensuring the correct image is displayed at all times.

There are essentially two distinct image generation modes available.  Text mode
creates a text image on the display, possibly using a variety of character sets
whilst graphics mode dispenses with characters, and presents purely graphical
images.  These two modes are handled quite differently within the controller.
Note that it is still possible to present text for display while using graphics
modes, but in this case, software will have to prepare the character outlines
ready for display.  The distinction between graphics mode presentation of text
and text mode presentation of text is simply that in the latter, hardware takes
care of all the character formation chores, which results in much faster output
of text than would be possible using software in graphics mode.  Of course, it
is only possible to create text in text mode, whereas text and graphics can be
created in graphics mode.

The sequencer generates a number of timing signals, that is, clock pulses.  We
list the more interesting ones below:-

  1.  Dot_clock
  2.  Character_clock

The dot clock is the fundamental unit of timing from which all other timing is
derived for image generation.  This clock defines the amount of time available
for displaying one pixel.  It therefore determines the image information output
frequency from the image generator to the display unit.  Each time this clock
marks a new pixel period, the image generator must transmit all information for
defining the next pixel to the display.  {There is one exception to this which
distinguishes 256 colour packed pixel mode from other graphics display modes.}

Facilities are provided to change the oscillator associated with the dot clock
which has the effect of selecting a different dot clock frequency.  Also it is
possible to invoke a frequency division on the selected oscillator frequency,
in order to produce new frequencies without using more oscillator units.

The character clock is derived from the dot clock, and one period of this clock
represents the width of a single character output to the display unit.  This is
only relevant when the image generator is operating in text mode. The character
clock can either represent characters of width 8 pixels width, or alternatively
of 9 pixels width.

The character clock represents the unit of timing for display unit purposes and
this is true in either of text display mode or graphics display mode.




7.02  Display timing generator:  { CRT Controller }
====  =============================================


The Cathode Ray Tube Controller accepts the Character_clock from the Sequencer
and generates the synchronisation signals required to keep the display unit in
lock-step with the image generator.  All the timing for horizontal and vertical
synchronisation is defined in terms of character widths.  For this reason, the
CRT Controller is also responsible for generating the hardware cursor which can
only appear in character aligned positions within the display image.  Some of
the signals developed by the CRT controller are:

  1.  Horizontal Synchronisation
  2.  Horizontal Blanking
  3.  Vertical Synchronisation
  4.  Vertical Blanking
  5.  Display Enable
  6.  Cursor Enable
  7.  Underline Enable
  8.  Increment Horizontal Character Counter
  9.  Reset Horizontal Character Counter
 10.  Increment Character Row Counter
 11.  Reset Character Row Counter
 12.  Increment Character Font Scan Line Counter
 13.  Reset Character Font Scan Line Counter
 14.  Increment Display Memory Address Counter
 15.  Reset Display Memory Address Counter

The effect of these signals is explored fully, in the main body of the text.
These control the intimate details of all information required from display
image memory in text or graphics mode display generation.  A display address
is generated by the CRT Controller which then provides the display image data
to the graphics controller, and thence to the attribute controller.




7.03  Image information processor:  { Graphics Controller }
====  =====================================================


The Graphics Controller acts as an interface between the processor and display
image memory, and also between the CRT Controller and display image memory.  A
simultaneous access attempt by both the processor and the CRT Controller gives
the access to the CRT Controller in all cases.

The Graphics Controller provides the processor with extensive image processing
ability for various graphics display modes which are available.  Facilities to
efficiently process multiplane image data are provided, with very low overhead.

The Graphics Controller provides pixel panning capability for generated image
data, which does not depend upon text mode or graphics mode operation.  Shift
registers provide conversion of multiplane display image memory format to the
serial multiplane parallel format required by the attribute controller.  They
have special functionality built in so that a wide range of these conversions
can be easily handled.  Shift register interconnections and architecture will
change depending upon the graphics mode in use.




7.04  Image presentation processor:  { Attribute Controller }
====  =======================================================


The Attribute Controller accepts image data from the Graphics Controller and
processes it before sending it out to the digital to analogue converters for
final display.  This involves performing colour selection code translation,
so that less image memory can be used for storage of images which use small
sets of colours.  The translation uses an internal colour palette register
which accepts a 4 bit colour code and produces either a 4 or 6 bit output.

Bit shift pixel panning is implemented, to be used in conjuction with those
complementary facilities provided by the Graphics Controller.  Selection of
display colour during blanking periods is also performed.

In text mode display generation, the attribute byte which is associated with
every text character is processed into the video data, to provide a blinking
cursor, underlining of text, and colour selection functions.

The output from the Attribute Controller is a stream of 8 bit wide image data
which specifies a pixel colour, suitable for input to the DAC Support Logic.




7.05  Colour presentation processor:  { DAC Support Logic }
====  =====================================================


The Digital to Analogue Converter support logic accepts 8 bit colour data, and
translates it into either 18 bit or 24 bit colour data, to drive three primary
colour electron guns in the display unit.  The translation is performed with a
large look-up table memory unit, termed the external colour palette.  This can
control the displayed colour set with a great degree of finess.  There is also
the possibility provided to edit some of the 8 bits of input data substituting
zero bits for data bits on option.  This provides for animation effects or for
multiple image storage with very fast recall.  This can be very useful for the
support of hierarchical design systems.




7.s   Summary
====  =======


A very brief sketch has been given for each of the major logic blocks involved
in producing a display image from data supplied by a processor.  The functions
described are explored in considerable detail in the main body of the text.




8.    VGA controller: Text
====  ====================

8.01  Text image generation
8.02  Text font representation
8.03  Text attribute representation
8.04  Text character set extensions
8.05  Text mode support for graphics


      Chapter in preparation.  Should be available for second edition.
      ----------------------------------------------------------------




9.    VGA controller: Graphics
====  ========================

9.01  Graphic image generation
9.02  Graphic multi-plane memory
9.03  Graphic packed pixel memory
9.04  Graphic line drawing
9.05  Graphic object drawing


      Chapter in preparation.  Should be available for second edition.
      ----------------------------------------------------------------




10.    VGA controller: Hardware Interface
===    ==================================


10.01  Hardware connector layout
=====  =========================


This information is provided for completeness only.  It is intended only as a
guide.  Further information should be sought if either serious design work or
diagnostic work needs to be performed.

The VGA subsystem pulls the Identity signal lines to +5V through a resistor.
The display then selectively connects these lines to ground.  The VGA then
detects the signal level and interprets the code in the appropriate manner.
Details are available on the coding scheme employed.

See {10.03} Monitor auto-configuration operation.




       Video Connector Pinouts
       =======================


       Pin Number  { 9 pin connector }
       ==-----------------------------

             Pin Number  { standard 15 pin connector }
       ==    ==---------------------------------------

                   Signal Description
       ==    ==    ==================---------------------------------------


        1     1    Red intensity             {analogue 75 ohms}
        2     2    Green intensity           {analogue 75 ohms}
        3     3    Blue intensity            {analogue 75 ohms}
        -     4    Identity bit 2            {logic pullup to +5V by VGA}
        -     5    Self test / must be grounded for use with 9 pin connector
        6     6    Red intensity ground      {analogue 75 ohms}
        7     7    Green intensity ground    {analogue 75 ohms}
        8     8    Blue intensity ground     {analogue 75 ohms}
        -     9    -  no connection
        9    10    Synch ground
        -    11    Identity bit 0            {logic pullup to +5V by VGA}
        -    12    Identity bit 1            {logic pullup to +5V by VGA}
        4    13    Horizontal synch
        5    14    Vertical synch
        -    15    -  no connection


       ---------------------------------------------------------------------




10.02  Monitor auto-detection operation
=====  ================================


A VGA subsystem can be arranged to detect whether a monochrome display unit or
alternatively, a colour display unit is in use.  This is made possible through
sensing the current flow in the lines carrying the analogue red green and blue
pixel intensity signals from the image generator to the display unit.

A colour display unit will make use of each one of these three signals, which
can be detected by suitable hardware measurement of current flow.  However, a
monochrome display unit will only use the green signal.  This difference will
cause the video subsystem to select an operational mode suitable for the unit
in use.

A simplified schematic is given below showing the arrangement provided for the
measurement of output current.  Note that the software must read the status at
the active video image generation time within a scan line.  This is decided by
means of the display enable status bit.  This bit should be monitored so as to
achieve synchonism with the program.  Then, the measurement can be confidently
made during the active display period of the horizontal scan.  This involves a
synchronisation with the vertical retrace so that the complete activity of the
display can be accurately predicted in advance of the measurement.

See {6.09.04} Input Status Register One.

The software interface for this hardware detection operation is provided by a
single status bit.

See {6.09.03} Input Status Register Zero.




       Schematic of Video Output Current Measurement
       =============================================




       ---------
       | DAC   |                   Red into
       | RED   |...........r....>  Display
       ---------           |       Unit
                           |
                           |
                           |
       ---------           |
       | DAC   |           |       Green into
       | GREEN |........g.......>  Display
       ---------        |  |       Unit
                        |  |
                        |  |
                        |  |
       ---------        |  |
       | DAC   |        |  |       Blue into
       | BLUE  |.....b..........>  Display
       ---------     |  |  |       Unit
                     |  |  |
                     |  |  |
                     |  |  |
                     |  |  |
                     |  |  |      |-----*
       ---------     |  |  r....>.| +      *
       | VOLT  |     |  |         | compare   *............
       | REFER-|..v.............>.| -      *              |
       | ENCE  |  |  |  |         |-----*                 |
       ---------  |  |  |                                 |
                  |  |  |                                 |
                  |  |  |                                 |
                  |  |  |                                 |
                  |  |  |         |-----*                 |
                  |  |  g.......>.| +      *              |
                  |  |            | compare   *.........  |
                  v.............>.| -      *           |  |
                  |  |            |-----*              |  |
                  |  |                                 |  |
                  |  |                                 |  |
                  |  |                                 |  |
                  |  |                                 |  |
                  |  |            |-----*              |  |
                  |  b..........>.| +      *           |  |
                  |               | compare   *......  |  |
                  v.............>.| -      *        |  |  |
                                  |-----*           |  |  |
                                                    |  |  |
                                                    |  |  |
                                                    |  |  |
                                                    |  |  |
                                                 =============
                                                    NOR GATE
                                                 =============
                                                       |
                                                       |
                                                       |
                                                       |
                                                       |
                                               =================

                                               STATUS BIT OUTPUT

                                               =================


       ---------------------------------------------------------




10.03  Monitor auto-configuration operation
=====  ====================================


There is another means for determining the type of display unit attached to a
VGA subsystem.  This depends on a simple code provided by the display unit to
the VGA subsystem, according to a predefined convention.


       Identity bit 2
       =-------------

            Identity bit 1
       =    =-------------

                 Identity bit 0
       =    =    =-------------

                      Significance
       =    =    =    ============--------------------------------------


       0    0    0    --  unassigned

       0    0    1    --  unassigned

       0    1    0    Interlaced colour display unit is connected

       0    1    1    --  unassigned

       1    0    0    --  unassigned

       1    0    1    Monochrome display unit is connected

       1    1    0    Non-interlaced colour display unit is connected

       1    1    1    No display unit connected to VGA subsystem


       -----------------------------------------------------------------


Note that strapping an identity signal line to ground has the effect of sending
a binary zero to the VGA subsystem sensing logic.

See {10.01} Hardware connector layout.




10.s   Summary
====   =======


A brief description of some of the hardware connections between a VGA subsystem
and a corresponding display unit has been given.




References  {in alphabetic order by company name}
===============================================================================


001    82C456 Enhanced Flat Panel/CRT VGA Controller Data Sheet
       Chips and Technologies Inc.


002    HT216 VGA Controller
       Headland Technology Inc.


003    iAPX 86/88, 186/188 User's Manual, Programmer's Reference
       Intel Corporation


004    TVGA8900C Technical Reference Manual
       Trident Microsystems


005    Computer IC's 1990-1991 Data Book
       United Microelectronics Corporation


006    WD90C20/WD90C22 VGA Flat Panel Display Controllers
       Western Digital Corporation


007    Many other documents were consulted, being too numerous to mention.
       These generally clarified only a single point, which in many cases
       could only be understood in combination with many other documents.
       It is felt that mentioning all of these could only add to the very
       great confusion surrounding this whole area of subject matter.  In
       some cases documents were found to be self contradictory.  Some of
       the documents were found to be factually correct, but no framework
       was provided for practical use and understanding of the material.

       Very often, there was no cross reference between different aspects
       of the VGA operation.  This presents what is felt by the author to
       be a difficult situation.  It is hoped that this work will address
       the worst of these problems, and provide a useful framework within
       which real knowledge can be gained.

       At the same time, the reader should appreciate that there are many
       different proprietary products in the marketplace with each giving
       proprietary extensions to the basic architecture.  It is vital for
       all serious work, that the user obtain all official technical data
       direct from the manufacturer concerned.  That is, unless only BIOS
       access is to be gained to the VGA facilities provided.  However it
       would be prudent even in this case to obtain technical data, since
       every BIOS is different, by definition.  The best way to avoid any
       implementation problems is to remain as well informed as possible.




Glossary
===============================================================================


Please note that this glossary is vestigial in the extreme with the motivation
for including it at all being completeness.  However, it is unlikely that this
paucity will impact significantly on the useability of this text, since jargon
is relatively scarcely used.  In those places where jargon is introduced there
is normally an explanation provided, except for those terms which are so basic
that a reader of this document must be expected to have knowledge of them.




80x86
-------------
             A family of related processor chips, produced by Intel Corp.  This
             processor family is important because it is used as the basis for
             all industry standard architecture computer systems.


Analogue
-------------
             A coding and interpretation scheme which does not rely on discrete
             steps.  Instead, continuous variation of some characteristic such
             as voltage or current is used as the analogue of a represented
             value.  Hence analogue, as opposed to digital, representation.  A
             significant practical advantage of this representation is the lack
             of need for more than two wire connections, which can save expense
             for suitable systems.  A display monitor might accept analogue or
             digital signals, but will be able to support many more colours if
             an analogue video signal is used.  Contrast this with digital.


BIOS
-------------
             Basic Input Output System.  This is a program which provides a set
             of services (usually standardised) to other programs.  VGA systems
             usually have their own BIOS which permits the VGA to support those
             interfaces usually provided by an industry compatible architecture
             computer system to the software running on it.


Blanking
-------------
             The action of display unit operation inhibition, during the time
             required to reinitialise the display ready for production of the
             next part of the image.  This is needed because an image is made
             up from a number of scan lines which are displayed left to right
             on the screen.  To begin again at the left side the display must
             be inhibited, to prevent the retrace from disturbing the image.
             In practise, there are horizontal and vertical blanking periods,
             which perform a similar function in orthogonal directions.


Bus
-------------
             A means for transmitting and receiving information at high speed
             within the confines of a single computer system.  Bus types that
             are used with VGA controllers fall into two categories.  Either
             the ISA PC/AT bus is used, or sometimes, Micro channel bus.  The
             latter is proprietary to IBM and is not so widely used by other
             manufacturers.


CGA
-------------
             Colour Graphics Array.  A rather old, but still widely used video
             graphics standard which is principally of interest for emulation.


Chip
-------------
             A highly integrated electronic device which is implemented as a
             silicon integrated circuit.  This makes possible the practical
             realisation of very complex circuits, such as processor chips
             and VGA controller chips.


Clock
-------------
             Almost all electronic systems operate by means of a regular signal
             which regulates in a uniform fashion, each information flow within
             the component circuits.  Since this signal has a constant form, it
             has come to be known as a clock signal, or sometimes clock pulse.

             The practical significance of a clock is that it controls the data
             rate within a system.  For this reason selecting a clock frequency is
             is vitally important for determining the quantity of data which is
             processed by, or transmitted from, a VGA controller.

             It is possible to derive a clock of lower frequency, directly from
             a master clock of higher frequency.  In the VGA controller this is
             a very common occurence.


CRT
-------------
             Cathode Ray Tube.  An important display technology which has been
             vitally important in establishing currently used video generation
             concepts and signal conventions.  See tube.


DAC
-------------
             Digital to Analogue Converter.  This is an electronic device which
             is able to convert a digital code into a high precision analogue
             signal suitable for describing an image in a form acceptable by a
             display unit.  These devices operate at very high speed.


Digital
-------------
             A coding and interpretation scheme which relies upon discrete step
             representation of values typically using a binary coding alphabet.
             Each digit is represented by a signal value over two wires.  This
             means that the scheme is very robust, but there is an attendant
             overhead cost in terms of the number of connections which must be
             made in order to convey digital information.  Contrast this with
             analogue.


DIP Switch
-------------
             Dual In-line Plastic Switch.  This is a miniture electronic switch
             component which is used to provide selectable option settings with
             hardware configuration use.  Typically a bank of 4, 6, or 8 of the
             switches are employed, with each governing one particular feature.
             Such features are generally set once and then forgotten since they
             control hardware compatibility which does not often need changing.


Display Unit
-------------
             A device which accepts information and produces a visual image as
             a translation of that information.  See monitor.


Dot
-------------
             A term used to describe a monochrome pixel.  This term arises in
             connection with the dot clock which is a principle timing source
             for VGA controller and also therefore, display unit operation.


DRAM
-------------
             Dynamic Random Access Memory.  A type of memory technology which
             stores data using a charged capacitor.  As charge will leak from
             a capacitor, every so often all the stored data must be read out
             and replaced afresh, thereby restoring the charge strength.  The
             process which performs the charge restitution is termed refresh.
             The refresh must be completed by accessing every DRAM address in
             a short period of time termed the refresh period.  This time for
             refresh is measured in a small number of milli-seconds.  See RAM.


EGA
-------------
             Extended Graphics Array.  This is a video graphics standard which
             is becoming less important in numerical terms of installed system
             count, as time goes on.  Emulation may be important for EGA.


Emulation
-------------
             The capability of a particular electronic device to mimic exactly
             another, different electronic device so that the operation of the
             former is indestinguishable from that of the latter.  This can be
             important for maintaining compatibility between software produced
             over a long period of time, and a wide range of computer systems.


Hercules
-------------
             A Hercules Computer Technology trademark.  This company produces
             video graphics image generators and Hercules refers particularly
             to a widely used product for which emulation can be helpful.


Hardware
-------------
             A description of electronic components, usually assembled into an
             electronic system, or subsystem.  This represents an unchangeable
             structure which may provide facilities for selection of different
             interconnection schemes between constituent components.  Any type
             of ability to vary the apparent internal structure, and therefore
             the externally visible behaviour of hardware is normally referred
             to as programmability.  Such hardware may be programmed.  Control
             of such hardware is exercised by a program which is distinguished
             from hardware by the term software.


IBM
-------------
             Inernational Business Machines, Corp.  This company was the first
             to introduce MDA, CGA, EGA, VGA graphics controllers, with their
             associated display units.  Many companies follow IBM in building
             products which are deemed IBM Compatible.  VGA controller chips
             are a good example of this, although compatibility does have many
             limits in practise.


Image Generator
-------------
             An electronic device which accepts control information and image
             information from a processor and translates this into a form of
             information acceptable as input to a display unit.


ISA
-------------
             Industry Standard Architecture.  This refers to a particular type
             of computer system usually built from widely available components
             which ideally fit together easily to produce a standard device of
             known capability.  In practise, there may be difficulties because
             of subtle incompatibility between various components.  Usually it
             is possible to provide a certain set of capabilities adequate for
             most practical purposes, in this manner.


MDA
-------------
             Monochrome Display Adaptor. This is a video graphics standard that
             has been important in times past, but which is now of interest for
             emulation purposes.


Micro channel
-------------
             A type of bus, which is proprietary to IBM.


Monitor
-------------
             An alternative term for display unit.


MultiSync
-------------
             A Nippon Electric Company (NEC) trademark.  Describes a family of
             display units which are able to accept a number of distinct video
             signals with different characteristics.  Importantly, the rate at
             which image information is transferred to the display unit can be
             changed so providing for a much higher definition image.  This is
             achieved without any changes to the display unit, which can adapt
             to the video signals by analysing them.  This automatically gives
             rise to any changes necessary in the display unit operation.


NMI
-------------
             Non Maskable Interrupt.  This is a higher priority interrupt than
             any other interrupt available to the processor.  Specifically, it
             is of higher priority than all maskable interrupts.  This fact is
             often used to provide emulation facilities in software, triggered
             by certain hardware conditions.  For example, write protection of
             special registers useful in emulation, is often achieved by using
             NMI interrupts in conjunction with special handler programs.


PC/AT
-------------
             Personal Computer, Model AT.  This type of IBM compatible computer
             is one of the most ubiquitous in the world.  Because of the force
             of sheer numbers, many software and hardware products have been
             built for use with this type of machine.  VGA controller chips are
             normally configured for use with the bus provided by this machine.


Pixel
-------------
             Picture ELement.  A display screen is made up from large numbers
             of elementary displayable elements.  Every element is controlled
             quite independantly of all other elements.  Since the assemblage
             of all the available elements constitutes a picture the smallest
             picture component has become known as a pixel.  See dot.


Processor
-------------
             The computational device which acts as the seat of all activity in
             a computer system.  Sometimes known as the CPU.  The processor is
             the main determinant of capability for a computer system.  It is
             implemented as a highly integrated electronic device.


RAM
-------------
             Random Access Memory.  This type of memory technology is able to
             store and retrieve information at high speed and is able to give
             access to any address in the same uniform access time.  There is
             no constraint such as sequential access to addresses, hence the
             term random.  Any address can be accessed at any time with equal
             facility.  Used for storing video image information in a digital
             form suitable for manipulation by an image generator.  See DRAM.


Refresh
-------------
             A process used to maintain the information stored in a DRAM.  For
             more details see the entries for RAM, and for DRAM.


ROM
-------------
             Read Only Memory.  This type of memory technology is manufactured
             complete with all the information it is to contain.  This data is
             immune to change so permanently required information such as font
             data describing the shape of the characters in a character set is
             usefully stored in this type of device.  A BIOS is usually stored
             in a ROM.  Contrast with RAM, DRAM.


Software
-------------
             The information associated with a particular function obtained by
             programming hardware, so that some required external behaviour is
             made available.  See hardware.


Standard
-------------
             A term applied to many computer systems and their components.  It
             is rather doubtful that this term actually means anything at all.
             It has been the subject of so much abuse by so many, for so long,
             that it has become almost meaningless.  See ISA.  In practise, it
             is possible to find some particular products or interfaces which
             are ubiquitous to the point of becoming a 'de facto' standard.
             In these cases the term may have some use, providing it indicates
             demonstrable compatibility with some readily obtained reference.


Synchronisation
-------------
             The state in which one electronic system is operated as though it
             was actually receiving clocking information from another separate
             system.  This apparent synchronism between the respective clocks,
             gives rise to the term synchronisation when describing the state.
             It is vitally important that a display unit operate with absolute
             synchronisation to the image generator from which it receives the
             input video signals.


TTL
-------------
             Transistor Transistor Logic, a logic family which gives rise to a
             characteristic interface for digital signals known as TTL.  These
             signals have certain well specified characteristics, so can be of
             use in transmission of digital information between systems.  Some
             display units accept digital data using TTL compatible signals.


Tube
-------------
             The common term for a display tube or CRT.  See CRT.


VGA
-------------
             Video Graphics Array.  This is the most important video graphics
             standard at the time of writing.  Inexpensive to produce this is
             becoming numerically the most common display generation scheme.
             It is capable of simple extension, but supports a common set of
             facilities.  It is particularly interesting for support given to
             emulation of other graphics standards.  It is more than adequate
             for almost all applications except the most demanding.


VGA Controller
-------------
             This is a highly integrated electronic device which contains all
             the logic functions required to implement a VGA controller which
             is the image generator for producing VGA video information ready
             for display.


Video
-------------
             An electronic signal carrying picture information into a display
             unit.  This information is in a form suitable for translation by
             a display unit into an image readily comprehensible to the eye.




Index
===============================================================================


There are extensive cross references provided for all the VGA hardware register
descriptions, and these cross references do not rely on any concepts of page or
line numbers.   This is done with a purpose.  Many different page sizes can be
produced by current printing equipment, so it is suggested that the user employ
a readily available indexing program if a conventional index is really needed.

This will of course, depend entirely upon the page format selected by the user
in printing the document.  Guidelines for obtaining a print are available.

See {0.06} Obtaining a print of this document.

The contents list gives a useful overview of the chapter and section contents,
which, when used with the extensive cross references provides for an entirely
practical navigation aid around the text.  For this reason it is not envisaged
that any users will find the need to produce a conventional index.

There are two indexes included below.  The first is concerned with a complete
list of all the functional register groups available to the VGA programmer.
The second expands on the first, by including each of the bit fields present
in each register.  The format in both cases is the same as that for the entry
proper, in the main body of the text.  Details of input output port addresses
are therefore included, with register index values if needed, and read, write
or index functionality as appropriate.




Complete Register Listing By Functional Grouping
------------------------------------------------




Sequencer Registers
------------------------------------------------------------------------------

6.04.01  Sequencer Address Register      { 3c4h    ---    R/W }

6.04.02  Reset Register                  { 3c5h    00h    R/W }

6.04.03  Clocking Mode Register          { 3c5h    01h    R/W }

6.04.04  Map Mask Register               { 3c5h    02h    R/W }

6.04.05  Character Map Select Register   { 3c5h    03h    R/W }

6.04.06  Sequencer Memory Mode Register  { 3c5h    04h    R/W }

6.04.07  ................................{ 3c5h    07h    R/W }
6.04.07  Horizontal Character Counter Reset Register...........

------------------------------------------------------------------------------




CRT Controller Registers
------------------------------------------------------------------------------

6.05.01  CRT Controller Address Register          { 3?4h    ---    R/W }

6.05.02  Horizontal Total Register                { 3?5h    00h    R/W }

6.05.03  Horizontal Display Enable End Register   { 3?5h    01h    R/W }

6.05.04  Start Horizontal Blanking Register       { 3?5h    02h    R/W }

6.05.05  End Horizontal Blanking Register         { 3?5h    03h    R/W }

6.05.06  Start Horizontal Retrace Pulse Register  { 3?5h    04h    R/W }

6.05.07  End Horizontal Retrace Register          { 3?5h    05h    R/W }

6.05.08  Vertical Total Register                  { 3?5h    06h    R/W }

6.05.09  CRT Controller Overflow Register         { 3?5h    07h    R/W }

6.05.10  Preset Row Scan Register                 { 3?5h    08h    R/W }

6.05.11  Maximum Scan Line Register               { 3?5h    09h    R/W }

6.05.12  Cursor Start Register                    { 3?5h    0ah    R/W }

6.05.13  Cursor End Register                      { 3?5h    0bh    R/W }

6.05.14  Start Address High Register              { 3?5h    0ch    R/W }

6.05.15  Start Address Low Register               { 3?5h    0dh    R/W }

6.05.16  Cursor Location High Register            { 3?5h    0eh    R/W }

6.05.17  Cursor Location Low Register             { 3?5h    0fh    R/W }

6.05.18  Vertical Retrace Start Register          { 3?5h    10h    R/W }

6.05.19  Vertical Retrace End Register            { 3?5h    11h    R/W }

6.05.20  Vertical Display Enable End Register     { 3?5h    12h    R/W }

6.05.21  Offset Register                          { 3?5h    13h    R/W }

6.05.22  Underline Location Register              { 3?5h    14h    R/W }

6.05.23  Start Vertical Blanking Register         { 3?5h    15h    R/W }

6.05.24  End Vertical Blanking Register           { 3?5h    16h    R/W }

6.05.25  CRTC Mode Control Register               { 3?5h    17h    R/W }

6.05.26  Line Compare Register                    { 3?5h    18h    R/W }

------------------------------------------------------------------------------




Graphics Controller Registers
------------------------------------------------------------------------------

6.06.01  Graphics Address Register    { 3ceh    ---    R/W }

6.06.02  Set/Reset Register           { 3cfh    00h    R/W }

6.06.03  Enable Set/Reset Register    { 3cfh    01h    R/W }

6.06.04  Colour Compare Register      { 3cfh    02h    R/W }

6.06.05  Data Rotate Register         { 3cfh    03h    R/W }

6.06.06  Read Map Select Register     { 3cfh    04h    R/W }

6.06.07  Graphics Mode Register       { 3cfh    05h    R/W }

6.06.08  Miscellaneous Register       { 3cfh    06h    R/W }

6.06.09  Colour Don't Care Register   { 3cfh    07h    R/W }

6.06.10  Bit Mask Register            { 3cfh    08h    R/W }

------------------------------------------------------------------------------




Attribute Controller Registers
------------------------------------------------------------------------------

6.07.01  Attribute Address Register       { 3c0h/I/W  3c0h/R  ---  R/W }

6.07.02  Palette Register 00              { 3c0h/I/W  3c1h/R  00h  R/W }

6.07.03  Palette Register 01              { 3c0h/I/W  3c1h/R  01h  R/W }

6.07.04  Palette Register 02              { 3c0h/I/W  3c1h/R  02h  R/W }

6.07.05  Palette Register 03              { 3c0h/I/W  3c1h/R  03h  R/W }

6.07.06  Palette Register 04              { 3c0h/I/W  3c1h/R  04h  R/W }

6.07.07  Palette Register 05              { 3c0h/I/W  3c1h/R  05h  R/W }

6.07.08  Palette Register 06              { 3c0h/I/W  3c1h/R  06h  R/W }

6.07.09  Palette Register 07              { 3c0h/I/W  3c1h/R  07h  R/W }

6.07.10  Palette Register 08              { 3c0h/I/W  3c1h/R  08h  R/W }

6.07.11  Palette Register 09              { 3c0h/I/W  3c1h/R  09h  R/W }

6.07.12  Palette Register 10              { 3c0h/I/W  3c1h/R  0ah  R/W }

6.07.13  Palette Register 11              { 3c0h/I/W  3c1h/R  0bh  R/W }

6.07.14  Palette Register 12              { 3c0h/I/W  3c1h/R  0ch  R/W }

6.07.15  Palette Register 13              { 3c0h/I/W  3c1h/R  0dh  R/W }

6.07.16  Palette Register 14              { 3c0h/I/W  3c1h/R  0eh  R/W }

6.07.17  Palette Register 15              { 3c0h/I/W  3c1h/R  0fh  R/W }

6.07.18  Attribute Mode Control Register  { 3c0h/I/W  3c1h/R  10h  R/W }

6.07.19  Overscan Colour Register         { 3c0h/I/W  3c1h/R  11h  R/W }

6.07.20  Colour Plane Enable Register     { 3c0h/I/W  3c1h/R  12h  R/W }

6.07.21  Horizontal PEL Panning Register  { 3c0h/I/W  3c1h/R  13h  R/W }

6.07.22  Colour Select Register           { 3c0h/I/W  3c1h/R  14h  R/W }

------------------------------------------------------------------------------




DAC Registers
------------------------------------------------------------------------------

6.08.01  DAC Pixel Mask Register          { 3c6h   R/W }

6.08.02  DAC Status Register              { 3c7h   R-- }

6.08.03  DAC Read Data Address Register   { 3c7h   W-- }

6.08.04  DAC Write Data Address Register  { 3c8h   R/W }

6.08.05  DAC Data Register                { 3c9h   R/W }

------------------------------------------------------------------------------




General Registers
------------------------------------------------------------------------------

6.09.01  Miscellaneous Output Register  { 3c2h  W-- }

6.09.02  Miscellaneous Output Register  { 3cch  --R }

6.09.03  Input Status Register Zero     { 3c2h  R-- }

6.09.04  Input Status Register One      { 3?ah  R-- }

------------------------------------------------------------------------------




Special Registers
------------------------------------------------------------------------------

6.10.01  Hardware Version Register {new definition}  { 3c5h    0bh    R-- }

6.10.02  Version Selector Register {old definition}  { 3c5h    0bh    --W }

6.10.03  Configuration Port Register 1               { 3c5h    0ch    R/W }

6.10.04  Mode Control Register 2                     { 3c5h    0dh    R/W }

6.10.05  Mode Control Register 1                     { 3c5h    0eh    R/W }

6.10.06  Power-up Mode Register 2                    { 3c5h    0fh    R/W }

6.10.07  CRTC Module Testing Register                { 3?5h    1eh    R/W }

6.10.08  Software Programming Register               { 3?5h    1fh    R/W }

6.10.09  CPU Latch Read Back Register                { 3?5h    22h    R-- }

6.10.10  Attribute State Read Back Register          { 3?5h    24h    R-- }

6.10.11  Attribute Index Read Back Register          { 3?5h    26h    R-- }

6.10.12  Clear Vertical Display Enable Register      { 3?5h    3nh    W-- }

6.10.13  Source Address Register                     { 3cfh    0eh    R/W }

6.10.14  Source Address Enable Register              { 3cfh    0fh    R/W }

------------------------------------------------------------------------------




Complete Register Listing Including Bit Fields
----------------------------------------------




Sequencer Registers
------------------------------------------------------------------------------


6.04.01  Sequencer Address Register      { 3c4h    ---    R/W }
         ------------------------------------------------------
         <3..0>   Sequencer Register Address
         <7..4>   Reserved. Always <=0000>.
         ------------------------------------------------------


6.04.02  Reset Register                  { 3c5h    00h    R/W }
         ------------------------------------------------------
         <0>      Fast Reset Command
         <1>      Safe Reset Command
         <7..2>   Reserved. Always <=000000>.
         ------------------------------------------------------


6.04.03  Clocking Mode Register          { 3c5h    01h    R/W }
         ------------------------------------------------------
         <0>      Character Dot Clock Select
         <1>      Reserved.  Always <=0>.
         <2>      Shift Load Two Control
         <3>      Dot Clock Divide by Two Enable
         <4>      Shift Load Four Control
         <5>      Screen Inhibit
         <7..6>   Reserved.  Always <=00>.
         ------------------------------------------------------


6.04.04  Map Mask Register               { 3c5h    02h    R/W }
         ------------------------------------------------------
         <0>      Map Plane 0 Write Enable Control
         <1>      Map Plane 1 Write Enable Control
         <2>      Map Plane 2 Write Enable Control
         <3>      Map Plane 3 Write Enable Control
         <7..4>   Reserved.  Always <=0000>.
         ------------------------------------------------------


6.04.05  Character Map Select Register   { 3c5h    03h    R/W }
         ------------------------------------------------------
         <0>      Character Font Memory Map 'B' Partial Offset 16K byte
         <1>      Character Font Memory Map 'B' Partial Offset 32K byte
         <2>      Character Font Memory Map 'A' Partial Offset 16K byte
         <3>      Character Font Memory Map 'A' Partial Offset 32K byte
         <4>      Character Font Memory Map 'B' Partial Offset 08K byte
         <5>      Character Font Memory Map 'A' Partial Offset 08K byte
         <7..6>   Reserved.  Always <=00>.
         ------------------------------------------------------


6.04.06  Sequencer Memory Mode Register  { 3c5h    04h    R/W }
         ------------------------------------------------------
         <0>      Reserved.  Always <=0>.
         <1>      Memory Size Specification
         <2>      Processor Image Memory Access Mode Select
         <3>      Processor Image Memory Access Mapping Select
         <7..4>   Reserved.  Always <=0000>.
         ------------------------------------------------------


6.04.07  Horizontal Character Counter Reset Register...........
6.04.07  ................................{ 3c5h    07h    R/W }
         ------------------------------------------------------
         <7..0>   Horizontal Character Counter Reset
         ------------------------------------------------------


------------------------------------------------------------------------------




CRT Controller Registers
------------------------------------------------------------------------------


6.05.01  CRT Controller Address Register          { 3?4h    ---    R/W }
         ---------------------------------------------------------------
         <5..0>   CRT Controller Register Address
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.05.02  Horizontal Total Register                { 3?5h    00h    R/W }
         ---------------------------------------------------------------
         <7..0>   Horizontal Total
         ---------------------------------------------------------------


6.05.03  Horizontal Display Enable End Register   { 3?5h    01h    R/W }
         ---------------------------------------------------------------
         <7..0>   Horizontal Display Enable
         ---------------------------------------------------------------


6.05.04  Start Horizontal Blanking Register       { 3?5h    02h    R/W }
         ---------------------------------------------------------------
         <7..0>   Start Horizontal Blanking
         ---------------------------------------------------------------


6.05.05  End Horizontal Blanking Register         { 3?5h    03h    R/W }
         ---------------------------------------------------------------
         <4..0>   End Horizontal Blanking
         <6..5>   Display Enable Skew
         <7>      Light Pen Register Enable
         ---------------------------------------------------------------


6.05.06  Start Horizontal Retrace Pulse Register  { 3?5h    04h    R/W }
         ---------------------------------------------------------------
         <7..0>   Start Horizontal Retrace Pulse
         ---------------------------------------------------------------


6.05.07  End Horizontal Retrace Register          { 3?5h    05h    R/W }
         ---------------------------------------------------------------
         <4..0>   End Horizontal Retrace
         <6..5>   Horizontal Retrace Skew
         <7>      End Horizontal Blanking Bit 5
         ---------------------------------------------------------------


6.05.08  Vertical Total Register                  { 3?5h    06h    R/W }
         ---------------------------------------------------------------
         <7..0>   Vertical Total
         ---------------------------------------------------------------


6.05.09  CRT Controller Overflow Register         { 3?5h    07h    R/W }
         ---------------------------------------------------------------
         <0>      Vertical Total Bit 8
         <1>      Vertical Display Enable End Bit 8
         <2>      Vertical Retrace Start Bit 8
         <3>      Start Vertical Blank Bit 8
         <4>      Line Compare Bit 8
         <5>      Vertical Total Bit 9
         <6>      Vertical Display Enable End Bit 9
         <7>      Vertical Retrace Start Bit 9
         ---------------------------------------------------------------


6.05.10  Preset Row Scan Register                 { 3?5h    08h    R/W }
         ---------------------------------------------------------------
         <4..0>   Preset Row Scan
         <6..5>   Byte Panning Control
         <7>      Reserved.  Always <=0>.
         ---------------------------------------------------------------


6.05.11  Maximum Scan Line Register               { 3?5h    09h    R/W }
         ---------------------------------------------------------------
         <4..0>   Maximum Scan Lines
         <5>      Start Vertical Blank Bit 9
         <6>      Line Compare Bit 9
         <7>      Double Scan Line Display
         ---------------------------------------------------------------


6.05.12  Cursor Start Register                    { 3?5h    0ah    R/W }
         ---------------------------------------------------------------
         <4..0>   Cursor Row Scan Start
         <5>      Cursor Enable
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.05.13  Cursor End Register                      { 3?5h    0bh    R/W }
         ---------------------------------------------------------------
         <4..0>   Cursor Row Scan End
         <6..5>   Cursor Skew Control
         <7>      Reserved.  Always <=0>.
         ---------------------------------------------------------------


6.05.14  Start Address High Register              { 3?5h    0ch    R/W }
         ---------------------------------------------------------------
         <7..0>   Start Address High
         ---------------------------------------------------------------


6.05.15  Start Address Low Register               { 3?5h    0dh    R/W }
         ---------------------------------------------------------------
         <7..0>   Start Address Low
         ---------------------------------------------------------------


6.05.16  Cursor Location High Register            { 3?5h    0eh    R/W }
         ---------------------------------------------------------------
         <7..0>   Cursor Location High
         ---------------------------------------------------------------


6.05.17  Cursor Location Low Register             { 3?5h    0fh    R/W }
         ---------------------------------------------------------------
         <7..0>   Cursor Location Low
         ---------------------------------------------------------------


6.05.18  Vertical Retrace Start Register          { 3?5h    10h    R/W }
         ---------------------------------------------------------------
         <7..0>   Vertical Retrace Start
         ---------------------------------------------------------------


6.05.19  Vertical Retrace End Register            { 3?5h    11h    R/W }
         ---------------------------------------------------------------
         <3..0>   Vertical Retrace End
         <4>      Clear Vertical Interrupt
         <5>      Enable Vertical Interrupt
         <6>      Refresh Bandwidth Select
         <7>      CRTC Register Protect
         ---------------------------------------------------------------


6.05.20  Vertical Display Enable End Register     { 3?5h    12h    R/W }
         ---------------------------------------------------------------
         <7..0>   Vertical Display Enable End
         ---------------------------------------------------------------


6.05.21  Offset Register                          { 3?5h    13h    R/W }
         ---------------------------------------------------------------
         <7..0>   Display Image Offset
         ---------------------------------------------------------------


6.05.22  Underline Location Register              { 3?5h    14h    R/W }
         ---------------------------------------------------------------
         <4..0>   Underline Location
         <5>      Display Address Dwell Count 4
         <6>      Display Memory Address Unit 4
         <7>      Reserved.  Always <=0>.
         ---------------------------------------------------------------


6.05.23  Start Vertical Blanking Register         { 3?5h    15h    R/W }
         ---------------------------------------------------------------
         <7..0>   Start Vertical Blanking
         ---------------------------------------------------------------


6.05.24  End Vertical Blanking Register           { 3?5h    16h    R/W }
         ---------------------------------------------------------------
         <7..0>   End Vertical Blanking
         ---------------------------------------------------------------


6.05.25  CRTC Mode Control Register               { 3?5h    17h    R/W }
         ---------------------------------------------------------------
         <0>      Display Address 13 Remap Row 0
         <1>      Display Address 14 Remap Row 1
         <2>      Horizontal Retrace Divisor
         <3>      Display Address Dwell Count 2
         <4>      Reserved.  Always <=0>.
         <5>      Display Address Unit 2 Remap
         <6>      Display Memory Address Unit 2
         <7>      Horizontal/Vertical Retrace Reset
         ---------------------------------------------------------------


6.05.26  Line Compare Register                    { 3?5h    18h    R/W }
         ---------------------------------------------------------------
         <7..0>   Line Compare
         ---------------------------------------------------------------


------------------------------------------------------------------------------




Graphics Controller Registers
------------------------------------------------------------------------------


6.06.01  Graphics Address Register    { 3ceh    ---    R/W }
         ---------------------------------------------------
         <3..0>   Graphics Register Address
         <7..4>   Reserved. Always <=0000>.
         ---------------------------------------------------


6.06.02  Set/Reset Register           { 3cfh    00h    R/W }
         ---------------------------------------------------
         <0>      Set/Reset Data Image Plane 0
         <1>      Set/Reset Data Image Plane 1
         <2>      Set/Reset Data Image Plane 2
         <3>      Set/Reset Data Image Plane 3
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------


6.06.03  Enable Set/Reset Register    { 3cfh    01h    R/W }
         ---------------------------------------------------
         <0>      Set/Reset Enable Image Plane 0
         <1>      Set/Reset Enable Image Plane 1
         <2>      Set/Reset Enable Image Plane 2
         <3>      Set/Reset Enable Image Plane 3
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------


6.06.04  Colour Compare Register      { 3cfh    02h    R/W }
         ---------------------------------------------------
         <0>      Colour Compare Plane 0
         <1>      Colour Compare Plane 1
         <2>      Colour Compare Plane 2
         <3>      Colour Compare Plane 3
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------


6.06.05  Data Rotate Register         { 3cfh    03h    R/W }
         ---------------------------------------------------
         <2..0>   Data Rotate
         <4..3>   Logic Unit Function Code
         <7..5>   Reserved.  Always <=000>.
         ---------------------------------------------------


6.06.06  Read Map Select Register     { 3cfh    04h    R/W }
         ---------------------------------------------------
         <1..0>   Read Map Select
         <7..2>   Reserved.  Always <=000000>.
         ---------------------------------------------------


6.06.07  Graphics Mode Register       { 3cfh    05h    R/W }
         ---------------------------------------------------
         <1..0>   Processor Write Mode
         <2>      Reserved.  Always <=0>.
         <3>      Processor Read Mode
         <4>      Graphics Memory Access Mode
         <5>      Graphics Shift Register Mode
         <6>      Graphics 256 Colour Control
         <7>      Reserved.  Always <=0>.
         ---------------------------------------------------


6.06.08  Miscellaneous Register       { 3cfh    06h    R/W }
         ---------------------------------------------------
         <0>      Display Generation Mode
         <1>      Memory Plane Pairing Control
         <3..2>   Memory Map Mode
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------


6.06.09  Colour Don't Care Register   { 3cfh    07h    R/W }
         ---------------------------------------------------
         <0>      Colour Don't Care Plane 0
         <1>      Colour Don't Care Plane 1
         <2>      Colour Don't Care Plane 2
         <3>      Colour Don't Care Plane 3
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------


6.06.10  Bit Mask Register            { 3cfh    08h    R/W }
         ---------------------------------------------------
         <0>   Update Value Source Bit 0
         <1>   Update Value Source Bit 1
         <2>   Update Value Source Bit 2
         <3>   Update Value Source Bit 3
         <4>   Update Value Source Bit 4
         <5>   Update Value Source Bit 5
         <6>   Update Value Source Bit 6
         <7>   Update Value Source Bit 7
         ---------------------------------------------------


------------------------------------------------------------------------------




Attribute Controller Registers
------------------------------------------------------------------------------


6.07.01  Attribute Address Register       { 3c0h/I/W  3c0h/R  ---  R/W }
         ---------------------------------------------------------------
         <4..0>   Attribute Address
         <5>      Palette Control
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.02  Palette Register 00              { 3c0h/I/W  3c1h/R  00h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.03  Palette Register 01              { 3c0h/I/W  3c1h/R  01h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.04  Palette Register 02              { 3c0h/I/W  3c1h/R  02h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.05  Palette Register 03              { 3c0h/I/W  3c1h/R  03h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.06  Palette Register 04              { 3c0h/I/W  3c1h/R  04h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.07  Palette Register 05              { 3c0h/I/W  3c1h/R  05h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.08  Palette Register 06              { 3c0h/I/W  3c1h/R  06h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.09  Palette Register 07              { 3c0h/I/W  3c1h/R  07h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.10  Palette Register 08              { 3c0h/I/W  3c1h/R  08h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.11  Palette Register 09              { 3c0h/I/W  3c1h/R  09h  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.12  Palette Register 10              { 3c0h/I/W  3c1h/R  0ah  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.13  Palette Register 11              { 3c0h/I/W  3c1h/R  0bh  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.14  Palette Register 12              { 3c0h/I/W  3c1h/R  0ch  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.15  Palette Register 13              { 3c0h/I/W  3c1h/R  0dh  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.16  Palette Register 14              { 3c0h/I/W  3c1h/R  0eh  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.17  Palette Register 15              { 3c0h/I/W  3c1h/R  0fh  R/W }
         ---------------------------------------------------------------
         <5..0>   Colour Value
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.18  Attribute Mode Control Register  { 3c0h/I/W  3c1h/R  10h  R/W }
         ---------------------------------------------------------------
         <0>      Display Generation Mode
         <1>      Display Generation Mode
         <2>      Line Graphics Character Code Control
         <3>      Text Mode Attribute Select
         <4>      Reserved.  Always <=0>.
         <5>      Split Screen Panning Control
         <6>      Shift Register 256 Colour Assembly Latch
         <7>      External Colour Palette Input Select
         ---------------------------------------------------------------


6.07.19  Overscan Colour Register         { 3c0h/I/W  3c1h/R  11h  R/W }
         ---------------------------------------------------------------
         <7..0>   Overscan Colour
         ---------------------------------------------------------------


6.07.20  Colour Plane Enable Register     { 3c0h/I/W  3c1h/R  12h  R/W }
         ---------------------------------------------------------------
         <0>      Colour Plane Enable 0
         <1>      Colour Plane Enable 1
         <2>      Colour Plane Enable 2
         <3>      Colour Plane Enable 3
         <5..4>   Display Status Select
         <7..6>   Reserved.  Always <=00>.
         ---------------------------------------------------------------


6.07.21  Horizontal PEL Panning Register  { 3c0h/I/W  3c1h/R  13h  R/W }
         ---------------------------------------------------------------
         <3..0>   Horizontal PEL Panning
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------------------


6.07.22  Colour Select Register           { 3c0h/I/W  3c1h/R  14h  R/W }
         ---------------------------------------------------------------
         <1..0>   External colour palette bits <5..4>
         <3..2>   External colour palette bits <7..6>
         <7..4>   Reserved.  Always <=0000>.
         ---------------------------------------------------------------


------------------------------------------------------------------------------




DAC Registers
------------------------------------------------------------------------------


6.08.01  DAC Pixel Mask Register          { 3c6h   R/W }
         -----------------------------------------------
         <0>      DAC Pixel Mask 0 {Digital to Analogue Converter Pixel Mask}
         <1>      DAC Pixel Mask 1 {Digital to Analogue Converter Pixel Mask}
         <2>      DAC Pixel Mask 2 {Digital to Analogue Converter Pixel Mask}
         <3>      DAC Pixel Mask 3 {Digital to Analogue Converter Pixel Mask}
         <4>      DAC Pixel Mask 4 {Digital to Analogue Converter Pixel Mask}
         <5>      DAC Pixel Mask 5 {Digital to Analogue Converter Pixel Mask}
         <6>      DAC Pixel Mask 6 {Digital to Analogue Converter Pixel Mask}
         <7>      DAC Pixel Mask 7 {Digital to Analogue Converter Pixel Mask}
         -----------------------------------------------


6.08.02  DAC Status Register              { 3c7h   R-- }
         -----------------------------------------------
         <1..0>   DAC Status
         <7..2>   Reserved.  Always <=000000>.
         -----------------------------------------------


6.08.03  DAC Read Data Address Register   { 3c7h   W-- }
         -----------------------------------------------
         <7..0>   DAC Read Data Address
         -----------------------------------------------


6.08.04  DAC Write Data Address Register  { 3c8h   R/W }
         -----------------------------------------------
         <7..0>   DAC Write Data Address
         -----------------------------------------------


6.08.05  DAC Data Register                { 3c9h   R/W }
         -----------------------------------------------
         <7..0>   DAC Data
         -----------------------------------------------


------------------------------------------------------------------------------




General Registers
------------------------------------------------------------------------------


6.09.01  Miscellaneous Output Register  { 3c2h  W-- }
         --------------------------------------------
         <0>      Input Output Address Select
         <1>      Display Memory Access Enable
         <3..2>   Dot Clock Frequency Select
         <4>      Reserved.  Always <=0>.
         <5>      Address Extension Bit
         <6>      Horizontal Synchronisation Signal Polarity
         <7>      Vertical Synchronisation Signal Polarity
         --------------------------------------------


6.09.02  Miscellaneous Output Register  { 3cch  --R }
         --------------------------------------------
         <7..0>   Miscellaneous Output
         --------------------------------------------


6.09.03  Input Status Register Zero     { 3c2h  R-- }
         --------------------------------------------
         <3..0>   Reserved.  Always <=0000>.
         <4>      Monitor Detect Status Bit
         <6..5>   Reserved.  Always <=00>.
         <7>      CRT Controller Interrupt State
         --------------------------------------------


6.09.04  Input Status Register One      { 3?ah  R-- }
         --------------------------------------------
         <0>      Inverted Display Enable Status
         <1>      Reserved.  Always <=0>.
         <2>      Reserved.  Always <=0>.  {Trident 8900 <=1>.}
         <3>      Vertical Retrace State
         <5..4>   Video Sampling State
         <7..6>   Reserved.  Always <=00>.
         --------------------------------------------


------------------------------------------------------------------------------




Special Registers
------------------------------------------------------------------------------


6.10.01  Hardware Version Register {new definition}  { 3c5h    0bh    R-- }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <3..0>   Chip version identification   {Trident}
         <7..4>   Reserved.
         ------------------------------------------------------------------


6.10.02  Version Selector Register {old definition}  { 3c5h    0bh    --W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         see main text body for details
         ------------------------------------------------------------------


6.10.03  Configuration Port Register 1               { 3c5h    0ch    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         Definition {only when NMI disabled}
         ------------------------------------------------------------------
         <0>      Address Decode Source
         <1>      ROM Chip Count Specify
         <2>      Reserved.
         <3>      ROM Address Span Specify
         <4>      VGA Control Port Specify
         <6..5>   DRAM Configuration
         <7>      DRAM Access Width
         ------------------------------------------------------------------
         Definition {only when NMI enabled}
         ------------------------------------------------------------------
         <0>      Software Status
         <1>      NMI State {Non Maskable Interrupt State}
         <3..2>   Testing Bits
         <7..4>   NMI Vector Enable
         ------------------------------------------------------------------


6.10.04  Mode Control Register 2                     { 3c5h    0dh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         New Definition
         ------------------------------------------------------------------
         <0>      Dot Clock Extended Select
         <2..1>   Dot Clock Division Ratio Select
         <3>      Software Status
         <5..4>   Software Status
         <7..6>   General Purpose Outputs
         ------------------------------------------------------------------
         Old Definition
         ------------------------------------------------------------------
         <2..0>   Video Generation Mode Select
         <3>      Processor Bandwidth during Blanking
         <4>      Memory Plane Architecture Select
         <5>      DRAM Clock Control
         <7..6>   Character Set Select High Extend
         ------------------------------------------------------------------


6.10.05  Mode Control Register 1                     { 3c5h    0eh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         New Definition
         ------------------------------------------------------------------
         <0>      Segment Selector
         <1>      Page Selector
         <3..2>   Bank Selector
         <6..4>   Software Status
         <7>      Write Protection State
         ------------------------------------------------------------------
         Old Definition
         ------------------------------------------------------------------
         <0>      Display Access Bank Selector
         <2..1>   Processor Access Bank Selector
         <3>      DRAM Access Width
         <4>      Reserved for Dot Clock Extended Select
         <5>      NMI State {Non Maskable Interrupt State}
         <6>      Interrupt Request Polarity Select
         <7>      Clock Pins Function Select
         ------------------------------------------------------------------


6.10.06  Power-up Mode Register 2                    { 3c5h    0fh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <3..0>   DIP Switch Image
         <4>      Bus Protocol Select
         <5>      Input Output Address Map Select
         <6>      ROM BIOS Address Decode Enable
         <7>      ROM BIOS Data Path Width
         ------------------------------------------------------------------


6.10.07  CRTC Module Testing Register                { 3?5h    1eh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <0>      Horizontal Clock Select
         <1>      Character Clock Select
         <2>      Interlace Enable
         <3>      Multipurpose Select
         <4>      CRT Controller Register Protection State
         <5>      Start Address Extension Bit 16
         <6>      Miscellaneous Output Register Protect State
         <7>      Start Address Extension Enable
         ------------------------------------------------------------------


6.10.08  Software Programming Register               { 3?5h    1fh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <1..0>   Reserved for BIOS use.
         <3..2>   Software Status Bits
         <7..4>   Reserved for BIOS use.  Do NOT disturb.
         ------------------------------------------------------------------


6.10.09  CPU Latch Read Back Register                { 3?5h    22h    R-- }
---------------------------------------------------------------------------
         standard register officially undocumented
         ------------------------------------------------------------------
         <7..0>   CPU Latch Read Back
         ------------------------------------------------------------------


6.10.10  Attribute State Read Back Register          { 3?5h    24h    R-- }
---------------------------------------------------------------------------
         standard register officially undocumented
         ------------------------------------------------------------------
         <4..0>   Attribute Controller Index
         <5>      Colour Palette Address Source {Internal palette}
         <6>      Reserved.
         <7>      Attribute State Read Back
         ------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <6..0>   Reserved.  Undefined.
         <7>      Attribute State Read Back
         ------------------------------------------------------------------


6.10.11  Attribute Index Read Back Register          { 3?5h    26h    R-- }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <4..0>   Attribute Index
         <7..5>   Reserved.
         ------------------------------------------------------------------


6.10.12  Clear Vertical Display Enable Register      { 3?5h    3nh    W-- }
---------------------------------------------------------------------------
         standard register officially undocumented
         ------------------------------------------------------------------
         <0>      Clear Vertical Display Enable
         <7..1>   Unused.  Any value can be present.
         ------------------------------------------------------------------


6.10.13  Source Address Register                     { 3cfh    0eh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         see main text body for details
         ------------------------------------------------------------------


6.10.14  Source Address Enable Register              { 3cfh    0fh    R/W }
---------------------------------------------------------------------------
         Trident 8900 only
         ------------------------------------------------------------------
         <0>      Source Address Enable
         <7..1>   Reserved.  Always <=0000000>.
         ------------------------------------------------------------------


------------------------------------------------------------------------------




Thank you for using this reference work.  If you have any useful comments which
others would benefit from, please do take a little of your valuable time to let
me know your thoughts.  Only by so doing will this work improve over time.  The
author really wants to hear!


[End of file: vga.doc]