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p102.jpg
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Tile
Joint Photographic Experts Group Image
|
2002-07-08
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178.8 KB
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960x1263
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8-bit (256 colors)
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ocr:
6522 VIA Control Registers 102 7 6 5 4 3 2 1 0 Timer 1( Ctrl Cores Shift Reg Control LatchCtr! Auxillary Control Register (Chip Address- +1 11) 0 0 PAI Latch disabled, PB Latch disabled 1 1 PAI Latch enabled, PBI Latch enabled 0 0 0 Shift Register disabled 0 0 1 Shift IN: shift rate controlled by Timer 2 0 1 0 Shift IN: shift rate controlled by $2 0 1 1 Shift IN: shift rate controlled by External Clock source 1 0 0 Shift OUT: Free-Running Mode, rate controlled by Timer2 1 0 1 Shift OUT: rate controlled by Timer 2 1 1 0 Shift OUT: rate controlled by 02 1 1 1 Shift OUT: rate controlled by Extern ...