ocr: IDALI DATAOUT OUFFEAS DATA COMMANO SECTOR TAACK STATUS REG REG REG REG REG DATA RD SHIFT AEG ALU AM DETECTOR DATA SEPARATOA WRITE CACLOGIC PRECOMP WD DAO WG INTRO WPRT MA CS TP AW COMPUTER CONTROL PLA CONTROL OISK TROO INTEAFACE CONTAOL INTERFACE AO CONTROL 1240x19) CONTROL STEP A1 OIRC ROY CLKI8MH21 (MOTORONI DOEN FIGURE 1. WD177X-00 BLOCK DIAGAAM Timing and Contral All computer and Floppy Disk PROCESSOR INTERFACE Intertace controls are generated through this logic. The interface to the processor is accomplished The internal device timing is generated from an exter- nal crystal clock. The WD1 ...
