ocr: INTEGRATED CIRCUIT TOSHIBA T6721A, T6772 TECHNICAL DATA T6684 ADDRESS ACH DATA ADLE MEMORY LABEL ALFESS PUVSICAL START AREM VOICE DATA CPU ABEL IS LOADED BY ACLE AND START ADDRESS VOICE DATA ROM IS READ BY RRDM. ADDRESS ROH DATA MEMORY ADLD ABTALTS VOICE DATA CPU START ADDRESS VOICE DATA ROM 19 RELOADED BY ADLD. (6) - ESY Output The period in which ESY signal is generated from T6721A is that period during which WR and RD from CPU must not be accepted by the synthesiz- ing ayscem. If WR or RD is performed disregarding chis period, the synthasizing ayacan does not accept WR or RD at all or opera ...
