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Text File | 1996-11-27 | 31.2 KB | 1,211 lines

cOMMODORE 8-BIT ic tECHNICAL rEFlAST UPDATED: 15.11.1996 tHIS FILE IS PART OF THE x64 eMULATOR PROJECT. c= cOMMODORE sEMICONDUCTOR gROUP mICROPROCESSORS pERIPHERAL iNTERFACE dEVICES vIDEO dISPLAY dEVICES sPECIAL aPPLICATION 6581/6582 sOUND iNTERFACE dEVICE (sid) sTATIC rEAD oNLY mEMORY sIGNETICS 82 s 100 fIELD pROGRAMMABLE lOGIC aRRAY ------------------------------------------------------------------------------- c= cOMMODORE sEMICONDUCTOR gROUP mICROPROCESSORS dESCRIPTION tHE 6500/8500 sERIES FAMILY INCLUDES A RANGE OF SOFTWARE COMPATIBLE MICRO- PROCESSORS WHICH PROVIDE A SELECTION OF ADDRESSABLE MEMORY RANGE, INTERRUPT INPUT OPTIONS AND ON-CHIP OSCILLATORS AND DRIVERS. aLL OF THE MICROPROCESSORS WITHIN THE GROUP ARE DIRECTLY BUS COMPATIBLE WITH THE mc6800 SERIES ic'S. tHE FAMILY INCLUDES TEN MICROPROCESSORS WITH ON-BOARD CLOCK OSCILLATORS AND SEVEN MICROPROCESSORS DRIVEN BY EXTERNAL CLOCKS. tHE ON-CHIP CLOCK VERSIONS ARE AIMED AT HIGH PERFORMANCE, LOW COST APPLICATIONS WHERE SINGLE PHASE CRYSTAL OR rc INPUTS PROVIDE THE TIME BASE. tHE EXTERNAL CLOCK VERSIONS ARE GEARED FOR MULTIPROCESSOR SYSTEM APPLICATIONS WHERE MAXIMUM TIMING CONTROL IS MANDATORY. cOMMON fEATURES sINGLE +5 VOLT SUPPLY n CHANNEL, SILICON GATE, DEPLETION LOAD TECHNOLOGY tRI-STATE ADDRESS BUS, DATA BUS AND r/w CONTROLLED BY aec INPUT "rEADY" INPUT (FOR SINGLE CYCLE EXECUTION) dIRECT MEMORY ACCESS CAPABILITY tRUE INDEXING CAPABILITY dECIMAL AND BINARY ARITHMETIC 56 iNSTRUCTIONS WITH 13 ADDRESSING MODES 8 BIT PARALLEL PROCESSING 8 BIT bI-DIRECTIONAL dATA bUS pROGRAMMABLE sTACK pOINTER aDDITIONAL fEATURES ON 6510 8-bIT bI-DIRECTIONAL i/o pORT vARIABLE LENGTH STACK iNTERRUPT CAPABILITY aDDRESSABLE MEMORY RANGE OF UP TO 64k BYTES bUS COMPATIBLE WITH m6800 pIPELINE ARCHITEHTURE 1 AND 2 mhZ OPERATION uSE WITH ANY TYPE OR SPEED MEMORY aVAILABLE mICROPROCESSORS dEVICE*cLOCKSpINSirq nmi rdypORTaDDRESSaec sYNC sPEED (mhZ) 6502 o40 x x x-64k - x 1,2,3,4 65ce02 o40 x x x-64k - x 0 - 10 6503 o28 x x -- 4k - - 1,2,3,4 6504 o28 x - -- 8k - - 1,2,3,4 6505 o28 x - x- 4k - - 1,2,3,4 6506 o28 x - -- 4k - - 1,2,3,4 6507 o28 - - x- 8k - - 1,2,3,4 6508 e40 x - -864k x - 1,2,3 6509 e40 x x x**1 m x x 1,2,3 6510 o,e40 x x x6,864k x - 1,2,3,4 r6511 6512 e40 x x x-64k - x 1,2,3,4 6513 e28 x x -- 4k - - 1,2,3,4 6514 e28 x - -- 8k - - 1,2,3,4 6515 e28 x - x- 4k - - 1,2,3,4 7501SAME AS 8501 8500SAME AS 6510 8501 o40 x - x7 (8?)64k x - 1,2,3 8502 o40 x x x764k x - 1,2,3,4 8503 o40 x - -864k x - 1,2,3,4 * o - oN CHIP CLOCKS, e - eXTERNAL cLOCKS ** fOUR EXTENDED ADDRESS PINS EXPAND MEMORY CAPACITY TO ONE MEGABYTE. pINOUT pIN65026510/85007501/85018502 1vSSpHI0 INpHI0 INpHI0 IN 2rdyrdyrdyrdy 3pHI1 OUT/irq/irq/irq 4/irq/nmiaec/nmi 5ncaecvCCaec 6/nmivCCa0vCC 7sYNCa0a1a0 8vCCa1a2a1 9ab0a2a3a2 10ab1a3a4a3 11ab2a4a5a4 12ab3a5a6a5 13ab4a6a7a6 14ab5a7a8a7 15ab6a8a9a8 16ab7a9a10a9 17ab8a10a11a10 18ab9a11a12a11 19ab10a12a13a12 20ab11a13gnda13 21vSSgnda14gnd 22ab12a14a15a14 23ab13a15gate ina15 24ab14p5p7p6 25ab15p4p6p5 26d7p3p4p4 27d6p2p3p3 28d5p1p2p2 29d4p0p1p1 30d3d7p0p0 31d2d6d7d7 32d1d5d6d6 33d0d4d5d5 34r/wd3d4d4 35ncd2d3d3 36ncd1d2d2 37pHI0 INd0d1d1 38sor/wd0d0 39pHI2 OUTpHI2 OUTr/wr/w 40/res/res/res/res pERIPHERAL pORT dESCRIPTION 8502 i/o rEGISTERS c128 MODE: 0000X0101111 0001XcAPSmOTORsENSEwRITEhiramloramcharen hiram,loram = COLOUR MEMORY BANK SELECTION charen = CHARACTER GENERATOR rom ENABLE/DISABLE 6510 c64 MODE: 000007-0mos 8502 dATA dIRECTION rEGISTER (XX101111) bIT= 1: oUTPUT, bIT=0: iNPUT, X = dON'T cARE 00011mos 8502 mICRO-pROCESSOR oN-cHIP i/o pORT 0/loram sIGNAL (0 = sWITCH basic rom oUT) 1/hiram sIGNAL (0 = sWITCH kERNAL rom oUT) 2/charen sIGNAL (0 = sWITH cHAR. rom iN) 3cASSETTE dATA oUTPUT lINE 4cASSETTE sWITCH sENSE: 1 = sWITCH cLOSED 5cASSETTE mOTOR cONTROL:0 = on, 1 = off 6-7uNDEFINED (BIT 6 IS cAPS LOCK ON THE c128) vic-20 AND pet tHERE IS NO pERIPHERAL pORT ON THE 6502. pERIPHERAL iNTERFACE dEVICES dEVICE: 6520 = pia (pARALLEL iNTERFACE aDAPTER) == mc6821 6522 = via (vERSATILE iNTERFACE aDAPTER) 6526 = cia (cOMPLEX iNTERFACE aDAPTER) 6532 = riot (ram, i/o AND tIMER) [uSED IN aTARI 2600] dESCRIPTION cOMMODORE OFFERS A WIDE ASSORTMENT OF PERIPHERAL INTERFACE DEVICES COMPATIBLE WITH THE 6500/8500 MICROPROCESSOR FAMILY. tHESE DEVICES WERE SPECIFICALLY DESIGNED TO SIMPLIFY THE IMPLEMENTATION OF iNPUT/oUTPUT CONTROL IN MICRO- PROCESSOR SYSTEMS. aLL OF THESE DEVICES ARE ttl COMPATIBLE, HAVE A SINGLE +5 VOLT SUPPLY, AND ARE BASED ON n-CHANNEL DEPLETION LOAD TECHNOLOGY. eACH DEVICE FEATURES FROM 8 TO 24 INDIVIDUALLY PROGRAMMABLE i/o LINES. aDDITIONAL FUNC- TIONS ON SELECTED DEVICES INCLUDE HANDSHAKING CAPABILITY, CONTROL/INTERRUPT INPUT LINES, INTERRUPT OUTPUT, SERIAL i/o, TIMERS, ram, AND rom. aVAILABLE pERIPHERAL dEVICES hAND-cONTROL/ dARLING- 8-BIT SHAKING iNTERRUPT TON sERIAL tIMER/ sPEED dEVICE pINS pORTS irq (pORT) i/p lINES dRIVE i/o tIMERS cOUNTERS ram (mhZ) 652040 2 2 652240 2 x rEAD a 4/4 pORT b x oNEoNE - 1,2 wRITE a,b cb1,cb2 16-BIT 16-BIT 652540 3** x rEAD a 2/5 - - - - - *** wRITE b 6526*40 2 x rEAD b 2/1 - x -tWO - 1,2,3 **** wRITE b16-BIT 652920 1 -- - - - - - - *** 653040 2 x- - pORT a,b - oNE - 64X8 1,2 8-BIT rom 1024X8 653240 2 x- - pORT b - oNE - 128X8 1,2 8-BIT 852040 2 x rEAD b 2/1 - x -tWO - 1,2 wRITE b16-BIT * nOTE: sUPPORTS tIME OF dAY cLOCK FUNCTION. ** nOTE: 2 PORTS IF USING CONTROL/INTERRUPT LINES. *** nOTE: tHESE DEVICES ARE NOT CLOCKED. sPEED IS DETERMINED BY ACCESS TIME. **** 6526 IS THE 1mhZ VERSION WHILE 6526a IS RATED FOR 2mhZ. eITHER ONE CAN BE USED ON cbm 8-BIT MACHINES, (c64, c128) AS THE i/o IS ALWAYS CLOCKED AT 1mhZ. pINOUT pIN652065226526 1vSSgnd 2pa0pa0 3pa1pa1 4pa2pa2 5pa3pa3 6pa4pa4 7pa5pa5 8pa6pa6 9pa7pa7 10pb0pb0 11pb1pb1 12pb2pb2 13pb3pb3 14pb4pb4 15pb5pb5 16pb6pb6 17pb7pb7 18cb1/pc 19cb2tod IN 20vCCvCC 21/irq/irq 22r/wr/w 23/cs2/cs 24cs1/flag 25pHI2pHI2 26d7d7 27d6d6 28d5d5 29d4d4 30d3d3 31d2d2 32d1d1 33d0d0 34/res/res 35rs3rs3 36rs2rs2 37rs1rs1 38rs0rs0 39ca2sp 40ca1cnt -- fROM: SCHAEFER@CLUSTER.DFKI.UNI-SB.DE (uLRICH sCHAEFER) sUBJECT: rE: 1551 FLOPPY DRIVE (AND: cbm 600 / 6525 tpi) iT IS POSSIBLE TO CONNECT TWO 1551S BECAUSE ONE DRIVE CAN HAVE TWO DIFFERENT DEVICE NUMBERS. iF (AND ONLY IF) YOU GIVE THEM TWO DIFFERENT NUMBERS, YOU CAN PLUG BOTH INTO THE COMPUTER (YOU WILL NEED A LARGE TABLE, OF COURSE...). sEE THE 1551'S USER'S GUIDE, APPENDIX a, PAGE 72. tHERE, THEY EXPLAIN HOW TO CHANGE THE DEVICE NUMBER BY SIMPLY REMOVING A JUMPER ON THE MAIN CIRCUIT OF THE DRIVE. i GUESS YOU DO NOT HAVE WARRANTY ANY MORE... tHE JUMPER SELECTS THE DECODING OF THE 6523 WHICH IS IN THE INTERFACE CARTRIDGE (BUT USES ADDRESS SPACE OF THE COMPUTER'S cpu!). iF THE DEVICE NUMBER IS 8, THE 6523'S BASE ADDRESS (AT THE COMPUTER SIDE) IS $fef0. iF THE DEVICE NUMBER IS 9, ITS BASE ADDRESS IS $fec0. bECAUSE OF THIS FIXED DECODING, NO MORE THAN TWO 1551S CAN BE PLUGGED INTO THE COMPUTER WITHOUT MAJOR CHANGES. mICHAEL CALLED THE 6523 A TRIPLE INTERFACE ADAPTER (WHICH IS IT'S OFFICIAL NAME, i GUESS). i WOULD RATHER CALL IT A CRIPPLE INTERFACE ADAPTER. iN MY OPINION, THE 6523 IS JUST A 'CRIPPLE' 6525 tpi (WHICH IS WELL KNOWN FROM THE cbm 500/600/700 SERIES, WHERE TWO OF THEM CONTROL THE ieee AND USER PORT INTERFACE). tHE 6525 HAS THREE 8 BIT PORTS (I.E. tpi=TRI PORT INTERFACE) AND 40 PINS, WHILE THE 6523 HAS THREE 'CRIPPLE' PORTS AND ONLY 28 PINS (WHICH MAKE IT CHEAPER). i GUESS THE INTERNAL ARCHITECTURE OF BOTH IS THE SAME. bOTH THE 6523 AND THE 6525 HAVE THREE DATA AND THREE DIRECTION REGISTERS. tHE 6525 HAS TWO ADDITIONAL: A CONTROL AND AN 'ACTIVE INTERRUPT REGISTER'. aDDRESS 6525 tpi 6523 tia -------------------------------------------------------------------------- 0 pORT a dATA pORT a dATA (FULL 8 BIT) 1 pORT b dATA pORT b dATA (ONLY BITS 0+1?) 2 pORT c dATA OR INTERRUPT LATCH REG. pORT c dATA (ONLY BITS 6+7?) 3 pORT a dIRECTION pORT a dIRECTION 4 pORT b dIRECTION pORT b dIRECTION 5 pORT c dIRECTION OR mir INTERR. MASK pORT c dIRECTION 6 cONTROL REG. - (?) 7 aCTIVE iNTERRUPT REG. - (?) tHIS IS WHAT i FOUND IN MY NOTES FROM 1987. i DO NOT HAVE ANY DATA SHEETS OF THESE CIRCUITS. iF ANYBODY HAS, i WOULD BE INTERESTED, BECAUSE i PLAN TO RE-USE MY OLD cbm 610 ... iN THE 1551 CARTRIDGE, PORT a OF THE 6523 IS USED AS THE DATA PORT (8 BIT PARALLEL, WHICH MAKES IT SO FAST). bIT 0 AND 1 OF PORT b ARE USED AS STATUS BITS, AND BIT 6 AND 7 OF PORT c ARE USED FOR 'BUSY' AND 'STROBE' (THIS IS WHAT i CALLED THEM IN MY NOTES). -- nEWSGROUPS: COMP.SYS.CBM fROM: RHIALTO@MBFYS.KUN.NL (oLAF sEIBERT) dATE: sUN, 30 aPR 1995 02:34:11 gmt fROM: pETio.DOC v1.2 08.01.95 riot 6532 --------- sOURCE: toUche MANUAL: THE KEYBOARD FOR THE aPPLE-ii CLONE FROM THE cOMPUTER hOBBYVERENIGING eINDHOVEN. (tHEY GOT ddra AND ddrb REVERSED.) tHE riot IS USED AT LEAST IN THE DISKDRIVES OF TYPE 2040, 3040, 4040, 8050, 8250. tHEY CONTAIJN TWO riotS (AT $0200 AND $0280) AND A via (AT $????). tHE riot (ram, i/o AND tIMER) HAS 128 BYTES OF ram, 2 8-BIT BIDIRECTIONAL i/o PORTS, AND A TIMER THAT CAN COUNT DOWN AT 4 DIFFERENT RATES. rEG.nAMEdESCRIPTION --------------------------- 0papORT a DATA 1ddrapORT a dATA dIRECTION rEGISTER 2pbpORT b DATA 3ddrbpORT b dATA dIRECTION rEGISTER 4tIMERtIMER READ REGISTER 14,0et11 CLOCKS PER DECREMENT 15,0ft88 16,10t6464 17,11t10241024 tHE dATA AND ddr REGISTERS ARE AS USUAL. tHE INPUT IS A BUFFER, THE OUTPUT IS A LATCH. tHE tIMER REGISTER READS OUT THE TIMER VALUE; ITS INITIAL VALUE IS SET BY WRITING INTO THE t1..t1024 REGISTERS. wHICH ONE IS USED DETERMINES THE NUMBER OF CLOCK CYCLES BETWEEN DECREMENTS OF THE tIMER REGISTER. tHE CHIP ALSO HAS AN irq LINE BUT THE CITED SOURCE DOES NOT SAY ANYTHING FURTHER ABOUT IT. tHE 8050 FDC ROM USAGE SUGGESTS AN IRQ IS GENERATED ON TIMER UNDERFLOW, WITH NO SPECIAL SETUP REQUIRED. pINOUT: 1 0v 21pb3 2 a5aDDRESS LINES 22pb2 3 a4(SEE ALSO PIN 40) 23pb1 4 a3 24pb0 5 a2 25irqN 6 a1 26d7dATA BUS LINES 7 a0 27d6 8 pa0 pORT a DATA 28d5 9 pa1 29d4 10 pa2 30d3 11 pa3 31d2 12 pa4 32d1 13 pa5 33d0 14 pa6 34resNrESET 15 pa7 35r/wN 16 pb7 pORT b DATA 36rsNram sELECT 17 pb6 37csN 18 pb5 38cscIRCUIT sELECT 19 pb4 39phi2cLOCK 20 +5v 40a6aDDRESS LINE ------------------------------------------------------------------------------- vIDEO dISPLAY dEVICES dESCRIPTION cOMMODORE'S FAMILY OF vIDEO cONTROLLERS OFFERS ATTRACTIVE INTEGRATION OF ALL VIDEO LOGIC NECESSARY FOR COLOR VIDEO GRAPHICS AND TEXT APPLICATIONS, SUCH AS LOW COST crt TERMINALS, INDUSTRIAL MONITORS, CONTROL SYSTEM DISPLAYS AND HOME VIDEO GAMES. cOMPLETE LOGIC TO IMPLEMENT ALL FORMAT TIMING, MEMORY INTERFACE, ATTRIBUTE CONTROL, ROW BUFFERING AND HIGH-SPEED SHIFTING OF PIXEL DATA ARE RESIDENT IN EACH DEVICE. tHE FAMILY OF vic ii AND ted DEVICES PROVIDE FIXED FORMAT DISPLAY WITH 5 SEPA- RATE CHARACTER/BIT-MAP MODES OF OPERATION. a RASTER cOMPARE iNTERRUPT ALLOWS THE EASY MIXING OF THESE MODES FOR DISPLAY OF HIGH-RES GRAPHICS WITH TEXT. a TRANSPARENT SCHEME OF USING pHo TIME FOR FETCHING VIDEO DATA FROM MEMORY ALLOWS FOR OPTIMAL cpu THRUPUT. tHE vicS A{$7c}SO CONTAIN A SPECIAL TYPE OF DISPLAY IMAGE, mOVABLE iMAGE bLOCK (mib), THAT ONCE DEFINED, CAN BE MOVED TO ANY SCREEN POSI- TION WITHOUT THE INHERENT CHARACTER CELL CONSTRAINTS. tHE PROGRAMMABLE 8563/68 FEATURES DIGITAL rgbi OUTPUT FOR VERY SHARP 640vX400h COLOR VIDEO. dIRECT VIDEO MEMORY INTERFACE TO 64k OF dram REQUIRES NO EXTERNAL LOGIC. aVAILABLE vIDEO dEVICES ------------------------------------------------------------------------------- dEVICE: vic pART nO: 6560 (ntsc (ntsc-m)) 6561 (pal-b) dISPLAY fORMAT: PROGRAMMABLE UP TO 24X25 TEXT, 192hX200v BIT-MAP *) dISPLAY mODES: 2 CHARACTER MODES: hIrES, mULTICOLOR vIDEO oUTPUT: 16 COLOR COMPOSITE fEATURES: ON CHIP SOUND SYSTEM, 2 8-BIT a/d CONVERTERS, INTERLACE/NON-INTERLACE, LIGHT PEN INPUT mEMORY iNTERFACE:ACCESS 16k, TRANSPARENT dma pINS: 40 sUPPLY: +5v *) mR. m{$e4}KEL{$e4} SAID: 6561:N TARKKUUS ON MITTAUSTENI MUKAAN 232 * 282, MERKKEIN{$e4} 29 * 35. kELLOJAKSOJA ON JUOVALLA 71 JA JUOVIA 312. 6560:SSA ON KELLOJAKSOJA JUOVALLA 65 JA JUOVIA 261. dESCRIPTION tHE 6560 vIDEO iNTERFACE cHIP (vic) IS DESIGNED FOR COLOR VIDEO GRAPHICS APPLICATIONS SUCH AS LOW COST crt TERMINALS, BIOMEDICAL MONITORS, CONTROL SYSTEM DISPLAYS AND ARCADE OR HOME VIDEO GAMES. iT PROVIDES ALL OF THE CIRCUITRY NECESSARY FOR GENERATING COLOR PROGRAMMABLE CHARACTER GRAPHICS WITH HIGH SCREEN RESOLUTION. vic ALSO INCORPORATES SOUND EFFECTS AND a/d CONVERTERSFOR USE IN A VIDEO GAME ENVIRONMENT. fEATURES fULLY EXPANDABLE SYSTEM WITH A 16k BYTE ADDRESS SPACE sYSTEM USES INDUSTRY STANDARD 8 BIT WIDE romS AND 4 BIT WIDE ramS mASK PROGRAMMABLE SYNC GENERATION, ntsc-6560, pal-6561 oN-CHIP COLOR GENERATION (16 COLORS) uP TO 600 INDEPENDENTLY PROGRAMMABLE AND MOVABLE BACKGROUND LOCATIONS ON A STANDARD tv sCREEN CENTERING CAPABILITY sCREEN GRID SIZE UP TO 192 hORIZONTAL AND 200 vERTICAL DOTS tWO SELECTABLE GRAPHIC CHARACTER SIZES oN-CHIP SOUND SYSTEM INCLUDING: A) tHREE INDEPENDENT, PROGRAMMABLE TONE GENERATORS B) wHITE NOISE GENERATOR C) aMPLITUDE MODULATOR tWO ON-CHIP 8 BIT a/d CONVERTERS oN-CHIP dma AND ADDRESS GENERATION nO cpu WAIT STATES OR SCREEN HASH DURING SCREEN REFRESH iNTERLACED/nON-iNTERLACED SWITCH 16 ADDRESSABLE CONTROL REGISTERS 2 MODES OF COLOR OPERATION pINOUT pIN6560/6561 1nc 2cOMP cOLOR 3sYNC & lUMIN 4r/w 5db11 6db10 7db9 8db8 9db7 10db6 11db5 12db4 13db3 14db2 15db1 16db0 17pot x 18pot y 19cOMP sND 20vSS 21a0 22a1 23a2 24a3 25a4 26a5 27a6 28a7 29a8 30a9 31a10 32a11 33a12 34a13 35p pHI 1 36p pHI 2 37oPTION 38pHI 2 iN 39pHI 1 iN 40vDD ------------------------------------------------------------------------------- dEVICE: vic ii pART nO: 6566 (ntsc (ntsc-m), NON-MULTIPLEXED ADDRESS LINES) 6567 (ntsc (ntsc-m)) 6569 (pal-b) 6572 (pal-n) 6573 (pal-m) 8562 (ntsc (ntsc-m)) 8565 (pal-b) dISPLAY fORMAT: 40X25 TEXT, 320hX200v BIT-MAP dISPLAY mODES: 3 CHARACTER MODES: sTANDARD, mULTICOLOR, eXTENDED 2 BIT-MAP MODES: hIrES, mULTICOLOR vIDEO oUTPUT: 16 COLOR COMPOSITE fEATURES: 8 mib'S (SPRITES), HORIZ. AND VERT. SCROLLING, LIGHT PEN INPUT, rASTER cOMPARE iNTERRUPT mEMORY iNTERFACE:ACCESS 16k, INTERFACE TO MULTIPLEXED dram, TRANSPARENT dma, PROVIDES SYSTEM ras AND cas (EXCEPT 6566) pINS: 40 sUPPLY 65XX:+5v AND +12v 85XX:+5v dESCRIPTION tHE 6566/6567 ARE MULTI-PURPOSE COLOR VIDEO CONTROLLER DEVICES FOR USE IN BOTH COMPUTER VIDEO TERMINALS AND VIDEO GAME APPLICATIONS. bOTH DEVICES CONTAIN 47 CONTROL REGISTERS WHICH ARE ACCESSED VIA A STANDARD 8-BIT MICROPROCESSOR BUS (65xx) AND WILL ACCESS UP TO 16k OF MEMORY FOR DISPLAY INFORMATION. pINOUT pIN65666567/65698565 1db6db6 2db5db5 3db4db4 4db3db3 5db2db2 6db1db1 7db0db0 8/irq/irq 9lplp 10/cs/cs 11r/wr/w 12baba 13vDD (+12v)vDD (+12v)vDD (+5v) 14cOLORcOLOR 15s/lums/lum 16aecaec 17ph0ph0 18phin/ras 19phcol/cas 20vSSvSS 21a0phcl 22a1phin 23a2a11 24a3a0 (a8) 25a4a1 (a9) 26a5a2 (a10) 27a6a3 (a11) 28a7a4 (a12) 29a8a5 (a13) 30a9a6 ("1") 31a10a7 32a11a8 33a12a9 34a13a10 35db11db11 36db10db10 37db9db9 38db8db8 39db7db7 40vCCvCCvCC ------------------------------------------------------------------------------- dEVICE: vic iie pART nO: 8564 (ntsc (ntsc-m)) 8566 (pal-b) 8569 (pal-n) dISPLAY fORMAT: 40X25 TEXT, 320hX200v BIT-MAP dISPLAY mODES: 3 CHARACTER MODES: sTANDARD, mULTICOLOR, eXTENDED 2 BIT-MAPO MODES: hIrES, mULTICOLOR vIDEO oUTPUT: 16 COLOR COMPOSITE fEATURES: 8 mib'S (SPRITES), HORIZ. AND VERT. SCROLLING, LIGHT PEN INPUT, rASTER cOMPARE iNTERRUPT, kEYBOARD cONTROL rEGISTER, 2mhZ CLOCK, TRUE EXTERNAL dma AND ARBITRATION CONTROL mEMORY iNTERFACE:ACCESS 16k, INTERFACE TO MULTIPLEXED dram, TRANSPARENT dma, PROVIDES SYSTEM ras AND cas pINS: 48 sUPPLY: +5v pINOUT pIN8564/8566 1d6 2d5 3d4 4d3 5d2 6d1 7d0 8/irq 9lp 10ba 11- 12aec 13/cs 14r/w 15- 16cOLOR 17sYNC 181mhZ 19/ras 20/cas 21mux 22ioacc 232mhZ 24vSS 25z80 pHI 26k0 27k1 28k2 29ph_cl 30ph_in 31a11 32a0 33a1 34a2 35a3 36a4 37a5 38a6 39a7 40a8 41a9 42a10 43d11 44d10 45d9 46d8 47d7 48vDD ------------------------------------------------------------------------------- dEVICE: ted pART nO: 7360/8360 (ntsc-m / pal-b BY SAME CHIP) 8365 (pal-n) 8366 (pal-m) dISPLAY fORMAT: 40X25 TEXT, 320hX200v BIT-MAP dISPLAY mODES: 3 CHARACTER MODES: sTANDARD, mULTICOLOR, eXTENDED 2 BIT-MAPO MODES: hIrES, mULTICOLOR vIDEO oUTPUT: 121 COLOR COMPOSITE fEATURES: 2 VOICE SOUND, 8-BIT KEYPORT CONTROL, cLK DOUBLING, HORIZ. AND VERT. SCROLLING, rASTER cOMPARE AND 3 TIMER GENERATED INTERRUPTS, HARDWARE CURSOR BLINK AND REVERSE VIDEO ATTRIBUTES TRUE EXTERNAL dma AND ARBITRATION CONTROL mEMORY iNTERFACE:ACCESS 64k, TRANSPARENT dma, PROVIDES SYSTEM ras, cas AND mux pINS: 48 sUPPLY: +5v pINOUT pIN7360/8360 1a2 2a1 3a0 4vDD 5/cs0 6/cs1 7r/w 8/irq 9mux 10/ras 11/cas 12pHI0 OUT 13color 14cLK IN 15k0 16k1 17k2 18k3 19k4 20k5 21k6 22k7 23sYN/lUM 24vSS 25d0 26d1 27d2 28d3 29d4 30d5 31d6 32d7 33sND 34ba 35aec 36a15 37a14 38a13 39a12 40a11 41a10 42a9 43a8 44a7 45a6 46a5 47a4 48a3 ------------------------------------------------------------------------------- dEVICE: dvdc pART nO: 8563 8568 dISPLAY fORMAT: PROGRAMMABLE UP TO UP TO 80X25 TEXT, 640hX400v BITMAP (INTERLACED UP TO 80X50 TEXT, 640hX480v BITMAP, AND MORE) dISPLAY mODES: 3 CHAR MODES: sTD, sEMIGRAPH AND PIXEL, DOUBLE WIDTH & hIrES BITMAP MODE vIDEO oUTPUT: DIGITAL rgbi 16 COLOR OR 16 GRAY-SHADES fEATURES: 8563: INTERLACE/NON-INTERLACE, HORIZ & VERT SCROLL, LIGHTPEN INPUT, HARDWARE CURSOR, UNDERLINE, BLINK AND REVERSE VIDEO, SUPPORTS 2 CHARACTER SETS OF 256 EACH 8568: ABOVE PLUS uPDATE rEADY iNTERRUPT, COMPOSITE VIDEO AND COMPOSITE SYNC mEMORY iNTERFACE:ACCESS 64k, PROGRAMMABLE TO INTERFACE EITHER 4164/4464 OR 4416 dram pINS: 48 sUPPLY: +5v mAKE SURE YOU GET ONE THAT SAYS r9A OR r9B AFTER THE 8568. tHESE ARE LATER rEVISIONS THAT SEEM TO WORK BETTER. pINOUT pIN8563 1cclk 2dclk 3hsyn 4/cs 5- 6- 7/cs 8/rs 9r/w 10d7 11d6 12vSS 13d5 14d4 15d3 16d2 17d1 18d0 19dispen 20vsyn 21dr/w 22init 23/res 24tst 25/lp2 26da0 27da1 28da2 29da3 30da4 31da5 32da6 33da7 34dd0 35dd1 36dd2 37vDD 38dd3 39dd4 40dd5 41dd6 42dd7 43i 44b 45g 46r 47/ras 48/cas tHE vdc vIDEOram uPGRADE fROM: rAYMOND cARLSEN <RRCC@U.WASHINGTON.EDU> nEWSGROUPS: COMP.SYS.CBM sUBJECT: rE: w: 8563 ram SWAP INSTRUCTIONS dATE: wED, 27 sEP 1995 20:50:02 -0700 > tHE SUBJECT SAYS IT ALL. hOW DO YOU DO THIS 16K TO 64K SWAP? i ASSUME YOU MEAN THE VIDEO ram UPGRADE FOR THE c-128. iF YOU'RE GOOD WITH A DE-SOLDERING IRON, IT JUST INVOLVES REMOVING TWO CHIPS FROM THE BOARD AND INSTALLING REPLACEMENTS. tHE ORIGINAL CHIPS ARE 4416 dram AT BOARD LOCATIONS u23 AND u25 INSIDE THE METAL CAN, BETWEEN THE vic AND rgb CHIPS. tHE REPLACEMENTS ARE 4464. tHE NUMBERS ON THE CHIPS MAY VARY WITH MANUFACTURERS, BUT THE ORIGINALS ARE 4 BIT WIDE 16k... TWO OF THEM MAKE 16k BY 8 BITS. tHE UPGRADE TO TWO 4 BIT WIDE 64k CHIPS GIVE A TOTAL OF 64k BY 8 FOR THE FLAT 128. tHE 128d WAS BUILT WITH 64k OF vram ALREADY INSTALLED. i ALWAYS INSTALL SOCKETS ANYTIME i REPLACE CHIPS IN A pc BOARD. rEMOVING THE OLD CHIPS IS THE WORST PART OF THE JOB. pROBABLY THE EASIEST WAY IS TO CUT ALL OF THE PINS ON THE OLD CHIP, THEN REMOVE THEM ONE AT A TIME WITH A REGULAR IRON. aS A TECH, i HATE TO DESTROY ANYTHING THAT STILL WORKS. i USE A DESOLDERING IRON TO FREE EACH PIN, THEN REMOVE THE CHIP INTACT. iF THE NEW CHIPS DON'T WORK FOR ANY REASON, i CAN CROSS CHECK MY WORK BY REINSTALLING THE OLD ONES. sOCKETS MEAN NEVER HAVING TO SOLDER AGAIN. iT'S IMPORTANT TO ORIENT THE NEW CHIPS IN THE BOARD CORRECTLY. oNE END OF THE CHIP WILL HAVE A NOTCH AND THE OUTLINE ON THE BOARD WILL MATCH. uNLESS YOU HAVE SOFTWARE THAT TAKES ADVANTAGE OF THE EXTRA VIDEO ram YOU WILL NOT SEE ANY DIFFERENCE IN THE PERFORMANCE OF YOUR COMPUTER. i THINK mAVERICK USES THAT ram SPACE TO SPEED UP COPYING FILES. iT'S USEFUL FOR IMPROVED BITMAPPED GRAPHICS. iT IS ONLY GOOD FOR THE 80 COLUMN SCREEN... THE 40 COLUMN vic DOESN'T ACCESS IT. tO VERIFY c-128 vram AS EITHER 16k OR 64k, RUN THIS LITTLE PROGRAM: poke dec("d600"),28:poke dec("d601"),63:sys dec("ff62"):scnclr <return> iF THE SCREEN SHOWS THE ready PROMPT AND LOOKS NORMAL, THE 128 HAS 64k OF vram INSTALLED. iF IT ONLY HAS 16k (STOCK 128 WITHOUT UPGRADE), THE SCREEN FILLS UP WITH ZEROS. hIT run/stop-restore TO CLEAR IT. aT ONE TIME, SOME COMPANY WAS SELLING A PIGGYBACK BOARD WITH THE ram INSTALLED. iT NEEDED NO SOLDERING AS THE ON-BOARD 4116S WERE BYPASSED. aLL THAT WAS NECESSARY WAS TO REMOVE THE 80 cOLUMN rgb (8563, ALSO KNOWN AS THE vdc) CHIP FROM ITS' SOCKET, INSTALL THE PIGGYBACK BOARD AND PLUG THE rgb CHIP INTO THE PIGGYBACK. i HAVEN'T SEEN THAT BOARD ADVERTISED FOR SOME TIME. [cHIPS ARE AVAILABLE FROM jAMECO eLECTRONICS @ 1-800-831-4242. oRDER PART #41582 (41464-12), OR 41574 (41464-10), OR 41611 (41464-80). tHEY COST LESS THAN 3 BUCKS EACH. jAMECO ALSO HAS OTHER REPLACEMENT CHIPS FOR cOMMODORE COMPUTERS.] rAY cARLSEN uNIV. OF wASHINGTON, sEATTLE ------------------------------------------------------------------------------- dEVICE: crtc pART nO: 6545-1 dISPLAY fORMAT: PROGRAMMABLE CONTROLLER dISPLAY mODES: - vIDEO oUTPUT: - fEATURES: PROGRAMMABLE CURSOR, LIGHTPEN INPUT mEMORY iNTERFACE:ACCESS 16k, STRAIGHT BINARY OR ROW/COLUMN pINS: 40 sUPPLY: +5v ------------------------------------------------------------------------------- nOTE: mib'S (mOVABLE iMAGE bLOCKS) ARE LATER KNOWN BETTER AS mob'S FOR mOVABLE oBJECT bLOCKS. sPECIAL aPPLICATION 6581/6582 sOUND iNTERFACE dEVICE (sid) dESCRIPTION tHE 6581 sOUND iNTERFACE dEVICE (sid) IS A SINGLE-CHIP, 3-VOICE ELECTRONIC MUSIC SYSTHESIZER/SOUND EFFECTS GENERATOR COMPATIBLE WITH THE 65xx AND SIMILAR MICROPROCESSOR FAMILIES. sid PROVIDES WIDE-RANGE, HIGH-RESOLUTION CONTROL OF PITCH (FREQUENCY), TONE COLOR (HARMONIC CONTENT), AND DYNAMICS (VOLUME). sPECIALIZED CONTROL CIRCUITRY MINIMIZES SOFTWARE OVERHEAD, FACILITATING USE IN ARCADE/HOME VIDEO GAMES AND LOW-COST MUSICAL INSTRUMENTS. tHE 6582 sOUND iNTERFACE dEVICE (sid) IS A SOUND GENERATOR CHIP COMPATIBLE WITH THE 6500/8500 MICROPROCESSOR FAMILIES. fEATURES 3 tONE oSCILLATORS, rANGE 0-4KhZ 4 wAVEFORMS PER oSCILLATOR: tRIANGLE, sAWTOOTH, vARIABLE pULSE, nOISE 3 aMPLITUDE mODULATORS, rANGE 48 Db rANDOM nUMBER/mODULATION gENERATOR 3 eNVELOPE gENERATORS eXPONENTIAL RESPONSE aTTACK rATE: 2 MS - 8 S dECAY rATE: 6 MS - 24 S sUSTAIN lEVEL: 0 - PEAK VOLUME rELEASE rATE: 6 MS - 24 S oSCILLATOR sYNCHRONIZATION rING mODULATION pROGRAMMABLE fILTER cUTOFF rANGE: 30hZ-12KhZ 12 Db/OCTAVE rOLLOFF lOW PASS, bAND PASS, hIGH PASS, nOTCH OUTPUTS vARIABLE RESONANCE mASTER vOLUME cONTROL 2 a/d pot iNTERFACES eXTERNAL aUDIO iNPUT pINS: 24 sUPPLY: +12 v (6581) +9 v (6582 / 8580) pINOUT pIN6581/8580 1cAP 1a 2cAP 1b 3cAP 2a 4cAP 2b 5/res 6pHI iN 7r/w 8/cs 9a0 10a1 11a2 12a3 13a4 14gnd 15d0 16d1 17d2 18d3 19d4 20d5 21d6 22d7 23pOT y 24pOT x 25+5 v 26eXT iN 27aUDIO oUT 28+12 v (6581) +9 v (8580) tHE 8580 IS USED IN THE NEWER (WHITE) c64'S. ------------------------------------------------------------------------------- sTATIC rEAD oNLY mEMORY dESCRIPTION cOMMODORE OFFERS A VARIETY OF HIGH PERFORMANCE romS WITH A WIDE RANGE OF ACCESS TIMES PROVIDING COMPATIBILITY WITH MOST MICROPROCESSOR SYSTEMS. tHE romS ARE ttl COMPATIBLE, HAVING A SINGLE +5 VOLT POWER SUPPLY AND TOTALLY STATIC OPERA- TION. tHE 2400 SERIES "pOWER dOWN" romS OFFER SIGNIFICANTLY REDUCED POWER CONSUMPTION WHILE IN STAND-BY MODE. eACH DEVICE HAS PROGRAMMABLE CHIP SELECT AND/OR OUTPUT ENABLE FOR OUTPUT BUS CONTROL AND IS DESIGNED TO REPLACE EQUIVALENT epromS. aVAILABLE roms oRGANIZATION aCCESS tIME (NS) oPERATING sTANDBY pROCESS dEVICEwORDS X bITSaDDRESS ce cs/oe cURRENT cURRENT tECHNOLOGY 2332/3 4096 X 8200n/a 75 100 Ma n/a hmos 2364 8192 X 8200n/a 100 100 Ma n/a hmos 2312816384 X 8250n/a 100 100 Ma n/a hmos 2412816384 X 8250250 100 100 Ma 12 Ma hmos 2425632768 X 8250250 100 100 Ma 12 Ma hmos 2451265536 X 8250250 100 100 Ma 12 Ma hmos 24c12816384 X 8200200 100 10 Ma 50 Ua cmos 24c25632768 X 8250250 100 10 Ma 50 Ua cmos ------------------------------------------------------------------------------- 82 s 100 fIELD pROGRAMMABLE lOGIC aRRAY (16 X 48 X 8) dESCRIPTION tHE 82s100 (tHREE-sTATE) AND 82 s 101 (oPEN cOLLECTOR) ARE bIPOLAR, fUSE-lINK pROGRAMMABLE lOGIC aRRAYS (fplaS). eACH DEVICE UTILIZES THE STANDARD and/or/iNVERT ARCHITECTURE TO DIRECTLY IMPLEMENT CUSTOM SUM-OF-PRODUCT LOGIC EQUATIONS. eACH DEVICE CONSISTS OF 16 DEDICATED INPUTS AND 8 DEDICATED OUTPUTS. eACH OUTPUT IS CAPABLE OF BEING ACTIVELY CONTROLLED BY ANY OR ALL OF THE 48 PRODUCT TERMS. tHE TRUE, COMPLEMENT, OR DON'T CARE CONDITION OF EACH OF THE 16 INPUTS andED TOGETHER COMPRISE ONE p-tERM. aLL 48 p-tERMS ARE THEN or-D TO EACH OUTPUT. tHE USER MUST THEN ONLY SELECT WHICH p-tERMS WILL ACTIVATE AN OUTPUT BY DISCONNECTING TERMS WHICH DO NOT AFFECT THE OUTPUT. iN ADDITION, EACH OUTPUT CAN BE FUSED AS ACTIVE HIGH (h) OR ACTIVE LOW (l). tHE 82s100 AND 82s101 ARE FULLY ttl COMPATIBLE AND INCLUDES CHIP-ENABLE CONTROL FOR EXPANSION OF INPUT VARIABLES AND OUTPUT INHIBIT. tHEY FEATURE EITHER tHREE-sTATE OR oPEN cOLLECTOR OUTPUTS FOR EASE OF EXPANSION OF PRODUCT TERMS AND APPLICATION IN BUS-ORGANIZED SYSTEMS. fEATURES: fIELD PROGRAMMABLE nI-cR LINKS 16 INPUTS 8 OUTPUTS 48 PRODUCT TERMS aDDRESS ACCESS TIME: s82s100/101:80 NS MAX n82s100/101:50 NS MAX (cOMMERCIAL VERION) pOWER DISSIPATION - 600Mw TYP iNPUT LOADING - 100Ua MAX cHIP ENABLE INPUT tHREE STATE OUTPUTS sEPARATE i/o ARCHITECTURE aPPLICATIONS crt DISPLAY SYSTEMS rANDOM LOGIC cODE CONVERSION pERIPHERAL CONTROLLERS fUNCTION GENERATORS lOOK-UP AND DECISION TABLES mICROPROGRAMMING aDDRESS MAPPING cHARACTER GENERATORS dATA SECURITY ENCODERS fAULT DETECTORS fREQUENCY SYNTHESIZERS 16-BIT TO 8-BIT BUS INTERFACE tHE 82s100 DEVICES ARE SHIPPED IN AN UNPROGRAMMED STATE CHARACTERISED BY: aLL INTERNAL nI-cR LINKS ARE INTACT AND THEREFORE EACH PRODUCT TERM CONTAINS BOTH TRUE AND COMPLEMENT VALUES OF EVERY INPUT VARIABLE, THE or MATRIX CONTAINS ALL 48 p-tERMS, THE POLARITY OF EACH OUTPUT IS SET TO ACTIVE HIGH, ALL OUTPUTS ARE AT A LOW LOGIC LEVEL. pINOUT pIN82S100 (cERDIP, pLASTIC, fLAT pACK) 1fe (OPEN OR GROUNDED IN NORMAL OPERATION) 2i7 3i6 4i5 5i4 6i3 7i2 8i1 9i0 10f7 11f6 12f5 13f4 14gnd 15f3 16f2 17f1 18f0 19/ce 20i15 21i14 22i13 23i12 24i11 25i10 26i9 27i8 28vCC ------------------------------------------------------------------------------- mORE INFO WANTED ON (AT LEAST) THESE: 8362 pal vIDEO cHIP csg 5719 csg 4567 vic-iii csg 8362 csg 8372a sUPER aGNUS (FOR aMIGA) tHE aMIGA HAS 8520'S AS cia'S, WHICH ARE THE aMIGA VERSION OF THE 6522 ET AL. cHARACTERISTICS ARE ALMOST THE SAME; THERE IS 24-BIT COUNTER IN PLACE OF THE cia'S tod CLOCK. fROM: PHDSS@WORF.NETINS.NET (pHD sOFTWARE sYSTEMS) nEWSGROUPS: COMP.SYS.CBM sUBJECT: rE: 6502 PIN CONFIGURATIO dATE: 7 aUG 1996 22:39:42 gmt dF> cOULD SOMEONE PLEASE SEND ME THE 6502 PIN CONFIGURATION OR dF> TELL ME WHERE i CAN FIND THIS INFO. --------------- vSS -1 40- res rdy -2 39- O2 (out) O1 (out) -3 38- so irq -4 37- O2 (in) nc -5 36- nc nmi -6 35- nc sync -7 34- r/w vDD -8 33- d0 a0 -9 6502 32- d1 a1 -10 31- d2 a2 -11 30- d3 a3 -12 29- d4 a4 -13 28- d5 a5 -14 27- d6 a6 -15 26- d7 a7 -16 25- a15 a8 -17 24- a14 a9 -18 23- a13 a10 -19 22- a12 a11 -20 21- vSS --------------- a b o r 0 m i r r v v e v m 2 l r t d p s s d / i b b q b y b s b a x n e /------------------------------------------- / 6 5 4 3 2 1 44 43 42 41 40 - nmib - 7 39 - e vpa - 8 38 - r/wb vdd - 9 37 - vdd a0 - 10 36 - d0/ba0 a1 - 11 35 - d1/ba1 vss - 12 w65c816s 34 - d2/ba2 a2 - 13 33 - d3/ba3 a3 - 14 32 - d4/ba4 a4 - 15 31 - d5/ba5 a5 - 16 30 - d6/ba6 a6 - 17 29 - d7/ba7 - 18 19 20 21 22 23 24 25 26 27 28 - ---------------------------------------------- a a a a a v v a a a a 7 8 9 1 1 s s 1 1 1 1 0 1 s s 2 3 4 5 44 PIN w65c816s plcc pINOUT bRETT tABKE ]-----------------------------------------------------[ ] phd sOFTWARE sYSTEMS : net: PHDSS@WORF.NETINS.NET [ ] po bOX 23 : [ ] mOVILLE, ia. usa 51039 : hOME OF res 80128 [ ]-----------------------------------------------------[