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  1.  
  2.                              820DIFF
  3.                        By Mitchell Mlinar
  4.                              10/6/85
  5.  
  6.  
  7. This small file is a composite difference description between the
  8. 820-I  Etch 1 and 820-I Etch 2.   An assumption is made that  you
  9. have  one or the other (hopefully,  both) of the 820  schematics.
  10. In  addition,  I would like to thank Dan Costello for helping  me
  11. out  with this document by providing some nicely drawn difference
  12. schematics to work from.
  13.  
  14. Briefly, the first board Xerox released was the Etch 1 (which had
  15. a serial number ending in 629A).   About a year later, Etch 2 was
  16. phased  into  production  (which had a serial  number  ending  in
  17. 644A).   There  were  a  number of  minor  technical  differences
  18. between  them;  it  is these items that this  article  addresses.
  19.  
  20. Note that with the sole exception of being able to detect double-
  21. sided  460 drives (special input line),  there are NO programming
  22. differences between the two versions.   All software which  works
  23. on Etch 1 will work on Etch 2.  However, the only item to observe
  24. is  that  there  was  a  slightly  different  ROM  release  which
  25. coincided  with  the  Etch 2 (v1.0 ROMs replaced by  v2.0  ROMs).
  26. Although all jump vectors perform the same operation,  there were
  27. many  more  added in v2.0.   In  addition,  location  of  monitor
  28. variables (real-time clock, track, sector, etc.) appear elsewhere
  29. in the later release.
  30.  
  31. There  are  four topic areas which are different in the two  etch
  32. versions:  processor clock,  CRT display generator,  system port,
  33. and floppy controller circuitry.  Each will be addressed.
  34. .PA
  35.  
  36.  
  37. PROCESSOR CLOCK
  38. ---------------
  39.  
  40. The clock and clock driver are slightly different between the two
  41. versions.
  42.  
  43.  
  44. ETCH 1: R16, R17 = 1k           C192 = .01uF
  45.         C90 = 47pf              C92 = 100pF
  46.         U9 = 74LS04
  47.  
  48.  
  49.       +--R16--+--R17-------+
  50.       |       |            |
  51.       |     C192           +-----> E2
  52.       |       |            |
  53.       |      gnd           |
  54.       |                    |
  55.       +---(13)..U9..(12)---+
  56.       |                    |
  57.       +----[20MHz XTAL]----+
  58.       |                    |
  59.      C90                  C92
  60.       |                    |
  61.      gnd                  gnd
  62.  
  63.  
  64.  
  65.         U9 = 74LS04
  66.  
  67.  
  68.       ^                    ^
  69.       |                    |
  70.       +----(3)..U9..(4)----+
  71.       |                    |
  72.       +----(1)..U9..(2)----+
  73.       |                    |
  74.       v                    v
  75. .PA
  76.  
  77.  
  78. ETCH 2: U9 = 74LS04             R14 = 100
  79.         R16, R17 = 470          C90 = 47pF
  80.         U9 = 74LS04
  81.  
  82.  
  83.    +------------------[20MHz XTAL]-----------------+
  84.    |                                               |
  85.    |                                               +--> E2
  86.    |                                               |
  87.    +---(1)..U9..(2)---+--R14--+---(13)..U9..(12)---+
  88.    |                  |       |                    |
  89.    +--------R16-------+       +---------R17--------+
  90.                               |
  91.                              C90
  92.                               |
  93.                              gnd
  94.  
  95.  
  96.  
  97.         U9 = 74LS04
  98.  
  99.  
  100.       ^                    ^
  101.       |                    |
  102.       |                    |
  103.       |                    |
  104.       +----(1)..U9..(2)----+
  105.       |                    |
  106.       v                    v
  107. .PA
  108.  
  109.  
  110. CRT DISPLAY GENERATION
  111. ----------------------
  112.  
  113. The clock is again different here.   Also,  the Not Vertical Sync
  114. (NVSync)  is processed through a one-shot 74LS123 in Etch 1,  but
  115. directly taken to the output gate (U117) in Etch 2.   The earlier
  116. version used the 'LS123 to extend the NVSync signal to work  with
  117. the  Ball monitors which required it for clocking.   Most present
  118. monitors could care less; hence, Etch 2 removed it.
  119.  
  120.  
  121. ETCH 1: U11 = 74LS04            R4, R5 = 470
  122.         C26 = marked as 33pF BUT IS a jumper wire
  123.         XTAL = 10.69425MHz
  124.         C27 = marked as .01uF BUT IS 100 ohm
  125.  
  126.  
  127. +------------------------"C27"------------------------------+
  128. |                                                           |
  129. |                                                           +--> E1
  130. |                                                           |
  131. +---(13)..U11..(12)---+-"C26"-[XTAL]--+---(11)..U11..(10)---+
  132. |                     |               |                     |
  133. +----------R4---------+               +----------R5---------+
  134.  
  135.  
  136.  
  137.         U32 = 74LS08            U33 = 74LS32
  138.         U36 = 74LS10            U106 = 74LS123
  139.         R11 = 47k               C72 = .01uF
  140.         U117 = 7406
  141.  
  142.  
  143.               (9)..U33
  144.                |
  145.                |
  146.  U32..(6)------+---------------------(3)..U36
  147.                |
  148.                |   (+5v)--R11--+--C72--+---gnd
  149.                |               |       |
  150.                |        U106..(7)     (6)..U106
  151.                |
  152.                +-------(10)..U107..(11)----------gnd
  153.  
  154.                gnd------(9)..U107..(5)-----------(5)..U117
  155. .PA
  156.  
  157. ETCH 2: U11 = 74LS04            R4, R5 = 470
  158.         R10 = 100               C26 = 100pF
  159.  
  160.  
  161.    +-----------------[10.69425MHz XTAL]----------------+
  162.    |                                                   |
  163.    |                                                   +--> E1
  164.    |                                                   |
  165.    +---(13)..U11..(12)---+--R10--+---(11)..U11..(10)---+
  166.    |                     |       |                     |
  167.    +----------R4---------+       +----------R5---------+
  168.                                  |
  169.                                 C26
  170.                                  |
  171.                                 gnd
  172.  
  173.  
  174.  
  175.         U32 = 74LS08            U33 = 74LS32
  176.         U36 = 74LS10            U117 = 7406
  177.  
  178.  
  179.                  (9)..U33
  180.                   |
  181.                   |
  182.     U32..(6)------+--------------------(3)..U36
  183.                   |
  184.                   |
  185.                  (5)..U117
  186.  
  187.  
  188.  
  189.  
  190. SYSTEM PORT
  191. -----------
  192.  
  193. On Etch 1,  bit 5 of the system PIO (PA5; port 1CH) was not used.
  194. Etch  2  added an input from 5.25" drives to detect  double-sided
  195. disks.
  196.  
  197.  
  198. ETCH 1: U105 = Z80 PIO
  199.  
  200.         U105..(9)---------  n/c
  201.  
  202.  
  203.  
  204. ETCH 2: U105 = Z80 PIO          R49 = 10k
  205.  
  206.  
  207.         U105..(9)---------+-----------> J1-3 (400/460)
  208.                           |
  209.                           +---R49---<+5v>
  210.  
  211.  
  212.  
  213.  
  214. FLOPPY CONTROLLER
  215. -----------------
  216.  
  217. Etch 1 and 2 differed in the data seperation circuitry.   Etch  2
  218. saw  the addition of a one-shot to improve clock/data  seperation
  219. as well as extensive re-routing of the RAW DATA signal as part of
  220. the improved circuitry.
  221.  
  222.  
  223. ETCH 1: U107 = 74LS157          U108 = 74LS14
  224.         U94 = 74LS08            U93 = 74LS193
  225.         U109 = FD1771
  226.  
  227.          U108..(5)               (5)..U94
  228.                 |                 |
  229.                 |                 |
  230.   U108..(4)-----+-----------------+
  231.                 |                 |
  232.                 |                 |
  233.          U107..(2)               (10)..U94
  234.  
  235.  
  236.   U107..(13)----gnd        [4MHz clock]----(4)..U93
  237.  
  238.  
  239.   U107..(4)-----(27)..U109       U107..(14)----<+5v>
  240.  
  241.  
  242.   U94..(6)-----(3)..U107
  243. .PA
  244.  
  245.  
  246. ETCH 2: U107 = 74LS157          U108 = 74LS14
  247.         U94 = 74LS08            U92 = 74LS193
  248.         U106 = 74LS123          C72 = 100pF
  249.         R11 = 7.5k              U109 = FD1771
  250.  
  251.  
  252.           U108..(5)               (5)..U94
  253.                  |                 |
  254.                  |                 |
  255.   U107..(12)-----+-----------------+
  256.                                    |
  257.                                    |
  258.                                   (10)..U94
  259.  
  260.  
  261.   [4MHz clock]----(3)..U107      U107..(4)-----(4)..U93
  262.  
  263.  
  264.   U94..(6)-----(27)..U109        [2MHz clock]----(2)..U107
  265.  
  266.  
  267.  
  268.           <+5v>----R11--+--C72--+----gnd
  269.                         |       |
  270.                         |       |
  271.                  U106..(7)     (6)..U106
  272.  
  273.  
  274.   U108..(4)-------+-------------(10)..U106..(5)----(14)..U107
  275.                   |
  276.                   |
  277.           U107..(13)      gnd----(9)..U106..(1)----<+5v>
  278.  
  279.