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- ;----------------------------------------------------------------
- ; Port Equates for HD64B180 CPU
- ;
- ; This library is used to talk to ports in the CPU chip.
- ;
- ; Written by Richard Holmes 27-05-87
- ; Last Update by Richard Holmes 27-05-87
- ;----------------------------------------------------------------
- ;
- base equ 0 ; Base port address
- ;
- ; Async. Serical Communication Interface equstes
- ;
- cntla0 equ base + 000h ; ASCI Control register A ch 0
- cntla1 equ base + 001h ; ASCI Control register A ch 1
- cntlb0 equ base + 002h ; ASCI Control register B ch 0
- cntlb1 equ base + 003h ; ASCI Control register B ch 1
- stat0 equ base + 004h ; ASCI status register ch 0
- stat1 equ base + 005h ; ASCI status register ch 1
- tdr0 equ base + 006h ; transmit data register ch 0
- tdr1 equ base + 007h ; transmit data register ch 1
- rdr0 equ base + 008h ; receive data register ch 0
- rdr1 equ base + 009h ; receive data register ch 1
- ;
- ; Clocked Serial I/O Ports
- ;
- cntr equ base + 00ah ; CSIO Control
- trdr equ base + 00bh ; CSIO transmit / receive data
- ;
- ; Timers ports
- ;
- tmdr0l equ base + 00ch ; Timer data register ch 0 low
- tmdr0h equ base + 00dh ; Timer data register ch 0 high
- rldr0l equ base + 00eh ; Reload register ch 0 low
- rldr0h equ base + 00fh ; Reload register ch 0 high
- tcr equ base + 010h ; Timer control register
- ;
- tmdr1l equ base + 014h ; Timer data register ch 1 low
- tmdr1h equ base + 015h ; Timer data register ch 1 high
- rldr1l equ base + 016h ; Reload register ch 1 low
- rldr1h equ base + 017h ; Reload register ch 1 high
- ;
- ; DMA Channels.
- ;
- sar0l equ base + 020h ; DMA Source address ch 0 low
- sar0h equ base + 021h ; DMA Source address ch 0 high
- sar0b equ base + 022h ; DMA Source address ch 0 B
- dar0l equ base + 023h ; DMA Source address ch 1 low
- dar0h equ base + 024h ; DMA Source address ch 1 high
- dar0b equ base + 025h ; DMA Source address ch 1 B
- bcr0l equ base + 026h ; DMA byte count ch 0 low
- bcr0h equ base + 027h ; DMA byte count ch 0 low
- mra1l equ base + 028h ; DMA memory addres reg. ch 1 low
- mra1h equ base + 029h ; DMA memory addres reg. ch 1 high
- mra1b equ base + 02Ah ; DMA memory addres reg. ch 1 B
- ;
- iar1l equ base + 02bh ; DMA address reg. ch 1 low
- iar1h equ base + 02ch ; DMA address reg. ch 1 high
- ;
- bcr1l equ base + 02eh ; DMA byte count reg. 1 low
- bcr1h equ base + 02fh ; DMA byte count reg. 1 high
- dstat equ base + 030h ; DMA Status reg.
- dmode equ base + 031h ; DMA Mode reg.
- dcntl equ base + 032h ; DMA wait/control reg.
- ;
- ; Interrupt control ports.
- ;
- il equ base + 033h ; IL register (Intrrupt vector reg)
- itc equ base + 034h ; INT / TRAP control register
- rcr equ base + 036h ; Refresh control register
- ;
- ; MMU
- ;
- cbr equ base + 038h ; MMU Common base register
- bbr equ base + 039h ; MMU Bank base register
- cbar equ base + 03ah ; MMU Commmmon/bank area register
- ;
- icr equ base + 03fh ; I/O control register
- ;
- ; A library of hardware equates for the DINOS PCB
- ;
- wdt equ 085h
- ;
- kbd$wr equ 086h
- kbd$rd1 equ 087h
- kbd$rd2 equ 088h
- led$dat equ 089h
- led$adr equ 08ah
- ip$rd equ 08bh
- gp$out equ 08ch
- lcd$wr equ 08dh
- lcd$rd equ 08eh
- cp$dat equ 08fh
- ;
- ; ---- End ----
- ;