CP/M/CPM_CDROM.iso/cpm/modems/modem/x25.ark/X25SYS.DOC

Text File | 1986-07-28 | 23.3 KB | 487 lines

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*                                                      *
*        X.25 Protocol Interface for CP/M-80           *
*                                                      *
*            SYSTEM FUNCTIONAL DESCRIPTION             *
*                                                      *
*   (C) 1985  Ed Elizondo                              *
*             6 Cypress Court                          *
*             East Windsor, NJ 08520                   *
*                                                      *
*   NOTICE:  All Rights Reserved - These programs and  *
*   accompanying documentation may be used freely for  *
*   non-commercial applications.  They may not be sold *
*   or used for commercial applications without the    *
*   written permission of the author.                  *
*                                                      *
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1.  Introduction


     Thσá techniquσ oµ packe⌠ transmissioε i≤ currentl∙ thσá mos⌠ ì
widel∙ useΣ messagσ switchinτ techniquσ iε compute≥ network≤á anΣ ì
ha≤á receiveΣá significan⌠ impetu≤ b∙ worlΣ widσá standardizatioε ì
efforts«á Thσá X.2╡ packe⌠ networδ interface¼á pioneereΣá b∙á thσ ì
FrencΦá posta∞á administratioε Transpaπ networδ anΣ thσá Canadiaε ì
Datapaπ network¼á wa≤ adopteΣ a≤ ß standarΣ b∙ thσá Internationa∞ ì
Consultativσá Committeσá oµ Telephon∙ anΣ Telegraph∙á (CCITT⌐á iε ì
1976¼ anΣ updateΣ t∩ it≤ curren⌠ forφ iε 1981.

     WitΦ rarσ exception≤ packe⌠ transmissioε ha≤ beeε limiteΣ t∩ ì
datßá communication≤á betweeεá largσá mainframσáá computers¼áá o≥ ì
interna∞á t∩ largσ networks«á  Thσ purposσ oµ thi≤ projec⌠ i≤á t∩ ì
providσáá ßá utilit∙á prograφá t∩á permi⌠á direc⌠áá packe⌠áá datß ì
communication≤ betweeε ß microcomputer¼ runninτ unde≥ thσ CP/M-8░ ì
operatinτá system¼á anΣ ß synchronou≤ networδ modeφ o≥á mainframσ ì
compute≥á por⌠ supportinτ thσ X.2╡ standarΣ acces≤ protocol«á Thσ ì
softwarσ packagσ developeΣ fo≥ thi≤ projec⌠ full∙ implement≤á thσ ì
function≤ oµ ß singlσ logica∞ channe∞ DTE¼ a≤ defineΣ b∙ thσ X.2╡ ì
standard.

     Thσ softwarσ packagσ wa≤ implementeΣ iε Inte∞ 808░á assembl∙ ì
language¼á compatiblσá witΦ thσ Digita∞ ResearcΦ RMA├á relocatinτ ì
macr∩áá assembler¼áá anΣá targeteΣá t∩á ruεá oεá aεáá inexpensivσ ì
microcompute≥á system¼áá thσá Digita∞á ResearcΦá Computersºá "Biτ ì
Board"«áá  Thσáá minimuφáá hardwarσá requirement≤áá arσáá ßáá Z8░ ì
microprocessor¼á ßá Ziloτá SI╧ synchronou≤ seria∞á communication≤ ì
port¼á anΣá ß Ziloτ CT├ counter/timer¼á al∞ interfaceΣ usinτá Z8░ ì
modσá ▓á interrupts«á  Memor∙á requirement≤á fo≥á thσá systeφá a≤ ì
implementeΣ arσ ß modes⌠ 26╦ fo≥ botΦ prograφ anΣ datß buffers.



è2. The X.25 Protocol


     Thσá rule≤á anΣá mechanism≤á b∙ whicΦ user≤á anΣá ßá networδ ì
exchangσá informatioεá iε ß controlleΣ manne≥ arσ referreΣ t∩á a≤ ì
protocols«áá  Thσáá complexit∙á anΣá diversit∙á oµá thσáá networδ ì
constituent≤á favo≥á multiplσ layer≤á oµá protocols¼á eacΦá laye≥ ì
providinτá communication≤ betweeε tw∩ simila≥ classe≤ oµ devices«  ì
Thσá Internationa∞á Standard≤ Organizatioε (ISO⌐ ha≤á proposeΣá ß ì
structurσá oµ seveε hierarchica∞ protoco∞ layer≤á (seσá ref«á 6)«  ì
Thσ X.2╡ standarΣ specifie≤ thσ threσ lowes⌠ layers¼ namely:

     1. the physical circuit level

     2. the link level

     3. the network level


     Leve∞áá 1¼áá thσá physica∞á circui⌠á level¼áá specifie≤á thσ ì
electrica∞ waveforms¼á voltages¼á anΣ piε connection≤ betweeε thσ ì
enΣá user¼á iεá X.2╡á terminology¼á thσá "hostóá o≥á "DTEóá (Datß ì
Terminatinτá Equipment)¼á anΣá thσá networδ nodσ o≥á "DCEóá (Datß ì
Communication≤ Equipment)«  Thσ X.2╡ standarΣ specifie≤ thσ Leve∞ ì
▒á interfacσ a≤ beinτ thσ CCIT╘ X.2▒ standarΣ (seσ referencσ ▒ o≥ ì
2)¼á bu⌠á allows¼á iε aε interiφ basis¼á thσ usσ oµá thσá X.21bi≤ ì
standard«á  Thσá X.21bi≤ standard¼á iε turn¼á permit≤ thσ usσá oµ ì
existinτá synchronou≤á modeφá standard≤ sucΦ a≤ thσá CCIT╘á V.24¼ ì
whicΦá i≤á equivalen⌠á t∩á thσ commoε (iεá thσá USA⌐á EI┴á RS232├ ì
standard.

     Leve∞ 2¼ thσ linδ level¼ control≤ bi⌠ datß transmissioε ove≥ ì
thσá physica∞ linδ betweeε thσ tw∩ end≤ oµ thσ leve∞á ▒á circuit«  ì
Thσá primar∙á purposσá oµ thσ Leve∞ ▓ protoco∞ i≤ tha⌠á oµá erro≥ ì
contro∞ anΣ oµ datß transparenc∙ t∩ highe≥ leve∞ protocols«á  Thσ ì
X.2╡á standarΣá specifie≤ thσ Leve∞ ▓ protoco∞ a≤ beinτá thσá IS╧ ì
standarΣ HigΦ Datß Linδ Contro∞ (HDLC).

     Informatioε i≤ passeΣ froφ Leve∞ ▓ t∩ Leve∞ ▒ iε thσ forφ oµ ì
datß block≤ calleΣ frames«  Thσ frame≤ utilizσ ß techniquσ calleΣ ì
zer∩á bi⌠á insertioεá (seσá referencσá 6)¼á t∩á achievσá completσ ì
transparenc∙ t∩ thσ datß a⌠ thσ bi⌠ level«á  Thu≤ thσ HDL├á framσ ì
i≤á capablσ oµ transmittinτ an∙ forφ oµ datß withou⌠ thσ neeΣ fo≥ ì
specia∞ contro∞ character≤ withiε thσ framσ a≤ iε thσ IB═á BYSYN├ ì
methoΣá oµ transmission«á  Erro≥ contro∞ a⌠ thσ Leve∞ ▓ interfacσ ì
i≤á achieveΣ b∙ transmittinτ ß cycliπ polynomia∞á checδá sequencσ ì
witΦá ever∙á frame«á  Thi≤ checδ sequencσ i≤ re-generateΣ a⌠á thσ ì
receivinτá enΣá and¼á iµá aε erro≥ i≤á detected¼á ßá reques⌠á fo≥ ì
retransmissioε i≤ automatically sen⌠ bacδ t∩ thσ sender.

     Leve∞ 3¼á thσ networδ level¼ control≤ thσ actua∞ transfe≥ oµ ì
informatioεá betweeε tw∩ host≤ (DTE's)«á  Thσ primar∙ purposσá oµ ì
thσá Leve∞á │á protoco∞á i≤ tha⌠á oµá datßá flo≈á control«á  Thi≤ ì
involve≤á individua∞á addressinτá anΣ sequencinτ oµá datßá block≤ ì
calleΣá packets«á  Flo≈ contro∞ i≤ achieveΣ primaril∙á b∙á packe⌠ ìèsequencσáá number≤á anΣá correspondinτá acknowledgemen⌠áá number≤ ì
incorporateΣá int∩á thσ returε flo≈ packet≤.

     Leve∞á │ packet≤ arσ transmitteΣ a≤ thσ informatioεá portioε ì
of Level 2 frames, one data packet to each HDLC frame.

     Highe≥á leve∞á protoco∞ task≤ arσ no⌠ specifieΣ b∙ thσá X.2╡ ì
standard«á  Iεá thσ IS╧ proposeΣ architecture¼á thesσá additiona∞ ì
level≤á includσá thσ transpor⌠á level¼á thσá sessioεá level¼á thσ ì
presentatioε leve∞ anΣ thσ applicatioε level«á Fo≥ thσ purposσ oµ ì
thi≤ project¼á tw∩ facilitie≤ arσ provideΣ t∩ handlσ thesσ highe≥ ì
functions.

     Onσá higΦ leve∞ facilit∙ provideΣ b∙ thσ systeφ i≤á tha⌠á oµ ì
termina∞ modσ emulation«á  WitΦ thi≤ facility¼ ß typeΣ messagσ a⌠ ì
thσ microcompute≥ consolσ i≤ sen⌠ t∩ thσ networδ a≤ ß singlσ datß ì
packe⌠á message«á  Messagσá packet≤ returneΣ b∙ thσá networδá arσ ì
similarl∙ displayeΣ oε thσ console.

     Thσá seconΣá higΦ leve∞ facilit∙ provideΣ b∙ thσá systeφá i≤ ì
tha⌠ oµ bidirectiona∞ datß filσ transfer«á  WitΦ thi≤ facility¼ ß ì
previousl∙ prepareΣ filσ ma∙ bσ sen⌠ t∩ thσ networδ a≤ ß sequencσ ì
oµ datß packets«á  Similarly¼ ß sequencσ oµ datß packet≤ receiveΣ ì
froφá thσá networδá ma∙á bσ saveΣ iε ßá loca∞á file«á  WitΦá thi≤ ì
facility¼á ß pre-arrangeΣ sequencσ oµ command≤ and/o≥ datß ma∙ bσ ì
sen⌠ t∩ thσ networδ hos⌠ anΣ thσ returneΣ result≤ saveΣ fo≥ late≥ ì
analysis.


3.  System Organization


     Thσá basiπá systeφ organizatioε consist≤ oµá tw∩á concurren⌠ ì
processes¼á aεá interrup⌠á handle≥ t∩ servicσ thσ rea∞ timσá datß ì
interfacσá function≤á betweeε thσ systeφ anΣá thσá communication≤ ì
portá anΣ ß sequentia∞ processo≥ t∩ handlσ thσá orderl∙á assembl∙ ì
anΣ disassembl∙ oµ datß packet≤ anΣ proces≤ loca∞ use≥ commands.

     Thσá interrup⌠á handle≥ perform≤ threσ basiπá functions║á a⌐ ì
receive≤á incominτá datßá froφ thσá communication≤á portá t∩á thσ ì
currentl∙ activσ receivσ buffer¼á b⌐ transmit≤ outgoinτ datß froφ ì
thσá currentl∙ activσ transmi⌠ buffe≥ t∩ thσ communication≤ port¼ ì
anΣ c⌐ keep≤ tracδ oµ elapseΣ timσ anΣ signal≤ timeou⌠ condition≤ ì
t∩ thσ sequentia∞ processor.

     Thσá sequentia∞ processo≥ perform≤ fivσ basiπ functions║á a⌐ ì
receive≤á anΣ transmit≤ datß t∩ anΣ froφ  thσ loca∞ use≥á consolσ ì
includinτá processinτá oµá loca∞á use≥á commands¼áá b⌐á assemble≤ ì
informatioεáá o≥áá supervisor∙á frame≤áá fo≥áá transmission¼áá c⌐ ì
disassemble≤ receiveΣ frame≤ anΣ processe≤ them¼á d⌐ disassemble≤ ì
receiveΣá packet≤ anΣ processe≤ them¼á anΣ e⌐ assemble≤á datßá o≥ ì
contro∞ packet≤ fo≥ transmission«

     Processinτá oµ receiveΣ frame≤ include≤ checkinτ fo≥á forma⌠ ì
error≤á anΣ fo≥ valiΣ framσ type≤ anΣ formattinτ thσá appropriatσ ìèrepl∙á frame≤á baseΣ oε thσ typσ oµ receiveΣá framσá anΣá curren⌠ ì
statσá oµá thσ system«á  Fo≥ informatioε frames¼á erro≥á checkinτ ì
include≤á checkinτá oµ framσ sequencσ numbers¼á updatinτá oµá thσ ì
framσáá transmissioεá windo≈á anΣá retransmissioεá oµá frame≤á iµ ì
requested by the remote system.

     Processinτá oµ receiveΣ packet≤ i≤ simila≥ t∩ processinτá oµ ì
receiveΣá frames¼áá excep⌠á retransmissioεá oµá packet≤á i≤áá no⌠ ì
required¼ sincσ thσ leve∞ │ transmissioε i≤ considereΣ erro≥ freσ ì
b∙ virtuσ oµ thσ erro≥ contro∞ mechanism≤ tha⌠ forφ ß par⌠ oµ thσ ì
level 2 link transmission.

     Thσá implementatioε architecturσ consist≤ oµ seveεá modules¼ ì
whose names and primary functions are as follows:

     X2╡       - thσ main program, which includes the system
                 initialization¼ use≥ interfacσ anΣ maiε ì
                 program sequencer

     LEVEL▒    - thσ interrup⌠ handler

     LEVEL▓    - thσ linδ leve∞ handler¼ whicΦ include≤ framσ                              ì
                 assembl∙ anΣ disassembl∙

     LEVEL│    - thσ packe⌠ leve∞ handler¼ whicΦ include≤ packet
                 assembl∙ anΣ disassembly

     FILES     - the disk file handler

     BUFFERS   - the data buffer handler

     XUTIL     - miscellaneous general use subroutines

     Thesσ .AS═ module≤ arσ separatel∙ assembleΣ int∩ relocatablσ ì
objec⌠á codσá .RE╠á file≤ b∙ mean≤ oµ thσ Digita∞á ResearcΦá RMA├ ì
macr∩á assembler¼á anΣá theεá linkeΣ togethe≥á witΦá thσá Digita∞ ì
ResearcΦ Z8░ anΣ SEQI╧ macr∩ librarie≤ int∩ thσ executablσ objec⌠ ì
codσá filσá X25.CO═á b∙ mean≤ oµá thσá Digita∞á ResearcΦá LINK-8░ ì
linker«


4.  System Data Flow

     Incominτá datßá froφ thσ communication≤ port i≤ placeΣá int∩ ì
thσá currentl∙á activσá buffe≥á b∙á thσá receivσá datßá interrup⌠ ì
handler«á  Thσ enΣ oµ ß receiveΣ framσ i≤ detecteΣ b∙ thσ leve∞ ▒ ì
hardwarσá (Z8░ SIO)¼á whicΦ als∩ check≤ fo≥ correc⌠ framσá forma⌠ ì
anΣá correc⌠ cycliπ polynomial«á InvaliΣ frame≤ arσ discardeΣá a⌠ ì
thi≤á point«á  ValiΣá frame≤ arσ passeΣ ont∩á thσá receivσá framσ ì
disassembl∙ processo≥ iε thσ leve∞ ▓ module.

     I⌠á shoulΣ bσ noteΣ a⌠ thi≤ poin⌠ tha⌠ thσá actua∞á receiveΣ ì
datßá i≤á no⌠ passeΣ froφ onσ leve∞ t∩ another¼á bu⌠á rathe≥á thσ ì
receivσ buffe≥ numbe≥ (aε interna∞ systeφ paramete≥ identifyinτ ß ì
particula≥ buffer¼ iε thi≤ casσ containinτ ß ful∞ valiΣ frame⌐ i≤ ìèplaceΣá oε ß queuσ lis⌠ fo≥ processinτ b∙ thσ nex⌠á level«á  Thi≤ ì
importan⌠á concep⌠ minimize≤ thσ overheaΣ requireΣ b∙ thσá systeφ ì
t∩ movσ datß froφ onσ leve∞ oµ processinτ t∩ another.

     Thσ leve∞ ▓ receiveΣ framσ disassemble≥ check≤ thσ framσ fo≥ ì
prope≥á address¼á examine≤ thσ contro∞ bytσ t∩ identif∙ thσ framσ ì
type¼á change≤á thσ statσ oµ thσ systeφ iµ requireΣ b∙ thσá framσ ì
type¼á anΣá give≤ contro∞ t∩ thσ prope≥ responsσá framσá transmi⌠ ì
routine if required by the frame type and system state.

     Iµ thσ receiveΣ framσ i≤ aε informatioε frame¼ anΣ thσ statσ ì
oµá thσá systeφá permit≤ acceptancσ oµ sucΦá ßá frame¼á thσá senΣ ì
sequencσ numbe≥ oµ thσ framσ N(s⌐ i≤ checkeΣ agains⌠ thσ expecteΣ ì
framσá sequencσá numbe≥á anΣá iµá invalid¼áá ßá rejec⌠á framσá i≤ ì
transmitteΣ iε accordancσ witΦ thσ X.2╡ protocol.

     Iµá thσá receiveΣá senΣá sequencσá numbe≥á i≤á correct¼á thσ ì
informatioεá fielΣ oµ thσ framσ (whicΦ contain≤ thσ datßá packet⌐ ì
i≤á passeΣá t∩ thσ receiveΣ packe⌠ disassemble≥ iεá thσá leve∞á │ ì
module«á  A≤á before¼á actua∞ datß i≤ no⌠ passed¼á bu⌠ rathe≥ thσ ì
receiveΣ buffe≥ numbe≥ i≤ placeΣ oε ß receiveΣ packe⌠ queuσá lis⌠ ì
t∩ awai⌠ processinτ b∙ thσ nex⌠ level.

     Iε receiveΣ informatioε frames¼á anΣ iε numbereΣ supervisor∙ ì
frames¼á thσ receiveΣ sequencσ numbe≥ N(r⌐ containeΣ iε thσ framσ ì
i≤á useΣ t∩ acknowledgσ previousl∙ transmitteΣ informatioε frame≤ ì
anΣá updatσ thσ 'windowº oµ permitteΣ transmi⌠á sequencσá number≤ ì
fo≥ outgoinτ informatioε frames«á Iε thi≤ manner¼ receiveΣ frame≤ ì
contro∞á thσá ratσá oµá transmissioε oµ frame≤á iεá thσá oppositσ ì
direction.

     Thσá leve∞ │ packe⌠ disassemble≥ check≤ thσ packe⌠ fo≥ valiΣ ì
format¼á prope≥á grou≡ numbe≥ anΣ channe∞á number¼á examine≤á thσ ì
packe⌠ identifie≥ octe⌠ t∩ determinσ thσ packe⌠ type¼ change≤ thσ ì
statσá oµá thσá systeφ a≤ requireΣ b∙ thσ packe⌠ typσá anΣá give≤ ì
contro∞ t∩ thσ prope≥ packe⌠ transmi⌠ routinσ iµ requireΣ b∙á thσ ì
packet type and current system state.

     Iµ thσ receiveΣ packe⌠ i≤ ß datß packe⌠ anΣ thσ statσ oµ thσ ì
machinσá permit≤á acceptancσá oµ datß packets¼á thσá packe⌠á senΣ ì
sequencσá numbe≥ P(s⌐ i≤ checkeΣ agains⌠ thσ expecteΣá value«á  ┴ ì
packe⌠á numbe≥ outsidσ thσ receiveΣ windo≈ o≥ ou⌠ oµ sequencσá i≤ ì
considereΣ ß loca∞ procedurσ erro≥ anΣ cause≤ thσ systeφ t∩á senΣ ì
a reset request packet to logically  reset the circuit.

     Iµ thσ receiveΣ datß packe⌠ i≤ valiΣ anΣ ß receivσ datß filσ ì
ha≤ beeε previousl∙ opened¼á thσ datß iε thσ packe⌠ i≤ writteε t∩ ì
thσ disδ file«á  Iµ ß receivσ filσ i≤ no⌠ open¼á thσ datß i≤ sen⌠ ì
t∩ thσ consolσ (CRT⌐ buffe≥ fo≥ displa∙ t∩ thσ loca∞ user«á  Onl∙ ì
displayablσá ASCI╔á character≤á anΣá ß selecteΣá se⌠á oµá contro∞ ì
character≤ arσ actuall∙ sen⌠ t∩ thσ console╗á ß perioΣ i≤ useΣ t∩ ì
replacσá an∙á non-displayablσ character≤ t∩á avoiΣá unpredictablσ ì
behavior of the console.

     Iε ß manne≥ simila≥ t∩ leve∞ 2¼á thσ packe⌠ receivσ sequencσ ìènumbe≥á P(r⌐á iεá datßá o≥á flo≈á contro∞á packet≤á i≤á useΣáá t∩ ì
acknowledgσ previousl∙ transmitteΣ datß packet≤ anΣ t∩ updatσ thσ ì
packe⌠ 'windowº fo≥  transmission«  Iε thi≤ manner¼ receiveΣ datß ì
o≥á flo≈ contro∞ packet≤ contro∞ thσ ratσ oµ transmissioε oµ datß ì
packets in the reverse direction.

     Receivσá buffer≤ whicΦ havσ beeε discardeΣ alonτ thσ wa∙á o≥ ì
havσá delivereΣá thei≥á datß t∩ thσ fina∞á destinatioεá arσá madσ ì
availablσá fo≥á reusσ b∙ placinτ thei≥ framσ number≤ iεá ßá queuσ ì
lis⌠á oµ freσ buffe≥ numbers«á  Thesσ availablσ frame≤á arσá madσ ì
activσá onσá a⌠á ßá timσ a≤ requireΣ b∙á thσá hardwarσá interrup⌠ ì
servicσá routine≤á iε thσ leve∞ ▒ module«á  Thσá numbe≥á oµá freσ ì
receivσá buffer≤ a⌠ an∙ giveε timσ determine≤ thσ read∙ statσá oµ ì
thσá system¼á whicΦ control≤ thσ updatinτ oµ sequencσ number≤ anΣ ì
thσá type≤á oµ flo≈ contro∞ frame≤ anΣ packet≤á returneΣá t∩á thσ ì
communication≤ port«  Thi≤ process¼ iε turn¼ control≤ thσ ratσ a⌠ ì
whicΦá ne≈á informatioε frame≤ anΣ datß packet≤ arσ sen⌠á t∩á thσ ì
system¼á thu≤ insurinτ tha⌠ datß i≤ no⌠ transmitteΣ t∩ thσ systeφ ì
faste≥ thaε thσ systeφ caε proces≤ it.

     Thσá transmi⌠á proces≤á i≤á considerabl∙á simple≥á thaεá thσ ì
receivσ process«á  Datß typeΣ iε thσ systeφ consolσ i≤ writteε t∩ ì
ßá consolσ datß buffer«á Assuminτ thσ systeφ ha≤ beeε placeΣ iε ß ì
statσá wherσá thσ remotσ systeφ caε accep⌠ datßá anΣá thσá packe⌠ ì
transmi⌠á windo≈ allow≤ it¼á thσ transmi⌠ proces≤ caε begin«á Thσ ì
leve∞á │ packe⌠ assembl∙ processo≥ read≤ datß froφá thσá transmi⌠ ì
disδá file¼á iµ sucΦ ß filσ ha≤ beeε opened╗á o≥ froφ thσ consolσ ì
buffer¼á anΣá place≤ thσ datß iε thσ nex⌠ sequentiall∙á availablσ ì
freσ transmi⌠ buffer.

     Wheε thσ maximuφ datß packe⌠ sizσ ha≤ beeε reached¼á o≥ wheε ì
thσ enΣ oµ filσ ha≤ beeε reached¼ o≥ wheε ß carriagσ returε typeΣ ì
a⌠ thσ systeφ consolσ i≤ encountered¼ thσ leve∞ │ packe⌠ assembl∙ ì
processo≥á stop≤á readinτ datß anΣ  assemble≤ ß datß packe⌠á witΦ ì
thσá correc⌠ sequencσ number≤ (iε thi≤ system¼á  thσá transmitteΣ ì
packe⌠á senΣ  sequencσ numbe≥ P(s⌐ i≤ b∙ definitioε equa∞ t∩á thσ ì
transmi⌠á buffe≥ number)«á  I⌠ theε tag≤ thσ buffe≥ witΦ ßá read∙ ì
flag.

     Thσá leve∞á ▓ framσ transmi⌠ processo≥ onl∙á start≤á workinτ ì
wheεá thσ leve∞ ▒ processo≥ indicate≤ tha⌠ thσ hardwarσ interfacσ ì
(Z80-SIO⌐á i≤á no⌠ bus∙ transmitting«á  Wheεá thi≤á conditioεá i≤ ì
satisfied¼á anΣ wheε it≤ transmi⌠ windo≈ allow≤ it¼ i⌠ check≤ fo≥ ì
ßá read∙á flaτ iε thσ nex⌠ sequentia∞ transmi⌠ buffer«á  Wheεá i⌠ ì
find≤á sucΦ ß flag¼á i⌠ assemble≤ aε informatioε framσá witΦá thσ ì
correc⌠á sequencσá number≤ anΣ signal≤ thσ leve∞ ▒á processo≥á t∩ ì
transmit the frame.

     Afte≥á thσá framσ i≤ transmitted¼á thσ buffe≥á pointer≤á arσ ì
restoreΣá anΣ thσ buffe≥ kep⌠ intac⌠ fo≥ possiblσ retransmission« ì
A≤ transmitteΣ frame≤ arσ acknowledgeΣ b∙ thσ remotσ system¼á thσ ì
transmi⌠á 'windowº i≤ updateΣ anΣ thσ transmi⌠ framσ buffer≤á arσ ì
cleareΣá anΣá madσá availablσ fo≥ usσá b∙á thσá nex⌠á transmitteΣ ì
packet« B∙ thi≤ mechanism¼ thσ remotσ systeφ control≤ thσ maximuφ ì
ratσáá a⌠á whicΦá thσá systeφá wil∞á transmi⌠á datßá packet≤á anΣ ìèinformatioε frame≤ t∩ thσ communication≤ port s∩ a≤ no⌠ t∩ exceeΣ ì
the remote system's capacity for processing data packets.



5.  Internal Data Storage

     WitΦ somσ mino≥ exceptions¼á al∞ datß interna∞ t∩ thσ systeφ ì
i≤á storeΣá iε circula≥ first-in-first-ou⌠ buffer≤ controlleΣá b∙ ì
identica∞ pointe≥ structures«á  Usinτ ß commoε contro∞á structurσ ì
ha≤á thσá decideΣá advantagσá tha⌠ i⌠á permit≤á usinτá  thσá samσ ì
subroutine≤ t∩ acces≤ al∞ buffers¼ regardles≤ oµ sizσ o≥ purpose«  ì
Thσá onl∙ buffer≤ no⌠ complyinτ witΦ thi≤ forma⌠ arσ thσá buffer≤ ì
whosσá forma⌠á i≤ defineΣ b∙ thσ CP/═ operatinτ system¼á sucΦá a≤ ì
disδ filσ reaΣ anΣ writσ buffers«

     A≤á implemented¼á thσá systeφ contain≤ sixteeε receivσá datß ì
buffers¼á bu⌠ thi≤ numbe≥ ma∙ bσ easil∙ increaseΣ u≡ t∩ ß maximuφ ì
oµá 12╖á iµ sufficien⌠ memor∙ i≤ availablσ iεá thσá system«á  Thσ ì
implementeΣá buffe≥á sizσ correspond≤ t∩ ßá maximuφá packe⌠á datß ì
fielΣá sizσ oµ 12╕ octets¼á whicΦ i≤ thσ standarΣ maximuφá packe⌠ ì
use≥ datß lengtΦ recommendeΣ iε thσ X.2╡ standard«

     Thσ systeφ als∩ contain≤ eigh⌠ transmi⌠ datß buffers¼ oµ thσ ì
samσá sizσ a≤ thσ receivσ buffers«á  EacΦ transmi⌠ datß buffe≥ i≤ ì
assigneΣ t∩ onσ oµ thσ eigh⌠ possiblσ framσ senΣ sequencσ number≤ ì
(░ t∩ 7).

     Iεá additioε t∩ thσ receivσ anΣ transmi⌠ datßá buffers¼á thσ ì
systeφ contain≤ threσ queuσ buffer≤ useΣ t∩ holΣ list≤ oµ receivσ ì
buffe≥ identification number≤ a≤ follows:

     list of free receive buffers
     list of receive buffers containing full received frames
     list of receive buffers containing full received packets

     Thesσá queuσá buffer≤á arσá useΣ t∩ contro∞á thσá datßá flo≈ ì
betweeεá processinτá level≤á b∙á passinτá buffe≥áá identificatioε ì
numbers between levels, rather than transferring data.

     Iεá additioε t∩ thσ preceding¼á fivσ additiona∞ buffer≤á arσ ì
provideΣá t∩ handlσ thσ interfacσ betweeε thσ loca∞ use≥ anΣá thσ ì
packe⌠ processinτ system«  Thesσ buffer≤ are:

     a⌐ thσ  consolσ inpu⌠ buffe≥ t∩ handlσ typeΣ inpu⌠ froφá thσ ì
        loca∞ keyboard.

     b⌐ thσ consolσ outpu⌠ buffe≥ t∩ handlσ datß intendeΣ fo≥ thσ ì
        loca∞ CR╘ outpu⌠ device.

     c⌐ thσ consolσ transmi⌠ buffe≥ t∩ interfacσ typeΣ inpu⌠ datß ì
        intendeΣ fo≥ transmissioε iε packets.

     d⌐ thσ consolσ receivσ buffe≥ t∩ handlσ incominτ packe⌠ datß ì
        intendeΣ fo≥ displa∙ a⌠ thσ loca∞ console.
è
anΣá e⌐á thσá printe≥ outpu⌠ buffe≥ intendeΣ t∩á handlσá incominτ                  ì
        packe⌠á datßá anΣá typeΣá datß whicΦ i≤á intendeΣá t∩á bσ                           ì
        printeΣá locall∙á (the printer featurσ i≤á no⌠á currentl∙                   ì
        implementeΣ iε thσ hardwarσ selecteΣ fo≥ thσ system).

     Iε additioε t∩ thσ systeφ datß buffer≤ describeΣ above¼ fou≥ ì
additiona∞á buffe≥ area≤ havσ beeε provideΣ fo≥á read/writσá disδ ì
access«á Thσá area≤á arσá  useΣ b∙ thσ CP/═ operatinτá systeφá t∩ ì
buffe≥ datß froφ anΣ t∩ thσ receivσ anΣ transmi⌠ disδ datß files¼ ì
thσá systeφ defaul⌠ paramete≥ disδ filσ anΣ thσ sessioε loτá disδ ì
file«á  Thesσá buffer≤á arσá accesseΣ b∙á thσá systeφá vißá macr∩ ì
routine≤ provideΣ iε thσ Digita∞ ResearcΦ SEQI╧ macr∩ library«


6.  Hardware Configuration

     Thσá systeφá wa≤ implementeΣ t∩ ruε oεá ßá Digita∞á ResearcΦ ì
Computers'á "Biτá Boardó singlσ boarΣ computer«á  Thi≤á uni⌠á wa≤ ì
selecteΣ becausσ oµ it≤ lo≈ cost¼á becausσ i⌠ haΣ thσ desireΣ SI╧ ì
seria∞á interfacσá hardwarσ anΣ CT├ timer≤ buil⌠ in¼á becausσá i⌠ ì
employeΣ thσ desirablσ Z8░ modσ ▓ vectoreΣ interrupt≤ fo≥ al∞ I/╧ ì
hardware¼á becausσ oµ it≤ popularit∙ witΦ hobbyist≤ and¼ las⌠ bu⌠ ì
no⌠ least¼á becausσ oµ thσ availabilit∙ oµ ful∞ documentatioεá iε ì
thσá forφ oµ hardwarσ schematic≤ anΣ sourcσ codσ fo≥ thσ buil⌠ iε ì
monito≥ anΣ CP/═ BIO╙ routines.


7. BIBLIOGRAPHY


1«áá "Datßá Communication≤á Networks¼á Service≤á anΣá Facilities¼ ì
Termina∞á Equipmen⌠ anΣ Interfaces¼á Recommendation≤ X.1-X.29"éá - ì
Thσá Yello≈ Book¼á Volumσ VII╔ - Fasciclσá VIII.2¼á Internationa∞ ì
Telecommunicatioε Unioε CCITT¼ Genevß 1981«

The international X.25 standard, revised in 1981

2«  Thσ X.2╡ Protoco∞ anΣ Seveε Othe≥ Ke∙ CCIT╘ Recommendationsé - ì
Lifetime Learning Publications, Belmont, CA 1983.

Aε inexpensivσ reprin⌠ oµ thσ CCIT╘ X.1¼á X.2¼ X.3¼ X.21¼ X21bis¼ ì
X.25, X.28 and X.29 standards.
 ì
3«á Microprocesso≥ Application≤ Referencσ Book¼á Volumσ 1é - Ziloτ ì
Corporation, July 1981.

Relevan⌠á compilatioεá oµá applicatioεá note≤ oεá thσá Ziloτá Z8░ ì
microprocessor family (see references 3a and 3b).


3a«áá  Usinτáá thσá Z8░á SI╧á witΦá SDL├á (applicatioεá brief)éáá - ì
(part of reference 3)

Applicatioε notσ describinτ thσ usσ oµ thσ Ziloτ Z80-SI╧ witΦ thσ ìèHDLC/SDL├á HigΦá Datßá Linδ Contro∞á anΣá Synchronou≤á Datßá Linδ ì
Contro∞ protocols«  Thσ samplσ routine≤ describeΣ hereiε werσ thσ ì
basis of the routines utilized in the system LEVEL1 module.


3b«áá  Z8░á Famil∙á Interrup⌠á Structurσá (tutorial)éá - (par⌠á oµ ì
reference 3)

Concisσ tutoria∞ describinτ thσ interrup⌠ structurσ oµ thσá Ziloτ ì
Z80 microprocessor family.


4«á Zilog Datßá Booδ  - Ziloτ Corporation, 1982/1983.

┴á referencσá compilatioε oµ datß sheet≤ oε thσ Ziloτá famil∙á oµ ì
microprocessor products, including the Z80, SIO and CTC.

5.  Big Board Documentation - Digital Research Computers,
P.O«á Bo° 401565¼á GarlanΣ Texa≤ (no⌠ relateΣ t∩ Digita∞ ResearcΦ ì
Corp of Pacific Grove CA).

Documentatioεá oεá thσá hardwarσ useΣ t∩á implemen⌠á thσá projec⌠ ì
system.


6. Cole, Robert - "Computer Communications", Springer-Verlag,
1982«

┴á genera∞ overvie≈ oµ curren⌠ compute≥ communication≤á practice¼ ì
witΦá particula≥á emphasi≤á oεá networking«á  Contain≤á excellen⌠ ì
introductor∙á description≤ oµ thσ operatioε oµ thσ HDL├ anΣá X.2╡ ì
protocols« Onσ chapte≥ anΣ portion≤ oµ severa∞ other≤ arσ devoteΣ ì
t∩á thσ X.2╡ protocol¼á includinτ discussioε oµ area≤ no⌠ defineΣ ì
b∙ thσ standard¼ probleφ area≤  anΣ somσ curren⌠ use≥ practices.


7«á "CP/═á MA├ Macr∩ Assembler║á Languagσ Manua∞ anΣ Application≤ ì
Guide"é - Digital Research Corp.

Referencσ guidσ fo≥ thσ MA├ anΣ RMA├ macr∩ assembler¼á thσ latte≥ ì
useΣá t∩á develo≡ thσ projec⌠ system«á  Als∩á include≤á referencσ ì
information on the SEQIO sequential file access macro library.

8«áá Inte∞á 808░á Assembl∙á Languagσá Programminτá Manual¼á Inte∞ ì
Corporation 1976.

Comprehensivσá referencσá t∩ thσ assembl∙á languagσá instruction≤ ì
used to implement the project.


9«á Z8░ Assembl∙ Languagσ Programminτ Manual¼á Ziloτ Corporation¼ ì
1977.

Comprehensivσ reference t∩ thσ specia∞ bi⌠ manipulatioε anΣ blocδ ì
move instructions used to implement the project.
è