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sparc-opcode.h
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1993-09-22
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637 lines
/* Table of opcodes for the sparc.
Copyright (C) 1989 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#if !defined(__STDC__) && !defined(const)
#define const
#endif
/*
* Structure of an opcode table entry.
*/
struct sparc_opcode
{
const char *name;
unsigned long int match; /* Bits that must be set. */
unsigned long int lose; /* Bits that must not be set. */
const char *args;
/* Nonzero if this is a delayed branch instruction. */
char delayed;
};
/*
All sparc opcodes are 32 bits, except for the `set' instruction (really
a macro), which is 64 bits. It is handled as a special case.
The match component is a mask saying which bits must match a
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing one character
for each operand of the instruction.
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
d rd register.
e frs1 floating point register.
f frs2 floating point register.
g frsd floating point register.
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
h 22 high bits.
i 13 bit Immediate.
l 22 bit PC relative immediate.
L 30 bit PC relative immediate.
a Annul. The annul bit is set.
A Alternate address space. Stored as 8 bits.
C Coprocessor state register.
F floating point state register.
p Processor state register.
q Floating point queue.
r Single register that is both rs1 and rsd.
Q Coprocessor queue.
S Special case.
t Trap base register.
w Window invalid mask register.
y Y register.
*/
/* The order of the opcodes in this table is significant:
* The assembler requires that all instances of the same mnemonic must be
consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes. */
static struct sparc_opcode sparc_opcodes[] =
{
{ "ldd", 0xc1980000, 0x0060201f, "[1],D", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc1982000, 0x00601fff, "[1],D", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc1982000, 0x00600000, "[1+i],D", 0 },
{ "ldd", 0xc1982000, 0x00600000, "[i+1],D", 0 },
{ "ldd", 0xc1980000, 0x00602000, "[1+2],D", 0 },
{ "ldd", 0xc1180000, 0x00e0201f, "[1],g", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc1182000, 0x00e01fff, "[1],g", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc1182000, 0x00e00000, "[1+i],g", 0 },
{ "ldd", 0xc1182000, 0x00e00000, "[i+1],g", 0 },
{ "ldd", 0xc1180000, 0x00e02000, "[1+2],g", 0 },
{ "ldd", 0xc0180000, 0x01e0201f, "[1],d", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc0182000, 0x01e01fff, "[1],d", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc0182000, 0x01e00000, "[1+i],d", 0 },
{ "ldd", 0xc0182000, 0x01e00000, "[i+1],d", 0 },
{ "ldd", 0xc0180000, 0x01e02000, "[1+2],d", 0 },
{ "ld", 0xc1880000, 0x0070201f, "[1],C", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1882000, 0x00701fff, "[1],C", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1882000, 0x00700000, "[1+i],C", 0 },
{ "ld", 0xc1882000, 0x00700000, "[i+1],C", 0 },
{ "ld", 0xc1880000, 0x00702000, "[1+2],C", 0 },
{ "ld", 0xc1800000, 0x0078201f, "[1],D", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1802000, 0x00781fff, "[1],D", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1802000, 0x00780000, "[1+i],D", 0 },
{ "ld", 0xc1802000, 0x00780000, "[i+1],D", 0 },
{ "ld", 0xc1800000, 0x00782000, "[1+2],D", 0 },
{ "ld", 0xc1080000, 0x00f0201f, "[1],F", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1082000, 0x00f01fff, "[1],F", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1082000, 0x00f00000, "[1+i],F", 0 },
{ "ld", 0xc1082000, 0x00f00000, "[i+1],F", 0 },
{ "ld", 0xc1080000, 0x00f02000, "[1+2],F", 0 },
{ "ld", 0xc1000000, 0x00f8201f, "[1],g", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1002000, 0x00f81fff, "[1],g", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1002000, 0x00f80000, "[1+i],g", 0 },
{ "ld", 0xc1002000, 0x00f80000, "[i+1],g", 0 },
{ "ld", 0xc1000000, 0x00f82000, "[1+2],g", 0 },
{ "ld", 0xc0000000, 0x01f8201f, "[1],d", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc0002000, 0x01f81fff, "[1],d", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc0002000, 0x01f80000, "[1+i],d", 0 },
{ "ld", 0xc0002000, 0x01f80000, "[i+1],d", 0 },
{ "ld", 0xc0000000, 0x01f82000, "[1+2],d", 0 },
{ "ldstuba", 0xc0d80000, 0x0100201f, "[1]A,d", 0 }, /* ldstuba [rs1+%g0],d */
{ "ldstuba", 0xc0d80000, 0x01002000, "[1+2]A,d", 0 },
{ "ldsha", 0xc0d00000, 0x0128201f, "[1]A,d", 0 }, /* ldsha [rs1+%g0],d */
{ "ldsha", 0xc0d00000, 0x01282000, "[1+2]A,d", 0 },
{ "ldsba", 0xc0c80000, 0x0130201f, "[1]A,d", 0 }, /* ldsba [rs1+%g0],d */
{ "ldsba", 0xc0c80000, 0x01302000, "[1+2]A,d", 0 },
{ "ldda", 0xc0980000, 0x0160201f, "[1]A,d", 0 }, /* ldda [rs1+%g0],d */
{ "ldda", 0xc0980000, 0x01602000, "[1+2]A,d", 0 },
{ "lduha", 0xc0900000, 0x0168201f, "[1]A,d", 0 }, /* lduha [rs1+%g0],d */
{ "lduha", 0xc0900000, 0x01682000, "[1+2]A,d", 0 },
{ "ldstub", 0xc0680000, 0x0190201f, "[1],d", 0 }, /* ldstub [rs1+%g0],d */
{ "ldstub", 0xc0682000, 0x01900000, "[1+i],d", 0 },
{ "ldstub", 0xc0682000, 0x01900000, "[i+1],d", 0 },
{ "ldstub", 0xc0680000, 0x01902000, "[1+2],d", 0 },
{ "lda", 0xc0800000, 0x0178201f, "[1]A,d", 0 }, /* lda [rs1+%g0],d */
{ "lda", 0xc0800000, 0x01782000, "[1+2]A,d", 0 },
{ "ldsh", 0xc0500000, 0x0000000d, "[1],d", 0 }, /* ldsh [rs1+%g0],d */
{ "ldsh", 0xc0502000, 0x01a81fff, "[1],d", 0 }, /* ldsh [rs1+0],d */
{ "ldsh", 0xc0502000, 0x01a80000, "[1+i],d", 0 },
{ "ldsh", 0xc0502000, 0x01a80000, "[i+1],d", 0 },
{ "ldsh", 0xc0500000, 0x01a82000, "[1+2],d", 0 },
{ "ldsb", 0xc0480000, 0x01b0201f, "[1],d", 0 }, /* ldsb [rs1+%g0],d */
{ "ldsb", 0xc0482000, 0x01b01fff, "[1],d", 0 }, /* ldsb [rs1+0],d */
{ "ldsb", 0xc0482000, 0x01b00000, "[1+i],d", 0 },
{ "ldsb", 0xc0482000, 0x01b00000, "[i+1],d", 0 },
{ "ldsb", 0xc0480000, 0x01b02000, "[1+2],d", 0 },
{ "ldub", 0xc0080000, 0x01f0201f, "[1],d", 0 }, /* ldub [rs1+%g0],d */
{ "ldub", 0xc0082000, 0x01f01fff, "[1],d", 0 }, /* ldub [rs1+0],d */
{ "ldub", 0xc0082000, 0x01f00000, "[1+i],d", 0 },
{ "ldub", 0xc0082000, 0x01f00000, "[i+1],d", 0 },
{ "ldub", 0xc0080000, 0x01f02000, "[1+2],d", 0 },
{ "lduba", 0xc0880000, 0x0170201f, "[1]A,d", 0 }, /* lduba [rs1+%g0],d */
{ "lduba", 0xc0880000, 0x01702000, "[1+2]A,d", 0 },
{ "lduh", 0xc0102000, 0x01e80000, "[1+i],d", 0 },
{ "lduh", 0xc0102000, 0x01e80000, "[i+1],d", 0 },
{ "lduh", 0xc0100000, 0x01e8201f, "[1],d", 0 }, /* lduh [rs1+%g0],d */
{ "lduh", 0xc0102000, 0x01e81fff, "[1],d", 0 }, /* lduh [rs1+0],d */
{ "lduh", 0xc0100000, 0x01e82000, "[1+2],d", 0 },
{ "st", 0xc0200000, 0x01d8201f, "d,[1]", 0 }, /* st d,[rs1+%g0] */
{ "st", 0xc0202000, 0x01d81fff, "d,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc0202000, 0x01d80000, "d,[1+i]", 0 },
{ "st", 0xc0202000, 0x01d80000, "d,[i+1]", 0 },
{ "st", 0xc0200000, 0x01d82000, "d,[1+2]", 0 },
{ "st", 0xc1200000, 0x00d8201f, "g,[1]", 0 }, /* st d[rs1+%g0] */
{ "st", 0xc1202000, 0x00d81fff, "g,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc1202000, 0x00d80000, "g,[1+i]", 0 },
{ "st", 0xc1202000, 0x00d80000, "g,[i+1]", 0 },
{ "st", 0xc1200000, 0x00d82