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Text File  |  1993-07-18  |  6.5 KB  |  179 lines
  1. DVSOR   RMB     3               24 bit divisor
  2. DVDND   RMB     3               24 bit dividend (entry) - result (exit)
  3. TEMPA   RMB     1
  4. TEMPB   RMB     1
  5. COUNT   RMB     1
  6. TEMP1   RMB     1
  7. TEMP2   RMB     1
  8. TEMP3   RMB     1
  9. TEMP4   RMB     1
  10. OCRH    RMB     1
  11. OCRL    RMB     1
  12. ALTCNTH RMB     1
  13. ALTCNTL RMB     1
  14.  
  15.  
  16. **** 16 BITS / 16 BITS = 16 BITS DIVISION subroutine ****
  17. *                                                       *       
  18. *       on entry : DVDND DVDND+1 = dividend             *
  19. *                  DVSR DVSR+1 = divisor                *
  20. *       on exit  : DVDND DVDND+1 = quotient             *
  21. *        (MSByte first - Motorola style)                *
  22. *********************************************************
  23. DIV1616 LDA     #1
  24.         TST     DVSOR
  25.         BMI     DIV153
  26. DIV151  INCA
  27.         ASL     DVSOR+1
  28.         ROL     DVSOR
  29.         BMI     DIV153
  30.         CMP     #17
  31.         BNE     DIV151
  32. DIV153  STA     COUNT
  33.         LDA     DVDND
  34.         LDX     DVDND+1
  35.         CLR     DVDND
  36.         CLR     DVDND+1
  37. DIV163  STA     TEMPA
  38.         TXA
  39.         SUB     DVSOR+1
  40.         TAX
  41.         LDA     TEMPA
  42.         SBC     DVSOR
  43.         BCC     DIV165
  44.         STA     TEMPA
  45.         TXA
  46.         ADD     DVSOR+1
  47.         TAX
  48.         LDA     TEMPA
  49.         ADC     DVSOR
  50.         CLC
  51.         BRA     DIV167
  52. DIV165  SEC
  53. DIV167  ROL     DVDND+1
  54.         ROL     DVDND
  55.         LSR     DVSOR
  56.         ROR     DVSOR+1
  57.         DEC     COUNT
  58.         BNE     DIV163
  59.         RTS
  60.  
  61.  
  62. **** 24 BITS / 24 BITS = 24 BITS DIVISION subroutine ****
  63. *                                                       *       
  64. *       on entry : DVDND DVDND+1 DVDND+2 = dividend     *
  65. *                  DVSR DVSR+1 DVSR+2 = divisor         *
  66. *       on exit  : DVDND DVDND+1 DVDND+2 = quotient     *
  67. *             (MSByte first - Motorola style)           *
  68. *            3055 cycles worst case time (0/1)          *
  69. *                                                       *
  70. *********************************************************
  71.  
  72. DIV2424 LDA     #1
  73.         TST     DVSOR                   divisor < 0 ? 
  74.         BMI     DIV233                  |
  75. DIV231  INCA
  76.         ASL     DVSOR+2                 move DVSOR's msb full left rotating
  77.         ROL     DVSOR+1                 it left COUNT times     
  78.         ROL     DVSOR                   |       
  79.         BMI     DIV233                  |
  80.         CMP     #25                     |
  81.         BNE     DIV231                  |
  82. DIV233  STA     COUNT                   |
  83.         LDA     DVDND+2                 Save dividend in TEMPB,A,X
  84.         STA     TEMPB                   and clear dividend area to store result
  85.         LDA     DVDND                   |
  86.         LDX     DVDND+1                 |
  87.         CLR     DVDND                   |
  88.         CLR     DVDND+1                 |
  89.         CLR     DVDND+2                 |
  90. DIV243  STA     TEMPA                   Subtract left-shifted divisor
  91.         LDA     TEMPB                   from dividend
  92.         SUB     DVSOR+2                 |
  93.         STA     TEMPB                   |
  94.         TXA                             |       
  95.         SBC     DVSOR+1                 |
  96.         TAX                             |
  97.         LDA     TEMPA                   |
  98.         SBC     DVSOR                   |
  99.         BCC     DIV245                  Divisor OK? (i.e. < dividend)
  100.         STA     TEMPA                   Divisor too large :
  101.         LDA     TEMPB                   Add divisor back to the result of the
  102.         ADD     DVSOR+2                 previous subtraction and shift a '0'
  103.         STA     TEMPB                   in the quotient (CLC, ROL)
  104.         TXA                             |
  105.         ADC     DVSOR+1                 |
  106.         TAX                             |
  107.         LDA     TEMPA                   |
  108.         ADC     DVSOR                   |
  109.         CLC                             |
  110.         BRA     DIV247
  111. DIV245  SEC                             If divisor OK, shift '1' in quotient
  112. DIV247  ROL     DVDND+2                 Rotate result
  113.         ROL     DVDND+1                 |
  114.         ROL     DVDND                   |
  115.         LSR     DVSOR                   Shift divisor
  116.         ROR     DVSOR+1                 |
  117.         ROR     DVSOR+2                 |
  118.         DEC     COUNT                   End of loop?
  119.         BNE     DIV243          
  120.         RTS                             
  121.  
  122.  
  123. *************** OCF timer update subroutine *************
  124. *                                                       *
  125. *       on entry : X reg = byte to add to OCRL          *
  126. *                          (output compare low reg)     *
  127. *       on entry : A reg = byte to add to OCRH          *
  128. *                          (output compare hi reg)      *
  129. *       each added bit = 4 cycles - 2 microsec @4MHz    *
  130. *                                                       *
  131. *       subroutine max exec time:24 cycles(inc return)  *
  132. *                            +10 parm. setup and call   *
  133. *                            (17 microsec @4MHz)        *
  134. *********************************************************
  135.  
  136. OCTUPD  ADD     ALTCNTH                 read alternate timer counter hi: this
  137.         STA     OCRH                    freezes ALTCNTL. Then store in OCRH:
  138.         TXA                             o.c. interrupts inhibited until OCRL is
  139.         ADD     ALTCNTL                 written. If carry from lower bytes,
  140.         BCC     NOCARRY                 increment OCRH.
  141.         INC     OCRH
  142. NOCARRY STA     OCRL                    
  143.         RTS
  144.  
  145. **** 16 BITS / 16 BITS = 32 BITS MULTIPLY subroutine ****
  146. *                                                       *
  147. * on entry:[1,DVDND:2,DVDND]=[MPCAND:1,MPCAND]=[X:1,X]  *
  148. *                                       =MULTIPLICAND   *
  149. *          [2,DVSOR:DVDND]=[MPLIER:1,MPLIER]=           *
  150. *                                       =MULTIPLIER     *
  151. * on exit:[DVSOR:DVDND]=[M16RES:3,M16RES]=              *
  152. *                                       =32 bit RESULT  *
  153. *             (MSByte first - Motorola style)           *
  154. *                                                       *
  155. *********************************************************
  156. MULT16  CLR     TEMP1
  157.         CLR     TEMP2
  158.         LDA     #16
  159.         STA     TEMPA                                                   
  160.         CLC
  161.  
  162. M16LOOP ROR     TEMP3
  163.         ROR     TEMP4
  164.         BCC     MLOOP5
  165.         LDA     TEMP2
  166.         ADD     1,X
  167.         STA     TEMP2
  168.         LDA     TEMP1
  169.         ADC     0,X
  170.         STA     TEMP1
  171.  
  172. MLOOP5  ROR     TEMP1
  173.         ROR     TEMP2
  174.         DEC     TEMPA
  175.         BNE     M16LOOP
  176.         ROR     TEMP3
  177.         ROR     TEMP4
  178.         RTS
  179.