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video7.txt
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1993-01-22
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392 lines
Video 7 Super VGA.
Now Headland Technologies
Earlier V7/Headland boards use Chips&Technologies and Cirrus chips.
Board: Chip:
V7VRAM HT-208
V71024i HT-208
? HT-216
100h (R/W?): Microchannel ID low
bit 0-7 Card ID bit 0-7
101h (R/W?): Microchannel ID high
bit 0-7 Card ID bit 8-15
102h (R/W): Alt Video Subsystem Enable
bit 0 Enable Video if set
Must be armed by 3C4h index 0FCh bit 7
or in setup mode (46E8h bit4) to change.
3C2h (W): Misc Output register
bit 5 Bit 1 of Bank no.
Note: This register can be read at 3CCh.
3C3h (R/W): Video Subsystem Enable
bit 0 Enable Microchannel Video if set
Must be armed by 3C4h index 0FCh bit 7 to change.
3C4h index 6 (R/W): Extension Control
bit 0 (Read Only) Extensions enabled if set
bit 0-7 (Write Only) 0EAh Enables extensions, 0AEh disables.
3C4h index 7 (R/W): Reset Horizontal Character Counter
3C4h index 80h (R/W): Test
3C4h index 81h (R/W): Test
3C4h index 82h (R/W): Test
3C4h index 83h (R/W): Attribute Control Index
3C4h index 8Eh-8Fh (R): Chip Version
bit 0-7 Chip version:
80h-FFh: VEGA VGA Chip,
70h: V7VGA chip revision 1,2 or 3
71h: V7VGA chip revision 4
50h-59h: V7VGA Version 5
41h-49h: 1024i.
3C4h index 94h (R/W): Pointer Pattern Address
bit 0-7 Bit 6-13 of the start address of the Pointer Pattern
3C4h index 9Ch (R/W): Pointer Horizontal Position High
bit 0-2 Bit 8-10 of the X coordinate of the Pointer
3C4h index 9Dh (R/W): Pointer Horizontal Position Low
bit 0-7 Bit 0-7 of the X coordinate of the Pointer
3C4h index 9Eh (R/W): Pointer Vertical Position High
bit 0-1 Bit 8-9 of the Y coordinate of the Pointer
3C4h index 9Fh (R/W): Pointer Vertical Position Low
bit 0-7 Bit 0-7 of the Y coordinate of the Pointer
3C4h index A0h (R/W): GC Memory Latch 0
bit 0-7 Plane 0 Memory Latch Data
3C4h index A1h (R/W): GC Memory Latch 1
bit 0-7 Plane 1 Memory Latch Data
3C4h index A2h (R/W): GC Memory Latch 2
bit 0-7 Plane 2 Memory Latch Data
3C4h index A3h (R/W): GC Memory Latch 3
bit 0-7 Plane 3 Memory Latch Data
3C4h index A4h (R/W): Clock Select
bit 2-4 0: 25.175 MHz
1: 28.322 MHz
2: 30.000 MHz
3: 32.514 MHz
4: 34.000 MHz
5: 36.000 MHz
6: 38.000 MHz
7: 40.000 MHz
3C4h index A5h (R/W): Cursor Attributes
bit 0 Cursor blink enabled if clear
3 Text Cursor Mode is XOR if set, Replace if clear
7 Graphics Cursor Enabled if set
3C4h index B0h-BFh (R/W): Scratch Registers
bit 0-7 Scratch
3C4h index E0h (R/W): Miscellaneous Control (Version 4+)
bit 0-3 Reserved
4 Interlaced
5-6 Reserved
7 Enables Split Bank Mode
3C4h index E8h (R/W): Single/Write Bank Register (Version 4+)
bit 4-7 Single/Write Bank no.
3C4h index E9h (R/W): Read Bank Register (Version 4+)
bit 4-7 Read Bank no.
Only Active if Split mode enabled (3C4h index E0h bit 7)
3C4h index EAh (W): Switch Strobe
Note: A write to this register copies the switch positions to
the Switch Readback Register (3C4h index F7h).
3C4h index EBh (R/W): Emulation Control
3C4h index ECh (R/W): Foreground Latch 0
bit 0-7 Foreground Latch for plane 0. When in Dither Foreground mode
(3C4h index FEh bit 2-3 = 2) the data in this register
replaces the data written from the processor.
3C4h index EDh (R/W): Foreground Latch 1
bit 0-7 Foreground Latch for plane 1.
3C4h index EEh (R/W): Foreground Latch 2
bit 0-7 Foreground Latch for plane 2.
3C4h index EFh (R/W): Foreground Latch 3
bit 0-7 Foreground Latch for plane 3.
3C4h index F0h (R/W): Fast Foreground Latch Load
bit 0-7 The Foreground Latches (3C4h index ECh to EFh) for the four
memory planes can be loaded by writing to this register.
The writes will cycle through planes 0-3.
A read will restart at plane 0.
3C4h index F1h (R/W): Fast Latch Load State
bit 0-1 Background Latch Load State. Determines which of the
four memory latches will be loaded by a write to 3C4h
index F2h. Each write to index F2h will increment this
value and each read from index F2h will reset it to 0.
2-3 Unused
4-5 Foreground Latch Load State. Determines which of the
four Foreground latches (3C4h index ECh to EFh) will
be loaded by the next write to 3C4h index F0h.
Each write to index F0h will increment this value
and each read from index F0h will reset it to 0.
6-7 Unused
3C4h index F2h (R/W): Fast Background Latch Load
bit 0-7 The Memory Data Latches for the four memory planes can be
loaded by writing to this register. The writes will cycle
through planes 0-3. A read will restart at plane 0.
3C4h index F3h (R/W): Masked Write Control (Only with VRAM)
bit 0 Enables Masked Writes if set
1 If set rotated CPU byte is used as WriteMask, else
Masked Write Mask register is used.
3C4h index F4h (R/W): Masked Write Mask (Only with VRAM)
bit 0-7 If Masked Writes enabled by 3C4h index F3h bit 0
Only the bits set here will be updated in Video memory.
3C4h index F5h (R/W): Foreground/Background Pattern
bit 0-7
3C4h index F6h (R/W): 1MB RAM Bank Select
bit 0-1 Write Bank no bit 2-3 if 256 color, bit 0-1 else.
2-3 Read Bank no bit 2-3 if 256 color, bit 0-1 else.
4-5 CRTC Bank (Address bit 16-17)
6 Display address Wraps Around at bank boundary if set
7 Split Screen Wraps around at bank boundary if set
3C4h index F7h (R/W): Switch Readback
bit 0-7 Switch positions as read by the last write to the Switch
Strobe Register (3C4h index EAh)
3C4h index F8h (R/W): Extended Clock Control
bit 5-7 Clock Source:
0: 25.175 MHz
1: 28.322 MHz
2: 30.000 MHz
3: 32.514 MHz
4: 34.000 MHz
5: 36.000 MHz
6: 38.000 MHz
7: 40.000 MHz
Note: depending on mode and other bits in this register other
values may be selected.
3C4h index F9h (R/W): Page Select
bit 0 bit 16 of Video Memory Address. (Only needed if in a
256 color mode, and 3C4h index FCh bit 1-2 = 1).
3C4h index FAh (R/W): Extended Foreground Color
bit 0-3 Foreground expansion color.
Bit 0 is written to plane 0 et cetera.
3C4h index FBh (R/W): Extended Background Color
bit 0-3 Background expansion color
Bit 0 is written to plane 0 et cetera.
3C4h index FCh (R/W): Compatibility Control
bit 0 Enable Extended Attribute functions if set
Extended attributes allows underlining using a mask
in plane 3 for each character.
1 256-Color Paging Enabled if set.
2 256-Color 64K/128K paging Select.
128K pages if set, 64K pages else.
3-6 Reserved.
7 If set allows enabling VGA via 102h bit 0 or 3C3h bit 0.
3C4h index FDh (R/W): Extended Timing Select
3C4h index FEh (R/W): Foreground/Background Control
bit 0 Unused
1 Foreground/background source select
Source is CPU data if set, 3C4h index F5h else.
2-3 Foreground/background mode select
0 Standard VGA mode
1 Color Expansion Mode
A monochrome bitmap is expanded to color.
For each bit of of data written from the processor
a zero bit causes the background color (3C4h index FBh)
to be written in the corresponding pixel, and a 1 bit
causes the foreground color (3C4h index FAh) to be written.
2 Dithered foreground. The data from the processor is
replaced by data from four Foreground Latches (3C4h index
ECh to EFh). The normal VGA Read Latches function as normal.
3 Invalid
4-7 Unused
3C4h index FFh (R/W): 16 bit Interface Control
bit 0 16 bit memory if set
1 16 bit I/O if set
2 Fast Write Enabled if set
3 16 bit ROM access if set
4 Enable bank selection
5-6 Cursor Pattern Page Select
7 (Read only) Card in 8 or 16 bit slot
3d4h index 1Fh (R): Identification register
bit 0-7 Returns bit 0-7 of the Start Address High Register
(3d4h index 0Ch)