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8514a.txt
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1993-01-22
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28KB
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659 lines
IBM 8514/A
8514/A clones:
ATI 38800-5 (MACH 8), 68800 (MACH 32)
Chips&Tech 82c480
Paradise ??
0102h (R/W): Setup Control Register
bit 0 If set the adapter is enabled, if clear the card is
invisible to the system.
1-7 Reserved(0)
02E8h W(R): Display Status Register
bit 0 SENSE is the result of a wired-OR of 3 comparators, one
for each of the RGB video signal.
By programming the RAMDAC for various values
and patterns and then reading the SENSE, the monitor type
(color, monochrome or none) can be determined.
1 VBLANK. Vertical Blank State
If Vertical Blank is active this bit is set.
2 HORTOG. Horizontal Toggle
This bit toggles every time a HSYNC pulse starts
3-15 Reserved(0)
02E8h W(W): Horizontal Total Register (H_TOTAL)
bits 0-8 Horizontal Total defines the total horizontal scan line width
including the display, blank and sync times.
All horizontal timings are in "double nuggets"
(8 or 10 pixels depending on the state of MEM_CNTL[0]).
The actual value is one latger than this register.
9-15 Reserved(0)
Note: this register is written at 02E8 and read at 26E8h.
02EAh (R/W): DAC Mask Register (DAC_MASK)
bits 0-7 DAC mask. This value is anded to the pixel data before going
to the DAC. Set to 0FFh for normal operation.
Note: In VGA passthrough mode writes to the VGA palette address 03C6h
will go to this address to allow the 8514/A to mirror palette changes.
02EBh (R/W): DAC Read Index Register (DAC_R_INDEX)
bits 0-7 DAC Read Index. Indicates which of the 256 palette entries
will be read by the current sequence of I/O read operations
to the DAC_DATA (02EDh) register.
Note: In VGA passthrough mode writes to the VGA palette address 03C7h
will go to this address to allow the 8514/A to mirror palette changes.
02ECh (R/W): DAC Write Index Register (DAC_W_INDEX)
bits 0-7 DAC Write Index. Indicates which of the 256 palette entries
will be written by the current sequence of I/O write operations
to the DAC_DATA (02EDh) register.
Note: In VGA passthrough mode writes to the VGA palette address 03C8h
will go to this address to allow the 8514/A to mirror palette changes.
02EDh (R/W): DAC DATA Register (DAC_DATA)
bits 0-7 DAC Data.
Note: In VGA passthrough mode writes to the VGA palette address 03C9h
will go to this address to allow the 8514/A to mirror palette changes.
06E8h W(W): Horizontal Displayed Register (H_DISP)
bits 0-7 Number of "double nuggets"-1 displayed in a scan line.
8-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
0AE8h W(W): Horizontal Sync Start Register (H_Sync_STRT)
bits 0-7 Hsync starts at (H_SYNC_STRT +1) double nugget periods.
8-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
0EE8h W(W): Horizontal Sync Width Register (H_SYNC_WID)
bits 0-4 Width of the Horizontal Sync pulse in "double nuggets".
5 Horizontal Sync Polarity (HSYNCPOL).
If set the Horizontal Sync Pulse is Negative, else Positive.
6-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
12E8h W(W): Vertical Total Register (V_TOTAL)
bits 0-2 Vertical Total Adjust (VTADJ).
3-11 Vertical Total Base (VTB).
The Vertical Total is calculated as:
Vertical Total = (Scan Modolus * VTB)+VTADJ+1
Where the Scan Modulus is found from the DBLSCAN and
MEMCFG bits of the DISP_CNTL register (22E8h).
DBLSCAN: MEMCFG: Scan Modulus:
0 0 0 2
0 0 1 4
0 1 0 6
0 1 1 8
1 0 0 4
1 0 1 8
1 1 0 12
1 1 1 16
12-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
16E8h W(W): Vertical Displayed Register (V_DISP)
bits 0-2 Vertical Displayed Adjust (VDADJ)
3-11 Vertical Displayed Base (VDB)
The Vertical Displayed is calculated as:
Vertical Displayed = (Scan Modolus * VDB)+VDADJ+1
Where the Scan Modulus is the same as for
Vertical Total in 12E8h.
12-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
1AE8h W(W): Vertical Sync Start Register (V_SYNC_STRT)
bits 0-2 Vertical Sync Start Adjust (VSADJ)
3-11 Vertical Sync Start Base (VSB)
The Vertical Sync Start is calculated as:
Vertical Sync Start = (Scan Modolus * VSB)+VSADJ+1
Where the Scan Modulus is the same as for
Vertical Total in 12E8h.
12-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
1EE8h W(W): Vertical Sync Width Register (V_SYNC_WID)
bits 0-4 Number of scanlines in the Vertical Sync pulse.
5 Vertical Sync Polarity (VSYNCPOL).
If set the Vertical Sync pulse is Negative, else Positive.
6-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
22E8h W(W): Display Control Register (DISP_CNTL)
bit 0 Odd Bank Enable (ODDBNKENAB).
If set use Horizontally Interleaved banks.
(Normal 8514/A mode).
1-2 Memory Configuration (MEMCFG).
0 NCLK (PS8 Mode)
1 NCLK/2 (Normal 8514/A Mode)
2 NCLK/3
3 NCLK/4
3 (Double Scan) DBLSCAN. If set doublescan is enabled.
4 INTERLACE. Interlace if set.
5-6 Display Enable (DISPEN)
0 = No effect
1 = Enable Hsync, Vsync, Blank, data transfer cycles
and refresh cycles.
2,3 = Disable Hsync, Vsync, Blank, data transfer cycles
and refresh cycles.
7-15 Reserved(0)
Note: In the 8514/A this register is Writeonly,
In the Chips&Tech 82c480 it is Read/Write.
26E8h W(R): Horizontal Total Register (H_TOTAL)
Note: this register is written at 02E8 and read at 26E8h.
2EE8h W(R): Subsystem Control Register (SUBSYS_CNTL)
Note: In the original IBM 8514/A this register is Write only.
In the CT82c480 it is written to 48E8h and read from 2EE8h.
42E8h W(R): Subsystem Status Register (SUBSYS_STAT)
bit 0-3 Interrupt requests. THese bits show the state of internal interrupt
requests. An interrupt will only occur if the corresponding bit(s) in
SUBSYS_CNTL is set. Interrupts can only be reset by writing a 1 to the
corresponding Interrupt Clear bit in SUBSYS_CNTL.
Bit 0: VBLNKFLG
1: PICKFLAG
2: INVALIDIO
3: GPIDLE
4-6 MONITORID.
1: IBM 8507 (1024x768) Monochrome
2: IBM 8514 (1024x768) Color
5: IBM 8503 (640x480) Monochrome
6: IBM 8512/13 (640x480) Color
7 8PLANE.
(CT82c480) This bit is latched on reset from pin P4D7.
8-11 CHIP_REV. Chip revision number.
12-15 (CT 82c480) CHIP_ID. 0=CT 82c480.
42E8h W(W): Subsystem Control Register (SUBSYS_CNTL)
bit 0-3 Interrupt Reset. Write 1 to a bit to reset the interrupt.
Bit 0 RVBLNKFLG Write 1 to reset Vertical Blank interrupt.
1 RPICKFLAG Write 1 to reset PICK interrupt.
2 RINVALIDIO Write 1 to reset Queue Overflow/Data
Underflow interrupt.
3 RGPIDLE Write 1 to reset GPIDLE interrupt.
4-7 Reserved(0)
8 IBLNKFLG. If set Vertical Blank Interrupts are enabled.
9 IPICKFLAG. If set PICK Interrupts are enabled.
10 IINVALIDIO. If set Queue Overflow/Data Underflow Interrupts are enabled.
11 IGPIDLE. If set Graphics Engine Idle Interrupts are enabled.
12-13 CHPTEST. Used for chip testing.
14-15 Graphics Processor Control (GPCTRL).
Note: In the original IBM 8514/A this register is Write only.
In the CT82c480 it is written to 48E8h and read from 2EE8h.
46E8h W(W): ROM Page Select Register