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File List  |  1978-03-06  |  8.7 KB  |  222 lines
  1.                     ===== Parallax PIC16Cxx Assembler v1.6 =====
  2.  
  3.  
  4.      1
  5.      2
  6.      3    0000-                                  DEVICE   PIC16C84,HS_OSC,WDT_OFF,PROTECT_OFF
  7.      4
  8.      5
  9.      6
  10.      7                                  ;this is a test source for PicSim (device=16C84)
  11.      8                                  ;the commands are from Microchip, the assembler from parallax
  12.      9                                  ;Copyright 04.02.97 Dirk Düsterberg
  13.     10
  14.     11
  15.     12
  16.     13
  17.     14
  18.     15    0000- 070C                    START    ADDWF    0Ch,0    ; C,DC,Z    add w and fileregister to w
  19.     16    0001- 078C                        ADDWF    0Ch,1    ; C,DC,Z    add w and fileregister to fileregister
  20.     17
  21.     18
  22.     19    0002- 3973                        ANDLW    115    ; Z         literal and w to w
  23.     20
  24.     21                                      
  25.     22    0003- 050C                        ANDWF    0Ch,0    ; Z        fileregister and w to w
  26.     23    0004- 058C                        ANDWF    0Ch,1    ; Z        fileregister and w to fileregister
  27.     24
  28.     25
  29.     26    0005- 138C                        BCF    0Ch,7    ;        clear bit from fileregister
  30.     27    0006- 178C                        BSF    0Ch,7    ;        set bit from fileregister
  31.     28
  32.     29
  33.     30    0007- 1A0C                        BTFSC    0Ch,4    ;        skip next command if bit 0
  34.     31    0008- 1E8C                        BTFSS    0Ch,5    ;        skip next command if bit 1
  35.     32
  36.     33
  37.     34    0009- 202E                        CALL    LABEL    ;        call subroutine
  38.     35
  39.     36
  40.     37    000A- 018C                        CLRF    0Ch    ; Z        clear fileregister
  41.     38    000B- 0100                        CLRW        ; Z        clear w
  42.     39    000C- 0064                        CLRWDT        ; TO,PD        clear watchdogtimer
  43.     40
  44.     41                                      
  45.     42    000D- 090C                        COMF    0Ch,0    ; Z        complement from fileregister to w
  46.     43    000E- 098C                        COMF    0Ch,1    ; Z        complement from fileregister to fileregister
  47.     44
  48.     45
  49.     46    000F- 030C                        DECF    0Ch,0    ; Z        count fileregister down to w
  50.     47    0010- 038C                        DECF    0Ch,1    ; Z        count fileregister down to fileregister
  51.     48
  52.     49
  53.     50    0011- 0B0C                        DECFSZ    0Ch,0    ;        count fileregister down to w and springe falls 0
  54.     51    0012- 0B8C                        DECFSZ    0Ch,1    ;        count fileregister down to fileregister and springe falls 0
  55.     52
  56.     53
  57.     54    0013- 0A0C                        INCF    0Ch,0    ; Z        count fileregister up to w
  58.     55    0014- 0A8C                        INCF    0Ch,1    ; Z        count fileregister up to fileregister
  59.     56
  60.     57                                      
  61.     58    0015- 0F0C                        INCFSZ    0Ch,0    ;        count fileregister up to w and springe falls 0
  62.     59    0016- 0F8C                        INCFSZ    0Ch,1    ;        count fileregister up to fileregister and springe falls 0
  63.     60
  64.     61                                      
  65.     62    0017- 3873                        IORLW    115    ; Z        write literal or w in w
  66.     63
  67.     64
  68.     65    0018- 040C                        IORWF    0Ch,0    ; Z        write fileregister or w to w
  69.     66    0019- 048C                        IORWF    0Ch,1    ; Z        write fileregister or w to fileregister
  70.     67
  71.     68
  72.     69    001A- 080C                        MOVF    0Ch,0    ; Z        write fileregister to w
  73.     70    001B- 088C                        MOVF    0Ch,1    ; Z        write fileregister to fileregister
  74.     71
  75.     72                                      
  76.     73    001C- 3073                        MOVLW    115    ;        write literal to w
  77.     74
  78.     75
  79.     76    001D- 008C                        MOVWF    0Ch    ;         write w to fileregister
  80.     77
  81.     78
  82.     79    001E- 0000                        NOP        ;         no operation
  83.     80
  84.     81
  85.     82    001F- 0062                        OPTION        ;        write w in optionregister
  86.     83
  87.     84
  88.     85    0020- 0D0C                        RLF    0Ch,0    ; C        rotate fileregister left to w
  89.     86    0021- 0D8C                        RLF    0Ch,1    ; C        rotate fileregister left to fileregister
  90.     87
  91.     88                                      
  92.     89    0022- 0C0C                        RRF    0Ch,0    ; C        rotate fileregister right to w
  93.     90    0023- 0C8C                        RRF    0Ch,1    ; C        rotate fileregister right to fileregister
  94.     91
  95.     92
  96.     93    0024- 0063                        SLEEP        ; TO,PD     do the sleep mode
  97.     94
  98.     95
  99.     96    0025- 020C                        SUBWF    0Ch,0    ; C,DC,Z    substract w from fileregister to w
  100.     97    0026- 028C                        SUBWF    0Ch,1    ; C,DC,Z    substract w from fileregister to fileregister
  101.     98
  102.     99
  103.    100    0027- 0E0C                        SWAPF    0Ch,0    ;        swap nibbles from fileregister to w
  104.    101    0028- 0E8C                        SWAPF    0Ch,1    ;        swap nibbles from fileregister to fileregister
  105.    102
  106.    103
  107.    104    0029- 0065                        TRIS    ra    ;        write w in tristate Register from port b
  108.    105    002A- 0066                        TRIS    rb    ;        write w in tristate Register from port b
  109.    106
  110.    107
  111.    108                                  ;    XORLW    #15    ; Z        write literal exclusiv oder w to w
  112.    109
  113.    110                                      
  114.    111    002B- 060C                        XORWF    0Ch,0    ; Z        write w exclusiv oder fileregister to w
  115.    112    002C- 068C                        XORWF    0Ch,1    ; Z        write w exclusiv oder fileregister to fileregister
  116.    113
  117.    114                                      
  118.    115                                      
  119.    116    002D- 2800                        GOTO    START
  120.    117
  121.    118
  122.    119
  123.    120
  124.    121
  125.    122
  126.    123
  127.    124
  128.    125
  129.    126
  130.    127    002E- 3005 0085               LABEL    MOV    RA,#05h    ;          write literal to port
  131.    128    0030- 30AA 0086                   MOV    RB,#0aah         
  132.    129
  133.    130
  134.    131    0032- 3000 0065                   MOV    !RA,#0h    ;          write literal ins tristate register
  135.    132    0034- 302D 0066                   MOV    !RB,#45
  136.    133
  137.    134                                      
  138.    135    0036- 0805                        MOV    w,RA    ;          write port to w
  139.    136    0037- 0806                        MOV    w,RB
  140.    137
  141.    138
  142.    139
  143.    140
  144.    141    0038- 1405                        SETB    RA.0    ;          set bit 0 from Port A
  145.    142    0039- 1005                        clrb    RA.0    ;          clear bit 0 from Port A
  146.    143
  147.    144
  148.    145    003A- 3002 0685                   XOR    RA,#00000010b    ;  toggle (exclusive or) bit 1 from port A
  149.    146
  150.    147    003C- 1885                        BTFSC    RA.1    ;          skip next command if not bit
  151.    148
  152.    149    003D- 347F                        RETW    127     ;       jump back from subroutine and write literal to w
  153.    150    003E- 343F                        RETW    63     ;       jump back from subroutine and write literal to w
  154.    151                                           
  155.    152                                      
  156.    153
  157.    154
  158.    155
  159.    156
  160.    157                                  ;indirect file addressing (clear fileregister betwen 0Ch and 1fh)
  161.    158
  162.    159
  163.    160    003F- 300C 0084                   mov    FSR,#0Ch    ;file adress pointer to 10h
  164.    161                                      
  165.    162
  166.    163    0041- 0180                    milka    clr    INDIRECT    ;clear the indirect address
  167.    164    0042- 0A84                        inc    FSR        ;next register
  168.    165    0043- 1E84                        sb    FSR.5        ;all done ? (FSR >= 20h ?)
  169.    166    0044- 2841                        jmp    milka        ;do it
  170.    167                                      
  171.    168
  172.    169
  173.    170
  174.    171
  175.    172
  176.    173
  177.    174
  178.    175                                  ;Data EEProm access
  179.    176
  180.    177    0045- 080E 0089               witedat mov     EEADR,0eh    ;0e is my address
  181.    178                                          
  182.    179    0047- 080F 0088                       mov     EEDATA,0fh    ;0f is my data
  183.    180                                          
  184.    181
  185.    182    0049- 1683                            setb    STATUS.5    ;select PAGE1
  186.    183
  187.    184    004A- 1508                            setb    EECON1.2    ;set EEPROM write enable
  188.    185
  189.    186    004B- 3055 0089                   mov     EECON2,#55h
  190.    187    004D- 30AA 0089                   mov     EECON2,#0AAh
  191.    188                                          
  192.    189    004F- 1488                            setb    EECON1.1    ;init a write cycle
  193.    190
  194.    191
  195.    192
  196.    193
  197.    194
  198.    195    0050- 1E08                    wait    sb    EECON1.4    ;wait for write to finish
  199.    196    0051- 2850                            jmp    wait
  200.    197    0052- 0188                        clr    EECON1        ;EEPROM write disable & int accept
  201.    198
  202.    199    0053- 1283                            clrb    STATUS.5    ;select PAGE0
  203.    200                                          
  204.    201
  205.    202
  206.    203
  207.    204
  208.    205    0054- 1283                    readdat clrb    STATUS.5
  209.    206    0055- 0089                        mov    EEADR,W
  210.    207    0056- 1683                            setb    STATUS.5            ;select PAGE1
  211.    208
  212.    209    0057- 1408                            setb    EECON1.0            ;EEPROM read
  213.    210    0058- 1283                            clrb    STATUS.5            ;select PAGE0
  214.    211                                   
  215.    212    0059- 0808                            mov    w,EEDATA
  216.    213                                          
  217.    214    005A- 2800                        GOTO    START
  218.    215
  219.  
  220.  
  221.                             ===== Errors: 0 =====
  222.