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Text File | 1997-03-18 | 25KB | 504 lines

===================================== 6x86opt Cyrix/IBM/ST 6x86 processor optimizer ===================================== v0.77 (c) Mikael Johansson 1997 Unregistered ShareWare version! *WHAT THIS PROGRAM DOES* ------------------------ This program optimizes the Cyrix/IBM/ST 6x86 (M1) processor. *HOW IT DOES IT* ---------------- By setting the appropriate configuration bits on the CPU to their appropriate values. Details on which bits are set are (very surprisingly) found in the section *WHICH BITS ARE SET* It can also set up a special address region configuration for the Linear Frame Buffer. When enabling Write Gathering for the LFB, writes to it get sped up from 2 to 8 times. *USING THE PROGRAM* ------------------- 6x86opt can be invoked without any parameters for default optimization. You can also define fourteen different command line parameters: -config (-c) ; Execute the configuration file 6x86opt.cfg instead of then default optimization. -x ; Set bit 1 in DBR0. See the topic *REDUCED PERFORMANCE* -FLOP (-F) ; Fast Loop. Will unset the SLOP bit (CCR5:1). -linbuf (-l) ; Searches for a Linear Frame Buffer and tries to define an ARR/RCR for it allowing Write Gathering. -manbuf (-m) ; Same as above, but the LFB address and size must be given like -manbuf:ADDR,SIZE. ADDR and SIZE in MB. -killbuf(-k) ; Clears the ARR and RCR that previously has been set up for the LFB. You can either let 6x86opt find the LFB itself, or tell it the address or ARR nr. manually: -killbuf or -killbuf:ADDR or -killbuf:ARR -justbuf(-j) ; When defined, only LFB related parameters are checked, and no optimization is done. Doesn't do anything on itself. -ARR0+1 (-A) ; Set up ARR/RCR 0 and 1 to recommended values, i.e video buffer and device/system ROM space. -nowb (-n) ; Do not enable caching and WriteBack. Note that this parameter doesn't disable these, just leaves them be. -defbtb (-d) ; Do not change the BTB configuration. -susphlt(-s) ; Set the SUSP_HLT bit (CCR2:3). -verbose(-v) ; Missä mennään. Shows what the program does during execution. -peek (-p) ; Does not change anything, just shows the bit states, and the LFB and Video Memory size. -force (-f) ; Forces execution of the program even if 6x86opt does not detect a 6x86 CPU. Can cause undefined behaviour. The parameters in parentheses are abbreviations for the parameters. If an unknown parameter is defined on the command line, 6x86opt will show some info about itself. NOTE! The processor is restored to default state on system reset. So it is probably a good idea to invoke 6x86opt from your AUTOEXEC.BAT file, or your Startup Folder. *THE LINEAR FRAME BUFFER AND THE -linbuf AND -manbuf PARAMETERS* ---------------------------------------------------------------- As the Linear Frame Buffer defined by the VESA 2.0 standard is located outside the area of physical memory, the 6x86 has all memory access to this area defaulted at poorest performance. To increase the performance of the LFB, an ARR and a corresponding RCR can be set up for it, allowing Write Gathering. When WG is enabled, multiple writes to sequential addresses are gathered and issued in one write cycle. The buffer is 64 bits wide, so for example 4 word writes are written in one cycle instead of four. Of course only applications that use the LFB, like Quake, get a performance increase from this. When the -linbuf parameter is defined, 6x86opt will automatically search for the LFB and the size of your Video Card memory, which also is the size of the LFB. It will then search the ARR:s to see if an ARR already is set at this address. If not, it will try to find an empty (zero-size) ARR. When it has decided what ARR to program it will do this. The RCR will be set with the bits WG and RCD (Region Cache Disable). If 6x86opt has problems setting up an ARR, a warning message will be shown. The optimization process will continue, but the exit code will be 2. If 6x86opt fails to detect your LFB or Video Memory correctly, or if you for example want to define a region before loading a VESA 2.0 driver, you can manually define it with the parameter -manbuf. The format is: -manbuf:ADDR,SIZE where ADDR and SIZE must be given in megabytes. If your Video Card has less than 1 MB of memory, you still must give this as a minimum size. This should not cause any problems. If your LFB is located at 3584 MB and you have a video card with 2 MB of RAM, the -manbuf declaration would be: -manbuf:3584,2 (or -m:3584,2). If you get a warning message complaining that the Address is not a multiple of the Block Size, you should reconfigure the LFB Address so that it is. This is a requirement of the 6x86 CPU. If -linbuf fails in detecting the environment correctly, tell me about it! NOTE 1: If you have several -manbuf parameters on the command line, only the _last_ will be processed. NOTE 2: -linbuf is executed before -manbuf, so if -manbuf defines the same address, but different size, the -manbuf definition will prevail. NOTE 3: Only so much checking of the ADDR and SIZE definitions of -manbuf is done so that 6x86opt will not (should not:) crash. Be careful in defining the right values for these. *REMOVING THE LINEAR FRAME BUFFER SPEED UP WITH THE -killbuf PARAMETER* ----------------------------------------------------------------------- You might want to remove the LFB speed up settings, if you for example remove your VESA 2.0 driver, or are going to use Windows 3 (Sometimes problems occur with this combination!). -killbuf is here to help you. Invoke 6x86opt with the -killbuf parameter to reset the ARR/RCR that was setup for LFB space. You have 2 main alternatives: 1) Use the automatic -killbuf. To do this, you must still have the LFB enabled. 6x86opt will detect it, and clear the ARR/RCR. Just write -killbuf (or -k) on the command line. 2) Use the manual -killbuf. If you already have disabled the LFB, or if 6x86opt just won't detect it correctly, you can either specify the Starting Address of the LFB, or what ARR/RCR was setup for the LFB. Use the parameter format -killbuf:ADDR (ADDR in MB) or then -killbuf:ARR. 6x86opt will interpret a value after the ':' as the ARR if the value is below 7, otherwise as the Starting Address. If some problems are encountered, you will see a WARNING! message materializing on your screen. *THE -ARR0+1 PARAMETER* ----------------------- When the parameter -ARR0+1 (or -A) is defined on the command line, 6x86opt will set up these registers to the recommended values, so that ARR/RCR0 defines the VGA video buffer, and ARR/RCR1 defines device/system ROM space. The reason why this is not set by default, is that some BIOS might already have set up these regions, but at other addresses, and now uses ARR0 and ARR1 for other purposes. I recommend that you try this switch and see if you can detect a speed increase. For exact definition on how these are set, see 6X86SET.TXT. *USING THE 6X86OPT.CFG CONFIGURATION FILE WITH -config* ------------------------------------------------------- You can instead of the default optimization let 6x86opt execute a config file generated by 6x86set. Just define the -config (or -c) parameter at the command line. The config file holds information on how to set all the bits on the system, that 6x86set can handle. Note that the config file _must_ be named 6x86opt.cfg, and be in the same directory as 6x86opt. (Actually the name of the config file must be *.cfg, where * is the name of 6x86opt). If 6x86opt can not find the configuration file, or detects that the file is damaged, it will show a Warning! message. A damaged file will not be processed to any extent. For more info on creating a config file, use 6x86set:s on-line help. Also see the file 6X86SET.TXT *REDUCED PERFORMANCE AND THE -x PARAMETER* ------------------------------------------ If running 6x86opt gives a decrease in performance you should give the -x command line parameter to 6x86opt when executing it. When defined, bit 1 of DBR0 will be set, and a performance increase should result. Some systems need to have this parameter defined. Also other systems can benefit from setting this bit. But as the documentation for the bit (along with other whole registers) is only available to specific OEM partners of Cyrix and IBM, I do not (yet) know exactly what it does. Therefore it is not included in the default optimization process. Feedback of experiences with this is very welcome! *WINBENCH PROCESSOR SCORES* --------------------------- The processor suites in WinBench gives different results every test run, and the second run is usually poorer than the first. To get reliable results, run these (and other) testsuites right after booting the system with either unoptimized or optimized configuration. You will find that the processor tests are not affected noticeably, as these tests apparently has no use of the optimized settings. Graphics scores should increase. So, the performance increase is dependent on the application. The performance increase is also dependent on how the BIOS sets the bits on boot. If the BIOS "sets'em all" itself there can of course be no improvement. I have not heard of any such systems. BIOS:es that does not support the 6x86 very well will have the highest improvement. In no case should 6x86 decrease overall performance (see previous topic). And to my knowledge there is no way that the speed up of the LFB would have opposite effect. So if you for some reason only want to use this, you can define the -justbuf parameter on the command line. *SHAREWARE* ----------- As from v0.76, the 6x86opt package is ShareWare. This is mainly because I thought I would see if I can get enough registrees so that I can go and support Microsoft by buing some NT development tools. By now I have also improved 6x86opt way beyond my original need to have two bits on my CPU set. So if you like the package (or some parts of it :-), please register! For detailed information on this, see the file REGISTER.NOW The files included in this package are: 6X86OPT.EXE 34000 bytes 6x86opt, the optimizer 6X86OPT.TXT 24917 bytes This textfile 6X86SET.EXE 87840 bytes 6x86set, the setup utility 6X86SET.TXT 3995 bytes Info on 6x86set CPUIDEN.EXE 7024 bytes CPUID instruction enabler/disabler/toggler REGISTER.NOW 3512 bytes Information on registering the software *CPUIDEN.EXE* ------------- This program toggles/sets/unsets the state of the CPUIDEN bit in CCR4:7. When set, the CPUID instruction can be executed. Programs that understand this can get additional information about the processor through this instruction. Some programs misinterpret this information, and it might be better if these programs are left without the additional info. Setting the bit causes for example Win95 (before OSR2 == Win95b) to identify the CPU as a Pentium (which is not necessarily a bad thing). For this CPUIDEN.EXE should be run from the AUTOEXEC.BAT file. You could encounter problems by enabling the CPUID instruction, as some badly written software could get tempted to execute some Pentium specific instructions or functions if they misidentify the 6x86. When invoked without parameters CPUIDEN toggles the state of the bit. The following command line parameters are recognized: -set (-s) ; Sets the bit (enables CPUID instruction) -unset (-u) ; Unsets the bit -force (-f) ; Forces execution even when CPUIDEN does not detect a 6x86 CPU. *CONTACTING THE AUTHOR* ----------------------- If you encounter any bugs in the program, have some suggestions, or especially if you know of any other optimization tricks for the 6x86, I would like to receive mail from you. All info about the undocumented registers is greatly appreciated (performance affecting or not)! e-mail: mpjohans@kumpu.helsinki.fi or: Mikael.Johansson@helsinki.fi Postman Pat employing mail: Mikael Johansson Kitarakuja 3C 220 00420 Helsinki FINLAND *WHICH BITS ARE SET* -------------------- The following bits are set: bit | reg:bit | why ------------------------------------------------------------------------ NO_LOCK | CCR1:4 | "With NO_LOCK set, previously noncacheable locked | | cycles are executed as unlocked cycles and, | | therefore, may be cached. This results in higher | | CPU performance." | | The reason the bit is not set as default is because | | software that requires locked cycles might exist. I | | have never had any problems with this. ------------------------------------------------------------------------ WL | RCR7:2 | This one is related to the one above. It enables | | weak locking for the memory region specified by | | ARR7, i.e. all memory. I am not sure if this is | | necessary, as my benchmark results vary. It does no | | harm however. ------------------------------------------------------------------------ DTE_EN | CCR4:4 | "DTE_EN allows Directory Table Entries (DTE) to be | | cached on the 6x86 microprocessor. This provides a | | performance improvement for some applications that | | access and modify the page table frequently." ------------------------------------------------------------------------ WT_ALLOC| CCR5:0 | "Write Allocate (WT_ALLOC) allows L1 cache write | | misses to cause a cache line allocation. This | | feature improves the L1 cache hit rate resulting | | in higher performance especially for Windows | | applications." ------------------------------------------------------------------------ IORT2-0 | CCR4:2-0| I/O Recovery Time. Defines the minimum time between | | I/O port accesses. Set to 111 == no delay. ------------------------------------------------------------------------ SUSP_HLT| CCR2:3 | If this bit is set, the HLT instruction causes the | | CPU to enter low power suspend mode. This works OK | | at least running Linux, doesn't affect DOS. Maybe | | also OS/2 can make use of it. Doesn't affect | | performance. Only set when -susphlt is defined! ------------------------------------------------------------------------ All quotations above are taken from the "IBM 6x86 Microprocessor BIOS Writer's Guide", Document #40205 The following bits are unset: bit | reg:bit | why ------------------------------------------------------------------------ CD | CR0:30 | When 'Cache Disable' is set, the cache is disabled(!) | | Naturally the cache should be enabled. I do not believe | | that this bit is ever set, but you never know. ------------------------------------------------------------------------ NW | CR0:29 | When 'No Write Back' is set, the L1 cache operates in | | Write Through mode. By unsetting the bit the cache | | strategy will be set to Write Back. ------------------------------------------------------------------------ The above bits are not affected if the -nowb parameter is defined bit | reg:bit | why ------------------------------------------------------------------------ SLOP | CCR5:1 | Unset to disable the slowdown of the LOOP instruction. | | Only unset if the -FLOP parameter is defined. ------------------------------------------------------------------------ The following bits are also modified: bit(s) | reg:bit | what and why ------------------------------------------------------------------------ MAPEN | CCR3:7-4| Set to 0001 during execution to get access to all | | register indexes. Set to 0000 after optimization. ------------------------------------------------------------------------ LOCK_NW| CCR2:2 | Unset so that the NW bit in CR0 can be modified. | | After optimization it's value is restored. ------------------------------------------------------------------------ ARREN | CCR5:5 | Unset during execution so that the RCR7 can be safely | | programmed. Restored after optimization. ------------------------------------------------------------------------ 6x86opt enables the Branch Target Buffer (BTB), configures it to store target addresses for both near and far Change-Of-Flow instructions (COFs), and enables it's return stack. See below: The following undocumented bits are modified : bit(s) | reg:bit | what and comment ------------------------------------------------------------------------ unknown | DBR0:1 | Will be set if the -x parameter is defined. ------------------------------------------------------------------------ D_FWDBYP| DBR0:5 | Data Forwarding/Bypassing enable ------------------------------------------------------------------------ BTBTR_EN| DBR0:6 | Set to 1 to get access to Test Registers below TR3. | | Unset after optimization. ------------------------------------------------------------------------ unknown | TR2i5:4 | If set, reduces performance -> will be unset. BTB_DIS?| TR2i5:3 | BTB Disable(?) Will be unset. RSTK_DIS| TR2i5:2 | BTB Return Stack Disable. Will be unset FARH_DIS| TR2i5:1 | BTB Far Hits Disable. Will be unset. BTB_DIS | TR2i5:0 | BTB Disable(!) Will be unset. ------------------------------------------------------------------------ If the -defbtb parameter is defined, no BTB related registers are affected. Only bits that I know exactly what they do are explained. When the -linbuf or -manbuf parameters are defined, 6x86opt tries to set up an ARR and RCR for the Linear Frame Buffer, allowing Write Gathering for this memory area. See the topic *LINEAR FRAME BUFFER* *FURTHER OPTIMIZATION* ---------------------- It is possible that your system could be sped up even more by toggling the right bits to the right states. Mess around with your 6x86 with 6x86set. But remember that your system might crash by setting the "wrong" bits! You might also want to check some bits that when in the "wrong" state decreases performance of your CPU, but that 6x86opt doesn't correct. One such bit is SLOP (CCR5:1), which should be 0, but could have been set by your system for some reason. 6x86opt doesn't unset it as default, as there could be a very good reason for it to be set. You must define the -FLOP parameter for it to be unset. See what happens. Also, why not check the ARRs and RCRs with 6x86set. Another thing that an interested person might want to check, is that if disabling SMM would affect performance (if it does, contact me!). And then, just go through the registers with 6x86set, and search for bits with comments like "reduces performance if set" and check them. For more information, see the file 6X86SET.TXT! And of course, I'm always interested in a setup that outperforms the default one! *EXIT CODES* ------------ The following exit codes can be generated: 0 : 6x86opt (at least thinks it) encountered no problems 1 : 6x86opt was invoked with some unknown (or misdefined) parameter 2 : 6x86opt issued a warning of some kind 3 : 6x86opt detected a load error while processing the config file 4 : 6x86opt did not detect a 6x86 CPU Any other codes _should_ never be generated. *VERSION HISTORY* ----------------- v0.64 : First released version. (5.11.1996) v0.64b: Some comments added to the document. (22.11.96) v0.72 : Command line parameters added. The program now unsets the CD and NW bits in CR0. The document was clarified. (3.12.1996) v0.73 : Added the -x and -verbose parameters. Some undocumented bits are now modified. Better code. (18.12.1996) v0.74 : Added the -linbuf, -manbuf and -peek parameters. (15.1.1997) v0.76 : Added the 6x86set utility. Added the -config, -killbuf -justbuf and -susphlt parameters. Now can set up ARR0 and ARR1 properly with the -ARR0+1 param. Does not set SUSP_HLT as a default anymore. Use -susphlt. Now sets IORT and TR2i5:4 OK. The exit codes got revised. Changed the distribution format from PD to SW. (15.3.1997) v0.77 : Corrected a bug that set SLOP instead of IORT. (I knew it was a bad idea to have 13 different parameters...) Added the -FLOP parameter. Some typos corrected. *WHY THIS PROGRAM EXISTS* ------------------------- Because I could find no good optimizer for the processor anywhere. The only one I found was IBM:s M1OPT. This program however changes every bit in the CCR:s and everywhere else according to some model machine of their own. For example all Power Management features are disabled even if they are set before. This program also does not set NO_LOCK. *TO BE DONE* ------------ Windows NT support: On hold for now, as the NT development tools were way too expensive for my current budget :-( However, Olivier Gilloire has written a nice tool for all NT owners, 6x86cfg :-) You can get it for example from Bryan Davis very good Cyrix page at www.ionet.net/~rbdavis. Contact Olivier at: ftiw186420@wanadoo.fr for more information! Anything else that sounds good. *SPECIAL THANKS* ---------------- Rich "Doc" Colley. For testing that helped deliver the -x parameter. Barry Shilliday for finding the SLOP bug so soon. All that replied to my IDDump project. Everyone who has sent me mail that helped improve 6x86opt. *THE ULTIMATE HEAVY METAL BAND* ------------------------------- Mercyful Fate *THINGS* -------- You use all files in this package entirely at your own risk. Cyrix and IBM and everyone else have copyright on what they have.