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ST-Computer Leser 1998 October
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STC_CD_10_1998.iso
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ANWEND
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CLA_V2
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EXAMPLES
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EXAMPLES.TXT
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1998-09-26
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Here's a short description of the example schematics:
3IPAND.NET - Simple 3 input AND gate.
ALLGATES.NET - All the primitives supported by CLA.
BLOCKTEST.NET - Demonstration of block structuring.
CCTD.NET - The simple circuit shown in the manual.
DFLIP.NET - The same complex implementation of a DFLIP-FLOP.
DF_TEST.NET - The DFLIP element actually wired up.
FULLADDR - Two bit binary adder with carry-in.
MUL_TEST.NET - The 3bit parallel multiplier connected up ready for
testing.
MULLER-C.NET - Complex implementation of the Muller-C element
used in high speed CMOS design to create self
timed circuits.
PAR_MULT.NET - 3-bit parallel binary multiplier.
PRIM_DF.NET - Example using the D-Register primitive instead of
the complex implementation.
SER_MUL.NET - 3-bit bit-serial binary multiplier using a primitive
systolic array.
SIGANAL.NET - Signature analysis register as used for built in
self-test applications.
SIM_RES.NET - Demonstration of how simulation resolution can affect
results.
SM_CG.NET - Another 3 bit serial multiplies, this time with a few
changes by me from the theoretical version - this may
not work properly, I'm not to hot on systolic array
structures.