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Transactor
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Transactor_22_1988_Transactor_Publishing.d64
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xmit.mae
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2023-02-26
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101 lines
0020 ; copyright 1986 jack bedard
0030 .
0040 ; output assembled code to serial data port
0050 .
0060 ; there are 2 separate routines here:
0070 ; the 1st (code.swap) modifies mae to transmit assembled code
0080 ; to a 2nd c-64 via s.r. port.
0090 ; it is activated with this command from mae 'ru $8500'
0100 .
0110 ; the 2nd sends the address to store (low/high)
0120 ; in the other c64 and the byte to store there.
0130 .
0140 mae.table .de $51 ;store address is in this table
0150 mod.adr .de $5feb ;my patch goes here
0160 u2.tima.lo .de $dd04
0170 u2.tima.hi .de $dd05
0180 u2.out .de $dd0c ;serial data port
0190 u2.icr .de $dd0d ;interrupt control register
0200 u2.cra .de $dd0e ;timer a control register
0210 output .de %01000000 ;bit 6 in $dd0e
0220 shift.reg .de %00001000 ;bit 3 in $dd0d
0230 disabl.all .de %01111111 ;0 in 7 causes the 1's to disable those bits
0240 timer.a .de %00000001 ;bit 0 in $dd0e
0250 .
0260 baud .de $04 ;the baud rate prescaler
0270 .
0280 .os
0290 .ba $8500
0300 .ce
0310 .
0320 code.swap ;patch 'jsr sendtodsp' into mae
0330 ldx #2
0340 mod.loop
0350 lda mod.adr,x
0360 pha
0370 lda mae.code.mod,x
0380 sta mod.adr,x
0390 pla
0400 sta mae.code.mod,x
0410 dex
0420 bpl mod.loop
0430 rts
0440 .
0450 mae.code.mod ;patch to our output routine
0460 jsr send.to.sdp
0470 .
0480 send.to.sdp ;send byte from stack (under return addr)
0490 sty save.y ;to other 64.
0500 stx save.x
0510 pla
0520 sta ret.adr ;save return address from stack
0530 pla
0540 sta ret.adr+1
0550 .
0560 lda mae.table,x ;find address for byte to be sent
0570 sta data.out+2
0580 lda mae.table+1,x
0590 sta data.out+1
0600 pla
0610 sta data.out ;byte to send (after address)
0620 .
0630 lda #disabl.all ;set up interrupt control reg
0640 sta u2.icr
0650 .
0660 lda #baud ;set up timer
0670 sta u2.tima.lo
0680 lda #0
0690 sta u2.tima.hi
0700 .
0710 lda #output+timer.a ;set up timer control register
0720 sta u2.cra
0730 .
0740 ldx #2 ;send the three bytes starting at dataout
0750 sei ;no interrupts, please
0760 out.data
0770 lda data.out,x
0780 sta u2.out ;put the byte on the output port
0790 .
0800 still.sending
0810 lda u2.icr ;wait until it has been sent
0820 and #shift.reg
0830 beq still.sending
0840 dex ;send the next one
0850 bpl out.data
0860 cli ;all sent
0870 .
0880 lda ret.adr+1 ;put return address back on the stack
0890 pha
0900 lda ret.adr
0910 pha
0920 ldx save.x
0930 ldy save.y
0940 rts
0950 .
0960 save.x .ds 1
0970 save.y .ds 1
0980 ret.adr .ds 2
0990 data.out .ds 3
1000 .
1010 .en