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- <?xml version="1.0" encoding="UTF-8"?>
- <!DOCTYPE language SYSTEM "language.dtd">
- <language _name="VHDL" version="1.0" _section="Sources" mimetypes="text/x-vhdl">
-
- <line-comment _name = "Line Comment" style= "Comment">
- <start-regex>--</start-regex>
- </line-comment>
-
- <string _name = "String" style = "String" end-at-line-end = "TRUE">
- <start-regex>"</start-regex>
- <end-regex>"</end-regex>
- </string>
-
- <pattern-item _name = "Character Constant" style = "String">
- <regex>'.'</regex>
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-
- <keyword-list _name = "Keyword" style = "Keyword" case-sensitive="FALSE">
- <keyword>access</keyword>
- <keyword>after</keyword>
- <keyword>alias</keyword>
- <keyword>all</keyword>
- <keyword>architecture</keyword>
- <keyword>array</keyword>
- <keyword>assert</keyword>
- <keyword>attribute</keyword>
- <keyword>begin</keyword>
- <keyword>block</keyword>
- <keyword>body</keyword>
- <keyword>buffer</keyword>
- <keyword>bus</keyword>
- <keyword>case</keyword>
- <keyword>component</keyword>
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- <keyword>disconnect</keyword>
- <keyword>downto</keyword>
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- <keyword>elsif</keyword>
- <keyword>end</keyword>
- <keyword>entity</keyword>
- <keyword>exit</keyword>
- <keyword>file</keyword>
- <keyword>for</keyword>
- <keyword>function</keyword>
- <keyword>generate</keyword>
- <keyword>generic</keyword>
- <keyword>group</keyword>
- <keyword>guarded</keyword>
- <keyword>if</keyword>
- <keyword>impure</keyword>
- <keyword>in</keyword>
- <keyword>inertial</keyword>
- <keyword>inout</keyword>
- <keyword>is</keyword>
- <keyword>label</keyword>
- <keyword>library</keyword>
- <keyword>linkage</keyword>
- <keyword>literal</keyword>
- <keyword>loop</keyword>
- <keyword>map</keyword>
- <keyword>new</keyword>
- <keyword>next</keyword>
- <keyword>null</keyword>
- <keyword>of</keyword>
- <keyword>on</keyword>
- <keyword>open</keyword>
- <keyword>others</keyword>
- <keyword>out</keyword>
- <keyword>package</keyword>
- <keyword>port</keyword>
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- <keyword>record</keyword>
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- <keyword>report</keyword>
- <keyword>return</keyword>
- <keyword>select</keyword>
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- <keyword>to</keyword>
- <keyword>transport</keyword>
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- <keyword>until</keyword>
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- <keyword>sla</keyword>
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- <keyword>sra</keyword>
- <keyword>srl</keyword>
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- <keyword>rem</keyword>
- <keyword>abs</keyword>
- <keyword>not</keyword>
- </keyword-list>
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- <keyword-list _name = "Type" style = "Data Type" case-sensitive="FALSE">
- <keyword>bit</keyword>
- <keyword>bit_vector</keyword>
- <keyword>character</keyword>
- <keyword>boolean</keyword>
- <keyword>integer</keyword>
- <keyword>real</keyword>
- <keyword>time</keyword>
- <keyword>string</keyword>
- <keyword>severity_level</keyword>
- <keyword>positive</keyword>
- <keyword>natural</keyword>
- <keyword>signed</keyword>
- <keyword>unsigned</keyword>
- <keyword>line</keyword>
- <keyword>text</keyword>
- <keyword>std_logc</keyword>
- <keyword>std_logic_vector</keyword>
- <keyword>std_ulogic</keyword>
- <keyword>std_ulogic_vector</keyword>
- <keyword>qsim_state</keyword>
- <keyword>qsim_state_vector</keyword>
- <keyword>qsim_12state</keyword>
- <keyword>qsim_12state_vector</keyword>
- <keyword>qsim_strength</keyword>
- <keyword>mux_bit</keyword>
- <keyword>mux_vectory</keyword>
- <keyword>reg_bit</keyword>
- <keyword>reg_vector</keyword>
- <keyword>wor_bit</keyword>
- <keyword>wor_vector</keyword>
- </keyword-list>
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- <pattern-item _name = "Number" style = "Decimal">
- <regex>\b[0-9]+(\b|\.|\.[0-9]*\b)</regex>
- </pattern-item>
-
- <keyword-list _name = "True and False" style = "Specials" case-sensitive="FALSE">
- <keyword>true</keyword>
- <keyword>false</keyword>
- </keyword-list>
-
- </language>
-