Vectronix 2/VECTRONIX2.iso/FILES_10/DEVELOP.LZH/DSP/DSPDEBUG/REGDTA.HLP

Text File | 1992-10-15 | 32KB | 597 lines

{Address Registers} ({Rn}){êR0}{êR1}{êR2}{êR3}{êR4}{êR5}{êR6}{êR7}

    The eight 16-bit address registers, R0-R7, can contain addresses or
general-purpose data. The 16-bit address in a selected address register is
used in the calculation of the effective address ofan operand. When
supporting parallel X and Y data memory moves, the address registers must be
thought of as two separate files, R0-R3 and R4-R7. The contents of an Rn
may point directly to data or may be offset. In addition, {Rn} can be
pre-updated or post-updated according to the addressing mode selected. If an
{Rn} is updated, modifier registers, {
Mn}, are always used to specify the type
of update arithmetic. Offset registers, {Nn}, are used for the
update-by-offset addressing modes. The address register modification is
performed by one of the two modulo arithmetic units. Most addressing modes
modify the selected address register in a read-modify-write fashion; the
address register is read, its contents are modified by the associated modulo
arithmetic unit, and the register is written with the appropriate output of
the modulo arithmetic unit. Each address register is preset to $FFFF during
a processor reset.


{Offset Registers} ({Nn}){êN0}{êN1}{êN2}{êN3}{êN4}{êN5}{êN6}{êN7}

    The eight 16-bit offset registers, N0-N7, can contain offset values used
to increment/decrement address registers in address register update
calculations or can be used for 16-bit general-purpose storage. For example,
the contents of an offset register can be used to step through a table at
some rate (e.g., five locations per step for waveform generation), or the
contents can specify the offset into a table or the base of the table for
indexed addressing. Each address register, {
Rn}, has its own offset
register, {Nn}, associated with it. Each offset register is preset to $FFFF
during a processor reset.


{Modifier Registers} ({Mn}){êM0}{êM1}{êM2}{êM3}{êM4}{êM5}{êM6}{êM7}

    The eight 16-bit modifier registers, M0-M7, define the type of address
arithmetic to be performed for addressing mode calculations, or they can be
used for general-purpose storage. The address ALU supports linear, modulo,
and reverse-carry arithmetic types for all address register indirect
addressing modes. For modulo arithmetic, the contents of {Mn} also specify
the modulus. Each address register, {
Rn}, has its own modifier register,
{Mn}, associated with it. Each modifier register is set to $FFFF on
processor reset, which specifies linear arithmetic as the default type for
address register update calculations.


{Data ALU Input Registers} ({X1},{X0},{Y1},{Y0}){êY}{êX}

    X1,X0,Y1, and Y0 are four 24-bit, general-purpose data registers. They
can be treated as four independent, 24-bit registers oras two 48-bit
registers called {X} and {Y}, develloped by the concatenation of {X1}:{X0}
and {Y1}:{Y0}, respectively. {X1} is the most significant word in {X} and
{Y1} is the mostsignificant word in {Y}. The registers serve as input
buffer registers between the XDB or YDB and the MAC unit. They are used as
data ALU source operands, allowing new operands to be loaded for the next
instruction while the register contents are used by the current instruction.
The registers may also be read back out to the appropriate data bus to
implement memory-delay operations and save/restore operations for interrupt
service routines.


{Data ALU Accumulator Registers} ({A2},{A1},{A0},{B2},{B1},{B0}){êA}{êB}

    The six data ALU registers ({A2},{A1},{A0},{B2},{B1}, and {B0}) form
two general-purpose, 56-bit accumulators, {A} and {B}. Each of these two
registers consists of the three concatenated registers ({A2}:{A1}:{A0} and
{B2}:{B1}:{B0}, respectively). The 24-bit MSP is stored in {A1} or {B1}; the
24-bit LSP is stored in {A0} or {B0}. The 8-bit EXT is stored in {A2} or {B2}.

The 8-bit extension registers offer protection against overflow. On the
DSP56000/DSP56001, the extreme values that a word operand can assume are
-1 and +0.9999998. if the sum of two numbers is less than -1 or greater than
+0.9999998, the result (which cannot be represented in a word operand --
i.e., 24 bits) has underflowed or overflowed. The 8-bit extension registers
can accurately represent the result of 255 overflows or 255 underflows.
Whenever the accumulator extension registers are in use, the {
V} bit in the
status register is set.

Automatic sign extension is provided when writing to the 56-bit accumulators
{A} or {B} with a 48- or 24-bit operand. When a 24-bit operand is written,
the low-order portion will be automatically zero filled to form a valid
56-bit operand. The registers may also be written without sign extension or
zero fill by specifying the individual register name. When accumulator
registers {A} or {B} are read, they may be optionnaly scaled one bit left
or one bit right for block floating-point arithmetic.

Reading the {A} or {B} accumulators over the XDB and YDB is protected
against overflow by substituing a limiting constant for the data that is
being transfered. The content of {A} or {B} is not affected should
limiting occur; only the value transferred over the XDB or YDB is limited.
This overflow protection is performed after the contents of the accumulator
have been shifted according to the scaling mode. Shifting and limiting will
be performed only when the entire 56-bit {A} or {B} register is specified
as the source for a parallel data move over the XDB or YDB. When {A0},{A1},{A2},
{B0},{B1}, or {B2} are specified as the source for a parallel data move,
shifting and limiting are not performed. The accumulator registers serve as
buffer registers between the MAC unit and the XDB and/or YDB. These
registers are used as both data ALU source and destination operands.

Automatic sign extension of the 56-bit accumulators is provided when the {A}
or {B} register is written with a smaller operand. Sign extension can occur
when writing {A} or {B} from the XDB and/or YDB or with the results of
certain data ALU operations (such as the transfer conditionally ({
Tcc}) or
transfer data ALU register ({
TFR}) instructions). If a word operand is to be
written to an accumulator register ({A} or {B}), the MSP ({A1} or {A2})
portion of the accumulator is written with the word operand, the LSP ({A0} or
{B0}) portion is zero filled, and the EXT ({A2} or {B2}) portion is sign
extended from MSP. Long-word operands are written into the low-order portion,
MSP:LSP, of the accumulator register, and the EXT portion is sign extended
from MSP. No sign extension is performed if an individual 24-bit register
is written ({A1},{A0},{B1}, or {B0}) Test logic is included in each
accumulator register to support operation of the data shifter/limiter
circuits. This test logic is used to detect overflows out of the data
shifter so that the limiter can substitute one of several constants to
minimize errors due to the overflow. This process is commonly referred to as
saturation arithmetic.


{Status Register} ({SR}){êMR}{êCCR}{êC}{êV}{êZ}{êN}{êU}{êE}{êL}{êI1}{êI0}{êS1}{êS0}{êT}{êl}{êMode Register}{êInterrupt 0}{êInterrupt 1}{êTrace}{êloop}{êCondition Code Register}{êCarry}{êOverflow}{êZero}{êNegative}{êUnnormalized}{êExtension}{êLimit}

    This 16-bit {SR} consists of a mode register ({MR}) in the high-order
eight bits and a condition code register ({CCR}) in the low-order eight
bits. The SR is stacked when program looping is initialized, when a
{
JSR} is performed, or when interrupts occur, (except for no-overhead
fast interrupts).

     15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|* |T |* |S1|S0|I1|I0|* |L |E |U |N |Z |V |C |
    ++-++-++-++-++-++-++-++-++-++-++-++-++-++-++-++-+
     | |  |  |  |  |  |  |  |  |  |  |  |  |  |  +--> CARRY
     | |  |  |  |  |  |  |  |  |  |  |  |  |  +-----> OVERFLOW
     | |  |  |  |  |  |  |  |  |  |  |  |  +--------> ZERO
     | |  |  |  |  |  |  |  |  |  |  |  +-----------> NEGATIVE
     | |  |  |  |  |  |  |  |  |  |  +--------------> UNNORMALIZED
     | |  |  |  |  |  |  |  |  |  +-----------------> EXTENSION
     | |  |  |  |  |  |  |  |  +--------------------> LIMIT
     | |  |  |  |  |  |  |  +-----------------------> RESERVED
     | |  |  |  |  |  +--+--------------------------> INTERRUPT MASK
     | |  |  |  +--+--------------------------------> SCALING MODE
     | |  |  +--------------------------------------> RESERVED
     | |  +-----------------------------------------> TRACE MODE
     | +--------------------------------------------> RESERVED
     +----------------------------------------------> LOOP FLAG

{Mode Register} ({MR})

The {MR} is a special-purpose control register defining the current
system state of the processor. The MR bits are affected by processor
reset, exception processing, the {
DO}, end current DO loop ({
ENDDO}),
return from interrupt ({
RTI}), and {
SWI} instructions and by instructions
that directly reference the MR register - OR immediate to control
register ({
ORI}) and AND immediate to control register ({
ANDI}). During
processor reset, the interrupt mask bits of the MR will be set; the
scaling mode bits, loop flag, and trace bit will be cleared.

{Condition Code Register} ({CCR})

The {CCR} is a special-purpose control register that defines the
current user state of the processor. The CCR bits are affected by data
arithmetic logic unit (ALU) operations, parallel move operations, and by
instructions that directly reference the CCR({
ORI} and {
ANDI}). The CCR bits
are not affected by parallel move operations unless data limiting occurs
reading {
A} or {
B} accumulators. During processor reset, all CCR bits are
cleared.

CARRY (BIT 0):
    The Carry {C} bit is set if carry is generated out of
the MSB of the result in an addition. This bit is also set if a borrow
is generated in subtraction. The carry borrow is generated from bit 55
of the result. The carry bit is also affected by bit manipulation,
rotate, and shift instructions. Otherwise, this bit is cleared.

OVERFLOW (BIT 1):
    The overflow {V} bit is set if an arithmetic
overflow occurs in the 56-bit result. This bit indicates that the
result cannot be represented in the accumulator register; thus, the
register has overflowed. Otherwise, this bit is cleared.

ZERO (BIT 2):
    The zero {Z} bit is set if the result equals zero;
otherwise, this bit is cleared.

NEGATIVE (BIT 3):
    The negative {N} bit is set if the MSB (bit 55) of the result
is set; otherwise, this bit is cleared.

UNNORMALIZED (BIT 4):
    The unnormalized {U} bit is set if the two MSBs of
the most significant product (MSP) portion of the result are identical.
Otherwise, this bit is cleared. The MSP portion of the {
A} or {
B}
accumulators, which is defined by the scaling mode and the U bit, is
computed as follows:

    +----+----+--------------+----------------------+
    | S1 | S0 | Scaling Mode | U Bit Computation    |
    +----+----+--------------+----------------------+
    |  0 | 0 | No Scaling    | U=~(Bit 47 ^ Bit 46) |
    +----+----+--------------+----------------------+
    |  0 | 1 | Scale Down    | U=~(Bit 48 ^ Bit 47) |
    +----+----+--------------+----------------------+
    |  1 | 0 | Scale Up      | U=~(Bit 46 ^ Bit 45) |
    +----+----+--------------+----------------------+

EXTENSION (BIT 5):
    The extension {E} bit is cleared if all the bits of
the integer portion of the 56-bit result are all ones or all zeros;
otherwise, this bit is set. The integer portion, defined by the scaling
mode and the E bit, is computed as follows:

    +----+----+--------------+-------------------+
    | S1 | S0 | Scaling Mode | U Bit Computation |
    +----+----+--------------+-------------------+
    |  0 |  0 | No Scaling   | Bits 55,54..48,47 |
    +----+----+--------------+-------------------+
    |  0 |  1 | Scale Down   | Bits 55,54..49,48 |
    +----+----+--------------+-------------------+
    |  1 |  0 | Scale Up     | Bits 55,54..47,46 |
    +----+----+--------------+-------------------+

If the E bit is cleared, then the low-order fraction portion contains
all the significant bits; the high-order integer portion is just sign
extension. In this case, the accumulator extension register can be
ignored. If the E bit is set, it indicates that the accumulator extension
register is in use.

LIMIT (BIT 6):
    The Limit {L} bit is set if the overflow bit is set. The
L bit is also set if the data shifter/limiter circuits perform a
limiting operation; otherwise, it is not affected. The L bit is cleared
only by a processor reset or by an instruction that specifically clears
it, which allows the L bit to be used as latching overflow bit (i.e.,
a "sticky" bit). L is affected by data movement operations that read the
{
A} or {
B} accumulator registers.

INTERRUPT MASKS (BITS 8 AND 9):
    The interrupt mask bits, {I1} and {I0},
reflect the current {
IPL} of the processor and indicate the IPL needed
for an interrupt source to interrupt the processor. The current IPL of
the processor can be changed under software control. The interrupt
mask bits are set during hardware reset but not during software reset.

    +----+----+---------------------+------------------+
    | I1 | I0 | Exception Permitted | Exception Masked |
    +----+----+---------------------+------------------+
    |  0 |  0 | IPL 0,1,2,3         | None             |
    +----+----+---------------------+------------------+
    |  0 |  1 | IPL 1,2,3           | IPL 0            |
    +----+----+---------------------+------------------+
    |  1 |  0 | IPL 2,3             | IPL 0,1          |
    +----+----+---------------------+------------------+
    |  1 |  1 | IPL 3               | IPL 0,1,2        |
    +----+----+---------------------+------------------+

SCALE MODE (BITS 10 AND 11):
    The scaling mode bits, {S1} and {S0},
specify the scaling to be performed in the data ALU shifter/limiter and
the rounding position in the data ALU multiply accumulator ({
MAC}). The
scaling modes are shown in the following table:

    +----+----+--------------+-------------------------------------------+
    | S1 | S0 | Rounding Bit | Scaling Mode                              |
    +----+----+--------------+-------------------------------------------+
    |  0 |  0 |           23 | No Scaling                                |
    +----+----+--------------+-------------------------------------------+
    |  0 |  1 |           24 | Scale Down (1-Bit Arithmetic Right Shift) |
    +----+----+--------------+-------------------------------------------+
    |  1 |  0 |           22 | Scale Up (1-Bit Arithmetic Left Shift)    |
    +----+----+--------------+-------------------------------------------+
    |  1 |  1 |           -- | Reserved for Future Expansion             |
    +----+----+--------------+-------------------------------------------+

The shifter/limiter scaling mode affects data read from the {
A} or {
B}
accumulator registers out to the XDB and YDB. Different scaling modes
can be used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point
arithmetic. The scaling mode also affects the {
MAC} rounding position
to maintain proper rounding when different portions of the accumulator
registers are read out of the XDB and YDB. The scaling mode bits, which
are cleared at the start of a long interrupt service routine, are also
cleared during a processor reset.

TRACE MODE (BIT 13):
    The trace mode {T} bit is specifies the tracing
function of the DSP. If the T bit is set at the begining of any
instruction execution, a trace exception will be generated after the
instruction execution is completed. If the T bit is cleared, tracing is
disabled and instruction instruction execution proceeds normally. If a
long interrupt is executed during a trace exception, the SR having the
trace bit set will will be staked, and the trace bit in the SR is
cleared. The T bit is also cleared during processor reset.

RESERVED STATUS (BITS 7,12,14):
    These bits, which are reserved for
future expansion, will read as zero during DSP read operations.

LOOP FLAG (BIT 15):
    The loop flag {LF} bit, set when a program loop is
is in progress, enables the detection of the end of a program loop. The
{LF} is the only {SR} bit that is restored when terminating a program loop.
Stacking and restoring the {LF} when initiating and exiting a program
loop, respectively, allow the nesting of program loops. At the start of
a long interrupt service routine, the SR (including the LF) is pushed
on the SS and the SR LF is cleared. When returning from the long
interrupt with an {
RTI} instruction, the {
SS} is restored. During a
processor reset, the {LF} is cleared.


{Operating Mode Register} {OMR}{êDE}{êSD}{êEA}{êData Rom Enable}{êStop Delay}{êExternal Memory Access}

    The {OMR} is a 24-bit register (only five bits are defined) that sets the
current operating mode of the processor (i.e., the memory maps for program
and data memories as well as the startup procedure). The OMR bits are only
affected by processor reset and by instructions directly referencing the
OMR: {
ANDI}, {
ORI}, and {
MOVEC}. During processor reset, the chip operating mode
bits, MB and MA, will be loaded from the external mode select pins B and A,
respectively. The data ROM enable {DE} bit will be cleared, disabling the X
and Y on-chip lookup-table ROMs.

OMR Format:

     23    8  7  6    5  4  3  2    1  0
    +-----------+--+--+--+--+--+--+--+--+
    |  *       |EA|SD| *| *| *|DE|MB|MA|
    ++---------+++-++-++-++-++-++-++-++-+
     |         | |  |  |  |  |  |  +--+---> OPERATING MODE
     |         | |  |  |  |  |  +---------> DATA ROM ENABLE
     |         | |  |  +--+--+------------> RESERVED
     |         | |  +---------------------> STOP DELAY
     |         | +------------------------> EXTERNAL MEMORY ACCESS
     +---------+--------------------------> RESERVED

DSP56001 Operating Mode Summary:

    +-----------+----+----+---------------------------------------------+
    | Operating |    |    | DSP56001 Program Memory Map                 |
    | Mode      | MA | MB +--------------+-------------+----------------+
    |           |    |    | Internal RAM | External    | Reset          |
    +-----------+----+----+--------------+-------------+----------------+
    |         0 |  0 |  0 | $0000-$01FF  | $0200-$FFFF | Internal-$0000 |
    +-----------+----+----+--------------+-------------+----------------+
    |           |    |    | Special bootstrap mode; after program RAM   |
    |         1 |  0 |  1 | loading, mode 2 is automatically selected   |
    |           |    |    | but PC = $0000                              |
    +-----------+----+----+--------------+-------------+----------------+
    |         2 |  1 |  0 | $0200-$FFFF  | $0200-$FFFF | External-$E000 |
    +-----------+----+----+--------------+-------------+----------------+
    |         3 |  1 |  1 |      ---     | $0000-$FFFF | External-$0000 |
    +-----------+----+----+--------------+-------------+----------------+

DSP56000/DSP56001 DE Memory Control:

    +----+--------------------------------------------------------------+
    |                          Data Memory Map                          |
    | DE +---------------------------+----------------------------------+
    |    |          Y Memory         |              X Memory            |
    +----+---------------------------+----------------------------------+
    |    | Internal RAM: $0000-$00FF | Internal RAM: $0000-$00FF        |
    |  0 | External: $0100-$FFFF     | External: $0100-$FFBF            |
    |    |           ---             | On-Chip Peripherals: $FFC0-$FFFF |
    +----+---------------------------+----------------------------------+
    |    | Internal RAM: $0000-$00FF | Internal RAM: $0000-$00FF        |
    |    | Internal ROM: $0100-$01FF | Internal ROM: $0100-$01FF        |
    |  1 | External: $0200-$FFFF     | External: $0200-$FFBF            |
    |    |           ---             | On-Chip Peripherals: $FFC0-$FFFF |
    +----+---------------------------+----------------------------------+

CHIP OPERATING MODE (BITS 0 AND 1):
    The chip operating mode bits, MB and MA,
indicate the bus expansion mode of the DSP56000/DSP56001. On processor
reset, these bits are loaded from the external mode select pins, ~MODB and
~MODA, respectively. After the DSP leaves the reset state, MB and MA can be
changed under program control. The "secure DSP56000" is an exception. The
external mode select pins, ~MODB and ~MODA, are disabled on the "secure
DSP56000" and are only used for interrupts as ~IRQA and ~IRQB. The operating
modes are shown in the following table:

    +----+----+------------------------------------+
    | MB | MA |         Chip Operating Mode        |
    +----+----+------------------------------------+
    |  0 |    0 | Single-Chip Nonexpanded            |
    +----+----+------------------------------------+
    |  0 |    1 | Special Bootstrap (DSP 56001 Only) |
    +----+----+------------------------------------+
    |  1 |    0 | Normal Expanded                    |
    +----+----+------------------------------------+
    |  1 |    1 | Development Expanded               |
    +----+----+------------------------------------+

DATA ROM ENABLE (BIT 2):
    The {DE} bit enables the two, on-chip, 256*24 data ROMs located at
address $0100-$01FF in the X and Y memory spaces. When DE is cleared,
the $0100-$01FF in the X and Y memory spaces. When DE is cleared,
the $0100-$01FF address space is part of the external X and Y data spaces,
and the on-chip data ROMs are disabled.

STOP DELAY (BIT 6):
    The {
STOP} instruction causes the DSP56000/DSP56001 to
indefinitely suspend processing in the middle of the {
STOP} instruction.
When exiting the stop state, if the stop delay bit is zero, a 64K clock
cycle delay (i.e., 131,072 T states) is selected before continuing the stop
instruction cycle. However, if the stop delay bit is one, the delay before
continuing the instruction cycle is 16 T states. The long delay allows a
clock stabilisation period for the internal clock to begin oscillating and
to stabilize. When a stable external clock is used, the shorter delay allows
faster startup of the DSP.

EXTERNAL MEMORY ACCESS (BIT 7):
    The external memory access mode bit selects
the function of two of the port A control pins. The DSP56000/DSP56001 comes
out of reset with these pins defined as bus request/bus grant (~BR/~BG) --
i.e., bit 7 is cleared. When bit 7 is clear, wait states are only introduced
into the port A timing by using the bus control register (BCR). When bit 7
is set under program control (using {
ANDI},{
ORI}, or {
MOVEC}), these pins are
defined as bus strobe (~BS) and wait (~WT). In this mode, wait states are
introduced into port A timing by using either the BCR or asserting ~WT. ~BR
and ~BG allow the DSP56000/DSP56001 to give the external bus to an external
device, thus preventing busconflicts. ~BS and ~WT allow the DSP56000/
DSP56001 to work with asynchronous devices (bus arbitrators) on port A. The
definition of the control pins is summarized in the following table.

    +-------------+-------------------+------------------+
    | OMR Bit 7   | ~BR Pin (Input)   | ~BG Pin (Output) |
    +-------------+-------------------+------------------+
    | 0 (Default) | Bus Request (~BR) | Bus Grand (~BG)  |
    +-------------+-------------------+------------------+
    |           1 | Wait (~WT)        | Bus Strobe (~BS) |
    +-------------+-------------------+------------------+

RESERVED OMR BITS (BITS 3-5 AND 8-23):
    These OMR bits, reserved for future expansion, will read as zero
 during DSP read operations.


{Loop Address Register} ({LA})

    The contents of the {LA} register indicate the location of the last
instruction word in a program loop. This register is stacked into the {
SSH} by
a {
DO} instruction and is unstackded by end-of-loop processing or by execution
of an {
ENDDO} instruction. When the instruction at the address contained in
this register is fetched, the contents of the {
LC} register are checked. If
the contents are not one, the {
LC} is decremented, and the next instruction is
taken from the address at the top of the {
SS}; otherwise, the {
PC} is
incremented, the loop flag is restored (pulled from the {
SS}), the {
SS} is
purged, the {LA} and {
LC} registers are pulled from the {
SS} and restored,
and instruction execution continues normally. The {LA} regsiter, a read/write
register, is written by a {
DO} instruction and read by the {
SS} when stacking
the register. Since the {
LC} register can be accessed under program control,
the number of times a loop has been executed can be determined.


{Loop Counter Register} ({LC})

    The {LC} register is a special 16-bit counter used to specify the number
of times a hardware program loop is to be repeated. This register is stacked
into the {
SSL} by a {
DO} instruction and unstacked by end-of-loop processing
or by execution of an {
ENDDO} instruction. When the end of a hardware
program loop is reached, the contents of the {LC} register are tested for
one. If the {LC} is one, the program loop is terminated, and the {LC}
register is loaded loaded with the previous {LC} contents stored on the {
SS}.
If {LC} is not one, it is decremented and the program loop is repeated. The
{LC} can be read under program control, which allows the number of times a
loop will be executed to be monitored/changed dynamically. The {LC} is also
used in the {
REP} instruction.


{System Stack} ({SS}){êSSH}{êSSL}{êStack Overflow}{êStack Underflow}{êSystem Stack High}{êSystem Stack Low}

    The {SS} is a separate 15*32-bit internal memory divided into two bank:
{SSH} and {SSL}, each 16 bits wide. The {SSH} stores the {
PC} contents,
and the {SSL} stores the {
SR} contents for subroutine calls and long
interrupts. The {SS} will also store the {
LA} and {
LC} registers in addition
to the {
PC} and {
SR} registers for program looping. The {SS} is in stack
memory space; its address is always inherent and implied by the current
instruction.

The contents of the {
PC} and {
SR} register are pushed on the top location
of the {SS} when a subroutine call and long interrupt occurs. When a return
from subroutine (RTS) occurs, the contents of the top location in the {SS}
are pulled and put in the {
PC}; the {
SR} is not affected. When an {
RTI}
occurs, the contents ofthe top location in the {SS} are pulled to both the
{
PC} and {
SR}.

The {SS} is also used to implement no-overhead nested hardware {
DO} loops.
When the {
DO} instruction is executed, the {
LA}:{
LC} are pushed on the {SS},
then the {
PC}:{
SR} are pushed on the {SS}. Since each {SS} location can
be addressed as a separate 16-bit registers ({SSH} and {SSL}), software stacks
can be created for unlimited nesting.

Up to 15 long interrupts, seven {
DO} loops, 15 {
JSR}s or combinations of
these can be accommodate by the {SS}. When the {SS} limit is exceeded, a
nonmaskable stack error interrupt occurs, and the {
PC} is pushed to {SS}
location zero, which isnot implemented in hardware. The {
PC} will be lost,
and there will be no {
SP} from the stack interrupt routine to the program
that was executing when the error occurred.


{Stack Pointer Register} ({SP}){êO}{êU}

    The 6-bit {SP} register indicates the location of the top of the {
SS}
(underflow, empty, full, and overflow). The {SP} register is referenced
implicitly by some instructions ({
DO},{
REP},{
JSR},{
RTI},etc. ) or directly
by the {
MOVEC} instruction. The {SP} register is implemented as a 6-bit
counter that address (selects) a 15-location stack with its four LSBs.

{SP} Register Format:

    +----+----+----+----+----+----+
    | UF | SE | P3 | P2 | P1 | P0 |
    +-+--+-+--+-+--+-+--+-+--+-+--+
      |    |    +----+----+----+----> STACK POINTER
      |    +------------------------> STACK ERROR FLAG
      +-----------------------------> UNDERFLOW FLAG

{SP Register Values}{êO}{êU}

     UF SE P3 P2 P1 P0
      1  1  1  1  1  0  STACK UNDERFLOW CONDITION AFTER DOUBLE PULL
      1  1  1  1  1  1  STACK UNDERFLOW CONDITION
      0  0  0  0  0  0  STACK EMPTY (RESET:) PULL CAUSES UNDERFLOW
      0  0  0  0  0  1  STACK LOCATION 1
            ...
            ...
      0  0  1  1  1  0  STACK LOCATION 14
      0  0  1  1  1  1  STACK LOCATION 15; PUSH CAUSES OVERFLOW
      0  1  0  0  0  0  STACK OVERFLOW CONDITION
      0  1  0  0  0  1  STACK OVERFLOW CONDITION AFTER DOUBLE PUSH

STACK POINTER (BITS 0-3):
    The {SP} points to the last used location on the {
SS}. Immediately
after hardware reset, these bits are cleared ({SP} = 0), indicating that the
{
SS} is empty.

Data is pushed onto the {
SS} by decrementing the {SP}, then writing data
to the location pointed to by the {SP}. An item is pulled off the stack by
copying it from the location pointed to by the SP and then by decrementing
{SP}.

STACK ERROR FLAG (BIT 4, {SE}):
    The stack error flag indicates that a stack error has occurred, and the
transition of the stack error flag from zero to one causes a priority
level-3 stack error exception.

When the stack is completely full, the {SP} reads 001111, and any operation
that pushes data onto the stack will cause a stack error exception to occur.
The {
SR} will read 010000 (or 010001 if an implied double push occurs).

Any implied pull operation with {SP} equal to zero will cause a stack error
exception, and the {SP} will read 111111 (or 111110 if an implied double
pull occurs). The stack error bit is set as shown before.

The stack error flag is a "sticky bit" which, once set, remains set until
cleared by the user. There is a sequence of instructions which can cause a
stack oveflow which, without the sticky bit, would not be detected because
the stack pointer is decremented before the stack error interrupt is taken.
The sticky bit keeps the stack error bit set until cleared by the user by
writing a zero to {SP} bit 4. It also latches the overflow/underflow bit
so that it cannot be changed by stack poibnter increments or decrements as
long as the stack error is set. The overflow/underflow bit remains latched
until the first move to {SP} is executed.

NOTE:    When {SP} is zero (stack empty), instructions that read the stack
without {SP} postdecrement and instructions that write to the stack without
{SP} preincrement do not cause a stack error exception (i.e,
1] {
DO} {
SSL},xxxx 2] {
REP} {
SSL} 3] {
MOVEC} or move peripheral data ({
MOVEP})
when {
SSL} is specified as a source or destination).

UNDERFLOW FLAG (BIT 5, {UF}):
    The undeflow flagis set when a stack underflow occurs. The stack
undeflow flag is a "sticky bit" when the stack error flag is set, the
underflow flag will not change state. The combination of "underflow=1" and
"stack error=0" is an illegal combination and will not occur unless it is
forced by the user. If this condition is forced by the user, the hardware
will correct itself based on the result of the next stack operation.

RESERVED STACK POINTER REGISTER BITS (BIT 6-23):
    Any unimplemented {SP} register bits are reserved for future expansion
and will read as zero during DSP56000/DSP56001 read operations.


{Program Counter} ({PC})

    This 16-bit register contains the address of the next
location to be fetched from program memory space. The {PC} can
point to instructions, data operands, or addresses of operands.
References to this register are always inherent and are implied by
most instructions. This special-purpose address register is
stacked when program looping is initialized, when a {
JSR} is
performed, or when interrupts occur (except for no-overhead fast
interrupts).