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- Path: informatik.tu-muenchen.de!fischerj
- From: fischerj@Informatik.TU-Muenchen.DE (Juergen "Rally" Fischer)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: Free cycles after a FAST-write?
- Date: 16 Mar 1996 03:06:16 GMT
- Organization: Technische Universitaet Muenchen, Germany
- Distribution: world
- Message-ID: <4idb78$b3p@sunsystem5.informatik.tu-muenchen.de>
- References: <38232831@kone.fipnet.fi> <666.6640T1273T725@ifi.uio.no>
- NNTP-Posting-Host: hphalle5.informatik.tu-muenchen.de
- X-Newsreader: TIN [version 1.2 PL2]
-
- Ludvig Pedersen (ludvigp@ifi.uio.no) wrote:
- : >I noticed a funny phenomena; I got 4 (four) free one-cycle
-
- I also first thought free cycles are a thing of writing to chipmem.
- but: cpu needing resync to dma channel won't give anything free.
-
- The rule is: 020+ can delay a mem store (to any mem, bus is bus)
- and continue with instructions that don't need a mem acess.
-
- : >register instruction after a FAST-ram write on my
- : >Warp Engine, 68040/40, SetPatch executed.
- : >The loop:
- : > REPT 32
- : > move.l d0,(a0)+ ;a0 points to FAST
- : > move.l d1,d1
- : > move.l d1,d1
- : > move.l d1,d1
- : > move.l d1,d1
- : > ENDR
-
- So I guess a mem store on your system is 5 cycles, kinda 32mb/sec ?
-
- : I tested that a long time ago, but after I remeber I only got 2 free
- : instuctons on my 030/50mhz.
-
- I guess a store needs 6 or 7 cycles on your system, 2 or 3 more than without
- waitstates.
-
- : Anyway, its something one should be aware of when optimising.
- yep!
-
- : Its not a funny phenomena but completly normal on fast cpu's.
-
- like the 020-14 for example :-> 2 free cycles after a fastmem write.
-
- : <sb>Ludde - Amiga Demo Coder
- : <sb>Virtual Reality & Official Be developer
- : <sb>ludvigp@ifi.uio.no
- ------------------------------------------------------------------------
- fischerj@Informatik.TU-Muenchen.DE (Juergen "Rally" Fischer) =:)
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