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Text File  |  1998-05-08  |  15KB  |  301 lines
  1. /*$Log: andis.h $
  2.  * Revision 1.4  93/03/29  17:53:50  DAN
  3.  * changed line "typedef struct xvppat" to "typedef struct xvppat_t"
  4.  * (immediate typedef'ing should not affect .c files, and few other
  5.  * .h files, though.)
  6.  *
  7.  * Revision 1.3  92/09/11  11:46:54  JJM
  8.  * now uses ibmandis.h for the header part of ppat
  9.  *
  10.  * Revision 1.2  92/09/08  12:47:01  JJM
  11.  * added some new defs
  12.  *
  13.  * Revision 1.1  92/09/02  19:05:44  JJM
  14.  * Initial revision
  15.  * */
  16. /***************************************************************************
  17. *file: andis.h
  18. *function:  This is the interface module for the andis.c module.
  19. *changes:
  20. *    SV_ANDIS added;
  21. *    USHORT- to ushort
  22. *    to the 3 typedef's, needed to name the  struct
  23. ****************************************************************************/
  24.  
  25. /*the following are defs I've added .........       */
  26.  
  27. /*create defines for the ppat's Phys_Conn_State field */
  28. #define SCPI_PCS_AVAILABLE    0x00     // hardware available AND present
  29. #define SCPI_PCS_DISCONNECTED 0x01     // Disconnected
  30. #define SCPI_PCS_CONN_PENDING 0x02     // Connect Pending
  31. #define SCPI_PCS_CONNECTED    0x03     // Connected
  32. #define SCPI_PCS_DISC_PENDING 0x04     // Disconnect Pending
  33.  
  34. /*defines for Conn_Type field */
  35. #define SCPI_CT_NONSWITCHED  0x01      // non switched connection type
  36. #define SCPI_CT_SWITCHED     0x02      // switched connection type
  37.  
  38. #define         SV_ANDIS              0x40000
  39.  
  40. #include        "ibmandis.h"
  41.  
  42. #define         XVLOG                 0x80
  43.  
  44. #define         REGDEV                  01
  45. #define         STARTREG                02
  46. #define         GETLST                  03
  47.  
  48. #define         SCPI_PCMID           ANDIS_PCMID      /* PCM ID for SCPI Calls */
  49. #define         SCPI_REQHANDLE       ANDIS_REQHANDLE  /* Request Handle for SCPI Calls */
  50. #define         SCPI_PARM_1          ANDIS_PARM_1     /* Parameter 1 for SCPI Calls */
  51. #define         SCPI_PARM_2          ANDIS_PARM_2     /* Parameter 2 for SCPI Calls */
  52. #define         SCPI_FC              ANDIS_FC         /* Function Code for SCPI Calls */
  53. #define         SCPI_MAC_DS          ANDIS_MAC_DS     /* MAC DS Parm for SCPI Calls */
  54.  
  55. #define  SCPI_PARMS ANDIS_PARMS
  56.  
  57. typedef struct xvppat_t
  58. {
  59.    ANDISPPAT      Header;
  60.    unsigned short PPI_Status;       // Physical Port Interface Status
  61.                                     // Bit   0 - DTR, Bit   1 - RTS
  62.                                     // Bit   2 - HDR, Bit   3 - Unused
  63.                                     // Bit   4 - CTS, Bit   5 - DSR
  64.                                     // Bit   6 - RI,  Bit   7 - DCD
  65.    unsigned long Port_Attribs;      // Port Attribute Indicator
  66.                                     // Bit  0 - Port Active
  67.                                     // Bit  1 - Port Owned
  68.                                     // Bit  2 - Port Parameters Modifiable
  69.                                     // Bit  3 - V.25bis Supported
  70.                                     // Bit  4 - V.54 Supported
  71.                                     // Bit  5 - Async Supported
  72.                                     // Bit  6 - BiSync Supported
  73.                                     // Bit  7 - Sync (HDLC) Supported
  74.                                     // Bit  8 - Mode is Software
  75.                                     //          Selectable/Resetable
  76.                                     // Bit  9 - Data Mode Active
  77.                                     // Bit 10 - High Data Rate (HDR)
  78.                                     //          Mode Supported
  79.                                     // Bit 11 - Port Monitors Ring
  80.                                     //          Indicate (RI)
  81.                                     // Bit 12 - NRZI/NRZ Supported
  82.                                     // Bit 13 - XON/XOFF Flow Control
  83.                                     //          Supported
  84.                                     // Bit 14 - Hardware Handshaking
  85.                                     // Bit 15 - ISO 3309.2 Supported
  86.                                     // Bit 16 - AWP 0224 Supported
  87.                                     // Bit 17 - Novell Async Supported
  88.                                     // Bit 18 - Bisync Supported
  89.                                     // Bit 19 - HDLC Supported
  90.                                     // Bit 20-31 - Reserved
  91.    unsigned char Clock_Type;        // Clocking Type - AWP-0209
  92.                                     //    01h - Internal-Sync
  93.                                     //    02h - External
  94.                                     //    04h - Local Attach
  95.                                     //    11h - Internal Async
  96.    unsigned char XVRESERVE_1;       // Reserved
  97. // NOTE:  The rest of the PPAT can be modified by a PCM or NULL DLC.
  98.    unsigned long Xmit_Speed;        // Transmit Speed
  99.    unsigned long Rcv_Speed;         // Receive Speed
  100.    unsigned char Comm_Type;         // Communication Type - AWP-0209
  101.                                     //    01h - Half Duplex (HDX)
  102.                                     //    02h - Full Duplex (FDX)
  103.                                     //    03h - FDX Facility
  104.    unsigned char Port_Mode;         // Current framing mode
  105.                                     //    01h - ISO 3309.2
  106.                                     //    02h - AWP 0224
  107.                                     //    03h - Novell Async
  108.                                     //    04h - BiSync
  109.                                     //    05h - HDLC
  110.    unsigned char Transparency;      // 00h - Negotiated 01h - None (Null DLC)
  111.                                     // 02h - Flow Control, 03h - Full
  112.    unsigned char Hard_Hand;         // Hardware Handshaking Type
  113.                                     //    Bit   0 - Inbound XON/XOFF
  114.                                     //    Bit   1 - Outbound XON/XOFF
  115.                                     //    Bit   2 - CTS Handshaking
  116.                                     //    Bit   3 - RTS Handshaking
  117.                                     //    Bit   4 - DSR Handshaking
  118.                                     //    Bit   5 - DTR Handshaking
  119.                                     //    Bit   6 - Reserved
  120.    unsigned char XOFF_Char;         // 13h - Default
  121.    unsigned char XON_Char;          // 11h - Default
  122.    unsigned short Port_Trans_Mode;  // Port Transfer Mode
  123.                                     // For Async
  124.                                     //  Bits 0-3 - Bits per Character
  125.                                     //  Bits 4-5 - Number of Start/Stop Bits
  126.                                     //             00h - 1 Bit
  127.                                     //             01h - 1.5 Bits
  128.                                     //             02h - 2 Bits
  129.                                     //  Bit  6-8 - Parity
  130.                                     //             00h - None
  131.                                     //             01h - Even
  132.                                     //             02h - Odd
  133.                                     //             03h - Mark
  134.                                     //             04h - Space
  135.                                     // For Sync
  136.                                     //  0h - NRZ
  137.                                     //  1h - NRZI
  138.    unsigned short Signal_Mask;      // Signal Indication Mask
  139.                                     //      Bit   0 - DTR
  140.                                     //      Bit   1 - RTS
  141.                                     //      Bit   2 - HDR
  142.                                     //      Bit   3 - Unused
  143.                                     //      Bit   4 - CTS
  144.                                     //      Bit   5 - DSR
  145.                                     //      Bit   6 - RI
  146.                                     //      Bit   7 - DCD
  147.                                     //      Bits  8-15 - Reserved
  148.                                     //
  149.                                     //   NOTE:  A value of one in any bit posi-
  150.                                     //   tion indicates that the upper layer
  151.                                     //   (the PCM or DLC) is interested in the
  152.                                     //   coresponding signal.
  153.    unsigned short Hw_Err_Mask;      // Hardware Error Mask
  154.                                     //    Bit   0 - DSR Dropped
  155.                                     //    Bit   1 - CTS Dropped
  156.                                     //    Bit   2 - DCD Dropped
  157.                                     //    Bit   3 - DSR Hot
  158.                                     //    Bit   4 - DSR Dead
  159.                                     //    Bit   5 - CTS Dead
  160.                                     //    Bit   6 - DCD Dead
  161.                                     //    Bit   7 - DSR Stuck
  162.                                     //    Bit   8 - CTS Stuck
  163.                                     //    Bit   9 - DCD Stuck
  164.                                     //    Bit  10 - CTS Hot HDX
  165.                                     //    Bit  11 - Break Detected
  166.                                     //    Bit  12 - Parity Error
  167.                                     //    Bit  13 - Framing Error
  168.                                     //    Bit  14 - Hardware Overrun
  169.                                     //    Bit  15 - Receive Buffer Overflow
  170.                                     //
  171.                                     // NOTE:  A value of one in any bit posi-
  172.                                     // tion indicates that the upper layer
  173.                                     // (the PCM or DLC) is interested in the
  174.                                     // coresponding error.
  175. } XVPPAT, far *PXVPPAT;
  176.  
  177. /* SCPI Function Codes */
  178.  
  179. #define SCPI_FC_REG_PCM         ANDIS_FC_REG_PCM
  180. #define SCPI_FC_REG_NULL_DLC    ANDIS_FC_REG_NULL_DLC
  181. #define SCPI_FC_REL_PCM         ANDIS_FC_REL_PCM
  182. #define SCPI_FC_REL_NULL_DLC    ANDIS_FC_REL_NULL_DLC
  183. #define SCPI_FC_ACT_MODE        ANDIS_FC_ACT_MODE
  184. #define SCPI_FC_RET_PPI_STAT    ANDIS_FC_RET_PPI_STAT
  185. #define SCPI_FC_GET_PPAT_PARMS  ANDIS_FC_GET_PPAT_PARMS
  186. #define SCPI_FC_SET_PPAT_PARMS  ANDIS_FC_SET_PPAT_PARMS
  187. #define SCPI_FC_RESET_PORT      ANDIS_FC_RESET_PORT
  188. #define SCPI_FC_ACT_PHYS_CONN   ANDIS_FC_ACT_PHYS_CONN
  189. #define SCPI_FC_DEACT_PHYS_CONN ANDIS_FC_DEACT_PHYS_CONN
  190. #define SCPI_FC_ACT_DTR         ANDIS_FC_ACT_DTR
  191. #define SCPI_FC_ACT_RTS         ANDIS_FC_ACT_RTS
  192.  
  193. #define PORT_MGMT_IND_MIN       0x0020
  194. #define SCPI_FC_CONN_ACTIVE     (ANDIS_FC_CONN_ACTIVE     + PORT_MGMT_IND_MIN)
  195. #define SCPI_FC_CONN_INACTIVE   (ANDIS_FC_CONN_INACTIVE   + PORT_MGMT_IND_MIN)
  196. #define SCPI_FC_PPI_SIGNAL      (ANDIS_FC_PPI_SIGNAL      + PORT_MGMT_IND_MIN)
  197. #define SCPI_FC_PPI_EXCEPTION   (ANDIS_FC_PPI_EXCEPTION   + PORT_MGMT_IND_MIN)
  198. #define SCPI_FC_PM_REQ_COMPLETE (ANDIS_FC_PM_REQ_COMPLETE + PORT_MGMT_IND_MIN)
  199.  
  200. #define XMIT_DATA_MIN           0X0030
  201. #define SCPI_FC_TX_IMM_DATA     (ANDIS_FC_TX_IMM_DATA     + XMIT_DATA_MIN)
  202. #define SCPI_FC_SEND_BREAK      (ANDIS_FC_SEND_BREAK      + XMIT_DATA_MIN)
  203.  
  204. #define XMIT_DATA_CNF_MIN       0X0040
  205. #define SCPI_FC_TX_IMM_DATA_CNF (ANDIS_FC_TX_IMM_DATA_CNF + XMIT_DATA_CNF_MIN)
  206.  
  207. #define RECV_DATA_MIN           0X0050
  208. #define SCPI_FC_RX_IMM_DATA     (ANDIS_FC_RX_IMM_DATA     + RECV_DATA_MIN)
  209.  
  210. #define XMIT_CNFM_MIN           0x0060
  211. #define SCPI_FC_RX_IMM_DATA_CNF (ANDIS_FC_RX_IMM_DATA_CNF + XMIT_CNFM_MIN)
  212.  
  213. #define SCPI_FC_UPDATE_PPAT     (ANDIS_FC_UPDATE_PPAT     + 0x0070)
  214.  
  215.  
  216. /* MAC Mode (Used in SCPI Word for Activate Mode primitive) */
  217.  
  218. #define SCPI_MAC_MODE_CONN      ANDIS_MAC_MODE_CONN
  219. #define SCPI_MAC_MODE_PROTOCOL  ANDIS_MAC_MODE_PROTOCOL
  220. #define SCPI_MAC_MODE_DATA      ANDIS_MAC_MODE_DATA
  221.  
  222.  
  223. /* Reset Type (Used in SCPI Word for Reset Port primitive) */
  224.  
  225. #define SCPI_RESET_SOFT         ANDIS_RESET_SOFT
  226. #define SCPI_RESET_HARD         ANDIS_RESET_HARD
  227.  
  228.  
  229. /* Connect Mode (Used in SCPI Word for Activate Phys Conn primitive) */
  230.  
  231. #define SCPI_CONN_MODE_PCM      ANDIS_CONN_MODE_PCM
  232. #define SCPI_CONN_MODE_DLC      ANDIS_CONN_MODE_DLC
  233. #define SCPI_CONN_MODE_NULL_DLC ANDIS_CONN_MODE_NULL_DLC
  234.  
  235.  
  236. /* State (Used in SCPI Word for Activate DTR and Activate RTS primitives) */
  237.  
  238. #define SCPI_STATE_DEACTIVATE   0x0000
  239. #define SCPI_STATE_ACTIVATE     0x0001
  240.  
  241.  
  242. /* PPI Exception (Used in SCPI Word for PPI Exception primitive) */
  243.  
  244. #define SCPI_XCPT_DSR_DROPPED   0x0001
  245. #define SCPI_XCPT_CTS_DROPPED   0x0002
  246. #define SCPI_XCPT_DCD_DROPPED   0x0004
  247. #define SCPI_XCPT_DSR_HOT       0x0008
  248. #define SCPI_XCPT_DSR_DEAD      0x0010
  249. #define SCPI_XCPT_CTS_DEAD      0x0020
  250. #define SCPI_XCPT_DCD_DEAD      0x0040
  251. #define SCPI_XCPT_DSR_STUCK     0x0080
  252. #define SCPI_XCPT_CTS_STUCK     0x0100
  253. #define SCPI_XCPT_DCD_STUCK     0x0200
  254. #define SCPI_XCPT_CTS_HOT_HDX   0x0400
  255. #define SCPI_XCPT_BREAK_DET     0x0800
  256. #define SCPI_XCPT_PARITY_ERR    0x1000
  257. #define SCPI_XCPT_FRAMING_ERR   0x2000
  258. #define SCPI_XCPT_HW_OVERRUN    0x4000
  259. #define SCPI_XCPT_RX_OVERFLOW   0x8000
  260.  
  261.  
  262. /* PPI Status (Used in SCPI Word for several primitives) */
  263.  
  264. #define SCPI_PPI_STAT_DTR       0x0001
  265. #define SCPI_PPI_STAT_RTS       0x0002
  266. #define SCPI_PPI_STAT_HDR       0x0004
  267. #define SCPI_PPI_STAT_CTS       0x0010
  268. #define SCPI_PPI_STAT_DSR       0x0020
  269. #define SCPI_PPI_STAT_RI        0x0040
  270. #define SCPI_PPI_STAT_DCD       0x0080
  271.  
  272.  
  273. /* SCPI Return Codes */
  274.  
  275. #define SCPI_RC_SUCCESS         ANDIS_RC_SUCCESS
  276. #define SCPI_RC_REQ_QUEUED      ANDIS_RC_REQ_QUEUED
  277. #define SCPI_RC_OUT_OF_RESOURCE ANDIS_RC_OUT_OF_RESOURCE
  278. #define SCPI_RC_INVALID_PARM    ANDIS_RC_INVALID_PARM
  279. #define SCPI_RC_INVALID_FUNC    ANDIS_RC_INVALID_FUNC
  280. #define SCPI_RC_NOT_SUPPORTED   ANDIS_RC_NOT_SUPPORTED
  281. #define SCPI_RC_HW_ERROR        ANDIS_RC_HW_ERROR
  282. #define SCPI_RC_TRANSMIT_ERROR  ANDIS_RC_TRANSMIT_ERROR
  283. #define SCPI_RC_BUFF_TOO_SMALL  ANDIS_RC_BUFF_TOO_SMALL
  284. #define SCPI_RC_DRIVER_NOT_INIT ANDIS_RC_DRIVER_NOT_INIT
  285. #define SCPI_RC_HW_NOT_FOUND    ANDIS_RC_HW_NOT_FOUND
  286. #define SCPI_RC_HW_FAILURE      ANDIS_RC_HW_FAILURE
  287. #define SCPI_RC_CONFIG_FAILURE  ANDIS_RC_CONFIG_FAILURE
  288. #define SCPI_RC_INT_CONFLICT    ANDIS_RC_INT_CONFLICT
  289. #define SCPI_RC_INCOMPAT_MAC    ANDIS_RC_INCOMPAT_MAC
  290. #define SCPI_RC_INIT_FAILED     ANDIS_RC_INIT_FAILED
  291. #define SCPI_RC_NO_BINDING      ANDIS_RC_NO_BINDING
  292. #define SCPI_RC_NET_NOT_CONN    ANDIS_RC_NET_NOT_CONN
  293. #define SCPI_RC_INCOMPAT_OS_VER ANDIS_RC_INCOMPAT_OS_VER
  294. #define SCPI_RC_ALREADY_REG     ANDIS_RC_ALREADY_REG
  295. #define SCPI_RC_PATH_NOT_FOUND  ANDIS_RC_PATH_NOT_FOUND
  296. #define SCPI_RC_INSUF_MEM       ANDIS_RC_INSUF_MEM
  297. #define SCPI_RC_INFO_NOT_FOUND  ANDIS_RC_INFO_NOT_FOUND
  298. #define SCPI_RC_GEN_FAILURE     ANDIS_RC_GEN_FAILURE
  299.  
  300.  
  301.