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Text File  |  1995-04-14  |  9KB  |  202 lines
  1. ;*DDK*************************************************************************/
  2. ;
  3. ; COPYRIGHT    Copyright (C) 1995 IBM Corporation
  4. ;
  5. ;    The following IBM OS/2 WARP source code is provided to you solely for
  6. ;    the purpose of assisting you in your development of OS/2 WARP device
  7. ;    drivers. You may use this code in accordance with the IBM License
  8. ;    Agreement provided in the IBM Device Driver Source Kit for OS/2. This
  9. ;    Copyright statement may not be removed.;
  10. ;*****************************************************************************/
  11. ;      /*****************************************************************/
  12. ;      /*                                                               */
  13. ;      /*                                                               */
  14. ;      /*****************************************************************/
  15. ;      /******************* START OF SPECIFICATIONS *********************/
  16. ;      /*                                                               */
  17. ;      /*  SOURCE FILE NAME: SERIAL.INC                                 */
  18. ;      /*                                                               */
  19. ;      /*  DESCRIPTIVE NAME: Serial COM IO equates                      */
  20. ;      /*                                                               */
  21. ;      /*                                                               */
  22. ;      /*  STATUS:  Version 1.0                                         */
  23. ;      /*                                                               */
  24. ;      /*  NOTES:                                                       */
  25. ;      /*                                                               */
  26. ;      /*  ENTRY POINTS:                                                */
  27. ;      /*      See public statements                                    */
  28. ;      /*  EXTERNAL REFERENCES:                                         */
  29. ;      /*      See extrn statements                                     */
  30. ;      /*                                                               */
  31. ;      /******************* END  OF  SPECIFICATIONS *********************/
  32.  
  33. Serial struc
  34.   comPort        db ?           ; com port number
  35.   port           dw ?           ; base IO port address
  36.   interruptLevel db ?           ; interrupt level
  37.   comdivisor     db ?           ; baud rate divisor value
  38.   comLCR         db ?           ; line control register value
  39.   comMCR         db ?           ; modem control register value
  40.   fcomFIFO       db ?           ; FIFO flag, 1=use it, 0=don't
  41.   comFCR         db 0C7h        ; FIFO control register value
  42.   @processByte   dw 0           ; Addr of routine to process bytes
  43.   @intHandler    dw 0           ; Addr of interrupt handler stub
  44.   @initRtn       dw 0           ; Addr of initialization routine
  45.   @errorRtn      dw 0           ; Addr of initialization routine
  46.   @DCB           dw 0           ; dcb address for this device
  47.   serialStatus   dw 0           ; status flag word
  48.   enable_8259    db 0           ; mask to enable PIC
  49.   disable_8259   db 0           ; mask to disable PIC
  50. Serial ends
  51.  
  52.  
  53. ; bits for serialStatus word
  54. ABIOSLID     EQU 0001h  ; Com port get ABIOS LID failed
  55. COMEXIST     EQU 0002h  ; com port does not exist
  56. SETIRQ_DONE  EQU 0004h  ; SetIRQ successful
  57.  
  58. ; Modem control registers
  59.  
  60. IIRMASK       EQU 11111000B     ; Interrupt ID Register permanent Mask bits
  61. MCRMASK       EQU 00001011B     ; Modem Control Register Mask
  62. IERMASK       EQU 00000001B     ; Interrupt Enable Register Mask
  63. LCRMASK       EQU 00000011B     ; Line Control Reg Mask, 8 data bits 1 stop bit
  64.  
  65. ;-------------------------------------------------------------------
  66. ;  Below are the offsets from the Port Base Address to the various -
  67. ;            Serial Port register addresses                        -
  68. ;-------------------------------------------------------------------
  69.  
  70. TXB              EQU          0     ; Transmit buffer
  71. RXB              EQU          0     ; Receive buffer
  72. LATLSB           EQU          0     ; Divisor latch least sig bits
  73. LATMSB           EQU          1     ; Divisor latch most sig bits
  74. IER              EQU          1     ; Interrupt enable register
  75. IIR              EQU          2     ; Interrupt indentification register
  76. FCR              EQU          2     ; FIFO Control Register
  77. LCR              EQU          3     ; Line control register
  78. MCR              EQU          4     ; Modem control register
  79. LSR              EQU          5     ; Line status register
  80. MSR              EQU          6     ; Modem status register
  81. SCR              EQU          7     ; Scratch register
  82.  
  83. ; These are the values that are written into the divisor latch for the
  84. ;       various baud rates. They are obtained by dividing the clock rate
  85. ;       (1.8432 MHz) by 16x the desired baud rate.
  86. ;
  87.  
  88. DIV_50          EQU     900h
  89. DIV_75          EQU     600h
  90. DIV_110         EQU     417h
  91. DIV_150         EQU     300h
  92. DIV_300         EQU     180h
  93. DIV_600         EQU     0C0h
  94. DIV_1200        EQU     060h
  95. DIV_1800        EQU     040h
  96. DIV_2000        EQU     03Ah
  97. DIV_2400        EQU     030h
  98. DIV_3600        EQU     020h
  99. DIV_4800        EQU     018h
  100. DIV_7200        EQU     010h
  101. DIV_9600        EQU     00Ch
  102. DIV_19200       EQU     006h
  103.  
  104. ;
  105. ;** Interrupt enable masks
  106. ;
  107.  
  108. IE_RX           EQU     00000001b       ; read data available
  109. IE_TX           EQU     00000010b       ; transmit buffer empty
  110. IE_LX           EQU     00000100b       ; line status change
  111. IE_MX           EQU     00001000b       ; modem status change
  112.  
  113. IERMASK         EQU     00000001B       ; Interrupt Enable Register Mask
  114.  
  115. ;
  116. ;** Interrupt identification masks
  117. ;
  118.  
  119. II_PENDING      EQU     00000001b       ; Clear if interrupt pending.
  120. IIRMASK         EQU      0F8H       ; Interrupt ID Register permanent Mask bits
  121.  
  122. ;** FIFO control masks
  123. FIFO_ENABLE     EQU     00000001b
  124. FIFO_DISABLE    EQU     00000000b
  125. FIFOMASK        EQU     01000000b
  126.  
  127. ;
  128. ;** Line control masks
  129. ;
  130.  
  131. LC_BMASK        EQU     00000011b       ; data bits mask
  132. LC_BITS5        EQU     00000000b       ; 5 data bits
  133. LC_BITS6        EQU     00000001b       ; 6 data bits
  134. LC_BITS7        EQU     00000010b       ; 7 data bits
  135. LC_BITS8        EQU     00000011b       ; 8 data bits
  136.  
  137. LC_SMASK        EQU     00000100b       ; stop bits mask
  138. LC_STOP1        EQU     00000000b       ; 1 stop bit
  139. LC_STOP2        EQU     00000100b       ; 2 stop bits (1.5 if 5 data bits)
  140.  
  141. LC_PMASK        EQU     00111000b       ; parity mask
  142. LC_PNONE        EQU     00000000b       ; none parity
  143. LC_PODD         EQU     00001000b       ; odd parity
  144. LC_PEVEN        EQU     00011000b       ; even parity
  145. LC_PMARK        EQU     00101000b       ; mark parity
  146. LC_PSPACE       EQU     00111000b       ; space parity
  147.  
  148. LC_BREAK        EQU     01000000b       ; transmit break
  149. LC_DLAB         EQU     10000000b       ; divisor latch access bit
  150. LC_MASK         EQU     01111111b       ; documented line control register bits
  151.  
  152. ;
  153. ;** Modem control register masks
  154. ;
  155.  
  156. MC_DTR          EQU     00000001b       ; data terminal ready
  157. MC_RTS          EQU     00000010b       ; request to send
  158. MC_OUT1         EQU     00000100b       ; output 1
  159. MC_OUT2         EQU     00001000b       ; output 2
  160. MC_LOOP         EQU     00010000b       ; loopback mode
  161.  
  162. MCRMASK         EQU     00001011B       ; Modem Control Register Mask
  163.  
  164. ;
  165. ;** Line status register masks
  166. ;
  167.  
  168. LS_DR           EQU     00000001b       ; data ready
  169. LS_OERR         EQU     00000010b       ; overrun error
  170. LS_PERR         EQU     00000100b       ; parity error
  171. LS_FERR         EQU     00001000b       ; framing error
  172. LS_BI           EQU     00010000b       ; break interrupt
  173. LS_THRE         EQU     00100000b       ; TX holding register empty
  174. LS_TSRE         EQU     01000000b       ; TX shift register empty
  175.  
  176. ;
  177. ;** Modem status register definitions:
  178. ;
  179.  
  180. MS_DCTS         EQU     00000001b       ; delta clear to send
  181. MS_DDSR         EQU     00000010b       ; delta data set ready
  182. MS_TERI         EQU     00000100b       ; trailing edge of ring indicator
  183. MS_DDCD         EQU     00001000b       ; delta receiver line signal detect
  184. MS_CTS          EQU     00010000b       ; clear to send
  185. MS_DSR          EQU     00100000b       ; data set ready
  186. MS_RI           EQU     01000000b       ; ring indicator
  187. MS_DCD          EQU     10000000b       ; receiver line signal detect
  188.  
  189. ;************************************************************************
  190. ;**     MyIODelay - Perform an IO delay as needed for hardware
  191. ;                   Example Code Only
  192. ;
  193. ;MyIODelay MACRO
  194. ;
  195. ;  push ax
  196. ;  DevIODelay <ax>              ; Trashes AX reg
  197. ;  pop  ax
  198. ;
  199. ;ENDM
  200.  
  201.  
  202.