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C/C++ Source or Header  |  1995-04-14  |  40KB  |  571 lines
  1. /*DDK*************************************************************************/
  2. /*                                                                           */
  3. /* COPYRIGHT    Copyright (C) 1995 IBM Corporation                           */
  4. /*                                                                           */
  5. /*    The following IBM OS/2 WARP source code is provided to you solely for  */
  6. /*    the purpose of assisting you in your development of OS/2 WARP device   */
  7. /*    drivers. You may use this code in accordance with the IBM License      */
  8. /*    Agreement provided in the IBM Device Driver Source Kit for OS/2. This  */
  9. /*    Copyright statement may not be removed.                                */
  10. /*                                                                           */
  11. /*****************************************************************************/
  12. /**************************************************************************
  13.  *
  14.  * SOURCE FILE NAME = atimain.c
  15.  *
  16.  * DESCRIPTIVE NAME = Chip specific PMI functions
  17.  *
  18.  *
  19.  * VERSION = V2.1
  20.  *
  21.  * DATE
  22.  *
  23.  * DESCRIPTION PMI-file handler - Exported entry points
  24.  *
  25.  * FUNCTIONS
  26.  *
  27.  * DEPENDENCIES:
  28.  *
  29.  * NOTES
  30.  *
  31.  * STRUCTURES
  32.  *
  33.  * EXTERNAL REFERENCES
  34.  *
  35.  * EXTERNAL FUNCTIONS
  36.  *
  37. */
  38.  
  39. #pragma langlvl(extended)
  40. #define CHIPS_ALREADY_DEFINED
  41. #include "ipmitype.h"
  42. #include <conio.h>
  43. /*****************************************************************************
  44.  *
  45.  *  FUNCTION NAME:      pfnSetATI32()
  46.  *
  47.  *  DESCRIPTIVE NAME:   Program the clock related registers based on the input data.
  48.  *
  49.  *  FUNCTION:
  50.  *
  51.  *  INPUT:              PVIDEO_ADAPTER - Pointer to current state of the adapter/mode
  52.  *                      PREGS- Pointer to current register state
  53.  *
  54.  *  EXIT:               APIRET - return code
  55.  *
  56.  *  NOTES:              It is not necessary to verify the manufacturer if this
  57.  *                      code handles only one manufacturer per chip. In that case,
  58.  *                      the identify adapter would fail to identify manufacturers which
  59.  *                      are not handled thru the ibmgpmi.dll so no futher calls into this
  60.  *                      dll for services would be expected. However, if there are
  61.  *                      multiple manufacturers (adapter) handled, then this function has
  62.  *                      to specifically identify which one is being handled. 
  63.  *
  64.  *  INTERNAL REFERENCES:
  65.  *    ROUTINES:
  66.  *
  67.  *  EXTERNAL REFERENCES:
  68.  *    ROUTINES:
  69.  ****************************************************************************/
  70. APIRET EXPENTRY  pfnSetATI32(PVIDEO_ADAPTER pAdapter,PREGS pRegs)
  71. {
  72.   ULONG rc = NO_ERROR;
  73.   BYTE r0;
  74.   BYTE bVrtRefresh;
  75.   if (pAdapter->ModeInfo.usType & MODE_FLAG_GRAPHICS)
  76.   {
  77.     switch(pAdapter->ModeInfo.usXResolution)
  78.     {
  79.       case 640:
  80.          switch(pAdapter->ModeInfo.bVrtRefresh)
  81.          {
  82.             default:
  83.             case 60:
  84.            _outp(0x22e8, 0x0043);                                                         
  85.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  86.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  87.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  88.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  89.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  90.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  91.                                                                               
  92.            _outpw(0x12e8, 0x0418);                             /* v_total */              
  93.            _outpw(0x1ae8, 0x03d6);                         /* v_sync_strt */              
  94.            _outpw(0x16e8, 0x03bf);                              /* v_disp */              
  95.            _outp(0x1ee8, 0x22);                             /* v_sync_wid */              
  96.            _outpw(0x02e8, 0x0063);                             /* h_total */              
  97.            _outpw(0x0ae8, 0x0052);                         /* h_sync_strt */              
  98.            _outpw(0x06e8, 0x004f);                              /* h_disp */              
  99.            _outpw(0x0ee8, 0x002c);                          /* h_sync_wid */              
  100.                                                                               
  101.            _outpw(0x26ee, 0x0050);                                                 
  102.            _outpw(0x76ee, 0x0050);                                                        
  103.                                                                                  
  104.            _outpw(0x22e8, 0x0023);                                                        
  105.            _outpw(0x4aee, 0x0251);                 /* dot clock 25.18 Mhz */              
  106.               break;
  107.          }   
  108.          break;
  109.       case 800:
  110.          switch(pAdapter->ModeInfo.bVrtRefresh)
  111.          {
  112.             case 76:
  113.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  114.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  115.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  116.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  117.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  118.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  119.                                                                               
  120.            _outpw(0x12e8, 0x0565);                             /* v_total */              
  121.            _outpw(0x1ae8, 0x04fa);                         /* v_sync_strt */              
  122.            _outpw(0x16e8, 0x04ab);                              /* v_disp */              
  123.            _outp(0x1ee8, 0x24);                             /* v_sync_wid */              
  124.            _outpw(0x02e8, 0x0086);                             /* h_total */              
  125.            _outpw(0x0ae8, 0x006d);                         /* h_sync_strt */              
  126.            _outpw(0x06e8, 0x0063);                              /* h_disp */              
  127.            _outpw(0x0ee8, 0x0028);                          /* h_sync_wid */              
  128.                                                                               
  129.            _outpw(0x26ee, 0x0070);                                                 
  130.            _outpw(0x76ee, 0x0070);                                                        
  131.                                                                               
  132.            _outpw(0x22e8, 0x0023);                                                        
  133.            _outpw(0x4aee, 0x0515);                 /* dot clock 56.64 Mhz */        
  134.               break;
  135.             case 72:
  136.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  137.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  138.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  139.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  140.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  141.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  142.                                                                               
  143.            _outpw(0x12e8, 0x0537);                             /* v_total */              
  144.            _outpw(0x1ae8, 0x04f8);                         /* v_sync_strt */              
  145.            _outpw(0x16e8, 0x04ab);                              /* v_disp */              
  146.            _outp(0x1ee8, 0x06);                            /* v_sync_wid */               
  147.            _outpw(0x02e8, 0x0082);                             /* h_total */              
  148.            _outpw(0x0ae8, 0x006a);                         /* h_sync_strt */              
  149.            _outpw(0x06e8, 0x0063);                              /* h_disp */              
  150.            _outpw(0x0ee8, 0x000f);                          /* h_sync_wid */              
  151.                                                                               
  152.            _outpw(0x26ee, 0x0070);                                                 
  153.            _outpw(0x76ee, 0x0070);                                                        
  154.                                                                               
  155.            _outpw(0x22e8, 0x0023);                                                        
  156.            _outpw(0x4aee, 0x0411);                 /* dot clock 50.35 Mhz */        
  157.               break;
  158.             default:
  159.             case 60:
  160.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  161.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  162.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  163.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  164.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  165.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  166.                                                                               
  167.            _outpw(0x12e8, 0x04e3);                             /* v_total */              
  168.            _outpw(0x1ae8, 0x04b0);                         /* v_sync_strt */              
  169.            _outpw(0x16e8, 0x04ab);                              /* v_disp */              
  170.            _outp(0x1ee8, 0x04);                            /* v_sync_wid */               
  171.            _outpw(0x02e8, 0x0083);                             /* h_total */              
  172.            _outpw(0x0ae8, 0x0068);                         /* h_sync_strt */              
  173.            _outpw(0x06e8, 0x0063);                              /* h_disp */              
  174.            _outpw(0x0ee8, 0x0010);                          /* h_sync_wid */              
  175.                                                                               
  176.            _outpw(0x26ee, 0x0070);                                                 
  177.            _outpw(0x76ee, 0x0070);                                                        
  178.                                                                               
  179.            _outpw(0x22e8, 0x0023);                                                        
  180.            _outpw(0x4aee, 0x0331);                 /* dot clock 40.00 Mhz */        
  181.               break;
  182.          }
  183.          break;
  184.       case 1024:
  185.          switch(pAdapter->ModeInfo.bVrtRefresh)
  186.          {
  187.             case 76:
  188.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  189.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  190.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  191.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  192.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  193.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  194.                                                                               
  195.            _outpw(0x12e8, 0x064a);                             /* v_total */              
  196.            _outpw(0x1ae8, 0x060b);                         /* v_sync_strt */              
  197.            _outpw(0x16e8, 0x05ff);                              /* v_disp */              
  198.            _outpw(0x1ee8, 0x4);                             /* v_sync_wid */               
  199.            _outpw(0x02e8, 0x00a2);                             /* h_total */              
  200.            _outpw(0x0ae8, 0x0087);                         /* h_sync_strt */              
  201.            _outpw(0x06e8, 0x007f);                              /* h_disp */              
  202.            _outpw(0x0ee8, 0xb);                          /* h_sync_wid */                 
  203.                                                                               
  204.            _outpw(0x26ee, 0x0080);                                                 
  205.            _outpw(0x76ee, 0x0080);                                                        
  206.                                                                               
  207.            _outpw(0x22e8, 0x0023);                                                        
  208.            _outpw(0x4aee, 0x062D);                  /* dot clock 80 Mhz */                
  209.               break;
  210.             case 70:
  211.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  212.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  213.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  214.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  215.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  216.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  217.                                                                               
  218.            _outpw(0x12e8, 0x0643);                             /* v_total */              
  219.            _outpw(0x1ae8, 0x0601);                         /* v_sync_strt */              
  220.            _outpw(0x16e8, 0x05ff);                              /* v_disp */              
  221.            _outp(0x1ee8, 0x08);                             /* v_sync_wid */              
  222.            _outpw(0x02e8, 0x00a6);                             /* h_total */              
  223.            _outpw(0x0ae8, 0x0083);                         /* h_sync_strt */              
  224.            _outpw(0x06e8, 0x007f);                              /* h_disp */              
  225.            _outpw(0x0ee8, 0x0016);                          /* h_sync_wid */              
  226.                                                                               
  227.            _outpw(0x22e8, 0x0023);                                                        
  228.            _outpw(0x4aee, 0x0639);                    /* dot clock 75 Mhz */              
  229.                                                                               
  230.            _outpw(0x26ee, 0x0080);                                                 
  231.            _outpw(0x76ee, 0x0080);                                                        
  232.               break;
  233.             case 72:
  234.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  235.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  236.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  237.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  238.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  239.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  240.                                                                               
  241.            _outpw(0x12e8, 0x0649);                             /* v_total */              
  242.            _outpw(0x1ae8, 0x0602);                         /* v_sync_strt */              
  243.            _outpw(0x16e8, 0x05ff);                              /* v_disp */              
  244.            _outp(0x1ee8, 0x26);                             /* v_sync_wid */              
  245.            _outpw(0x02e8, 0x00a1);                             /* h_total */              
  246.            _outpw(0x0ae8, 0x0082);                         /* h_sync_strt */              
  247.            _outpw(0x06e8, 0x007f);                              /* h_disp */              
  248.            _outpw(0x0ee8, 0x0032);                          /* h_sync_wid */              
  249.                                                                               
  250.            _outpw(0x22e8, 0x0023);                                                        
  251.            _outpw(0x4aee, 0x0639);                   /* dot clock 75 Mhz */             
  252.                                                                               
  253.                                                                               
  254.            _outpw(0x26ee, 0x0080);                                                 
  255.            _outpw(0x76ee, 0x0080);                                                        
  256.               break;
  257.             case 60:
  258.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  259.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  260.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  261.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  262.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  263.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  264.                                                                               
  265.            _outpw(0x12e8, 0x063b);                             /* v_total */              
  266.            _outpw(0x1ae8, 0x0600);                         /* v_sync_strt */              
  267.            _outpw(0x16e8, 0x05ff);                              /* v_disp */              
  268.            _outp(0x1ee8, 0x04);                             /* v_sync_wid */              
  269.            _outpw(0x02e8, 0x00a7);                             /* h_total */              
  270.            _outpw(0x0ae8, 0x0085);                         /* h_sync_strt */              
  271.            _outpw(0x06e8, 0x007f);                              /* h_disp */              
  272.            _outpw(0x0ee8, 0x0008);                          /* h_sync_wid */              
  273.                                                                               
  274.            _outpw(0x22e8, 0x0023);                                                        
  275.            _outpw(0x4aee, 0x053d);                    /* dot clock 65 Mhz */              
  276.                                                                               
  277.            _outpw(0x26ee, 0x0080);                                                 
  278.            _outpw(0x76ee, 0x0080);                                                        
  279.             default:
  280.             case 44:
  281.             case 87:
  282.             case 43:
  283.            _outpw(0x5aee, 0x0001);                /* shadow CRT registers */              
  284.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  285.            _outpw(0x5aee, 0x0002);                /* shadow CRT registers */              
  286.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  287.            _outpw(0x5aee, 0x0000);                /* shadow CRT registers */              
  288.            _outpw(0x4ae8, 0x0006);                 /* disable passthrough */              
  289.                                                                               
  290.            _outpw(0x12e8, 0x0660);                             /* v_total */              
  291.            _outpw(0x1ae8, 0x0600);                         /* v_sync_strt */              
  292.            _outpw(0x16e8, 0x05ff);                              /* v_disp */              
  293.            _outp(0x1ee8, 0x08);                             /* v_sync_wid */              
  294.            _outpw(0x02e8, 0x009d);                             /* h_total */              
  295.            _outpw(0x0ae8, 0x0081);                         /* h_sync_strt */              
  296.            _outpw(0x06e8, 0x007f);                              /* h_disp */              
  297.            _outpw(0x0ee8, 0x0016);                          /* h_sync_wid */              
  298.                                                                               
  299.            _outpw(0x22e8, 0x0033);                                                        
  300.            _outpw(0x4aee, 0x031d);                    /* dot clock 45 Mhz */              
  301.                                                                               
  302.            _outpw(0x26ee, 0x0080);                                                 
  303.            _outpw(0x76ee, 0x0080);                                                        
  304.               break;
  305.          }
  306.          break;
  307.       case 1280:
  308.          bVrtRefresh = pAdapter->ModeInfo.bVrtRefresh;
  309.          if (DACType != ATI68875_DAC) 
  310.          {
  311.            /*
  312.            ** support only interlaced
  313.            */
  314.            bVrtRefresh = 46;
  315.          }
  316.          switch(bVrtRefresh)
  317.          {
  318.             case 74:
  319.            _outpw(0x22e8, 0x0043);                           /* disp_cntl */              
  320.            _outpw(0x4aee, 0x0e21);                /* dot clock 135.00 Mhz */              
  321.                                                                               
  322.            _outpw(0x5aee, 0x0002);              /* shadow 2 CRT registers */              
  323.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  324.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  325.                                                                               
  326.            _outpw(0x02e8, 0x00d5);                             /* h_total */              
  327.            _outpw(0x06e8, 0x009f);                              /* h_disp */              
  328.            _outpw(0x0ae8, 0x00a3);                         /* h_sync_strt */              
  329.            _outpw(0x0ee8, 0x0012);                          /* h_sync_wid */              
  330.                                                                               
  331.            _outpw(0x12e8, 0x084b);                             /* v_total */              
  332.            _outpw(0x16e8, 0x07ff);                              /* v_disp */              
  333.            _outpw(0x1ae8, 0x07ff);                         /* v_sync_strt */              
  334.            _outpw(0x1ee8, 0x001e);                          /* v_sync_wid */              
  335.                                                                               
  336.            _outpw(0x22e8, 0x0023);                           /* disp_cntl */              
  337.                                                                               
  338.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  339.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  340.                                                                               
  341.               _outpw(0x46ee, 0x003f);                          /* shadow_ctl */
  342.                                                                                 
  343.                                                                                 
  344.               /* Set DAC values for MUX mode */                                  
  345.                                                                                 
  346.               /* disable vga pass through and set pixel clock slow */        
  347.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  348.               _outp(0x4aee, 0x51);                           /* clock_sel */   
  349.                                                                               
  350.                                                                               
  351.               /* config High DAC addr via ext_ge_config and set to 8bpp */   
  352.               _outpw(0x7aee, 0x201a);                       /* ext_ge_config */
  353.                                                                               
  354.                                                                               
  355.               /* set input_clk_sel, output_clk_sel, and mux_ctl */           
  356.               _outp(0x02ed, 0x01);                   /* input_clk_sel - last */
  357.               _outp(0x02ea, 0x09);                         /* _outpput_clk_sel */
  358.               _outp(0x02eb, 0x1d);                                /* mux_ctl */
  359.                                                                              
  360.                                                                              
  361.                                                                              
  362.                                                                              
  363.               /* reset ext_ge_config to 8bpp and select multiplex pixels */  
  364.               /* also select 6-bit DAC operation */                          
  365.               _outpw(0x7aee, 0x011a);                       /* ext_ge_config */
  366.                                                                              
  367.                                                                              
  368.               /* set pixel_delay, blank_adjust, horizontal_skew */           
  369.               /* blank_adjust = 1, pixel_delay = 0. */                       
  370.                                                                              
  371.               r0 = _inp(0x92ef);                            /* r_rom_cntl + 1 */
  372.               r0 &= 0xf0;
  373.               r0 |= 0x01;
  374.               _outp(0x7eef, r0);                      /* rom_eeprom_cntl + 1 */
  375.                                                                              
  376.                                                                              
  377.                                                                              
  378.                                                                              
  379.               /* set dac_mask to 0xff for 8bpp */                            
  380.               _outp(0x02ea, 0xff);                               /* dac_mask */
  381.                                                                               
  382.                                                                               
  383.            _outpw(0x4aee, 0x0e21);                     /* reset clock_sel */              
  384.            _outpw(0x4ae8, 0x0007);               /* re enable 8514 compat */              
  385.                                                                               
  386.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  387.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  388.                                                                               
  389.               break;
  390.             case 70:
  391.            _outpw(0x22e8, 0x0043);                            /* disp_cntl */             
  392.            _outpw(0x4aee, 0x0e05);                            /* clock_sel */             
  393.                                                                               
  394.            _outpw(0x5aee, 0x0002);              /* shadow 2 CRT registers */              
  395.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  396.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  397.                                                                               
  398.            _outpw(0x02e8, 0x00d2);                             /* h_total */              
  399.            _outpw(0x06e8, 0x009f);                              /* h_disp */              
  400.            _outpw(0x0ae8, 0x00a9);                         /* h_sync_strt */              
  401.            _outpw(0x0ee8, 0x000e);                          /* h_sync_wid */              
  402.                                                                               
  403.            _outpw(0x12e8, 0x0851);                             /* v_total */              
  404.            _outpw(0x16e8, 0x07ff);                              /* v_disp */              
  405.            _outpw(0x1ae8, 0x0800);                         /* v_sync_strt */              
  406.            _outpw(0x1ee8, 0x0005);                          /* v_sync_wid */              
  407.                                                                               
  408.            _outpw(0x22e8, 0x0023);                            /* disp_cntl */             
  409.                                                                               
  410.            _outpw(0x26ee, 0x00a0);                            /* crt_pitch */      
  411.            _outpw(0x76ee, 0x00a0);                             /* ge_pitch */             
  412.                                                                               
  413.               _outpw(0x46ee, 0x003f);                           /* shadow_ctl */                                                                             
  414.                                                                                 
  415.                                                                                 
  416.               /* Set DAC values for MUX mode */                                  
  417.                                                                               
  418.               /* disable vga pass through and set pixel clock slow */        
  419.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  420.               _outp(0x4aee, 0x51);                           /* clock_sel */   
  421.                                                                               
  422.                                                                               
  423.               /* config High DAC addr via ext_ge_config and set to 8bpp */   
  424.               _outpw(0x7aee, 0x201a);                       /* ext_ge_config */
  425.                                                                               
  426.                                                                               
  427.               /* set input_clk_sel, output_clk_sel, and mux_ctl */           
  428.               _outp(0x02ed, 0x01);                   /* input_clk_sel - last */
  429.               _outp(0x02ea, 0x09);                         /* output_clk_sel */
  430.               _outp(0x02eb, 0x1d);                                /* mux_ctl */
  431.                                                                               
  432.                                                                               
  433.                                                                               
  434.               /* reset ext_ge_config to 8bpp and select multiplex pixels */  
  435.               /* also select 6-bit DAC operation */                          
  436.               _outpw(0x7aee, 0x011a);                       /* ext_ge_config */
  437.                                                                               
  438.                                                                               
  439.               /* set pixel_delay, blank_adjust, horizontal_skew */           
  440.               /* blank_adjust = 1, pixel_delay = 0. */                       
  441.                                                                               
  442.               r0 = _inp(0x92ef);                            /* r_rom_cntl + 1 */
  443.               r0 &= 0xf0;
  444.               r0 |= 0x01;
  445.               _outp(0x7eef, r0);                      /* rom_eeprom_cntl + 1 */
  446.                                                                               
  447.                                                                               
  448.                                                                               
  449.                                                                               
  450.               /* set dac_mask to 0xff for 8bpp */                            
  451.               _outp(0x02ea, 0xff);                               /* dac_mask */
  452.                                                                               
  453.                                                                               
  454.            _outpw(0x4aee, 0x0e05);                     /* reset clock_sel */              
  455.            _outpw(0x4ae8, 0x0007);               /* re enable 8514 compat */              
  456.                                                                               
  457.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  458.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  459.               break;
  460.             case 60:
  461.               /* Set CRTC values into Shadow Set 2 then select it */             
  462.                                                                                  
  463.            _outpw(0x22e8, 0x0043);                           /* disp_cntl */              
  464.            _outpw(0x4aee, 0x0a29);                /* dot clock 110.00 Mhz */              
  465.                                                                              
  466.                                                                              
  467.            _outpw(0x5aee, 0x0002);              /* shadow 2 CRT registers */              
  468.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  469.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  470.                                                                              
  471.                                                                              
  472.            _outpw(0x02e8, 0x00d6);                             /* h_total */              
  473.            _outpw(0x06e8, 0x009f);                              /* h_disp */              
  474.            _outpw(0x0ae8, 0x00a9);                         /* h_sync_strt */              
  475.            _outpw(0x0ee8, 0x002e);                          /* h_sync_wid */              
  476.                                                                              
  477.            _outpw(0x12e8, 0x0852);                             /* v_total */              
  478.            _outpw(0x16e8, 0x07ff);                              /* v_disp */              
  479.            _outpw(0x1ae8, 0x0800);                         /* v_sync_strt */              
  480.            _outpw(0x1ee8, 0x0025);                          /* v_sync_wid */              
  481.                                                                               
  482.            _outpw(0x22e8, 0x0023);                           /* disp_cntl */              
  483.                                                                               
  484.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  485.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  486.                                                                               
  487.               _outpw(0x46ee, 0x003f);                          /* shadow_ctl */
  488.                                                                                   
  489.               /* Set DAC values for MUX mode */                                  
  490.                                                                                   
  491.               /* disable vga pass through and set pixel clock slow */        
  492.            _outpw(0x4ae8, 0x0007);                 /* disable passthrough */              
  493.               _outp(0x4aee, 0x51);                           /* clock_sel */   
  494.                                                                              
  495.                                                                              
  496.               /* config High DAC addr via ext_ge_config and set to 8bpp */   
  497.               _outpw(0x7aee, 0x201a);                       /* ext_ge_config */
  498.                                                                              
  499.                                                                              
  500.               /* set input_clk_sel, output_clk_sel, and mux_ctl */           
  501.               _outp(0x02ed, 0x01);                   /* input_clk_sel - last */
  502.               _outp(0x02ea, 0x09);                         /* output_clk_sel */
  503.               _outp(0x02eb, 0x1d);                                /* mux_ctl */
  504.                                                                              
  505.                                                                              
  506.                                                                              
  507.                                                                              
  508.               /* reset ext_ge_config to 8bpp and select multiplex pixels */  
  509.               /* also select 6-bit DAC operation */                          
  510.               _outpw(0x7aee, 0x011a);                       /* ext_ge_config */
  511.                                                                              
  512.                                                                              
  513.               /* set pixel_delay, blank_adjust, horizontal_skew */           
  514.               /* blank_adjust = 1, pixel_delay = 0. */                       
  515.                                                                              
  516.               r0 = _inp(0x92ef);                            /* r_rom_cntl + 1 */
  517.               r0 &= 0xf0;
  518.               r0 |= 0x01;
  519.               _outp(0x7eef, r0);                      /* rom_eeprom_cntl + 1 */
  520.                                                                               
  521.                                                                               
  522.                                                                               
  523.                                                                               
  524.               /* set dac_mask to 0xff for 8bpp */                            
  525.               _outp(0x02ea, 0xff);                               /* dac_mask */
  526.                                                                               
  527.                                                                               
  528.            _outpw(0x4aee, 0x0a29);                     /* reset clock_sel */              
  529.            _outpw(0x4ae8, 0x0007);               /* re enable 8514 compat */              
  530.                                                                             
  531.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  532.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  533.               break;                                                                  
  534.             default:
  535.             case 46:
  536.            _outp(0x22e8, 0x0043);                            /* disp_cntl */              
  537.            _outpw(0x4aee, 0x062d);                           /* clock_sel */              
  538.                                                                               
  539.            _outpw(0x5aee, 0x0000);            /* non-shadow CRT registers */              
  540.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  541.            _outpw(0x5aee, 0x0001);              /* shadow 1 CRT registers */              
  542.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  543.            _outpw(0x5aee, 0x0002);              /* shadow 2 CRT registers */              
  544.            _outpw(0x46ee, 0x0000);                       /* unlock values */              
  545.            _outpw(0x4ae8, 0x0005);                 /* disable passthrough */              
  546.                                                                               
  547.            _outpw(0x02e8, 0x00c7);                             /* h_total */              
  548.            _outpw(0x06e8, 0x009f);                              /* h_disp */              
  549.            _outpw(0x0ae8, 0x00a9);                         /* h_sync_strt */              
  550.            _outpw(0x0ee8, 0x000a);                          /* h_sync_wid */              
  551.                                                                               
  552.            _outpw(0x12e8, 0x08f8);                             /* v_total */              
  553.            _outpw(0x16e8, 0x07ff);                              /* v_disp */              
  554.            _outpw(0x1ae8, 0x0811);                         /* v_sync_strt */              
  555.            _outpw(0x1ee8, 0x000a);                          /* v_sync_wid */              
  556.                                                                               
  557.            _outpw(0x26ee, 0x00a0);                           /* crt_pitch */       
  558.            _outpw(0x76ee, 0x00a0);                            /* ge_pitch */              
  559.                                                                               
  560.               _outpw(0x46ee, 0x003f);                          /* shadow_ctl */
  561.                                                                               
  562.            _outpw(0x22e8, 0x0033);                           /* disp_cntl */              
  563.               break;
  564.          }
  565.       default:
  566.          rc = ERROR_MODE_NOT_SUPPORTED;
  567.     }
  568.   }
  569.   return rc;
  570. }
  571.