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EEEEEEEE K A | EE R R EE K AA | The BITS ArcSIG EE U U RR RR E E K K A A | Newsletter EEEEEEE U U R EEEE KK AA A | EE U U R E K K A AA | Issue #02 EEEEEEEE UUUU R EEE K K A A | Compiled and Linked by Dave ---------------------------------------------------------------------------- *INFO ~~~~~ First of all, a little home news; Rob Wheeler has set up an Archimedes forum on seqa; many thanks Rob, and I hope you get some lively debates and hack interchanges going. I'll have to get myself a seqa account one of these days.... Also, the planned instalment of "Down to the Metal" has been postponed, as we present instead, after much hackification and scouring of docs, the first release of the Assembler Programmer's Pocket Guide. For those of you who don't know already (yes, both of you), RISC OS 3.10 has been released, priced #40 for the full set including User Guide, and a mere #20 for the "A5000 Upgrade," which doesn't include the docs. This leaves me with the impression that 3.10 is basically 3.00 with most of the major bugs fixed, but I will reserve full judgement until my copy shows up. Latest news from the AU show is that the RISC OS 3 Programmer's Reference Manual is on release, in draft (beta test) form; it's rather shorter than I'd heard (5 volumes instead of the expected 7), although this may change in the final release version. Purchasers of the draft will get a free copy of the production version when it has been completed. Price is #120; time for a nice talk with my bank manager, I think. As stated in the last issue of EurekA, the new ARM250 based A3010, 3020 and 4000 have arrived; this represents an interesting move by Acorn, in that they are now attacking the price bracket currently held, and very successfully so, by the 16 bit "home" machines. The ARM250 itself is a major exercise in IC integration, as it contains the standard 4-chip ARM set (ARM, MEMC, VIDC, IOC), crunched down onto a single wafer. Among other things (like a reduction in production costs), this squeezes another 2 MIPS out of the processor, as compared to the standard ARM2 around which it is based. The number of discrete components on the motherboard has been dramatically reduced; I hear that the 3010 only has about 6 ICs in it, total. Although this move throws upgradability options clean out the window (with the honourable exception of a 3000-like half-size podule slot), the speed increase could be very interesting if applied to a hypothetical "ARM350." Rumours still abound about the possibility of a new top-end Archimedes to replace the now aging A540, obviously fuelled by the fact that RISC OS 3.10 is aware of the new ARM610 chip, based on the 600 design macro and coming into circulation soon inside Apple's Newton palmtop. Whether this will mean an entirely new machine, a drop-in processor board replacement for the 540 or maybe even both remains to be seen, but as the 610 may be built into a parallel architecture, the 4-processor ARM610 Hypercube is not an impossibility. Also (tear, rend) the FPA, promised for this month, still hasn't shown up. Please correct me if I'm wrong on this, as I want one! *OBEY !RUN ~~~~~~~~~ Marginal Hacks (Part 10 of 1<<31) ~~~~~~~~~~~~~ Further to the discussion in the last issue on undocumented device streams,three more have surfaced. These are: kbd: Keyboard (input only), returned by OS_ReadLine rawkbd: Keyboard (input only), returned by OS_ReadC rawvdu: VDU output, issued via OS_WriteC In addition, the vdu: stream described previously is processed by GS_Read before being directed to OS_WriteC. Also, some interesting but so far unverified hacks have come to me via the bush telegraph: First, from Rob Wheeler, an easter egg in RISC OS 3.10: let !formed be seen by the filer. open Resources::resources.$.resources.fileswitch (might be filer) load in the template file - have a look at 'report' or some similar file see an interesting message. And from Graham Willmott, a way to get anti-aliased fonts as default on the Desktop under RISC OS 2.00: Save the WindowManager module to disk and reload at &8000. Turn the conditional branch at &10534 to a NOP (ie E1A00000 since Acorn don't want us to use the NV condition code any more). Resave and make it a module. You will have to load it from outside the desktop, after setting Wimp$Path to a suitable templates directory. What is does is this - since the WIMP templates are loaded by all sorts of different modules, I decided that the only way to force it to load the fonts without an "Unable to bind..." error was to make it look for fonts in all template files; ie to ignore the font flag in the LoadTemplate SWI (assuming that it is a font flag; I have no manual, remember.) At least I think that's how it works. Features ~~~~~~~ Trials and Tribulations of the PCM (Part 2) ---------------------------------- Since EurekA #01, I've upgraded to the 1.81 version of the PCM; although it's nice to have VGA graphics at last, I feel obliged to issue the following warning: When you install the new PCEm on your hard drive and configure a partition, you may have to do a complete DOS reformat and reinstall; especially if you decide to use the VGA driver set. I found out (by playing around with MultiFS) that the new emulator stores the PC data differently, so be certain that your virtual PC drive is fully backed up before making the upgrade. Also, the old (1.60) MultiFS doesn't work with the new emulator's storage format, so be sure to install the new version of this, too. I recently acquired a DOS-based program from Compu$erve, which is designed to give full information about the system it is running on; this is what it made of the Acorn virtual PC. Advanced Personal Systems SYSCHK Information Printout Tuesday, Oct. 27, 1992 Version: 2.34 PROCESSOR------------------------------------------------------------------- Model: IBM PC Processor: 8088 Coprocessor:Unknwn SYSTEM BIOS----------------------------------------------------------------- Source: Unknown Date: 11/08/82 BIOS Extentsions:(none) INPUT/OUTPUT---------------------------------------------------------------- Keyboard: 101 Key Enhanced Mouse Installed: No Parallel Ports: 1 Device Base Address LPT1 378h Serial Ports: 1 Device Base Address UART 3F8h COM1 8250 HARD DISKS------------------------------------------------------------------ Tracks: 863 Heads: 6 Sectors Per Track: 17 Size: 42.98 MB Logical Drives: A: B: C: FLOPPY DISKS---------------------------------------------------------------- Floppy Disk 1: 720 KB 3+" Floppy Disk 2: 720 KB 3+" VIDEO----------------------------------------------------------------------- Active Video: VGA + Analog Color Monitor BIOS Source: No Copyright found MEMORY---------------------------------------------------------------------- Conventional Memory: 640 KB (572 KB Free) Extended Memory: None Expanded Memory: RESIDENT PROGRAMS----------------------------------------------------------- Program Name Size Program Interfaces ------------ ------------------------------ DOS Kernel 0k DOS Config 17k (Files = 30, Buffers = 0) COMMAND.COM 5k Microsoft DOS 5.0 SPEED----------------------------------------------------------------------- Throughput Speed: 71.74MHz CPU Clock Speed: 9 MHz Interesting results, these. The first thing to note is that the program reports the machine as being based on the 8088, as opposed to the Acorn-claimed 80188. Apparently, this is because the 188 was never actually used as a PC main processor, its main circulation being as a microcontroller. Very surprisingly, the program failed to identify the emulated 8087 math co-pro. Looking at the BIOS, it is clear that Acorn either fudged the date or paid licence fees to legitimately copy someone else's BIOS; probably IBM's own. However, the program cannot find a copyright, which is a point for concern. I/O: Bang on right. I didn't have AMOUSE.COM installed at the time I ran the prog, but I'll check on this at a later date. Having run the program on a friend's 386SX clone, I noted that his UART maps in at 16450, but this is probably a side effect of the different virtual architecture. Drives: I could have sworn (and indeed I do) that I never set a second floppy. However, I like the emulation of the hard drive partition right down to the number of heads, but this may just be either a function of the program or the real drive may be a 6-header (as it's a 120Mb Conner, about 2 cm thick, I doubt this latter possibility). Video: Same again; no copyright. However, it's interesting that the VGA drivers actually register the Arc monitor type, as opposed to just driving a virtual display which the Arc then interprets transparently. One of the more useful features in the 1.81 is the ability to use expanded memory; for those of you who don't know PCs, memory is split into conventional, high, extended and/or expanded, ie a right mess compared with our flat model. The latter two types require extra software drivers to enable the processor to map them. Unfortunately, expanded is the slower of the two, as it operates by swapping pages with a page designated in processor-mappable me mory. Needless to say, some PC programs need this flavour of memory, despite the fact that most current PCs are now equipped with extended instead. This requires a patch for extended to emulate expanded...pity it's not possible to produce one the other way around. Speed: A bit lost for words here. From what I can gather, the CPU clock speed is about right. However, the processor throughput appears to be "leaking" into native ARM-like speeds (my friend's 20 MHz 386 clocked a throughput of 25.72 MHz). Either this is the correct case, or it's the rest of the surrounding emulated chippery which loses us all the speed on the emulator. This is definitely worth looking into. BAU Show Review: Courtesy of Rob Wheeler ---------------------------------------- This is a list of vendors present at the recent Acorn User show, and their latest products. However, some of the hoped-for major products proved to be still unavailable, the most notable case being the Floating Point Accelerator chip from Acorn, designed to go into the A5000 and A540. Many thanks to Rob for this list, and the accompanying brief reviews. Acorn: all new machines on display, staff wearing technicolour 'dream'coats riscos3.1 prms available in draft - cash or cheque not plastic loads of interest in pocket book and a4. Aleph One / Atomwide: new cyrix 486slx card 1-4Mb RAM - 700quid prices down on 386 cards - new windows driver software claims to make an arm/386slx faster at windows than a true 33MHz486dx plenty of 8Mb upgrades for machines with upper limits of 4Mb new AUN / Ethernet cards available. Archimedes World / BBC Acorn User / Micro User (under new name): usual stuff - old mags at no discount Beebug/ Risc Developements: nothing new - just a wide selection from their store at minimal show discount. BirdTech: various packages for high quality colour printing Calligraph: new 12ppm 600dpi laser printer for under a grand Clares: Rhapsody3, other new music stuff, csv data plotter Colton: Pipedream4 - no new stuff CC & Wild Vision: Artworks - looks nice'n'fast as promissed - _very_ fast seller Colour Card - 512k onboard ram, 24bit palette, 65536 max colours on screen, 256 colour desktop up to 1024x768 - nice bar price - 300quid Impression 2.18 - less bugs Compression - now riscos 3 compatible Digital Services: new version of squirrel - better parser and inter-system compatibility EMR: Usual musical stuff. EFF: Loads of new fonts. ICS: ColourSep - 24bit cmyk splitting software for arcs, full review follows (when i get it) but it looks very good. Icon: Easiwriter2 and Techwriter - set to hit CC very hard if they dont improve impression/equasor very soon. Integrex: more colour printers. Irlam Instruments: i-Mage. Proi-Mage - realtime video digitisers and flatbed colour scanners - all run in desktop Moving i-Mage - real time video in a window Krisalis: Loads of new 16bit conversions: Populous - port of Bulfrogs game where you play one of two gods trying to gain total control of a world by defeating non-believers and increasing your own 'flock' - well worth getting, (populousII next year) Lotus turbo espriteII - 1 or 2 player car racing game - like outrun but _much_ better - looks very good when played on two machines. Omar Sharif's Bridge - samples of the man himself on the game, good tutorial section, but the computer does play some _very strange_ cards sound effects are really irritating after a while, the manual is lousy sections for pc, atari, amiga but not arc - extra features not easy to get - not worth getting unless you want to have fun - not really for serious play (unless you play as four humans and no computer players) Millipede: videographics boards - realtime image manipulation. Minerva: nothing amazing but plenty of good software. Morley: loads of reasonably priced scsi addons ruined by an expensive card, the card can be got for half their price at cj computing - westbury new back up software for streamers/ floppies. TDK: buy a tdk colour 5 pack of disks and try to win an a4 - offer still valid. 4th dimension: loads of new games: chopper force (at last): good but if you've ever played gunship2000 on the pcs leave this one out and get gunship and an aleph one pc card black angel, dungeon and galactic dan! also released. Serial port: floptical drives on sale, arcterm 7 - new comms software !sparkfs - new archive file system from david pilling _very_ good will read almost any archive except !cfs - faster than arcfs and more compatible with unix/pc/mac systems Turcan Research: Dreadnoughts - WWI naval warfare system - _very_ good gameplay, graphics are slowish and it returns to mode 12 on the desktop but is very well thought out and well worth getting. Watford Electronics: the usual over priced under supported stuff (unbiassed honest) State Machine: g8 graphics card - more of a vidc1a booster than a separate card like cc's colour card - dont buy either untill full reviews have been done comparing the two. Guile: wierd flight-sim-in-a-dungeon-adventure type game. ARM Assembler Programmer's Pocket Reference ------------------------------------------- After many problems trying to get the text to print sideways on a sheet of A4 small enough to fit, while remaining legible, I've decided to issue the first release as part of EurekA in the hope that those who want copies can assemble their own until I can get things working properly. Read, enjoy, hardcopy and have fun with photo-reducing so it'll actually go in a pocket. If there are _ANY_ errors, please get back to me ASAP. ----------------------------------------------------------------------------- ARM ASSEMBLER PROGRAMMER'S POCKET REFERENCE (v.0.1A) A BITS PUBLICATION WRITTEN AND ENTERED INTO THE PUBLIC DOMAIN BY DAVE WALKER NOVEMBER 1992 (CORRECTIONS FOR VER A BY GRAHAM WILLMOTT) Memory Assignment, Parameter Passing and Assembly Directives ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Memory is reserved with DIM &<code length> ; set P% to start of code as normal. P% acts as (usual) load address, and then execute address. O% may be used for offset assembly, as with the Acorn Proton; however this is now redundant as RMs are NOT paged, but sent to the Heap Manager. Range checking has now been implemented, so program assembly aborts if reserved memory is exceeded. This is done using L%, and produces a listing like: DIM code% 256 P%=code% L%=P%+256 [.... Parameters may be passed to an assembler program either by assigning integers to variables A% to H % which are then copied into R0-R7, or by using CALL <address> {<parameters>} The parameter set may be decoded by examining R9 and R10 on entry to the routine; R9 contains a pointer to the parameter descriptor block, and R10 contains the number of parameters passed. The memory block indicated by R9 has a 2-word entry in it for each parameter, the entries being set up in reverse order (last parameter passed is described by first 2 words of block). The first word of an entry is a pointer to the address where the variable itself is stored (or, in the case of a string, to where a pointer to it is stored), and the second word indicates the type of the variable. Type number First word points to Example of possible BASIC var passed ----------- -------------------- ------------------------------------ 0 Single-byte number ?var 4 4-byte integer !var,var%,var%(n) 5 5-byte real var, var(n) 128 String info block var$, var$(n) 129 Terminated char string $var 256+4 Integer array block var%() 256+5 Real array block var() 256+128 String array block var$ The locations pointed to by the first word are not guaranteed to be word-aligned. In the case of types 4, 5 and 129, the first word points directly to the variable; otherwise, it points to a further information block. For the case of strings, the first word points to a word-aligned string information block, which has the format Bytes 0-3: Pointer to the characters comprising the string Byte 4: Current number of characters in the string. The value of R0 produced by a routine may be read back into a BASIC variable using the command <var>=USR(<routine entry point>) Registers and Processor Modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ User Mode --------- 16 registers, R0-R15, visible. Conventionally: R13 used as primary stack pointer R14 used as link register R0-R12 are general and available. R15 used as program counter (PC) and is also location of status flags: Bits 2-25 used as PC; "current" memory location is 2 instructions (8 bytes) past instruction being executed, as a result of pipelining. Need subtraction to compensate when writing interrupt routines. Bits 26-31 are the main status flags: Bit Letter Description --- ------ ----------- 26 F Fast Interrupt disable 27 I Interrupt disable 28 V Arithmetic overflow 29 C Carry 30 Z Zero 31 N Negative Bits 0 and 1 set processor status mode: Bit 1 (S1) Bit 0 (S0) Mode ---------- ---------- ---- 0 0 User (default) 0 1 Fast interrupt (FIQ) 1 0 Interrupt (IRQ) 1 1 Supervisor (SVC) Interrupts may NOT be disabled by directly writing masked bits to R15 in User Mode, but SWI"IntOn" and SWI"IntOff" may be used to toggle IRQ (bit 27). FIQ Mode -------- R8-R14 are replaced by private R8_FIQ - R14_FIQ IRQ Mode -------- R13 and R14 replaced by private R13_IRQ and R14_IRQ SVC Mode -------- R13 and R14 replaced by private R13_SVC and R14_SVC. Direct writing to writable support hardware is permitted. All hardware devices are memory mapped. Interrupts and SVC Mode ----------------------- SWI calls WILL corrupt R14_SVC. When executing an SWI from IRQ or FIQ, the code supplied by Acorn to get round this is: MOV R9,PC ; Preserve current processor mode ORR R8,R9,#3 ; Move to R8, selecting SVC mode TEQP R8,#0 ; Enter SVC mode MOVNV R0,R0 ; No-op to sync internal registers STMFD R13!,{R14} ; Preserve R14_SVC on SVC stack <Insert necessary SWI calls here> LDMFD R13!,{R14} ; Restore R14_SVC from SVC stack TEQP R9,#0 ; Back to original processor mode MOVNV R0,R0 ; No-op to sync internal registers In IRQ and FIQ modes, it is necessary to set bits 26 and 27 of R15, and then reset them before re-entering User mode. Assembler Mnemonics ~~~~~~~~~~~~~~~~~~ Register Loading ---------------- MOV <reg>,<expr> Loads register with absolute value of expression; ie if expression is a label, the absolute address of same at compile time. Affects N,Z. MVN <reg>,<op1> Loads NOT(op1) into reg. As 2's complement is -n=NOT(n)+1, use MVN <reg>,(n-1) to load reg with -n. ADR <reg>,<expr> Loads register with address given as offset from P%, giving relocatable code. For expr=label, the offset calculations are user-transparent. Shift Instructions ------------------ LSL#n or Rx Shifts the operated register left by n places, or by the no. of places indicated by Rx. Zeroes are inserted into bit 0, successive bit 31s are shifted into the carry, overflow is lost. ASL #n or Rx Use is exactly the same as LSL. LSR #n or Rx Zeroes inserted at bit 31; data shifted right and through bit 0. Data overflow at least significant end is lost. ASR #n or Rx As LSR, but bit 31 (sign) is preserved and bit 0 moves into the carry. For a shift of 1 place, bit 31 is copied to bit 30; afterwards treat as an LSR on a 31 bit word, bit 32 remaining signed. ROR #n or Rx Barrel shift right n places; bits move from bit 0 to bit 31. A copy of the initial bit 0 is preserved in the carry flag. RRX Rotate right by one place, using the carry as a "bit 32." Bit 0 goes to the carry, the carry goes to bit 31 etc. Essentially, a 33 bit rotate. Logical Processing Instructions ------------------------------- ADD <dest>,<op1>,<op2> Add operand 1 to operand 2, store in destination. N,Z,C,V are updated. ADC <dest>,<op1>,<op2> As ADD, but accounts for the initial status of the carry flag. N,Z,C,V affected if S suffix used. SUB <dest>,<op1>,<op2> Subtract operand 2 from operand 1, store in destination. Valid if op1 and op2 are both unsigned or both 2's complement. Affects N,Z,C,V if S suffix used. SBC <dest>,<op1>,<op2> Subtract with carry; ie dest=op1-op2-NOT(carry). Affects N,Z,C,V if S suffix used. RSB <dest>,<op1>,<op2> Subtract op1 from op2, so shift ops can be done on op2. Affects N,Z,C,V. RSC <dest>,<op1>,<op2> dest=op2-op1-NOT(carry). Affects N,Z,C,V. CMP <op1>,<op2> Reflect notional result of op1-op2 in N,Z,C,V flags. S suffix is implicitly assumed. CMN <op1>,<op2> Reflect notional result of op1-(-op2). Note not NOT(op2)! Sets Z if op1=op2. Affects N,Z,C,V. S suffix implicitly assumed. AND <dest>,<op1>,<op2> dest=op1 AND op2. Affects N,Z. ORR <dest>,<op1>,<op2> dest=op1 OR op2. Affects N,Z. EOR <dest>,<op1>,<op2> dest=op1 EOR op2. Affects N,Z. BIC <dest>,<op1>,<op2> dest=op1 AND (NOT (op2)). If we take op1 and treat op2 as a mask, a set bit in op2 will cause the corresponding bit in op1 to clear. Perform for all 32 bits, then store the modified op1 in dest. Affects N,Z. TST <op1>,<op2> Bitwise notional AND of op1 and op2. Either op can be the bit mask; Z sets if the a bit set in the mask is set in the op. Affects N,Z. S suffix is implicitly assumed. TEQ <op1>,<op2> Notional bitwise OR, used to test equivalence. Affects N,Z. S suffix implicitly assumed. MUL <dest>,<op1>,<op2> dest=op1*op2. Restrictions: op1 and op2 must be simple registers, must be different, and must not be R15. N and Z reflect the result, V is unchanged and C becomes ill-defined. MLA <dest>,<op1>,<op2>,<op3> dest=(op1*op2)+op3. Useful for running totals. Permissible for dest to be the same as op3. Flags set as with MUL. Block Data Transfer ------------------- LDM<options><base>{!},<list> ] ] See "Stack Implementation" section STM<options><base>{!},<list> ] Miscellany ---------- B <addr> Direct branch to routine at addr; wasteful on pipeline. BL <addr> Copies pipeline-corrected PC to R14 and branches to routine at addr; return may be affected by MOV PC,R14 at end of subroutine. SWI <expr> Executes an SWI routine. See available list of routines. Conditional Execution Suffixes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ All ARM assembler operations may be executed conditionally; the conditions are defined by a two-letter extension appended to the mnemonic to be executed subject to the conditions. In the table below, "flag status" refers to the conditions required for a command extended by the suffix to be executed. Suffix Literal Meaning Flag Status Comments ------ --------------- ----------- -------- EQ Equal Z set eg from CMPS with equal args NE Not equal Z clear VS Overflow set V set VC Overflow clear V clear AL Always Default, implicit NV Never Only workable in a large chunk of Boolean; use now prohibited by Acorn HI Higher (unsigned) C set AND arg1>arg2 ] Z clear ]Use after a CMP or ]CPN LS Less than or same as C clear OR Z arg1<=arg2] (unsigned) set PL Plus N clear Zero is positive MI Minus N set Bit 31 of prev. result is 1 CS Carry set C set prev. instruction carried or overflowed CC Carry clear C clear GE Greater than or equal (N set AND V clear)OR(N clear AND V clear) (signed) LT Less than (signed) (N set AND V clear)OR(N clear AND V set) GT Greater than (signed) ((N set AND V set)OR(N clear AND V clear))AND Z clear LE Less than or equal ((N set AND V clear)OR(N clear AND V set))AND (signed) Z clear For signed suffixes, signing convention is 2's complement (ie NOT and add 1) Other Mnemonic Extenders ------------------------ B Byte flag Operator only operates on 8-bit operand; word alignment not necessary S Status flag Reflect result of operation in status flags. Beware; this is implicit in 6502, but must be specified in ARM unless otherwise stated (above) P Pipeline suspend Disable pipelining to allow writing to R15; result of operand (usually TEQ) is written back _directly_ to status bits (26-31) of R15. Stack Implementation -------------------- Stacks are most easily implemented using STM and LDM. Both of these instructions take the syntax <mnemonic><extender> <base>{!},<list> where <mnemonic> is either STM (store multiple) or LDM (load multiple) <extender> is I Increment address after storing each register D Decrement address after storing each register A Modify address after storing each register B Modify address before storing each register FA Operate on full ascending stack FD Operate on full descending stack EA Operate on empty ascending stack ED Operate on empty descending stack <base> is the address of the stack pointer; usually held in R13 {!} specifies write-back of the modified address to the stack pointer (to prevent data being accidentally overwritten) <list> is a comma-separated list of arguments, enclosed in braces {}, to be pushed to the stack. First entry in the list goes on first. The FA-ED extenders save the problem of having to reverse the usual extenders when pushing and pulling; to pull from a stack which had been pushed to using STMIA, it was necessary to use LDMDB. Now we can just use STMEA and LDMEA, for example. Floating Point Model ~~~~~~~~~~~~~~~~~~~ The following instructions are _NOT_ included in the standard ARM BASIC assembler; however, for those of you who may have cross-assemblers or the Acorn Object Assembler, or are prepared to hand-code the instructions in hex, here goes. The FP model complies with the IEEE specification, and provides a further 8 registers, F0-F7. Numbers may be stored in the following 4 formats: IEEE Single Precision (S) 32 bits: 1 sign bit 23 bit mantissa 8 bit exponent IEEE Double Precision (D) 64 bits (double word): 1 sign bit 52 bit mantissa 11 bit exponent Double Extended Prec. (E) 96 bits (triple word): 1 sign bit 64 bit mantissa 15 bit exponent 16 bits unused Packed decimal BCD (P) 96 bits (triple word): 1 sign digit 19 digit mantissa 4 digit exponent The FP status register has separate flags for Overflow, Underflow, Division by Zero, Inexact result and Invalid operation; a subset of the flags indicating these is copied into the ARM status register (R15) by the co-processor interface. In brief, the instructions are: LDF<suffix><precision> <reg>,<address> STF<suffix><precision> <reg>,<address> where: <suffix> is one of S,D,F,P <reg> is F0-F7 <Address> is either [Rn]{,#offset} or [Rn,#offset]{!} and is defined as an offset from the ARM base register specified; the offset is in the range -1020 to +1020. The offset is added to the base register when write-back {!} is specified with pre-indexed addressing, and is always added with post-indexed. FLT Change integer to FP FIX Change FP to integer WPS Write FP status to FP status reg. RFS Read FP status from FP status reg. WFC Write FP control ] Processor SVC mode only RFC Read FP control ] This set uses the general form eg FLT<suffix><precision>{rounding mode} <Freg>,(<reg> #value) Unary Operations ---------------- Command format: <unaryop><suffix><precision>{rounding mode} <Fdest>,(<Fop> #val) Mnemonic Effect Calculation -------- ------ ----------- MVF Move Fdest=Fop MNF Move negated Fdest=-Fop ABS Absolute value Fdest=ABS(Fop) RND Round to integer Fdest=INT(Fop) SQT Square root Fdest=SQR(Fop) LOG Log to base #10d Fdest=LOG(Fop) LGN Natural log Fdest=LN(Fop) EXP Exponent Fdest=EXP(Fop) SIN Obvious Fdest=SIN(Fop) COS Equally obvious Fdest=COS(Fop) TAN Ditto Fdest=TAN(Fop) ASN ] Fdest=ASN(Fop) ACS ] (Obvious)^-1 Fdest=ACS(Fop) ATN ] Fdest=ATN(Fop) Binary Operations ----------------- Command format: <binaryop><suffix><precision>{rounding mode} <Fdest>,<Fop1>,(<Fop2> #value) Mnemonic Effect Calculation -------- ------ ----------- ADF Add Fdest=Fop1+Fop2 MUF Multiply Fdest=Fop1*Fop2 SUB subtract Fdest=Fop1-Fop2 RSF Reverse subtract Fdest=Fop2-Fop1 DVF Divide Fdest=Fop1/Fop2 RDF Reverse divide Fdest=Fop2/Fop1 POW Raise to power Fdest=Fop1^Fop2 RPW Reverse raise... Fdest=Fop2^Fop1 RMF Remainder Fdest=Fop1 MOD Fop2 FML Fast multiply Fdest=Fop1*Fop2 FDV Fast divide Fdest=Fop1/Fop2 FRD Fast reverse divide Fdest=Fop2/Fop1 POL Polar angle Fdest=angle between Fop1 and Fop2 Note that the "fast" instructionsonly produce single-figure accuracy, regardless of the precision specified in the mnemonic. System Memory Map ~~~~~~~~~~~~~~~~ Please note that this is the provisional version of the memory map details; the master table (at the top) is for an A540/R200 series machine (the addresses are the same on the entire Archimedes range, but there are no Acorn-endorsed RAM expansions to take you over the 4Mb), whereas the logically-mapped RAM area was assigned from much hacking on an A310. The addresses in this latter table are, of course, affected directly by machine configuration, and the data thus given is merely representative of the setup of that machine at that time. Read Write Addr ---- ----- ---- -------------------------------- 3FFFFFF ROM (high) | Logical to Physical | address translator ------------------- -------------------------------- 3800000 / 4Mb daughter card ROM (low) | DMA Address / 3rd slot MEMC (z) | generators / ------------------- |-------------------- 3600000 / 4Mb daughter card | Video Controller / 2nd slot MEMC (y) -------------------------------- 3400000 / ------------------- Input/Output Controllers / 4Mb daughter card -------------------------------- 3000000 / Ist slot MEMC (x) Physically mapped RAM ------------------- -------------------------------- 2000000 \ 4Mb on motherboard Logically mapped RAM \ Master MEMC (w) -------------------------------- 0000000 \----- ------------------- 0 ---------------------- \ ARM Reset \ \ 4 ---------------------- \ \ Undefined instruction \ \ 8 ---------------------- \ \ Software Interrupt (SWI) \ \ C ---------------------- \ 0 --------------------------------- Abort (pre-fetch) Bootstrap and hardware exception 10 ---------------------- vectors Abort (data) / 1C --------------------------------- 14 ---------------------- / System and BASIC workspace Address exception / 8000 --------------------------------- 18 ---------------------- / Application RAM IRQ_Vec / (RISC OS Desktop Tasks map to here) 1C --------------------- / A7FFF --------------------------------- FIQ_Vec / Unassigned address space --------------------- 1800000 --------------------------------- RAM-based Relocatable Modules (incl. those downloaded from podules) Font definitions grow downwards 1825FFF --------------------------------- Unassigned address space 1C00000 --------------------------------- System Heap 1C03FFF --------------------------------- Unassigned address space 1F00000 --------------------------------- Cursor data and Desktop scratchpad 1F07FFF --------------------------------- Unassigned address space 1FEC000 --------------------------------- Screen RAM (grows downwards) 1FFFFFF --------------------------------- In addition, the RAM disk maps in at &1000000. IOC --- The I/O controller is mapped into RAM from &3000000 to &3400000, and _ALL_ I/O devices are also thus memory mapped. The chip has 4 operation modes; sync, fast, medium and slow. It therefore follows that a good many operations will be duplicated in different modes. A (necessarily incomplete) list of some device entry points follows: Device Addr ------ ---- Serial &3200004 Parallel printer &3250010 (slow mode) Podule IRQ (mask reg) &3360000 IOC base (slow mode) &3250000 NB -- When writing to a device via IOC, the data must be on the top 16 bits of the data word. Data to be read appears on the bottom 16 bits. ----------------------------------------------------------------------------- Needless to say, there could be much, much more included here. Please let me know what you'd like to see covered; however, bear in mind that this is meant to be a brief pocket guide, not the PRM set! *LIB ~~~ Further texts now available for perusal from your friendly neighbourhood SIG Leader: Archimedes Operating System: A. & N. van Someren, Dabs Press --------------------------- Some rather good internal stuff here. However, stops short of direct chip addressing; I need to get the ARM data book. Good section on MEMC, though, and probably the de-facto guide to writing modules. Interesting sections on the sound system. Acorn A540/R200 Technical Reference Manual ------------------------------------------ If you've got a 540 or R series machine, this should be top of your "must read" list. Much stuff in the first couple of sections which covers the entire Archimedes range, however. Also covers the SCSI podule, and has exhaustive info (down to timing diagrams) on the Ethernet podules. Includes blueprints! Further plans are to get hold of the VLSI ARM Data Book (I have the ISBN), and the full schematic and timing diagrams to the backplane (Acorn will supply free;strange they weren't included in the Tech Ref). Also, I don't think my willpower can stop me delving into my bank account for a 3.1 PRM set... *SHUTDOWN ~~~~~~~~ Well, another issue; don't worry, I don't envisage another one being this big for a _LONG_ time (although I'm perfectly willing to lay this down as a challenge to those of you who want to contribute articles)! I'm delighted to see some reader contributions at this early stage in EurekA's life; having had experience last year editing Cassini (the HP48 SIG Newsletter), where it turned out that, with the exception of one piece of feedback the entire year's newsletters were written by Tony Duell and myself, I think we may well make a real success out of this newsletter. Remember, Cassini went international within six months of the first issue.. Meantime, editor keels over....<thud>