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- Logical memory map
- ”’’’’’’’’’’’’’’’’’’’’’’’’’„ 2 000 000
- ‹ Screen memory ‹
- †’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’œ
- ‹ Cursor/System/Sound ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 F00 000
- ‹ Font cache ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 E00 000
- ‹ System Heap and Stack ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 C00 000
- ‹ Relocatable Module Area ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 800 000
- ‹ Sprite Area ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 400 000
- ‹ RAM Disc ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 1 000 000
- ‹ ‹
- ‹ Application Workspace ‹
- ‹ ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 0 008 000
- ‹ System Workspace ‹
- ›’’’’’’’’’’’’’’’’’’’’’’’’’“ 0 000 000Memory Map
- Read Write Hex Address
- ”’’’’’’’’’’’’’’’’’’’’’’’’’„ 4 000 000
- ‹ ‹ ‹
- ‹ ROM (low) ‹ ‹
- ‹ ‹ <MEMC> ‹
- †’’’’’’’’’’’’œ ‹ 3 800 000
- ‹ ‹ ‹
- ‹ ROM (high) †’’’’’’’’’’’’œ 3 600 000
- ‹ ‹ <VIDC> ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 3 400 000
- ‹ <I/O Controllers=>IOC> ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 3 000 000
- ‹ ‹
- ‹ ‹
- ‹ Physical RAM ‹
- ‹ ‹
- ‹ ‹
- †’’’’’’’’’’’’’’’’’’’’’’’’’œ 2 000 000
- ‹ ‹
- ‹ ‹
- ‹ <Logical RAM=>Logical> ‹
- ‹ ‹
- ‹ ‹
- ›’’’’’’’’’’’’’’’’’’’’’’’’’“ 0 000 000Video Controller (VIDC)
- The VIDC can be programmed by writing
- a <word=>VIDC1> to anywhere in the range
- &3400000 to &35FFFFF.VIDC registers
- Top eight bits are reg address. Bits 24,25
- are always 0, so address goes 0,4,8...
- Data lies in bits 0-23
-
- Address Register function
- ------- -----------------
- 00-3C <Video palette=>VIDC00> 0-F
- 40 <Border col=>VIDC40>
- 44-4C <Cursor palette=>VIDC40> 1-3
- 50-5C reserved
- 60-7C <Stereo Image channel=>VIDC60> 7,0-6
- 80 Horizontal Cycle „
- 84 Horizontal Sync Width ‹
- 88 Horizontal Border Start ‹
- 8C Horizontal Display Start †’„
- 90 Horizontal Display End ‹ ‹
- 94 Horizontal Border End ‹ Œ
- 98 Horizontal Cursor Start “
- 9C Horizontal Interlace <Diagr=>VIDC_diagr>
- A0 Vertical Cycle „
- A4 Vertical Sync Width ‹ −
- A8 Vertical Border Start ‹ ‹
- AC Vertical Display Start †’“
- B0 Vertical Display End ‹
- B4 Vertical Border End ‹
- B8 Vertical Cursor Start ‹
- BC Vertical Cursor End “
- C0 Sound Frequency
- C4-DC reserved
- E0 <Control=>VIDCE0>
- E4-FC reservedVIDC Display parameters
-
- ‹—’’’’’’ HCS ’’’’’’– ‹
- ’’’‘’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’‘’’
- − ‹ −− −− ‹
- ‹ ‹ VBSŒ‹ ”’’’’’’’’’’’’’’’’’’’„ ‹‹ ‹
- ‹ ‹ ‹ ‹///// Border //////‹ ‹‹ ‹
- ‹ ‹ VDS Œ ‹//”’’’’’’’’’’’’’„//‹ ‹‹ ‹
- ‹ ‹ ‹//‹ Display ‹//‹ ‹‹ ‹
- ‹ ‹ || ‹//‹ ”’„ ‹//‹ ‹ŒVCS ‹
- ‹ ‹ ‹‹ ‹//‹ ›’“—’„ ‹//‹ Œ VCE ‹
- ‹ ‹ ‹‹ ‹//‹ Cursor “ ‹//‹ ‹
- ‹ ‹ VDE‹Œ ‹//›’’’’’’’’’’’’’“//‹ ‹
- ‹ ‹ ‹ ‹///////////////////‹ ‹
- ‹ ‹ VBEŒ ›’’’’’’’’’’’’’’’’’’’“ ‹
- VCŒ ‹ ‹
- − ‹—’’ HBS ’– -’’’’’’ HBE ’’’’’’– ‹
- VSWŒ ‹—’’’ HDS ’’’– -’’ HDE ’’’’– ‹
- ’’’‘’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’‘’’
- ‹—’’’’’’’’’’’’’’’ HC ’’’’’’’’’’’–—’HSW’–‹
- Video Palette
- Bit 0 - 3 : Red amplitude
- 4 - 7 : Green amplitude
- 8 -11 : Blue amplitude
- 12 : Supremacy bit
-
- In 256-colour modes:
- Bit 0-3 of byte, decides which
- palette reg to use.
- Bit 4-8 of byte, replaces bits
- 3,6,7,11 of palette reg.Physical colour
- Bit 0 - 3 : Red amplitude
- 4 - 7 : Green amplitude
- 8 -11 : Blue amplitude
- 12 : Supremacy bitStereo Image
- Only bits 0-2 are used:
- -----------------------
- 0 undefined
- 1 100% left
- 2 83% left
- 3 67% left
- 4 Center
- 5 67% right
- 6 83% right
- 7 100% right
-
- All Stereo Image registers must be programmed.
- When only 4 are used: 4,5,6,7 = 0,1,2,3
- When only 2 are used: (2,4,6),(3,5,7) = 0,1
- When only 1 is used: 1,2,3,4,5,6,7 = 0Control Register
- 11100000xxxxxxxx--xxxxx---------
- ‹“ ‹‹‹›‹›‹›‹
- Test Mode ’’’’’’“ ‹‹‹ ‹ ‹ ›’ Pixel rate
- 00 Normal ‹‹‹ ‹ ‹ 00 8 MHz
- 01 Test mode 0 ‹‹‹ ‹ ‹ 01 12 MHz
- 10 Test mode 1 ‹‹‹ ‹ ‹ 10 16 MHz
- 11 Test mode 2 ‹‹‹ ‹ ‹ 11 34 MHz
- ‹‹‹ ‹ ‹
- Test Mode ’’’’’’’’’’’’’“‹‹ ‹ ›’’’ Bits per pixel
- 0 Normal ‹‹ ‹ 00 1 bpp
- 1 Test mode 3 ‹‹ ‹ 01 2 bpp
- ‹‹ ‹ 10 4 bpp
- Composite Sync ’’’’’’’’’“‹ ‹ 11 8 bpp
- 0 Vertical ‹ ‹
- 1 Composite ‹ ›’’’’’ DMA request
- ‹ 00 End word 0,4
- Interlace Sync ’’’’’’’’’’“ 01 End word 1,5
- 0 Interlace off 10 End word 2,6
- 1 Interlace on 11 End word 3,7Memory Controller (MEMC)
- When programming the MEMC,
- everything is contained
- in the address used.
-
- You can program:
- <Control register=>MEMC1>
- Address translator
- <DMA address generators=>MEMC3>MEMC control register
- Write any word to this address (or use <OS_UpdateMEMC=>SWI.OS_UpdateMEMC>)
-
- %00000011011x111xxx0-----------xx
- ‹‹‹‹“›‹›‹›‹
- OS mode ’’’’’’’’’’’“‹‹‹ ‹ ‹ ›’ Page Size
- 0 On ‹‹‹ ‹ ‹ 00 4Kb
- 1 Off ‹‹‹ ‹ ‹ 01 8Kb
- ‹‹‹ ‹ ‹ 10 16Kb
- Sound DMA control ’’“‹‹ ‹ ‹ 11 32Kb
- 0 Disable ‹‹ ‹ ‹
- 1 Enable ‹‹ ‹ ›’’’ Low ROM Access
- ‹‹ ‹ 00 450ns
- Video/Cursor DMA ’’’’“‹ ‹ 01 325ns
- 0 Disable ‹ ‹ 10 200ns
- 1 Enable ‹ ‹
- ‹ ›’’’’’ High ROM Access
- DRAM refresh control ’“ 00 450ns
- 00 None 01 325ns
- 01 During video flyback 10 200ns
- 10 None
- 11 ContinousMEMC DMA Address generators
- New value here
- Vinit 00000011011x000...............xx
- Vstart 00000011011x001...............xx
- Vend 00000011011x010...............xx
- Cinit 00000011011x011...............xx
- SstartN 00000011011x100...............xx
- SendN 00000011011x101...............xx
- Sptr 00000011011x110xxxxxxxxxxxxxxxxx
-
- Vptr
- Cptr
-
- Value in bits 2-16 is physical address
- divided by 16 => All values are in the
- lower 0.5 Mb of physical memory.
-
- Video:
- ------
- Circular buffer from Vstart to Vend.
- Vptr is set to Vinit just before new
- display frame begins.
-
- Cursor:
- -------
- Cptr is initialised to Cinit during video
- flyback, and data is read from here when
- cursor DMA is requested.
-
- Sound:
- ------
- SstartN and SendN is start and end of the
- next sound buffer. When the VIDC has 'used up'
- the current buffer:
- If next is valid (1st SendN and then SstartN
- set), it sets current = next, marks next as
- 'invalid' and triggers the sound interrupt.
- Else it will go back to start of current buffer.I/O Controller (IOC)
- Address:
- %000000110xx.....xxxxxxxxx.....00
- ‹“‹’“ ›’’„’’“
- Type ’’’’’’’“ ‹ Address
- 00 slow ›’ Bank
- 01 med 0 <Control registers=>IOC0>
- 10 fast 1-7 <Other devices=>IOC1-7>
- 11 syncBank 1-7 : Other devices
- Bank Type Address IC Use
- ---- ---- ------- ------- -------------------------
- 1 Fast 3310000 1772 Floppy disc controller
- 2 Sync 33A0000 6854 Econet controller
- 3 Sync 33B0000 6551 Serial port controller
- 4 Slow 3240000 - Internal expansion cards
- 4 Med 32C0000 - Internal expansion cards
- 4 Fast 3340000 - Internal expansion cards
- 4 Sync 33C0000 - Internal expansion cards
- 5 Med 32D0000 HD63463 Harddisc register write
- 5 Med 32D0008 HD63463 Harddisc DMA read
- 5 Med 32D0020 HD63463 Harddisc register read
- 5 Med 32D0028 HD63463 Harddisc DMA write
- 5 Fast 3350010 HC374 Printer Data
- 5 Fast 3350018 HC574 Latch A
- 5 Fast 3350040 HC574 Latch B
- 7 Slow 3270000 - External expansion cardsBank 0 : Control registers
- (Type=don't care)
-
- Offset Read Write ‹ Offset Read Write
- ------ ------------- ----------- ‹ ------ ------------- ----------------
- 00 Control Control ‹ 40 T0 count low T0 latch low
- 04 Kbd receive Kbd send ‹ 44 T0 count high T0 latch high
- 08 - - ‹ 48 - T0 Go command
- 0C - - ‹ 4C - T0 Latch command
- 10 IRQ status A - ‹ 50 T1 count low T1 latch low
- 14 IRQ request A IRQ clear ‹ 54 T1 count high T1 latch high
- 18 IRQ mask A IRQ mask A ‹ 58 - T1 Go command
- 1C - - ‹ 5C - T1 Latch command
- 20 IRQ status B - ‹ 60 T2 count low T2 latch low
- 24 IRQ request B - ‹ 64 T2 count high T2 latch high
- 28 IRQ mask B IRQ mask B ‹ 68 - T2 Go command
- 2C - - ‹ 6C - T2 Latch command
- 30 FIQ status - ‹ 70 T3 count low T3 latch low
- 34 FIQ request - ‹ 74 T3 count high T3 latch high
- 38 FIQ mask FIQ mask ‹ 78 - T3 Go command
- 3C - - ‹ 7C - T3 Latch command