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- Instructions :
- <ADC> Add with Carry
- <ADD> Add
- <AND> And
- B Branch
- BIC Bit Clear
- CMN Compare Negative
- CMP Compare
- EOR Exlusive OR
- LDM Load Multiple
- LDR Load Register
- MLA Multiply with Accumulate
- MOV Move
- MUL Multiply
- MVN Move Negative
- ORR Inclusive OR
- RSB Reverse Subtract
- RSC Reverse Subtract with Carry
- SBC Subtract with Carry
- STM Store Multiple
- STR Store Register
- SUB Subtract
- SWI Software Interrupt
- TEQ Test for Equality
- TST Test MaskedADC
- Aritmetic add with carry
-
- Syntax: ADC\<<cond>>\<<S>> <Rd>,<Rn>,<Op2>
-
- NZCV
- Flags : ****ADD
- Aritmetic add
-
- Syntax: ADD\<<cond>>\<<S>> <Rd>,<Rn>,<Op2>
-
- NZCV
- Flags : ****Logical AND
- %0011
- AND %0101
- ------------
- = %0001
-
- Syntax: AND\<<cond>>\<<S>> <Rd>,<Rn>,<Op2>
-
- NZCV
- Flags : ***-Condition codes
- All instructions are conditionally executed. If the condition
- in the top four bits of the instruction is not met, then even
- illegal instructions will have no effect...
-
- Condition field Execute IF
- --------------- -------------------------------------------
- 0000 = EQ : Z (equal)
- 0001 = NE : ~Z (not equal)
- 0010 = CS : C (unsigned higher or same)
- 0011 = CC : ~C (unsigned lower)
- 0100 = MI : N (negative)
- 0101 = PL : ~N (positive or zero)
- 0110 = VS : V (overflow)
- 0111 = VC : ~V (no overflow)
- 1000 = HI : C and ~Z (unsigned higher)
- 1001 = LS : ~C or Z (unsigned lower or same)
- 1010 = GE : N = V (signed higher or same)
- 1011 = LT : N != V (signed lower)
- 1100 = GT : ~Z and (N = V) (signed higher)
- 1101 = LE : Z or (N != V) (signed lower or same)
- 1110 = AL : 1 (always)
- 1111 = NV : 0 (never)
-
- ( 1 is true, 0 is false, ~ is NOT )R15
- 3 2 1
- 10987654321098765432109876543210
- %NZCOIF....program.counter.....MM
- 00 = User mode
- FIRQ Disable 01 = FIRQ mode
- IRQ Disable 10 = IRQ mode
- Overflow 11 = Supervisor mode
- Carry / Not borrow / Rotate Extend
- Zero
- Negative / Signed less thanS
- Flags will only be updated if this
- is present. The S flag is implicit
- in CMP, CMN, TEQ and TST
-
- SUBS R1,R1,R2 ; --|
- ADD R1,R1,R3 ; |
- Beq xxx ; jump if R1-R2 = 0Rd
- Rd can be any of the registers
- from R0 to R15. If Rd = R15 then
- only the PC bits will be set,
- not the flags.Rn
- Rn can be any of the registers
- from R0 to R15. If Rn = R15 then
- only the PC bits are used. The
- flag bits will appear cleared.Op2
- This can take several forms :
- - Reg
- - Reg <shift> #constant
- - Reg <shift> Reg
- (Note: This takes an
- extra clock cycle)
- - #constant
- (this constant is limited
- to numbers of the form
- byte ROR n*2, where n
- goes from 0 to 15 )Shift
- The shift types are :
- LSL Logical Shift Left
- LSR Logical Shift Right
- ASR Arithmetic Shift Right
- ROR ROtate Right
- RRX Rotate Right eXtendex
-
- RRX is special. It is a rotate
- by one, where bit 31 = old carry
- and new carry = old bit 0.
-
- For all shifts the carry flag is
- set to the last bit shifted out.