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C/C++ Source or Header  |  1994-11-13  |  4KB  |  111 lines
  1. // sersetup.h
  2. // Created by Id Software for SERSETUP.EXE, 1993, 1994.
  3. // Hacked by Russell Gilbert and others SER4.EXE, SER5.EXE, and SER6.EXE 1994.
  4. // Hacked by Paul T. Hermann for SER5.EXE, SER6.EXE 1994.
  5. //
  6. // Compiled under Borland C++ 3.1 using the Compact Memory module
  7. // Using 80386 instruction set and 80387 emualation support
  8. // Optimizations for speed enabled
  9. //
  10.  
  11. #include <conio.h>
  12. #include <stdio.h>
  13. #include <stdlib.h>
  14. #include <string.h>
  15. #include <ctype.h>
  16. #include <dos.h>
  17. #include <dir.h>
  18. #include <process.h>
  19. #include <stdarg.h>
  20. #include <bios.h>
  21.  
  22.  
  23. #define INPUT( port )        inp( port )
  24. #define OUTPUT( port, data ) (void) outp( port, data )
  25. #define CLI()                disable()
  26. #define STI()                enable()
  27.  
  28. typedef enum {false, true} boolean;
  29. typedef unsigned char byte;
  30.  
  31.  
  32. #define TRANSMIT_HOLDING_REGISTER            0x00
  33. #define RECEIVE_BUFFER_REGISTER              0x00
  34. #define INTERRUPT_ENABLE_REGISTER            0x01
  35. #define   IER_RX_DATA_READY                  0x01
  36. #define   IER_TX_HOLDING_REGISTER_EMPTY      0x02
  37. #define   IER_LINE_STATUS                    0x04
  38. #define   IER_MODEM_STATUS                   0x08
  39. #define INTERRUPT_ID_REGISTER                0x02
  40. #define   IIR_MODEM_STATUS_INTERRUPT         0x00
  41. #define   IIR_TX_HOLDING_REGISTER_INTERRUPT  0x02
  42. #define   IIR_RX_DATA_READY_INTERRUPT        0x04
  43. #define   IIR_LINE_STATUS_INTERRUPT          0x06
  44. #define FIFO_CONTROL_REGISTER                0x02
  45. #define   FCR_FIFO_ENABLE                    0x01
  46. #define   FCR_RCVR_FIFO_RESET                0x02
  47. #define   FCR_XMIT_FIFO_RESET                0x04
  48. #define   FCR_RCVR_TRIGGER_LSB               0x40
  49. #define   FCR_RCVR_TRIGGER_MSB               0x80
  50. #define   FCR_TRIGGER_01                     0x00
  51. #define   FCR_TRIGGER_04                     0x40
  52. #define   FCR_TRIGGER_08                     0x80
  53. #define   FCR_TRIGGER_14                     0xc0
  54. #define LINE_CONTROL_REGISTER                0x03
  55. #define   LCR_WORD_LENGTH_MASK               0x03
  56. #define   LCR_WORD_LENGTH_SELECT_0           0x01
  57. #define   LCR_WORD_LENGTH_SELECT_1           0x02
  58. #define   LCR_STOP_BITS                      0x04
  59. #define   LCR_PARITY_MASK                    0x38
  60. #define   LCR_PARITY_ENABLE                  0x08
  61. #define   LCR_EVEN_PARITY_SELECT             0x10
  62. #define   LCR_STICK_PARITY                   0x20
  63. #define   LCR_SET_BREAK                      0x40
  64. #define   LCR_DLAB                           0x80
  65. #define MODEM_CONTROL_REGISTER               0x04
  66. #define   MCR_DTR                            0x01
  67. #define   MCR_RTS                            0x02
  68. #define   MCR_OUT1                           0x04
  69. #define   MCR_OUT2                           0x08
  70. #define   MCR_LOOPBACK                       0x10
  71. #define LINE_STATUS_REGISTER                 0x05
  72. #define   LSR_DATA_READY                     0x01
  73. #define   LSR_OVERRUN_ERROR                  0x02
  74. #define   LSR_PARITY_ERROR                   0x04
  75. #define   LSR_FRAMING_ERROR                  0x08
  76. #define   LSR_BREAK_DETECT                   0x10
  77. #define   LSR_THRE                           0x20
  78. #define MODEM_STATUS_REGISTER                0x06
  79. #define   MSR_DELTA_CTS                      0x01
  80. #define   MSR_DELTA_DSR                      0x02
  81. #define   MSR_TERI                           0x04
  82. #define   MSR_DELTA_CD                       0x08
  83. #define   MSR_CTS                            0x10
  84. #define   MSR_DSR                            0x20
  85. #define   MSR_RI                             0x40
  86. #define   MSR_CD                             0x80
  87. #define DIVISOR_LATCH_LOW                    0x00
  88. #define DIVISOR_LATCH_HIGH                   0x01
  89.  
  90. /* QUESIZE must be a power of 2 */
  91.  
  92. #define    QUESIZE    2048
  93.  
  94. typedef struct
  95. {
  96.     int    head, tail;        // bytes are put on head and pulled from tail
  97.     int    size;
  98.     unsigned char    data[QUESIZE];
  99. } que_t;
  100.  
  101. void InitPort (void);
  102. void ShutdownPort (void);
  103.  
  104. int read_byte( void );
  105. void write_byte( int );
  106. void Error (char *error, ...);
  107.  
  108. void showReadStats(void);
  109. void showWriteStats(void);
  110. void showUartErrors(void);
  111.