Hot Shareware 32/hot34.iso/ficheros/DTOOL/INTER57D.ZIP/PORTS.A

Text File | 1998-03-22 | 342KB | 9,373 lines

PORTS LIST            Release 57        Last change 22mar98
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998 Ralf Brown
[This file originally by Wim Osterholt <[e-mail]>,
 though it has grown considerably since.]

        XT, AT and PS/2     I/O port addresses

Do NOT consider this information to be complete and accurate.  If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!).  Be aware that erroneous port programming
can put your data or even your hardware at risk.

There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.

--------!---Note-----------------------------
Note: the port description format is:

PPPPw RW  description

where:    PPPP    is the four-digit hex port number or a plus sign and three hex
        digits to indicate an offset from a base port address
    w    is blank for byte-size port, 'w' for word, and 'd' for dword
    R    is blank or dash if not readable, 'r' if sometimes readable,
        'R' if "always" readable, '?' if readability unknown
    W    is blank or dash if not writable, 'w' if sometimes writable,
        'W' if "always" writable, 'C' if write-clear, and
        '?' if writability unknown
----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000  R-  DMA channel 0    current address        byte  0, then byte 1
0000  -W  DMA channel 0    base address        byte  0, then byte 1
0001  RW  DMA channel 0 word count        byte 0, then byte 1
0002  R-  DMA channel 1    current address        byte  0, then byte 1
0002  -W  DMA channel 1    base address        byte  0, then byte 1
0003  RW  DMA channel 1 word count        byte 0, then byte 1
0004  R-  DMA channel 2    current address        byte  0, then byte 1
0004  -W  DMA channel 2    base address        byte  0, then byte 1
0005  RW  DMA channel 2 word count        byte 0, then byte 1
0006  R-  DMA channel 3    current address        byte  0, then byte 1
0006  -W  DMA channel 3    base address        byte  0, then byte 1
0007  RW  DMA channel 3 word count        byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P001)
0008  -W  DMA channel 0-3 command register (see #P002)
0009  -W  DMA channel 0-3 write request register (see #P003)
000A  RW  DMA channel 0-3 mask register (see #P004)
000B  -W  DMA channel 0-3 mode register (see #P005)

000C  -W  DMA channel 0-3 clear byte pointer flip-flop register
      any write clears LSB/MSB flip-flop of address and counter registers
000D  R-  DMA channel 0-3 temporary register
000D  -W  DMA channel 0-3 master clear register
      any write causes reset of 8237
000E  -W  DMA channel 0-3 clear mask register
      any write clears masks for all channels
000F  rW  DMA channel 0-3 write mask register (see #P006)
Notes:    the temporary register is used as holding register in memory-to-memory
      DMA transfers; it holds the last transferred byte
    channel 2 is used by the floppy disk controller
    on the IBM PC/XT channel 0 was used for the memory refresh and
      channel 3 was used by the hard disk controller
    on AT and later machines with two DMA controllers, channel 4 is used
      as a cascade for channels 0-3
    command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s)    Description    (Table P001)
 7    channel 3 request active
 6    channel 2 request active
 5    channel 1 request active
 4    channel 0 request active
 3    channel terminal count on channel 3
 2    channel terminal count on channel 2
 1    channel terminal count on channel 1
 0    channel terminal count on channel 0
SeeAlso: #P002,#P125

Bitfields for DMA channel 0-3 command register:
Bit(s)    Description    (Table P002)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1 extended write selection
    =0 late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing (two clocks instead of four per transfer)
    =1 normal timing (default)
    =0 compressed timing
 2    =1 enable controller
    =0 enable memory-to-memory
 1-0    channel number
SeeAlso: #P001,#P004,#P005,#P126

Bitfields for DMA channel 0-3 request register:
Bit(s)    Description    (Table P003)
 7-3    reserved (0)
 2    =0 clear request bit
    =1 set request bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P004

Bitfields for DMA channel 0-3 mask register:
Bit(s)    Description    (Table P004)
 7-3    reserved (0)
 2    =0 clear mask bit
    =1 set mask bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P001,#P002,#P003,#P128

Bitfields for DMA channel 0-3 mode register:
Bit(s)    Description    (Table P005)
 7-6    transfer mode
    00 demand mode
    01 single mode
    10 block mode
    11 cascade mode
 5    direction
    =0 increment address after each transfer
    =1 decrement address
 3-2    operation
    00 verify operation
    01 write to memory
    10 read from memory
    11 reserved
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P002,#P129

Bitfields for DMA channel 0-3 write mask register:
Bit(s)    Description    (Table P006)
 7-4    reserved
 3    channel 3 mask bit
 2    channel 2 mask bit
 1    channel 1 mask bit
 0    channel 0 mask bit
Note:    each mask bit is automatically set when the corresponding channel
      reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P004,#P130
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018  -W  extended function register (see #P007)
001A  -W  extended function execute register

Bitfields for DMA extended function register:
Bit(s)    Description    (Table P007)
 7-4    function code (see #P008)
 3    reserved (0)
 2-0    channel number
    000 channel 0 select
    001 channel 1 select
    010 channel 2 select
    011 channel 3 select
    100 channel 4 select
    101 channel 5 select
    110 channel 6 select
    111 channel 7 select

(Table P008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value    Description          Parameters  Results
 00h    current address register      -          CA0,CA1
 02h    write address              -          A0,A1,P
 03h    read  address           A0,A1,P     -
 04h    write word count register   C0,C1     -
 05h    read  word count register     -           C0,C1
 06h    read status register          -         S
 07h    mode register              -         M
 09h    mask channel              -         -
 0Ah    unmask channel              -         -
 0Dh    master clear              -         -
Note:    CA0/CA1      LSB/MSB of the current address register
    A0/A1      LSB/MSB of the base address register
    P      DMA page address
    C0/C1      LSB/MSB of the word count register
    S      status register value (see #P001, #P125)
    M      mode register value (see #P005, #P129)
    first, the extended function register is written, then the extended
      function register execute register is read/written if the function
      being executing requires

Bitfields for DMA extended mode register:
Bit(s)    Description    (Table P009)
 7    reserved (0)
 6    =0 8-bit transfer
    =1 16-bit transfer
 5-4    reserved (0)
 3    transfer type
    =0 read from memory
    =1 write to memory
 2    =0 disable memory write
    =1 enable  memory write
 1    reserved (0)
 0    address select
    =0 use 0 as base address
    =1 use a value from base address register
Note:    the IBM PS/2 model 80 technical reference doesn't seem to mention this
      register's address
----------P0020003F--------------------------
PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020  -W  PIC initialization command word ICW1 (see #P010)
0020  -W  PIC output control word OCW2 (see #P015)
0020  -W  PIC output control word OCW3 (see #P016)
0020  R-  PIC  interrupt request/in-service registers after OCW3
        request register:
         bit 7-0 = 0  no active request for the corresponding int. line
             = 1  active request for corresponding interrupt line
        in-service register:
         bit 7-0 = 0  corresponding line not currently being serviced
             = 1  corresponding int. line currently being serviced

0021  -W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P011,#P012,#P013)
0021  RW  PIC master interrupt mask register OCW1 (see #P014)

Bitfields for PIC initialization command word ICW1:
Bit(s)    Description    (Table P010)
 7-5    0 (only used in 8080/8085 mode)
 4    ICW1 is being issued
 3    (LTIM)
    =0  edge triggered mode
    =1  level triggered mode
 2    interrupt vector size
    =0 successive interrupt vectors use 8 bytes (8080/8085)
    =1 successive interrupt vectors use 4 bytes (80x86)
 1    (SNGL)
    =0  cascade mode
    =1  single mode, no ICW3 needed
 0    ICW4 needed
SeeAlso: #P011,#P012,#P013

Bitfields for PIC initialization command word ICW2:
Bit(s)    Description    (Table P011)
 7-3    address lines A0-A3 of base vector address for PIC
 2-0    reserved
SeeAlso: #P010,#P012,#P013

Bitfields for PIC initialization command word ICW3:
Bit(s)    Description    (Table P012)
 7-0    =0 slave controller not attached to corresponding interrupt pin
    =1 slave controller attached to corresponding interrupt pin
SeeAlso: #P010,#P011,#P013

Bitfields for PIC initialization command word ICW4:
Bit(s)    Description    (Table P013)
 7-5    reserved (0)
 4    running in special fully-nested mode
 3-2    mode
    0x nonbuffered mode
    10 buffered mode/slave
    11 buffered mode/master
 1    Auto EOI
 0    =0  8085 mode
    =1  8086/8088 mode
SeeAlso: #P010,#P011,#P012

Bitfields for PIC output control word OCW1:
Bit(s)    Description    (Table P014)
 7    disable IRQ7 (parallel printer interrupt)
 6    disable IRQ6 (diskette interrupt)
 5    disable IRQ5 (fixed disk interrupt)
 4    disable IRQ4 (serial port 1 interrupt)
 3    disable IRQ3 (serial port 2 interrupt)
 2    disable IRQ2 (video interrupt)
 1    disable IRQ1 (keyboard, mouse, RTC interrupt)
 0    disable IRQ0 (timer interrupt)
SeeAlso: #P015,#P016,#P124

Bitfields for PIC output control word OCW2:
Bit(s)    Description    (Table P015)
 7-5    operation
    000 rotate in auto EOI mode (clear)
    001 (WORD_A) nonspecific EOI
    010 (WORD_H) no operation
    011 (WORD_B) specific EOI
    100 (WORD_F) rotate in auto EOI mode (set)
    101 (WORD_C) rotate on nonspecific EOI command
    110 (WORD_E) set priority command
    111 (WORD_D) rotate on specific EOI command
 4-3    reserved (00 - signals OCW2)
 2-0    interrupt request to which the command applies
    (only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P014,#P016

Bitfields for PIC output control word OCW3:
Bit(s)    Description    (Table P016)
 7    reserved (0)
 6-5    special mask
    0x  no operation
    10  reset special mask
    11  set special mask mode
 4-3    reserved (01 - signals OCW3)
 2    poll command
 1-0    function
    0x  no operation
    10  read interrupt request register on next read from PORT 0020h
    11  read interrupt in-service register on next read from PORT 0020h
Note:    the special mask mode permits all other interrupts (even those with
      lower priority) to be processed while an interrupt is already in
      service, but will not re-issue an interrupt for a particular IRQ
      while it remains in service
SeeAlso: #P014,#P015
----------P00220023--------------------------
PORT 0022-0023 - CHIP SET DATA
Note:    These two ports are used by numerous chipsets.    Various chipsets are
      detailed below.

0022  -W  index for accesses to data port
0023  RW  chip set data
----------P00220023--------------------------
PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P017)
0023  RW  cache configuration register array (indexed by PORT 0022h)
    Note:    the index must be written to PORT 0022h before every access
          to PORT 0023h; out-of-sequence accesses or index values
          not supported by the processor generate external I/O cycles

(Table P017)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h    CR0 (see #P019)
 C1h    CR1 (see #P020)
 C4h    non-cacheable region 1, start address bits 31-24
 C5h    non-cacheable region 1, start address bits 23-16
 C6h    non-cacheable region 1, start addr 15-12, size (low nibble) (see #P018)
 C7h    non-cacheable region 2, start address bits 31-24
 C8h    non-cacheable region 2, start address bits 23-16
 C9h    non-cacheable region 2, start addr 15-12, size (low nibble) (see #P018)
 CAh    non-cacheable region 3, start address bits 31-24
 CBh    non-cacheable region 3, start address bits 23-16
 CCh    non-cacheable region 3, start addr 15-12, size (low nibble) (see #P018)
 CDh    non-cacheable region 4, start address bits 31-24
 CEh    non-cacheable region 4, start address bits 23-16
 CFh    non-cacheable region 4, start addr 15-12, size (low nibble) (see #P018)
SeeAlso: #P023,#P021

(Table P018)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h    disabled
 01h    4K
 02h    8K
 03h    16K
 04h    32K
 05h    64K
 06h    128K
 07h    256K
 08h    512K
 09h    1M
 0Ah    2M
 0Bh    4M
 0Ch    8M
 0Dh    16M
 0Eh    32M
 0Fh    4G
SeeAlso: #P017

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)    Description    (Table P019)
 0    "NC0" first 64K of each 1M noncacheable in real/V86
 1    "NC1" 640K-1M noncacheable
 2    "A20M" enables A20M# input pin
 3    "KEN"  enables KEN# input pin
 4    "FLUSH" enables FLUSH input pin
 5    "BARB" enables internal cache flushing on bus holds
 6    "C0" cache direct-mapped instead of 2-way associative
 7    "SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P017,#P020,#P032

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)    Description    (Table P020)
 0    "RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P017,#P019,#P024
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P021)
0023  RW  cache configuration register array (indexed by PORT 0022h)
    Note:    the index must be written to PORT 0022h before every access
          to PORT 0023h; out-of-sequence accesses or index values
          not supported by the processor generate external I/O cycles

(Table P021)
Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number:
 C2h    CR2 (see #P025)
 C3h    CR3 (see #P026)
 CDh    SMM region, start address bits 31-24
 CEh    SMM region, start address bits 23-16
 CFh    SMM region, start addr 15-12, size (low nibble) (see #P018)
 FEh R    Device Identification #0 (see #P022)
    CPU device ID
 FFh R    Device Identification #1
    bits 3-0: revision
    bits 7-4: stepping
SeeAlso: #P017,#P023,#P031

(Table P022)
Values for Cyrix device identification:
(#0 /#1)
 00h    Cx486SLC
 01h    Cx486DlC
 02h    Cx486SLC2
 03h    Cx486DLC2
 04h    Cx486SRx
 05h    Cx486DRx
 06h    Cx486SRx2
 07h    Cx486DRx2
 10h    Cx486S (B-step)
 11h    Cx486S2 (B-step)
 12h    Cx486Se (B-step)
 13h    Cx486S2e (B-step)
1Ah/05h    Cx486DX-40
1Bh/08h    Cx486DX2-50
1Bh/0Bh    Cx486DX2-66
1Bh/31h    Cx486DX2-v80
1Fh/36h    Cx486DX4-v100
 28h    5x86 1xs
 29h    5x86 2xs
 2Ah    5x86 1xp
 2Bh    5x86 2xp
 2Ch    5x86 4xs
 2Dh    5x86 3xs
 2Eh    5x86 4xp
 2Fh    5x86 3xp
 30h    6x86 1xs
 31h    6x86 2xs
 32h    6x86 1xp
 33h    6x86 2xp
 34h    6x86 4xs
 35h    6x86 3xs
 36h    6x86 4xp
 37h    6x86 3xp
Note:    #0 is the value in configuration register FEh, while #1 is the value
      in configuration register FFh
SeeAlso: #P021
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P023)
0023  RW  configuration control register array (indexed by PORT 0022h)
    Note:    the index must be written to PORT 0022h before every access
          to PORT 0023h; out-of-sequence accesses or index values
          not supported by the processor generate external I/O cycles

(Table P023)
Values for Cyrix 5x86 configuration registers:
 20h    Performance Control (see #P028)
 C1h    Configuration Control #1 (CCR1) (see #P024)
 C2h    Configuration Control #2 (CCR2) (see #P025)
 C3h    Configuration Control #3 (CCR3) (see #P026)
 CDh    System Memory Management address region #0 (smar0) (see #P029)
 CEh    System Memory Management address region #1 (smar1)
 CFh    System Memory Management address region #2 (smar2)
 E8h    Configuration Control Register 4
 F0h    Power Management (see #P030)
 FEh R    Device Identification #0 (see #P022)
    CPU device ID
 FFh R    Device Identification #1
    bits 3-0: revision
    bits 7-4: stepping
SeeAlso: #P017,#P021,#P031

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1):
Bit(s)    Description    (Table P024)
 0    reserved
 1    enable SMM pins
 2    system management memory access
 3    main memory access
 4    (6x86) no LOCK during bus cycles
 6-5    reserved
 7    (6x86) use address region 3 as SMM space
Note:    bits 1,2,7 may only be written when CCR3 bit 0 is enabled
SeeAlso: #P020,#P025,#P026,#P027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2):
Bit(s)    Description    (Table P025)
 0    reserved
 1    enable write-back cache interface pins
 2    lock NW bit
 3    suspend on HLT instruction
 4    write-through region 1
 5    reserved
 6    enable burst write cycles
 7    enable suspend pins
SeeAlso: #P024,#P026,#P027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3):
Bit(s)    Description    (Table P026)
 0    SMM register lock (can only be cleared in SMM mode or by CPU reset)
 1    NMI enable
 2    linear address burst cycles (5x86,6x86 only)
    =0 Pentium-compatible
    =1 linear sequencing
 3    SMM mode (5x86 only)
    =0 486SL
    =1 Cyrix
 7-4    map enable (5x86,6x86 only)
    0000 only allow access to configuration registers C0h-CFh,FEh,FFh
    0001 enable access to all configuration registers
SeeAlso: #P024,#P025,#P027,#P028,#P030

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4):
Bit(s)    Description    (Table P027)
 2-0    I/O recovery time (000 = none, else 2^N clocks)
 3    enable memory-read bypassing (5x86 only)
 4    enable directory table entry cache
 6-5    reserved
 7    enable CPUID instruction (stepping 1+ and Cx6x86)
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P024,#P025,#P026

Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)    Description    (Table P028)
 0    return stack enabled (speculatively execute code after current CALL)
 1    branch-target buffer enabled
 2    loop enable
 6-3    reserved (0)
 7    load-store serialization enabled
    (memory reads and writes may be reorganized into optimum order)
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P030,#P024

Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s)    Description    (Table P029)
 3-0    block size
 23-4    starting address

Bitfields for Cyrix 5x86 Power Management register:
Bit(s)    Description    (Table P030)
 1-0    core clock to bus clock ratio
    00 1:1
    01 2:1
    10 reserved
    11 3:1
 2    CPU running at half bus speed, ignore bits 1-0
Note:    this register is only accessible when bits 7-4 of CCR3 are 0001
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86"

0022  -W  index for accesses to next port (see #P023)
0023  RW  configuration control register array (indexed by PORT 0022h)
    Note:    the index must be written to PORT 0022h before every access
          to PORT 0023h; out-of-sequence accesses or index values
          not supported by the processor generate external I/O cycles

(Table P031)
Values for Cyrix 6x86 configuration registers:
 C0h    Configuration Control Register 0 (CCR0) (see #P032)
 C1h    Configuration Control #1 (CCR1) (see #P024)
 C2h    Configuration Control #2 (CCR2) (see #P025)
 C3h    Configuration Control #3 (CCR3) (see #P026)
 C4h    Address region 0 (bits 31-24)
 C5h    Address region 0 (bits 23-16)
 C6h    Address region 0 (bits 15-12 and size)
 C7h    Address region 1 (bits 31-24)
 C8h    Address region 1 (bits 23-16)
 C9h    Address region 1 (bits 15-12 and size)
 CAh    Address region 2 (bits 31-24)
 CBh    Address region 2 (bits 23-16)
 CCh    Address region 2 (bits 15-12 and size)
 CDh    Address region 3 (bits 31-24)
 CEh    Address region 3 (bits 23-16)
 CFh    Address region 3 (bits 15-12 and size)
 D0h    Address region 4 (bits 31-24)
 D1h    Address region 4 (bits 23-16)
 D2h    Address region 4 (bits 15-12 and size)
 D3h    Address region 5 (bits 31-24)
 D4h    Address region 5 (bits 23-16)
 D5h    Address region 5 (bits 15-12 and size)
 D6h    Address region 6 (bits 31-24)
 D7h    Address region 6 (bits 23-16)
 D8h    Address region 6 (bits 15-12 and size)
 D9h    Address region 7 (bits 31-24)
 DAh    Address region 7 (bits 23-16)
 DBh    Address region 7 (bits 15-12 and size)
 DCh    Region Control 0
 DDh    Region Control 1
 DEh    Region Control 2
 DFh    Region Control 3
 E0h    Region Control 4
 E1h    Region Control 5
 E2h    Region Control 6
 E3h    Region Control 7
 E8h    Configuration Control Register 4 (see #P027)
 E9h    Configuration Control Register 5 (see #P033)
 FEh R    Device Identification #0 (see #P022)
    CPU device ID
 FFh R    Device Identification #1
    bits 3-0: revision
    bits 7-4: stepping
SeeAlso: #P017,#P023

Bitfields for Cyrix 6x86 Configuration Control Register 0:
Bit(s)    Description    (Table P032)
 7-2    ???
 1    address region 640K-1M is noncacheable
 0    ???
SeeAlso: #P019

Bitfields for Cyrix 6x86 Configuration Control Register 5:
Bit(s)    Description    (Table P033)
 7-6    reserved
 5    enable all address-region registers (control registers C4h-DBh)
 4    assert LBA# pin on all accesses to 640K-1M
 3-1    reserved
 0    allocate new cache lines only on read misses
SeeAlso: #P032,#P027,#P031
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes:    this chip uses a chip ID of 01
    the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P035,#P036,#P037)
0023  RW  chip set data

(Table P034)
Values for Intel 82351/82359 chip ID:
 01h    82359 DRAM controller, general registers
 02h    82351 EISA local I/O support
 A1h    82359 DRAM controller, EMS registers
 FFh    no chip accessible (default)
SeeAlso: #P035,#P036,#P037

(Table P035)
Values for 82359 DRAM controller general register index:
 00h    DRAM bank 0 type
    bit 7    unknown
    bit 6-4    000 DRAM in bank 0 (standard)
        001 bank 1
        010 bank 2
        011 bank 3
        100 banks 0,1
        101 banks 2,3
        110 banks 0,1,2,3
        111 empty (standard for 1,2,3)
    bit 3-2    unknown
    bit 1-0    00 64K chips used
        01 256K
        10 1M
        11 4M
 01h    DRAM bank 1 type
 02h    DRAM bank 2 type
 03h    DRAM bank 3 type
 04h    DRAM speed detection/selection
 05h    DRAM interleave control
 06h    RAS line mode
 07h    cache-enable selection
 08h    mode register A (DRAM, cache)
 09h    mode register B (cache, burst modes, BIOS size)
 0Ah    mode register C (concurrency control, burst/cycle speed)
 10h    host timing
 11h    host-system delay timing
 12h    system timing
 13h    DRAM row precharge time
 14h    DRAM row timing
 15h    DRAM column timing
 16h    CAS pulse width
 17h    CAS-to-MDS delay
 21h    chip ID register -- selects which chip responds on these ports
    (see #P034)
 28h-2Ch    parity-error trap address
 30h    page hit cycle length (read)
 31h    page miss cycle length (read)
 32h    row miss cycle length (read)
 33h    page hit cycle length (write)
 34h    page miss cycle length (write)
 35h    row miss cycle length (write)
 40h    memory enable 00000h-7FFFFh
 41h    memory enable 80000h-9FFFFh
 42h    memory enable A0000h-AFFFFh
 43h    memory enable B0000h-BFFFFh
 44h    memory enable C0000h-CFFFFh
 45h    memory enable D0000h-DFFFFh
 46h    memory enable E0000h-EFFFFh
 47h    memory enable F0000h-FFFFFh
 4Eh    remap 80000h-FFFFFh to extended memory
 50h-53h    programmable attribute map 1
 54h-57h    programmable attribute map 2
 58h-5Bh    programmable attribute map 3
 5Ch-5Fh    programmable attribute map 4
 83h-84h    split address register (address bits A31-A20)
 85h    cache control
 8Bh    system throttle
 8Ch    host throttle
 8Dh    host memory throttle watchdog
 8Eh    host system throttle
 8Fh    host system throttle watchdog
 90h    RAM enable
 91h    RAM disable
 92h-93h    elapsed-time registers
 94h-95h    host memory ownership request
 96h-97h    system memory ownership request
 98h-99h    host memory ownership
 9Ah-9Bh    system bus ownership
 9Ch-9Dh    host system bus request
 9Eh-9Fh    memory ownership transfer
SeeAlso: #P036,#P037

(Table P036)
Values for Intel 82359 DRAM controller EMS register index:
 00h    EMS cotnrol
 21h    chip ID register -- selects which chip responds on these ports
    (see #P034)
 80h-8Fh    EMS page registers, pages 0-7
SeeAlso: #P035,#P037

(Table P037)
Values for Intel 82351 EISA Local I/O register index:
 21h    chip ID register -- selects which chip responds on these ports
    (see #P034)
 C0h    peripheral enable register A
 C1h    peripheral enable register B
 C2h    parallel configuration register
 C3h    serial configuration register A
 C4h    floppy disk controller configuration register
 C5h    serial configuration register B
 C6h    COM3 port address (low)
 C7h    COM3 port address (high)
 C8h    COM4 port address (low)
 C9h    COM4 port address (high)
 D0h-D3h    general chip select lines 0-3 (mask registers)
 D4h-D7h    general chip select line addresses 0-3 (low bytes)
 D8h-DBh    general chip select line addresses 0-3 (high bytes)
 DCh    extended CMOS RAM page port address (low)
 DDh    extended CMOS RAM page port address (high)
 DFh    extended CMOS RAM access select address (high byte)
 E8h-EBh    EISA ID configuration registers (reflect at PORT 0C80h)
SeeAlso: #P035,#P036
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82374EB/SB EISA CHIPSET
Index: Intel 82374EB;Intel 82374SB

0022  -W  index for accesses to data port (see #P038)
0023  RW  chip set data

(Table P038)
Values for Intel 82374 register index:
 02h    ESC identification register
    (82374 will only respond to ports 0022h and 0023h after an 0Fh
     is written to this register)
!!!29047604.pdf pg. 36
 08h    revision ID register
 40h    mode select
 42h    BIOS Chip Select A
 43h    BIOS Chip Select B
 4Dh    EISA clock divisor
 4Eh    peripheral Chip Select A
 4Fh    peripheral Chip Select B
 50h-53h EISA ID registers
 57h    scatter/gather relocate base address (see also #0871)
    (specifies bits 15-0 if S/G port addresses [low byte always 10h-3Fh])
 59h    APIC base address relocation
 60h-63h PCI IRQn# route control (see also #0872)
 64h    general-purpose chip select low address 0
 65h    general-purpose chip select high address 0
 66h    general-purpose chip select mask register 0
 68h    general-purpose chip select low address 1
 69h    general-purpose chip select high address 1
 6Ah    general-purpose chip select mask register 1
 6Ch    general-purpose chip select low address 2
 6Dh    general-purpose chip select high address 2
 6Eh    general-purpose chip select mask register 2
 6Fh    general-purpose peripheral X-Bus control
---SB only---
 70h    PCI/APIC control
 88h    test control
 A2h-A3h  SMI enable
 A4h-A7h  System Event Enable
 A8h    Fast-Off timer
 AAh-ABh SMI Request
 ACh    Clock Scale STPCLK# low timer
 AEh    Clock Scale STPCLK# high timer
----------P00220023--------------------------
PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P039)

(Table P039)
Values for Etec Cheetah ET6000 chip set register index:
 10h    system configuration register (see #P040)
 11h    cache configuration & non-cacheable block size register (see #P041)
 12h    non-cacheable block address register
    bit 7-1    non-cacheable address, A25-A19
    bit 0    reserved
 13h    DRAM bank & type configuration register (see #P042)
 14h    DRAM configuration register (see #P043)
 15h    shadow RAM configuration register (see #P044)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)    Description    (Table P040)
 7-6    00 turbo/non-turbo
    01 local device supported
    10 suspend mode
    11 illegal
 5    reserved
 4    refresh selection
    0 = AT type refresh
    1 = concurrent refresh
 3    slow refresh  95mSec enabled
 2    fast reset delay
    0 = do not use delay
    1 = wait for 2mSec delay
 1    wait for HALT after KBDRST
 0    RAM at A0000-BFFFF
    0 = AT bus cycle
    1 = local bus cycle
SeeAlso: #P039

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)    Description    (Table P041)
 7-5    000 disabled
    001 512K
    010 1M
    011 2M
    100 4M
    101 8M
    110 16M
    111 32M
 4    DRAM banks
    0 = 2-bank DRAM
    1 = 4-bank DRAM
 3-0    reserved
SeeAlso: #P039

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)    Description    (Table P042)
 7-6    bank 3 DRAM type
    00 none
    01 256K
    10 1M
    11 4M
 5-4    bank 2 DRAM type
 3-2    bank 1 DRAM type
 1-0    bank 0 DRAM type
SeeAlso: #P039

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)    Description    (Table P043)
 7    on-board memory range 15M to 16M disabled
 6    on-board memory range 512K-640K disabled
 5    ROM chip select at C0000-DFFFF enabled
 4    RAS to CAS time
    0 = 1 SYSCLCK,    not for R0WS
    1 = 2 SYSCLCK
 3    RAS precharge time
    0 = 1.5 SYSCLCK
    1 = 2.5 SYSCLCK
 2-1    read cycle wait state
    00 = 0 wait state
    01 = 1 ws
    10 = 2 ws
    11 = 3 ws
 0    write cycle wait state
    0 = 0 ws
    1 = 1 ws
SeeAlso: #P039

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)    Description    (Table P044)
 7    shadow at C0000-FFFFF
    0 = non-cacheable
    1 = cacheable and cache-write-proteced
 6    access ROM/RAM at F0000-FFFFF
    0 = read from ROM, write to RAM
    1 = read from shadow, write is protected
 5    access ROM/RAM at E0000-EFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow E0000-EFFFF enabled
 4    RAM at E0000-EFFFF is read-only
 3    access ROM/RAM at D0000-DFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow D0000-DFFFF enabled
 2    RAM at D0000-DFFFF is read-only
 1    access ROM/RAM at C0000-CFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow C0000-CFFFF enabled
 0    RAM at C0000-CFFFF is read-only
SeeAlso: #P039
----------P00220023--------------------------
PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data

(Table P045)
Values for HP Hornet chipset register index:
 1Eh    buzzer volume/clock oscillator speed
    bit 7-6: buzzer volume
    bit 5-4: system oscillator speed
        00: 10.738636MHz
        01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
        10: 21.477272MHz
        11: 31.673550MHz
 21h    display timing???
 23h    LCD contrast (see INT15h AH=62h)
    valid values: 00h-1fh (1fh is the darkest)
 51h    power adapter status
    bit 7-1: ???
    bit 0: power adapter status(0=inactive/1=active)
 52h    nicad charge status
    bit 7-3: ???
    bit 2: battery charging status(0=???/1=slow charge)
    bit 1-0: ???
 53h    nicad charge status
    bit 7-1: ???
    bit 0: battery charging status(0=???/1=fast charge)
 80h    memory wait for internal ROM
    valid values: 00h-07h
 81h    memory wait for internal RAM
    valid values: 00h-03h
 82h    memory wait for external RAM
    valid values: 00h-0fh
 87h    battery status???
---------------------------------------------
PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P450)
0023  RW  configuration register data

(Table P450)
Values for Chips&Technologies 82C100/110 configuration register index:
 40h    clock mode/size (see #P451)
 41h    system configuration (see #P452)
 42h    configuration valid (see #P453)
 43h    DIP switch emulation (see #P458)
 44h-47h substitute NMI vector, bytes 0-3
    (these specify the vector to be substituted at the INT 02 vector's
      memory address whenever an NMI occurs, preventing application
      software from modifying the NMI handler)
 48h    refresh timer counter (see #P454)
 49h    wait state select, refresh enable, keyboard type (see #P455)
 4Ah    reserved
 4Bh    sleep/memory configuration (see #P456)
 4Ch    EMS configuration (see #P457)
 4Dh-4Fh reserved

Bitfields for Chips&Technologies 82C100 clock mode/size register:
Bit(s)    Description    (Table P451)
 !!!
!!!chips\82c110.pdf p.35
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 system configuration register:
Bit(s)    Description    (Table P452)
 !!!
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 configuration valid register:
Bit(s)    Description    (Table P453)
 !!!
SeeAlso: #P450

Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register:
Bit(s)    Description    (Table P458)
 !!!chips\82c110.pdf p.36
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 refresh timer count register:
Bit(s)    Description    (Table P454)
 !!!
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 wait state select register:
Bit(s)    Description    (Table P455)
 !!!
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 sleep/memory configuration:
Bit(s)    Description    (Table P456)
 !!!
SeeAlso: #P450

Bitfields for Chips&Technologies 82C100 EMS configuration register:
Bit(s)    Description    (Table P457)
 !!!
SeeAlso: #P450
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P459)
0023  RW  configuration register data

(Table P459)
Values for Chips&Technologies 82C235 configuration register index:
 01h    DMA wait-state control
 40h    version (read-only)
 41h    clock control
 42h-43h reserved (but listed as read-write in docs)
 44h    peripheral control
 45h    miscellaneous status
 46h    power management
 47h    reserved
 48h    ROM enable
 49h    RAM write-protect control
 4Ah    shadow RAM enable 1
 4Bh    shadow RAM enable 2
 4Ch    shadow RAM enable 3
 4Dh    DRAM configuration
 4Eh    extended boundary
 4Fh    EMS control
 !!!chips\82c235.pdf p.87, p.140
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P460)
0023  RW  configuration register data

(Table P460)
Values for Chips&Technologies 82C311 configuration register index:
 04h    version (read-only)   !!!chips\82c311.pdf p.65
 05h    AT-bus command delay
 06h    AT-bus wait-state control
 08h    identification
 09h    low RAM/ROM configuration
 0Ch    memory enable map (80000h-9FFFFh)
 0Dh    memory enable map (A0000h-BFFFFh)
 0Eh    memory enable map (C0000h-DFFFFh)
 0Fh    memory enable map (E0000h-FFFFFh)
 10h    block 0 type and start address
 11h    block 0 DRAM timing
 12h    block 1 type and start address
 13h    block 1 DRAM timing
 14h    block 2 type and start address
 15h    block 2 DRAM timing
 16h    block 3 type and start address
 17h    block 3 DRAM timing
 18h    memory block types
 20h    cache control
 21h    directory RAM control 1
 22h    tag RAM directory address (low)
 23h    reference location
 24h    SRAM configuration/direct access address
 25h    directory RAM control 2
 26h    READY timeout
 28h    error source/address
 29h    error address (bits 23-16)
 2Ah    memory enable map (00000h-7FFFFh)
 2Bh    miscellaneous control
 2Ch    middle RAM/ROM configuration
 2Fh    page mode posted-write control (82C311 rev. C only)
 30h    block 0 non-cacheable address (bits 23-16)
 31h    block 0 non-cacheable address (bits 15-12) and size
 32h    block 1 non-cacheable address (bits 23-16)
 33h    block 1 non-cacheable address (bits 15-12) and size
 34h    block 2 non-cacheable address (bits 23-16)
 35h    block 2 non-cacheable address (bits 15-12) and size
 36h    block 3 non-cacheable address (bits 23-16)
 37h    block 3 non-cacheable address (bits 15-12) and size
 38h    block 0/1 non-cacheable addresses (bits 26-24)
 39h    block 2/3 non-cacheable addresses (bits 26-24)
 60h    fast reset control
!!!chips\82c311.pdf p.76, p.115
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C316"

0022  -W  configuration register index (see #P461)
0023  RW  configuration register data

(Table P461)
Values for Chips&Technologies 82C315 configuration register index:
 07h    processor and bus clock source selection (see #P462)

Bitfields for C&T 82C315 clock source selection register:
Bit(s)    Description    (Table P462)
 7-5    reserved (0)
 4    80387 is present
 3    processor clock select
    =0 CLK2IN
    =1 AT bus state machine clock
 2-0    bus clock source select
    000 CLK2IN/5
    001 CLK2IN/4
    010 CLK2IN/3
    011 CLK2IN/2
    100 ATCLK
SeeAlso: #P461
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315",PORT 0022h"82C811"

0022  -W  configuration register index (see #P463)
0023  RW  configuration register data

(Table P463)
Values for Chips&Technologies 82C316 configuration register index:
 01h    clock/wait-state control    !!!chips\cs8233.pdf p.178
 26h    RTC/NMI/Coprocessor reset    !!!chips\cs8233.pdf p.231
 71h    programmable I/O port 1 address, bits 15-8
 72h    programmable I/O port 1 address, bits 7-0
 73h    programmable I/O port 1 enable
 74h    programmable I/O port 2 address, bits 15-8
 75h    programmable I/O port 2 address, bits 7-0
 76h    programmable I/O port 2 enable
 77h    programmable I/O port 3 address, bits 15-8
 78h    programmable I/O port 3 address, bits 7-0
 79h    programmable I/O port 3 enable
SeeAlso: #P461
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P467)
0023  RW  configuration register data

(Table P467)
Values for Chips&Technologies 82C811/812 configuration register index:
 60h    (82C811) processor clock select (see #P468)
 61h    (82C811) command delay (see #P469)
 62h    (82C811) wait states (see #P470)
---82C812---
 64h    version (see #P471)
 65h    ROM configuration
 66h    memory enable 1
 67h    memory enable 2
 68h    memory enable 3
 69h    memory enable 4
 6Ah    bank 0/1 enable
 6Bh    memory configuration
 6Ch    bank 2/3 enable
 6Dh    EMS base address
 6Eh    EMS address extension
 6Fh    miscellaneous
!!!chips\cs8281.pdf p.48

Bitfields for C&T 82C811 processor clock select:
Bit(s)    Description    (Table P468)
 7-6    82C811 release number (00 = initial release)
 5    fast CPU reset initiated by changing this bit from 0 to 1
 4    processor clock
    0 CLK2IN (default)
    1 BCLK
 3    reserved
 2    enable NMI generate on timeout of local-bus READY# signal
 1    reserved
 0    local-bus READY# signal timed out (128 clock cycles0
SeeAlso: #P467,#P469,#P470

Bitfields for C&T 82C811 command delay register:
Bit(s)    Description    (Table P469)
 7    enable additional address bus hold time
 6    reserved (1)
 5-4    AT-bus 16-bit memory access delay, in BCLK cycles (default = 0)
 3-2    AT-bus 8-bit memory access delay, in BCLK cycles (default = 1)
 1-0    I/O command delay, in BCLK cycles (default = 1)
SeeAlso: #P467,#P468,#P470

Bitfields for C&T 82C811 wait states register:
Bit(s)    Description    (Table P470)
 7    80387sx is present
 6    coprocessor is ready
 5-4    AT-bus 16-bit cycle wait states (default = 3)
 3-2    AT-bus 8-bit cycle wait states (00=two ... 11=five [default])
 1-0    bus clock (BCLK)
    00 CLK2IN/2 (default)
    01 CLK2IN/3
    10 ATCLK
    11 reserved
SeeAlso: #P467,#P468,#P469

Bitfields for C&T 82C812 version register:
Bit(s)    Description    (Table P471)
 7    NEATsx memory controller (0 = 82C812)
 6-5    82C812 revision (00 = initial release)
 4-0    reserved
SeeAlso: #P467
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS
Note:    each access to PORT 0023h must immediately follow a write to
      PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P464)
0023  RW  configuration register data

(Table P464)
Values for Chips&Technologies 84031/84035 configuration register index:
 01h    (84035) IPC DMA controller wait states and clock (see #P477)
!!!chips\82310.pdf p.71
!!!chips\api22.pdf p.33
 05h    (84031) ISA-bus command delays (see #P478)
 06h    (84031) ISA-bus wait states (see #P479)
 07h    (84031) ISA-bus clock select (see #P480)
 08h    (84035) performance control (see #P481)
 09h    (84035) miscellaneous control (see #P482)
 0Ah    (84035) DMA clock select (see #P483)
 10h    (84031) DRAM timing (see #P484)
!!!chips\api22.pdf p.49
 11h    (84031) DRAM setup
 12h    (84031) block 0/1 DRAM configuration
 13h    (84031) block 2/3 DRAM configuration
 14h    (84031) DRAM block 0 start address
 15h    (84031) DRAM block 1 start address
 16h    (84031) DRAM block 2 start address
 17h    (84031) DRAM block 3 start address
 18h    (84031) video shadow / local bus control
 19h    (84031) shadow RAM read enable
 1Ah    (84031) shadow RAM write enable
 1Bh    (84031) ROMCS enable
 1Ch    (84031) soft reset / GATEA20

Bitfields for C&T 84035 IPC DMA controller configuration:
Bit(s)    Description    (Table P477)
 7-6    reserved
 5-4    wait states for 16-bit DMA
    00 one (default)
    01 two
    10 three
    11 four
 3-2    wait states for 8-bit DMA (settings same as bits 5-4)
 1    disable one-cycle delay of MEMR# signal    after IOR#
 0    DMA clock (0 = BUSCLK/2 [default], 1 = BUSCLK)
SeeAlso: #P464,#P481

Bitfields for C&T 84031 ISA-bus command delays:
Bit(s)    Description    (Table P478)
 !!!
SeeAlso: #P464,#P479,#P480

Bitfields for C&T 84031 ISA-bus wait states:
Bit(s)    Description    (Table P479)
 !!!
SeeAlso: #P464,#P478,#P480

Bitfields for C&T 84031 ISA-bus clock select:
Bit(s)    Description    (Table P480)
 !!!
SeeAlso: #P464,#P478,#P479

Bitfields for C&T 84035 performance control:
Bit(s)    Description    (Table P481)
 7    flush 486 cache during every slow-mode hold (keeps CPU from running out
      of L1 cache during holds)
 6-0    width of CPU hold pulse in BUSCLKs (0-127)
SeeAlso: #P464,#P477,#P482

Bitfields for C&T 84035 miscellaneous control:
Bit(s)    Description    (Table P482)
 7    floating-point error mode
    =0 generate IRQ13 internally on FERR#
    =1 use external logic to generate IRQ13
 6    keyboard interrupt mode
    =0 receive IRQ1 directly on IRQ1 pin
    =1 receive IRQ1 over control link
 5    disable GATEA20 emulation
    =0 A20 controlled solely by PORT 0092h
    =1 A20 is OR of PORT 0092h and emulated 8042 A20 control
 4    A20M#/TEST# function
    =0 pin is TEST# input
    =1 pin is A29M# output
 3    reserved
 2    enable 8254 Timer 1 refresh requests
    clearing this bit prevents problems that may be caused by a refresh
      request which occurs during a reset sequence
 1    use VL-bus-compatible preemptive arbitration for LGNT#
 0    deturbo mode (enable CPU holds as specified by performance-control
      register) (see #P481)
Note:    the documentation says that bit 6 should remain clear
SeeAlso: #P464,#P481

Bitfields for C&T 84035 DMA clock select:
Bit(s)    Description    (Table P483)
 7    disable internal real-time clock
 6-4    reserved (0)
 3-0    DMA clock
    0000 SCLK/10
    0001 SCLK/8
    0010 SCLK/6
    1000 SCLK/5 (use with 40 MHz SCLK)
    1001 SCLK/4 (use with 33 MHz SCLK)
    1010 SCLK/3 (use with 25 MHz SCLK)
    1011 SCLK/2.5 (for 20 MHz SCLK)
    1100 SCLK/2 (for 16 MHz SCLK)
    1101 SCLK/1.5
    else reserved
Note:    bits 3-0 should normally be set the same as register 07h bits 3-0
SeeAlso: #P464

Bitfields for C&T 84031 DRAM timing:
Bit(s)    Description    (Table P484)
 7-6    reserved (0)
 5
 4
 3
 2    !!!
 1    reserved (0)
 0    read timing
    0 = 3-2-2-2
    1 = 4-3-3-3
SeeAlso: #P464,#P485

Bitfields for C&T 84031 DRAM setup:
Bit(s)    Description    (Table P485)
 7    enable DRAM parity
    (PORT 0061h bits 7 and 2 must also both be clear to enable parity)
 6-4    reserved (0)
 3-0    enable interleave for banks 3-0
    (enabling interleave doubles address range for bank; banks 0/2 and 1/3
      may be interleaved with each other)
SeeAlso: #P464,#P484
----------P00220023--------------------------
PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS
Note:    many other OPTi chipsets integrate the functionality of the 82C206, and
      thus support the 82C206's configuration register (e.g. the
      82C558 from the Viper chipset)

0022  ?W  index for accesses to data port (set to 01h)
0023  RW  chip set data

Bitfields for OPTi 82C206 configuration register 01h:
Bit(s)    Description    (Table P046)
 7-6    82C206 wait states
    00 1 SYSCLK
    01 2 SYSCLKs
    10 3 SYSCLKs
    11 4 SYSCLKs (default)
 5-4    number of wait states for 16-bit DMA cycles
    00 1 wait state (default)
    01 2 wait states
    10 3 wait states
    11 4 wait states
 3-2    number of wait states for 8-bit DMA cycles
    00 1 wait state (default)
    01 2 wait states
    10 3 wait states
    11 4 wait states
 1    enable early DMAMEMR#
 0    DMA speed
    0 SYSCLK/2
    1 SYSCLK
----------P00220023--------------------------
PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral
Range:    PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
      PORT 0398h (ISA)
SeeAlso: PORT 0024h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0022  ?W  configuration register index (see #P649)
0023  RW  configuration register data

(Table P649)
Values for Intel 82091AA configuration register index:
 00h    product ID (read-only)
    A0h Intel 82091AA
 01h    product revision (read-only) (see #P650)
 02h    configuration 1 (see #P651)
 03h    configuration 2 (see #P652)
 04h-0Fh reserved
 10h    floppy-disk controller configuration (see #P653)
 11h    floppy-disk controller power management/status (see #P654)
 12h-1Fh reserved
 20h    parallel port configuration (see #P655)
 21h    parallel port power management/status (see #P656)
 22h-2Fh reserved
 30h    serial port A configuration (see #P657)
 31h    serial port A power management/status (see #P658)
 32h-3Fh reserved
 40h    serial port B configuration (see #P657)
 41h    serial port B power management/status (see #P658)
 42h-4Fh reserved
 50h    IDE configuration (see #P659)
 51h-FFh reserved

Bitfields for Intel 82091AA product revision register:
Bit(s)    Description    (Table P650)
 7-4    stepping number
 3-0    "dash"-number
SeeAlso: #P649

Bitfields for Intel 82091AA configuration register 1:
Bit(s)    Description    (Table P651)
 7    unused (0)
 6    supply voltage (read-only) (1 = 3.3V, 0 = 5.0V)
 5-4    configuration mode
    00 software motherboard
    01 software add-in
    10 extended hardware
    11 basic hardware
 3    configuration address (read-only)
    0 primary address (PORT 0022h for X-Bus, PORT 026Eh for ISA)
    1 secondary address (PORT 0024h for X-Bus, PORT 0398h for ISA)
 2-1    reserved
 0    power-down AIP's main clock circuitry
SeeAlso: #P649,#P652

Bitfields for Intel 82091AA configuration register 2:
Bit(s)    Description    (Table P652)
 7-3    IRQ7-IRQ3 mode select
    0 = active high (ISA-compatible tri-state drive)
    1 = active low (EISA-compatible open-collector drive)
 2-0    reserved
SeeAlso: #P649,#P651

Bitfields for Intel 82091AA floppy-disk controller configuration register:
Bit(s)    Description    (Table P653)
 7    four floppy drive support enabled (with external decoder)
 6-2    reserved
 1    FDC address
    0 = primary (03F0h)
    1 = secondary (0370h)
 0    enable FDC
SeeAlso: #P649,#P654

Bitfields for Intel 82091AA floppy-disk controller power management register:
Bit(s)    Description    (Table P654)
 7-4    reserved
 3    enable FDC auto-powerdown on idle
 2    reset FDC
    (this bit must be pulsed, remaining high for at least 1.2 us)
 1    (read-only) FDC is idle
 0    power-down FDC
Note:    to restore FDC from explicit powerdown via bit 0, clear bit 0, then
      reset the FDC using bit 2 (hardware reset) or using a software reset
      (FDC's DOR bit 2 or DSR bit 7)
SeeAlso: #P649,#P653

Bitfields for Intel 82091AA parallel port configuration:
Bit(s)    Description    (Table P655)
 7    FIFO threshold
    0 = 8 slots in each direction
    1 = one slot forward, 15 reverse
 6-5    parallel-port hardware mode
    00 ISA-compatible
    01 PS/2-compatible
    10 EPP
    11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg)
 4    reserved
 3    IRQ select
    0 = IRQ5
    1 = IRQ7
 2-1    address select
    00 PORT 0378h-037Bh
    01 PORT 0278h-027Bh
    10 PORT 03BCh-03BEh (not for EPP mode)
    11 reserved
 0    enable parallel port
SeeAlso: #P649,#P656,#P663,PORT 0678h"ECP"

Bitfields for Intel 82091AA parallel port power managment register:
Bit(s)    Description    (Table P656)
 7-6    reserved
 5    FIFO overrun or underrun has occurred
    this bit is cleared by resetting the port via bit 2
 4    reserved
 3    enable auto-powerdown
 2    reset parallel port (pulse this bit; must remain high for 1.13 us)
 1    (read-only) parallel port is idle
 0    power-down parallel port
Note:    an explicit power-down may be canceled by either clearing bit 0 or
      pulsing bit 2 to reset the port
SeeAlso: #P649,#P655

Bitfields for Intel 82091AA serial port configuration:
Bit(s)    Description    (Table P657)
 7    enable 2MHz MIDI clock for MIDI baud rate
 6-5    reserved
 4    IRQ select
    0 = IRQ3
    1 = IRQ4
 3-1    address select
    000 PORT 03F8h-03FFh
    001 PORT 02F8h-02FFh
    010 PORT 0220h-0227h
    011 PORT 0228h-022Fh
    100 PORT 0238h-023Fh
    101 PORT 02E8h-02EFh
    110 PORT 0338h-033Fh
    111 PORT 03E8h-03EFh
 0    enable serial port
Note:    although it is possible to configure both serial ports at the same
      address, this is not recommended because the 82091AA disables serial
      port B without placing it into powerdown mode
SeeAlso: #P649,#P658

Bitfields for Intel 82091AA serial port power management register:
Bit(s)    Description    (Table P658)
 7-5    reserved
 4    enable test mode
    when enabled, and DLAB bit in LCR is set, the baud rate clock is output
      on the SOUTA pin
 3    enable auto-powerdown on idle
 2    reset serial port (should be pulsed, high for at least 1.13 us)
 1    (read-only) serial port is idle
 0    power-down serial port
Notes:    setting powerdown mode via bit 0 resets both receiver and transmitter,
      including the FIFOs, so software should check that port is idle
      before powering it down
    the serial port may be brought out of an explicit powerdown by either
      clearing bit 0 or pulsing bit 2
SeeAlso: #P649,#P657

Bitfields for Intel 82091AA IDE configuration:
Bit(s)    Description    (Table P659)
 7-3    reserved
 2    enable both primary and secondary addresses
 1    address select (when bit 2 is clear)
    0 PORT 01F0h-01F7h and 03F6h (primary)
    1 PORT 0170h-0177h and 0376h (secondary)
 0    enable IDE interface
 !!!intel\29048603.pdf p.45
SeeAlso: #P649,#P653
----------P00220024--------------------------
PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS
Note:    every access to PORT 0024h must be preceded by a write to PORT 0022h,
      even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P047)
0024  RW  chip set data

(Table P047)
Values for OPTi 82C281/82C282/82C283 configuration register index:
 10h    DRAM configuration register (see #P048)
 11h    Shadow RAM control register (see #P049)
 12h    Shadow RAM control register 2 (see #P050)
 13h    Shadow RAM control register 3 (see #P051)
 14h    miscellaneous control register (see #P052)
 15h    cache control register (see #P053)
 16h    cache control register 2 (see #P054)

Bitfields for OPTi 82C281/282/283 DRAM configuration register:
Bit(s)    Description    (Table P048)
 7-6    82C281/2 revision number (read-only)
 7    82C283 revision (0 = A, 1 = B)
 6    82C283A: reserved
    82C283B: DRAM is pipelined
 5    local DRAM read wait states
    82C281/2: 0=one, 1=two      82C283: 0=none, 1=one
 4    local DRAM write wait states
    82C281/2: 0=one, 1=two      82C283: 0=none, 1=one
 3-0    local DRAM memory configuration
    (val)    Bank0    Bank1    Bank2    Bank3
    0001    256K    256K    256K    256K
    0010    256K    256K    1M    -
    0011    256K    256K    1M    1M
    0100    256K    256K    4M    -
    0101    1M    -    -    -
    0110    1M    1M    -    -
    0111    1M    1M    1M    -
    1000    1M    1M    1M    1M
    1001    1M    4M    -    -
    1010    1M    1M    4M    -
    1011    4M    4M    -    -
    1100    4M    -    -    -  (82C283B only)
    1111    256K    256K    -    -
SeeAlso: #P047

Bitfields for OPTi 82C281 shadow RAM control register:
Bit(s)    Description    (Table P049)
 7    BIOS ROM F000-FFFF shadowing
    0 read-only from shadow RAM
    1 read from ROM, write to shadow RAM
 6    adapter ROM at E000-EFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by configuration register 12h
      (see #P050)
 5    adapter ROM at D000-DFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by configuration register 12h
 4    adapter ROM at C000-CFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by configuration register 13h
      (see #P051)
 3    shadow RAM Copy Enable control (C000-EFFF)
    0 write to expansion bus
    1 write to local DRAM
 2    shadow RAM E000-EFFF writeability
    0 read/write
    1 read-only
 1    shadow RAM D000-DFFF writeability
    0 read/write
    1 read-only
 0    shadow RAM C000-CFFF writeability
    0 read/write
    1 read-only
SeeAlso: #P047,#P050

Bitfields for OPTi 82C281 shadow RAM control register 2:
Bit(s)    Description    (Table P050)
 7    enable EC00-EFFF
 6    enable E800-EBFF
 5    enable E400-E7FF
 4    enable E000-E3FF
 3    enable DC00-DFFF
 2    enable D800-DBFF
 1    enable D400-D7FF
 0    enable D000-D3FF
Note:    bits 7-4 are only in effect when register 11h bit 6 is set; bits 3-0
      are only in effect when register 11h bit 5 is set
SeeAlso: #P047,#P049,#P051

Bitfields for OPTi 82C281 shadow RAM control register 3:
Bit(s)    Description    (Table P051)
 7    enable CC00-CFFF
 6    enable C800-CBFF
 5    enable C400-C7FF
 4    enable C000-C3FF
 3-0    unused shadow RAM remap address; supplies bits 23-20 of
      address at which to map A000-BFFFF and D000-EFFF is not used
      for shadowing (except if this field is set to 0, the remapping
      is disabled)
SeeAlso: #P047,#P049,#P050

Bitfields for OPTi 82C281 miscellaneous control register:
Bit(s)    Description    (Table P052)
 7    allow F0000-F0FFF to be written even while F0000-FFFFF is
      write-protected ("Zenith mode")
 6    keyboard reset control
    =1 HLT must be executed before 82C281 generates CPU reset from
        keyboard controller Reset command
 5    master byte swap enable
 4    82C281/2: fast NMI request
    82C283A: reserved (0)
    82C283B: ATCLK setting (=0 from register 14h bit 0; =1 CLK/8)
 3    82C281/2/3A: reserved
    82C283B: on-board DRAM parity error enable
 2    enable slow refresh mode
    (every 95.5 us (281/282) or 63.6 us (283) instead of 15.9 us)
 1    enable turbo switch function
 0    clock select
    =0 ATCLK2 = CPUCLK2 / 6
    =1 ATCLK2 = CPUCLK2 / 4
SeeAlso: #P047

Bitfields for OPTi 82C281/82C282 cache control register:
Bit(s)    Description    (Table P053)
 7    enable cache
 6    reserved (0)
 5    enable posted write (82C281 only)
 4    ALL accesses are non-cacheable
 3    reserved (0)
 2-0    non-cacheable region size (see also #P054)
    000  64K
    001 128K
    ...
    101  4M
    110  8M
    111 disabled
SeeAlso: #P047,#P054

Bitfields for OPTi 82C281/82C282 cache control register 2:
Bit(s)    Description    (Table P054)
 7-0    starting address bits 23-16 of non-cacheable region
Note:    the specified starting address must be a multiple of the region size
SeeAlso: #P047,#P053
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS
Note:    every access to PORT 0024h must be preceded by a write to PORT 0022h,
      even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P055)
0024  RW  chip set data

(Table P055)
Values for OPTi 82C291/82C295 configuration register index:
 20h    Revision/AT Bus configuration register (see #P056)
 21h    System Control register (see #P057)
 22h    DRAM configuration register (see #P775)
 23h    ROM Chip Select Control register (see #P776)
 24h    Shadow RAM control register E (see #P777)
 25h    Shadow RAM control register D (see #P778)
 26h    Shadow RAM control register C (see #P779)
 27h    Shadow RAM Write Protect/Remap Area (see #P780)
 28h    Cache Control register (see #P781)
 29h    Cacheable Upper Bound register (see #P782)
 2Ah    Non-Cacheable Segments register 1 (see #P783)
 2Bh    Non-Cacheable Segments register 2 (see #P784)
 2Ch    Non-Cacheable Segments register 3 (see #P785)

Bitfields for OPTi 82C291/82C295 AT Bus configuration register:
Bit(s)    Description    (Table P056)
 7-6    82C291/295 revision (read-only)
 5-4    back-to-back I/O recovery time
    00-11 = 3-6 ATCLKs between I/O accesses
 3    enable slow refresh mode
 2    enable hidden refresh
 1-0    AT clock selection
    00 ATCLK = CLK2 / 10
    01 ATCLK = CLK2 / 8
    10 ATCLK = CLK2 / 6
    11 ATCLK = CLK2 / 4
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 System Control register:
Bit(s)    Description    (Table P057)
 7    AT bus master byte swap enabled
 6    ALE generation for each AT cycle
    0 a new ALE will be generated during bus conversion cycles
    1 multiple ALEs will be generated during bus conversion cycles
 5    keyboard fast reset emulation control
    0 enable, a "Halt" is required before a fast CPU reset is generated
    1 disable, fast CPU reset is generated directly after the "FE" I/O
      command to port 64h is decoded
 4    AT cycle additional wait state
    0 disable, standard AT cycle
    1 enable, inserts one extra wait state in standard AT bus cycle
 3-2    reserved
 1    local device ready control
    0 RDYI# input to the 82C291 will be synchronized and set as RDY# to
      the CPU one T-state delayed
    1 RDYI# input to the 82C291 will not be output to the CPU. RDY# from
      the local device must be directed to the 82C291 and the CPU
 0    system memory parity checking
    0 disable, no parity checking
    1 enable, will check parity
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 DRAM Configuration register:
Bit(s)    Description    (Table P775)
 7-6    number of DRAM read cycle wait states
 5-4    number of DRAM write cycle wait states
 3-0    Banks 0 thru 3 DRAM configuration
    (val)    Bank0    Bank1    Bank2    Bank3
    0000    256K    256KB    -    -
    0001    256K    256K    256K    256K
    0010    256K    256K    1M    -
    0011    256K    256K    1M    1M
    0100    256K    256K    4M    -
    0101    1M    -    -    -
    0110    1M    1M    -    -
    0111    1M    1M    1M    -
    1000    1M    1M    1M    1M
    1001    1M    4M    -    -
    1010    1M    1M    4M    -
    1011    4M    -    -    -
    1100    4M    4M    -    -
    1101    reserved
    1110    reserved
    1111    reserved
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 ROM Chip Select Control register:
Bit(s)    Description    (Table P776)
 7    enable ROM Chip Select for write cycles (to support flash ROMs)
 6    enable ROMCS# for 0F0000-0FFFFF segments
 5    enable ROMCS# for 0E8000-0EFFFF segments
 4    enable ROMCS# for 0E0000-0E7FFF segments
 3    enable ROMCS# for 0D8000-0DFFFF segments
 2    enable ROMCS# for 0D0000-0D7FFF segments
 1    enable ROMCS# for 0C8000-0CFFFF segments
 0    enable ROMCS# for 0C0000-0C7FFF segments
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Shadow RAM control register E:
Bit(s)    Description    (Table P777)
 7    enable shadow RAM reads for EC000-EFFFF segments
 6    enable shadow RAM reads for E8000-EBFFF segments
 5    enable shadow RAM reads for E4000-E7FFF segments
 4    enable shadow RAM reads for E0000-E3FFF segments
 3    enable shadow RAM writes for EC000-EFFFF segments
 2    enable shadow RAM writes for E8000-EBFFF segments
 1    enable shadow RAM writes for E4000-E7FFF segments
 0    enable shadow RAM writes for E0000-E3FFF segments
Note:    OPTi documentation incorrectly states the segment range for bits 5
      and 1 as E4000-E7000.
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Shadow RAM control register D:
Bit(s)    Description    (Table P778)
 7    enable shadow RAM reads for DC000-DFFFF segments
 6    enable shadow RAM reads for D8000-DBFFF segments
 5    enable shadow RAM reads for D4000-D7FFF segments
 4    enable shadow RAM reads for D0000-D3FFF segments
 3    enable shadow RAM writes for DC000-DFFFF segments
 2    enable shadow RAM writes for D8000-DBFFF segments
 1    enable shadow RAM writes for D4000-D7FFF segments
 0    enable shadow RAM writes for D0000-D3FFF segments
Note:    OPTi documentation incorrectly states the segment range for bits 5
      and 1 as D4000-D7000.
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Shadow RAM control register C:
Bit(s)    Description    (Table P779)
 7    enable shadow RAM reads for CC000-CFFFF segments
 6    enable shadow RAM reads for C8000-CBFFF segments
 5    enable shadow RAM reads for C4000-C7FFF segments
 4    enable shadow RAM reads for C0000-C3FFF segments
 3    enable shadow RAM writes for CC000-CFFFF segments
 2    enable shadow RAM writes for C8000-CBFFF segments
 1    enable shadow RAM writes for C4000-C7FFF segments
 0    enable shadow RAM writes for C0000-C3FFF segments
Note:    OPTi documentation incorrectly states the segment range for bits 5
      and 1 as C4000-C7000.
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Shadow RAM Write Protect/Remap Area:
Bit(s)    Description    (Table P780)
 7    enable Write Protect for F0000-FFFFF segments
 6    enable Write Protect for E0000-EFFFF segments
 5    enable Write Protect for D0000-DFFFF segments
 4    enable Write Protect for C0000-CFFFF segments
 3-0    DRAM remap starting address, bits 23-20
    0000  disabled, no mapping
    0001  1M
    0010  2M
    ...
    1111 15M
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Cache Control register:
Bit(s)    Description    (Table P781)
 7    enable write-back cache controller operation
 6    enable DRAM performance mode
    this bit should not be enabled unless external cache is disabled
      (intended to optimize DRAM performance)
 5    enable all memory accesses no-cacheable mode
 4    enable 640K-1M area no-cacheable mode
 3-2    cache timing control bits
    00 invalid
    01 0 wait state cache write w/o CAWE# extended, use when 8K*8 SRAMs
    10 1 wait state cache write hit
    11 0 wait state cache write hit with CAWE# extended when 32K*8 SRAMs
 1-0    cache size/cacheable DRAM
    00  16K /  2M
    01  32K /  4M
    10  64K /  8M
    11 128K / 16M
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Cacheable Upper Bound register:
Bit(s)    Description    (Table P782)
 7-4    reserved
 3-0    cacheable upper bound address, bits 23-20
    0000  feature disabled
    0001  1M
    0010  2M
    ...
    1111 15M
SeeAlso: #P055

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 1:
Bit(s)    Description    (Table P783)
 7    enable non-cacheable segment A
 6-4    size of no-cacheable memory segment A
    000  64K
    001 128K
    010 256K
    011 512K
    100   1M
    101   2M
    110   4M
    111   8M
 3    enable non-cacheable segment B
 2-0    size of no-cacheable memory segment B (same values as bits 6-4)
SeeAlso: #P055,#P784

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 2:
Bit(s)    Description    (Table P784)
 7-0    address bits 23-16 for starting address of non-cacheable memory
      segment A
SeeAlso: #P055,#P783,#P785

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 3:
Bit(s)    Description    (Table P785)
 7-0    address bits 23-16 for starting address of non-cacheable memory
      segment B
SeeAlso: #P055,#P783,#P784
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS
Note:    every access to PORT 0024h must be preceded by a write to PORT 0022h,
      even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P058)
0024  RW  chip set data

(Table P058)
Values for OPTi 82C381/82C382 configuration register index:
 00h    clock selects (see #P059)
 01h    reset control (see #P060)
 10h    remapping address (see #P061)
 11h    shadow RAM (see #P062)
 12h    memory enable (see #P063)
 13h    bank configuration (see #P064)
 14h    DRAM configuration (see #P065)
 15h    video adapter shadow (see #P066)
 16h    fast GateA20 (see #P067)
 17h    cache configuration (see #P068)
 18h    non-cacheable block 1 size (see #P069)
 19h    non-cacheable block 1 address (see #P070)
 1Ah    non-cacheable block 2 size (see #P069)
 1Bh    non-cacheable block 2 address (see #P070)
 1Ch    cacheable area (see #P071)
Note:    registers 00h and 01h address the 82C381, the remaining registers
      address the 82C382
SeeAlso: #P073

Bitfields for OPTi 82C381/82C382 clock selects:
Bit(s)    Description    (Table P059)
 7-6    cache controller enable
    00 cache controller disabled (default)
    01 cache controller disabled; PPCS#, SPCS#, NPCS# signals are
          active if selected
    10 external cache controller installed
    11 on-chip cache controller installed
 5    hot CPU reset (low->high transition generates reset)
 4    enable ATCLK stretch
 3    turbo clock
    =0 CLKIN is CPU clock
    =1 HIGH pin selected clock (HIGH=0: CLKIN, HIGH=1: ICLK)
 2-1    ICLK clock select
    00 CLKIN/4 (default)
    01 CLKIN/3
    10 CLKIN/2
    11 reserved
 0    master byte swap enable (default = 0)
SeeAlso: #P058,#P060

Bitfields for OPTi 82C381/82C382 reset control:
Bit(s)    Description    (Table P060)
 7-2    reserved
 1    RESET3 control
    =1 generate RESET3 on RESET2 only after a HLT instruction
    =0 generate RESET3 immediately on RESET2 (default)
 0    activate cache controller FLUSH# pin (default = 1)
SeeAlso: #P058,#P059,#P061

Bitfields for OPTi 82C381/82C382 remapping address:
Bit(s)    Description    (Table P061)
 7-5    reserved
 4    enable remapping
 3-0    remap address range, bits 23-20
    0000  no mapping
    0001  1M
    0010  2M
    ...
    1111 15M
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 shadow RAM control:
Bit(s)    Description    (Table P062)
 7    BIOS ROM at F0000-FFFFF Shadowing
    0 read only from shadow RAM
    1 read from ROM, write to shadow RAM
 6    ROM at D0000-DFFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by configuration register 12h
 5    Adaptor ROM at E0000-EFFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by configuration register 12h
 4    write-protect shadow RAM at D0000h-DFFFFh (default = not protected)
 3    write-protect shadow RAM at E0000h-EFFFFh
 2    enable Timeout precharge counter
 1-0    reserved
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 memory enable:
Bit(s)    Description    (Table P063)
 7    enable EC000-EFFFF
 6    enable E8000-EBFFF
 5    enable E4000-E7FFF
 4    enable E0000-E3FFF
 3    enable DC000-DFFFF
 2    enable D8000-DBFFF
 1    enable D4000-D7FFF
 0    enable D0000-D3FFF
Note:    0 = disable Shadow RAM (default), 1 = enable Shadow RAM
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 memory bank configuration:
Bit(s)    Description    (Table P064)
 7    Reserved
 6-4    Bank0 and Bank1 configuration
    (val)    Bank0    Bank1
    000     256K     -
    001     256K     256K
    010     256K     1M
    011     1M       256K
    100     1M       -
    101     1M       1M
    110     -        -
    111     256K     -
 3    reserved
 2-0    Bank2 and Bank3 configuration
    (val)   Bank2    Bank3
    000     256K     -
    001     256K     256K
    010     -        -
    011     1M       256K
    100     1M       -
    101     1M       1M
    11X     -        -
SeeAlso: #P058,#P065

Bitfields for OPTi 82C381/82C382 DRAM configuration:
Bit(s)    Description    (Table P065)
 7,6    number of read cycle wait states (default = 01)
 5    write cycle wait state
    0 = 0 wait
    1 = 1 wait (default)
 4-0    reserved
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 video adapter shadow:
Bit(s)    Description    (Table P066)
 7    reserved
 6    copy enable for C0000-EFFFF
    0 write to AT Channel (default)
    1 write to local DRAM
 5    Shadow RAM at C0000-CFFFF writability
    0 read/write (default)
    1 read only
 4    ROM at C0000-CFFFF
    0 disable shadow RAM
    1 shadow RAM selectively enabled by Bits<0:3> (default)
 3    enable Shadow RAM at CC000-CFFFF
 2    enable Shadow RAM at C8000-CbFFF
 1    enable Shadow RAM at C4000-C7FFF
 0    enable Shadow RAM at C0000-C3FFF
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 fast GateA20 control:
Bit(s)    Description    (Table P067)
 7-4    Reserved
 3    Fast GateA20 Control
    0 Signal controled by GATEA20 signal from Keyboard Controler
    1 CPUA20 enabled onto GA20
 2-0    reserved
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 cache configuration:
Bit(s)    Description    (Table P068)
 7    force NCA* Output Pin low
    if this bit is clear, it has no effect on NCA* Output Pin
 6    enable Cache
 5    write-through cache (Note: this bit must be set)
 4-3    line size
    00  4 bytes
    01  8 bytes
    10  16 bytes
    11  reserved
 2-0    reserved
SeeAlso: #P058

Bitfields for OPTi 82C381/82C382 non-cacheable block size:
Bit(s)    Description    (Table P069)
 7-5    block size
    000 64K
    001 128K
    010 256K
    011 512K
    100 1M
    101 4M (block 1 only)
    101 reserved (block 2 only)
    110 8M (block 1 only)
    110 reserved (block 2 only)
    111 disabled (default)
 4-0    reserved (0)
SeeAlso: #P058,#P068,#P070

Bitfields for OPTi 82C381/82C382 non-cacheable block address:
Bit(s)    Description    (Table P070)
 7-0    bits 23-16 of non-cacheable block's address
Note:    the selected address must be a multiple of the block size
      selected by register 18h/1Ah
SeeAlso: #P058,#P069,#P071

Bitfields for OPTi 82C381/82C382 cacheable area:
Bit(s)    Description    (Table P071)
 7-4    cacheable address range
    0000 16M
    0001 1M
    0010 2M
    0011 3M
    ...
    1111 15M
 3    256K remapped area is cacheable
 2-0    reserved
SeeAlso: #P058
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS
Desc:    the 82C463MV contains a memory control unit (MCU), an AT Bus
      Control Unit (BCU), a Power Management Unit (PMU), data
      buffers and a 82C206 type IPC (without real time clock)
Note:    every access to PORT 0024h must be preceded by a write to PORT 0022h,
      even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P072)
0024  RW  chip set data

(Table P072)
Values for OPTi 82C463MV configuration register index:
 30h    general control 1 (see #P525)
 31h    general control 2 (see #P526)
 32h    shadow RAM control 1 (see #P527)
 33h    shadow RAM control 2 (see #P528)
 34h    DRAM size (see #P529)
 35h    DRAM timing and caching control (see #P530)
 36h    shadow RAM control 3 (see #P531)
 37h    D000h and E000h segment access control (see #P532)
 38h    non-cacheable block 1 size, controls and address bit A24 (see #P533)
 39h    non-cacheable block 1 address bits A23-A16
 3Ah    non-cacheable block 2 size and address bit A24 (see #P534)
 3Bh    non-cacheable block 2 address bits A23-A16
 3Ch-3Fh    reserved
 40h    PMU control 1 (see #P535)
 41h    PMU control 2: doze timer (see #P536)
 42h    PMU control 3: other timers (see #P537)
 43h    PMU control 4 (see #P538)
 44h    LCD timer count (should not be loaded with a value <5)
 45h    disk timer count (should not be loaded with a value <5)
 46h    keyboard timer count (should not be loaded with a value <5)
 47h    GNR_ACCESS timer count (should not be loaded with a value <5)
 48h    GNR_ACCESS I/O base address (lines A8-A1, A0 is a "don't care")
 49h    GNR_ACCESS control and I/O base address line A9 (see #P539)
 4Ah    CSG0# base address (lines A8-A1, A0 is a "don't care")
 4Bh    CSG0# control and base address line A9 (see #P540)
 4Ch    CSG1# base address (lines A8-A1, A0 is a "don't care")
 4Dh    CSG1# control and base address line A9 (see #P541)
 4Eh    idle timer control (see #P542)
 4Fh    idle timer count (should not be loaded with a value <5)
 50h    suspend/resume control (see #P543)
 51h    beeper/sequencer control (see #P544)
 52h    PMU general-purpose storage 1
 53h    PMU general-purpose storage 2
 54h    PMU Periferal Power (PPWR) control 1 (see #P545)
 55h    PMU Periferal Power (PPWR) control 2 (see #P546)
 56h    PIO control 1 (see #P547)
 57h    PIO control 2 (see #P548)
 58h    PMU event control 1 (see #P549)
 59h    PMU event control 2 (see #P550)
 5Ah    PMU event control 3 (see #P551)
 5Bh    PMU event control 4 (see #P552)
 5Ch    SMI source (low) (see #P553)
 5Dh    SMI source (high) (see #P554)
 5Eh    clock stretching control (see #P555)
 5Fh    resume interrupt control (see #P556)
 60h    software sequencer address (write only)
 61h    debounce control (see #P557)
 62h    doze-mode IRQ selects (see #P558)
 63h    idle timer IRQ selects (see #P559)
 64h    PMI#6 IRQ select (see #P560)
 65h    doze-mode configuration (see #P561)
 66h    suspend control (see #P562)
 67h    CPU frequency (see #P563)
 68h    timer clock source (see #P564)
 69h    R_TIMER count (should not be loaded with a value <5)
 6Ah    resume IRQ selects (see #P565)
 6Bh    resume sources (see #P566)
 6Ch-6Fh    TMP0 - TMP3

Bitfields for 82C463MV general control 1 (register 30h):
Bit(s)    Description    (Table P525)
 7-6    chipset revision number (read only)
 5    MASTER#/RI pin function (RI = modem Ring Indicator)
    =1 RI (default)
    =0 MASTER#
 4    enable turbo VGA
 3    enable global relocation/translation for SMI addresses (see also
      register 31h bit 4 at #P526)
 2    enable extra wait state in AT cycle
 1    fast reset control
      =1 does not require Halt instruction
      =0 requires Halt instruction before generation of CPURST (SRESET
           if Intel SL Enhanced or Cyrix Cx486S/S2 CPUs
 0    reserved (0)
SeeAlso: #P072

Bitfields for 82C463MV general control 2 (register 31h):
Bit(s)    Description    (Table P526)
 7    enable master byte swap
 6    reserved, read-only (1)
 5    disable parity check
 4    Dynamic SMI relocation
      if no SMI sequence is running
        =1 allow relocation of addresses from the CPU in the 3000h/4000h
           segment to the B000h/A000h SMI memory space
        =0 disable relocation
      if SMI sequence is running (qualified by SMIACT#)
        =1 allow data accesses to the 3000h and 4000h segments
        =0 relocate all accesses in the 3000h/4000h segment to the
           B000h/A000h SMI segment (normal operation)
      if SMI sequence is running (qualified by SMIADS#)
        =1 not allowed
        =0 for a SMIADS# cycle, relocate all accesses in the 6000h/7000h
           segment to the A000h/B000h SMI segment
           for a normal ADS# operation, there is no relocation
 3    EC000h-EFFFFh access control
    if register 36h bit 6=0
      =1 R/W from ROMCS#
      =0 R/W from AT-Bus
    if register 36h bit 6=1
      =1 Read from ROMCS# if not shadowed (see register 33h bits 7-4),
        write to DRAM
      =0 Read from AT-Bus if not shadowed (see register 33h bits 7-4),
        write to DRAM
 2    E8000h-EBFFFh access control (see bit 3)
 1    E4000h-E7FFFh access control (see bit 3)
 0    E0000h-E3FFFh access control (see bit 3)
SeeAlso: #P072,#P528,#P531

Bitfields for 82C463MV shadow RAM control 1 (register 32h):
Bit(s)    Description    (Table P527)
 7    segment F000h access control
      =1 read from ROMCS#, write to ROMCS# (if register 36h bit 7=1)
         or DRAM (if register 36h bit 7=0)
      =0 read from DRAM and write protect (enable shadowing)
 6-5    reserved (1)
 4    write protect segment D000h
 3    write protect segment E000h
 2    reserved, read-only (1)
 1    reserved (0)
 0    ALE control
      =1 single ALE during bus conversion
      =0 multiple ALE
SeeAlso: #P072,#P531,#P528

Bitfields for 82C463MV shadow RAM control 2 (register 33h):
Bit(s)    Description    (Table P528)
 7    enable shadowing for EC000h-EFFFFh
 6    enable shadowing for E8000h-EBFFFh
 5    enable shadowing for E4000h-E7FFFh
 4    enable shadowing for E0000h-E3FFFh
 3    enable shadowing for DC000h-DFFFFh
 2    enable shadowing for D8000h-DBFFFh
 1    enable shadowing for D4000h-D7FFFh
 0    enable shadowing for D0000h-D3FFFh
SeeAlso: #P072,#P527

Bitfields for 82C463MV DRAM size (register 34h):
Bit(s)    Description    (Table P529)
 7-4    DRAM Bank 0 and 1 Size
    0000 256K, unused
    0001 256K, 256K
    0010 256K, 1M
    0011 256K, 4M
    0100 512K, unused
    0101 512K, 512K
    0110 512K, 1M
    0111 512K, 4M
    1000 1M, unused
    1001 1M, 1M
    1010 1M, 4M
    1011 4M, 1M
    1100 4M, unused
    1101 4M, 4M
    1110 1M, 2M
    1111 both unused
 3-0    DRAM Bank 2 and 3 Size
    0000 1M, unused
    0001 1M, 1M
    0010 1M, 4M
    0011 4M, 4M
    0100 4M, unused
    0101 both unused
    0110 1M, 2M
    0111 512K, 512K
    10xx both unused
    110x both unused
    1110 2M, unused
    1111 2M, 2M (default)
SeeAlso: #P072

Bitfields for 82C463MV DRAM timing and caching control (register 35h):
Bit(s)    Description    (Table P530)
 7-6    DRAM read wait states
    00 = 0 wait states, burst mode 2-1-1-1
    01 = 1 wait state, burst mode 3-1-1-1
    10 = 1 wait state, burst mode 3-2-2-2
    11 = 2 wait states, burst mode 4-3-3-3 (default)
 5-4    DRAM write wait states
    00 = 0 wait states
    01 = 1 wait state
    10 = 2 wait states
    11 = reserved (default)
 3    MP2/STRAP2 status (read-only)
    =1 1X Clock
    =0 2X Clock
 2    disable caching of F000h segment (this bit is effective only when
      register 32h bit 7 =0)
 1    global DRAM cache control (1=disable, default)
 0    disable caching of C0000h-C7FFFh (default)
SeeAlso: #P072,#P527

Bitfields for 82C463MV shadow RAM control 3 (register 36h):
Bit    Description    (Table P531)
 7    segment F000h write control
    =1 write to ROMCS#
    =0 write to DRAM
    don't care if register 32h bit 7=0
 6    C0000h-EFFFFh control
    =1 read from AT-Bus or ROMCS# (if ROMCS# is enabled to that block),
      write to DRAM
    =0 R/W from AT bus or ROMCS# (if ROMCS# is enabled to that block)
 5    write protect segment C000h
 4    reserved (1)
 3    enable shadowing for CC000h-CFFFFh
 2    enable shadowing for C8000h-CBFFFh
 1    enable shadowing for C4000h-C7FFFh
 0    enable shadowing for C0000h-C3FFFh
SeeAlso: #P072,#P527

Bitfields for 82C463MV D000h and E000h segments access control (register 37h):
Bit    Description    (Table P532)
 7    DC000h-DFFFFh access control
    if register 36h bit 6=1
        =1 read from ROMCS# if not shadowed, write to DRAM
        =0 read from AT-Bus if not shadowed, write to DRAM
    if register 36h bit 6=0
        =1 R/W from ROMCS#
        =0 R/W from AT-Bus
 6    D8000h-DBFFFh access control (see bit 7)
 5    D4000h-D7FFFh access control (see bit 7)
 4    D0000h-D3FFFh access control (see bit 7)
 3    disable caching for EC000h-EFFFFh (default)
 2    disable caching for E8000h-EBFFFh (default)
 1    disable caching for E4000h-E7FFFh (default)
 0    disable caching for E0000h-E3FFFh (default)
SeeAlso: #P072,#P531

Bitfields for non-cacheable block 1 size, control and A24 (register 38h):
Bit(s)    Description    (Table P533)
 7-5    size of non-cacheable memory block 1
    000 64K
    001 128K
    010 256K
    011 1M
    1xx disabled (default)
 4    CC000h-CFFFFh access control
    if register 36h bit 6=1
        =1 read from ROMCS# if not shadowed, write to DRAM
        =0 read from AT-Bus if not shadowed, write to DRAM
    if register 36h bit 6=0
        =1 R/W from ROMCS#
        =0 R/W from AT-Bus
 3    C8000h-CBFFFh access control (see bit 4)
 2    C4000h-C7FFFh access control (see bit 4)
 1    C0000h-C3FFFh access control (see bit 4)
 0    address bit A24 of non-cacheable memory block 1
SeeAlso: #P072,#P531

Bitfields for non-cacheable block 2 size and A24 (register 3Ah):
Bit(s)    Description    (Table P534)
 7-5    size of non-cacheable memory block 2
    000 64K
    001 128K
    010 256K
    011 1M
    1xx disabled (default)
 4    unused
 3    enable internal HLDA latch during stop clock (must be disabled
      before DMA transfers are performed)
 2    reserved (1)
 1    unused
 0    address bit A24 of non-cacheable memory block 2
SeeAlso: #P072

Bitfields for 82C463MV PMU control 1 (register 40h):
Bit    Description    (Table P535)
 7    Reset/SMI indication (read-only)
    =1 the last read or fetch from address XXXFFFF0h was a SMIADS#
         cycle
    =0 the last read or fetch from address XXXFFFF0h was a regular
         ADS# cycle
 6    divide global timer by 4
 5    LLOWBAT polarity selector
    =1 low active
    =0 high active
 4    LOWBAT polarity selector (see bit 5)
 3    SQWIN input clock frequency
    =1 128KHz
    =0 32KHz
 2    external EPMI2 pin polarity
    =1 active low
    =0 active high
 1    external EPMI1 pin polarity (see bit 2)
 0    send reset pulse during resume
Note:    for 1X clock with Intel SL Enhanced CPU, bit 6 must be =1
SeeAlso: #P072,#P536,#P537

Bitfields for 82C463MV PMU control 2 (doze timer, register 41h):
Bit(s)    Description    (Table P536)
 7-5    hardware doze time-out selector
    101 512 ms
    110 2 sec
    111 8 sec
 4-2    hardware doze-mode CPU clock selector
    000 CPUCLK/1
    001 CPUCLK/2
    010 CPUCLK/4
    011 CPUCLK/8 (should be used during CPU stop clock only)
    100 CPUCLK/16 (should be used during CPU stop clock only)
    101 CPUCLK/3
    110 reserved
    111 reserved
 1    enable LCD_ACCESS, KBD_ACCESS, DSK_ACCESS access to auto trigger
      the hardware doze timer
 0    disable hardware doze-mode (enable APM doze-mode support)
SeeAlso: #P072,#P535,#P537

Bitfields for 82C463MV PMU control 3 (timers other than doze, register 42h):
Bit(s)    Description    (Table P537)
 7-6    clock source for general-purpose timer
    00 SQW0
    01 SQW1
    10 SQW2
    11 SQW3
 5-4    clock source for keyboard timer (see bits 7-6)
 3-2    clock source for disk timer (see bits 7-6)
 1-0    clock source for LCD timer (see bits 7-6)
SeeAlso: #P072,#P536,#P538

Bitfields for 82C463MV PMU control 4 (register 43h):
Bit(s)    Description    (Table P538)
 7    disable monitoring of PORT 3B0h-3DFh
 6    disable monitoring of memory range A0000h-BFFFFh
 5-4    LOWBAT pin sample rate
    if register 40h bit 6 =1
        00 32 seconds
        01 64 seconds
        10 128 seconds
        11 reserved
    if register 40h bit 6     =0
        00 8 seconds
        01 16 seconds
        10 32 seconds
        11 reserved
 3    reserved (0)
 2-0    AT clock select
    000 OSCCLK2/8
    001 OSCCLK2/6
    010 OSCCLK2/4
    011 OSCCLK2/3
    100 OSC14/2 (7.2 MHz)
    111 stop
SeeAlso: #P072,#P535,#P538,#P539

Bitfields for 82C463MV GNR_ACCESS control, I/O base address line A9 (reg. 49h):
Bit(s)    Description    (Table P539)
 7    GNR_ACCESS I/O base address bit A9
 6    enable compare in WRITE cycle
 5    enable compare in READ cycle
 4-0    I/O address A5-A1 mask bits. For each bit =1, the corresponding bit
      in register 48h is not compared (this is used to determine I/O
      address block size)
SeeAlso: #P072,#P538

Bitfields for 82C463MV CSG0# control and base address line A9 (register 4Bh):
Bit(s)    Description    (Table P540)
 7    Programmable Chip Select 0 (CSG0#) - I/O base address line A9
 6    enable CSG0# for I/O write cycles
 5    enable CSG0# for I/O read cycles
 4    =1 CSG0# active before ALE
    =0 CSG0# active just like I/O command pulse
 3-0    I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
      in register 4Ah (bits 4-1) is not compared (this is used to
      determine I/O address block size)
SeeAlso: #P072,#P541

Bitfields for 82C463MV CSG1# control and base address line A9 (register 4Dh):
Bit(s)    Description    (Table P541)
 7    Programmable Chip Select 1 (CSG1#) - I/O base address line A9
 6    enable CSG1# for I/O write cycles
 5    enable CSG1# for I/O read cycles
 4    =1 CSG1# active before ALE
    =0 CSG1# active just like I/O command pulse
 3-0    I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
    in register 4Ch (bits 4-1) is not compared (this is used to
    determine I/O address block size)
SeeAlso: #P072,#P540

Bitfields for OPTi 82C463MV idle timer control (register 4Eh):
Bit    Description    (Table P542)
 7    CSG1 access
 6    CSG0 access
 5    LPT access (it refers to PORT 378h-37Fh, PORT 278h-27Fh and
      PORT 3BCh-3BFh)
 4    COM access (it refers to PORT 3F8h-3FFh and PORT 2F8h-2FFh)
 3    GNR_ACCESS
 2    KBD_ACCESS
 1    DSK_ACCESS
 0    LCD_ACCESS
Note:    If a bit is =1, the corresponding access will reload IDLE_TIMER
      otherwise not.
SeeAlso: #P072

Bitfields for 82C463MV suspend/resume control (register 50h):
Bit    Description    (Table P543)
 7    software generation of SMI (enabled by bit 7 of register 59h)
      writing 1 asserts SMI to CPU to start SMM operation
      writing 0 clears the SMI (the SMI routine must clear this bit)
 6    reserved (0)
 5    IRQ8 active level
    =1 high active
    =0 low active
 4    disable the internal 14.3MHz clock (to conserve power)
 3    start doze-mode / read DOZE_TIMER status
    write: start APM doze-mode
        =1 start doze-mode (if register 40h bit 0 =1)
        =0 no effect
    read: hardware DOZE_TIMER time-out status bit
        =1 hardware DOZE_TIMER has timed out
        =0 hardware DOZE_TIMER still counting
 2    Ready To Resume (RTR), read-only
 1    PMU mode (read-only)
    =1 suspend-mode still active
    =0 all other modes
 0    start suspend-mode (write only)
    =1 start suspend-mode
    =0 no effect
SeeAlso: #P072,#P535,#P550

Bitfields for 82C463MV beeper/sequencer control (register 51h):
Bit(s)    Description    (Table P544)
 7-2    sequencer base address translated-to A17-A12 (A19-A18 are always 1
      during this operation)
 1-0    beeper control (independent from PORT 61h)
    if register 40h bit 6 =1
        00 no action
        01 1KHz
        10 off
        11 2KHz
    if register 40h bit 6 =0
        00 no action
        01 4KHz
        10 off
        11 8KHz
SeeAlso: #P072,#P535

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 1 (register 54h):
Bit(s)    Description    (Table P545)
 7-4    write mask of PPWR low nibble
    =1 enable write on corresponding bit
    =0 write disable
 3-0    read/write data bits for PPWR (low nibble)
SeeAlso: #P072,#P546

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 2 (register 55h):
Bit(s)    Description    (Table P546)
 7-4    write mask of PPWR high nibble
    =1 enable write on corresponding bit
    =0 write disable
 3-0    read/write data bits for PPWR (high nibble) (default =1)
SeeAlso: #P072,#P545

Bitfields for OPTi 82C463MV PIO control 1 (register 56h):
Bit(s)    Description    (Table P547)
 7-4    write mask of PIO bits 3-0
    =1 enable write on corresponding bit
    =0 write disable
 3-0    read/write data bits for PIO
SeeAlso: #P072,#P548,#P562

Bitfields for OPTi 82C463MV PIO control 2 (register 57h):
Bit    Description    (Table P548)
 7    enable refresh (BIOS must set this bit to 1 after power up)
 6    enable interrupts to generate PMI #6 (see also #P556,#P560)
 5    disable monitoring floppy drive accesses
 4    disable monitoring hard drive accesses
 3    PIO3/STPGNT# pin direction
    =1 output
    =0 input
 2    PIO2/CPUSPD pin direction (see bit 3)
 1    PIO1/NOWS# pin direction (see bit 3)
 0    PIO0 pin direction (see bit 3)
SeeAlso: #P072,#P547

Bitfields for OPTi 82C463MV PMU event control 1 (register 58h):
Bit(s)    Description    (Table P549)
 7-6    LOWBAT PMI #3 configuration
    00 disable
    01 sequencer
    10 reserved
    11 SMI
 5-4    EPMI2 PMI #2 configuration (see bits 7-6)
 3-2    EPMI1 PMI #1 configuration (see bits 7-6)
 1-0    LLOWBAT PMI #0 configuration (see bits 7-6)
SeeAlso: #P072

Bitfields for OPTi 82C463MV PMU event control 2 (register 59h):
Bit(s)    Description    (Table P550)
 7    global software SMI enable (see also bit 7 of register 50h at #P543)
 6    reload timers during a resume sequence
 5-4    resume or INTR PMI #6 and Suspend PMI #7 configuration
    00 disable
    01 sequencer
    10 reserved
    11 SMI
 3-2    R_TIMER PMI #5 configuration (see bits 5-4)
 1-0    IDLE_TIMER PMI #4 configuration (see bits 5-4)
SeeAlso: #P072

Bitfields for OPTi 82C463MV PMU event control 3 (register 5Ah):
Bit(s)    Description    (Table P551)
 7-6    GNR_TIMER time out PMI #11 and access PMI #15 configuration
    00 disable
    01 sequencer
    10 reserved
    11 SMI
 5-4    KBD_TIMER time out PMI #10 and access PMI #14 cfg (see bits 7-6)
 3-2    DSK_TIMER time out PMI #9 and access PMI #13 cfg (see bits 7-6)
 1-0    LCD_TIMER time out PMI #8 and access PMI #12 cfg (see bits 7-6)
SeeAlso: #P072,#P552

Bitfields for OPTi 82C463MV PMU event control 4 (register 5Bh):
Bit    Description    (Table P552)
 7    IRQ15 SMI select
    =1 enable SMI select (SMI internally connected to IRQ15) and
      disable IRQ15 hardware pin function
    =0 disable SMI select (enable IRQ15 pin function as normal)
 6    disable all SMI
 5    enable sequencer
 4    SMI Type
    =0 Intel style SMI (SMM identified by SMIACT#)
    =1 AMD DXLV or Cyrix style SMI (SMM identified by SMIADS#)
    Note:    for Intel-style SMI, the 3000h/4000h segments will relocate to
          B000h/A000h when in SMM; for AMD/Cyrix, the 7000h/6000h
          segments will relocate to B000h/A000h when in SMM
 3    enable PMI source #15
 2    enable PMI source #14
 1    enable PMI source #13
 0    enable PMI source #12
SeeAlso: #P072,#P551,#P553

Bitfields for OPTi 82C463MV SMI source (low) (register 5Ch):
Bit    Description    (Table P553)
 7    PMI #7 - SUSPEND
 6    PMI #6 - RESUME or INTR
 5    PMI #5 - R_TIMER time out
 4    PMI #4 - IDLE_TIMER time out
 3    PMI #3 - LOWBAT pin
 2    PMI #2 - EPMI2 pin (external PMI source)
 1    PMI #1 - EPMI1 pin (external PMI source)
 0    PMI #0 - LLOWBAT pin
SeeAlso: #P072,#P554

Bitfields for OPTi 82C463MV SMI source (high) (register 5Dh):
Bit    Description    (Table P554)
 7    PMI #15 - GNR_ACCESS
 6    PMI #14 - KBD_ACCESS
 5    PMI #13 - DSK_ACCESS
 4    PMI #12 - LCD_ACCESS
 3    PMI #11 - GNR_TIMER
 2    PMI #10 - KBD_TIMER
 1    PMI #9 - DSK_TIMER
 0    PMI #8 - LCD_TIMER
SeeAlso: #P072,#P553

Bitfields for OPTi 82C463MV clock stretching control (register 5Eh):
Bit    Description    (Table P555)
 7    enable CPU clock stretch memory code cycle
 6    enable CPU clock stretch write cycle
 5    enable CPU clock stretch read cycle
 4    enable CPU clock stretch I/O cycle
 3    enable CPU clock stretch memory data cycle
 2    enable stop ATCLK when not in AT bus cycle
 1    ATCLK stretch
    =1 synchronous
    =0 asynchronous
 0    reserved (0)
SeeAlso: #P072

Bitfields for OPTi 82C463MV resume interrupt control (register 5Fh):
Bit(s)    Description    (Table P556)
 7    LCD_ACCESS includes AT bus video access
 6    LCD_ACCESS includes Local bus video access
 5    enable all resume sources of register 6Ah (see also #P565,#P548)
 4    RI counter count out will generate resume
 3-0    number of RI counts
SeeAlso: #P072

Bitfields for OPTi 82C463MV debounce control (register 61h):
Bit(s)    Description    (Table P557)
 7-6    LOWBAT and LLOWBAT pin debounce rate select
    if register 40h bit 6 =1
        00 no debounce
        01 250 microseconds
        10 8ms
        11 500ms
    if register 40h bit 6 =0
        00 no debounce
        01 62.5 microseconds
        10 2 ms
        11 125 ms
 5-4    SUSP/RSM pin debounce rate select
    if register 40h bit 6 =1
        00 reserved
        01 latch high to low edge
        10 4 ms (low to high)
        11 8 ms (low to high)
    if register 40h bit 6 =0
        00 reserved
        01 latch high to low edge
        10 1 ms (low to high)
        11 2 ms (low to high)
 3    reserved (0)
 2    enable STPCLK protocol for switching CPU clock frequencies
 1-0    STPCLK# delay (for use when STPCLK protocol is enabled)
    00 no delay
    01 120 microseconds
    10 240 microseconds
    11 1ms, if register 40h bit 6 set; 240 microseconds if clear
SeeAlso: #P072,#P535

Bitfields for OPTi 82C463MV doze-mode IRQ selects (register 62h):
Bit    Description    (Table P558)
 7    enable IRQ13
 6    enable IRQ8
 5    enable IRQ7
 4    enable IRQ12
 3    enable IRQ5
 2    enable IRQ4
 1    enable IRQ3
 0    enable IRQ0
Notes:    in hardware doze-mode the selected interrupts will be used to re-load
      the hardware DOZE_TIMER and/or trigger the system out of doze-mode
    in APM doze-mode the selected interrupts will be used to trigger the
      system out of doze-mode only
SeeAlso: #P072,#P561,#P559

Bitfields for OPTi 82C463MV idle timer IRQ selects (register 63h):
Bit    Description    (Table P559)
 7    enable EPMI1 (level trigger)
 6    enable IRQ13
 5    enable IRQ8
 4    enable IRQ7
 3    enable IRQ5
 2    enable IRQ4
 1    enable IRQ3
 0    enable IRQ0
SeeAlso: #P072,#P558,#P560

Bitfields for OPTi 82C463MV PMI#6 IRQ selects (register 64h):
Bit    Description    (Table P560)
 7    enable IRQ14
 6    enable IRQ8
 5    enable IRQ7
 4    enable IRQ6
 3    enable IRQ5
 2    enable IRQ4
 1    enable IRQ3
 0    enable IRQ1
Note:    the value written into this register selects which IRQs generate
      PMI#6 in normal mode, the value read from this register indicates
      active IRQs at the time of the read
SeeAlso: #P072,#P548,#P559

Bitfields for OPTi 82C463MV doze-mode configuration (register 65h):
Bit    Description    (Table P561)
 7    enable monitoring all interrupt signals during hw or sw doze-mode
 6    doze-mode STPCLK protocol selector (see also #P557)
    =1 STPCLK will latch for stopping the CPU clock (APM)
         The delay is determined by register 61h bits 1-0
    =0 STPCLK will pulse for changing the frequency of the CPU clock
      (hw doze-mode).
         The pulse width is determined by register 61h bits 1-0
 5    enable EPMI1 to reload hardware DOZE_TIMER and exit from hardware or
      software doze-mode
 4    enable recognition of SMI during APM stop clock
 3    allow IRQ1 to exit from hw or sw doze-mode (write-only)
    (see also #P558)
 2-0    reserved (0)
SeeAlso: #P072,#P562

Bitfields for OPTi 82C463MV suspend control (register 66h):
Bit    Description    (Table P562)
 7    refresh type during suspend
    =1 self refresh
    =0 normal refresh (refresh rate selected by register 67h bit 6)
 6    KBCLK during suspend
    =1 16 KHz
    =0 7.16 MHz (14.318 MHz /2)
 5    software (APM) CPU stop-clock control
    =1 the CPU clock can be stopped by entering APM doze-mode (that is
      setting register 50h bit 3 to 1)
    =0 APM doze-mode will use the hw doze-mode clock selected by
      bits 4-2 of register 41h
 4    avoid asserting HOLD before stopping the clock
 3    PIO3/STPGNT# pin selector
    =1 STPGNT# function (set register 57h bit 3 to input mode)
        This is for use with CPUs that use the hw stop grant signal
          to acknowledge stop request
    =0 PIO3 function (set register 57h bit 3 to determine input or
      output mode)
 2    PIO2/CPUSPD pin selector
    =1 CPUSPD function, CPU speed indicator output (set register 57h
      bit 2 to output mode)
    =0 PIO2 function (set register 57h bit 2 to determine input or
      output mode)
 1    PIO1/NOWS# pin selector
    =1 NOWS# function (set register 57h bit 1 to input mode)
    =0 PIO1 function (set register 57h bit 1 to determine input or
      output mode)
 0    enable CPU clock change request protocol
Note:    for hardware doze mode, bit 5 must be 0
SeeAlso: #P072,#P536,#P543,#P548,#P563

Bitfields for OPTi 82C463MV CPU frequency (register 67h):
Bit(s)    Description    (Table P563)
 7    CPU clock control during suspend
    =1 dynamic CPU (in suspend-mode, bits 2-0 select the CPU clock)
    =0 static CPU (in suspend-mode, 82C463MV stops the CPU clock)
 6    refresh control
    =1 slow refresh (128 ms)
    =0 normal refresh (15 ms for normal operation, 30 ms for suspend mode)
 5    PMU global enabler
 4    reserved (1)
 3    reserved (0)
 2-0    CPU clock frequency
    000 CPUCLK/1
    001 CPUCLK/2
    010 CPUCLK/4
    101 CPUCLK/3
    else reserved
SeeAlso: #P072

Bitfields for OPTi 82C463MV timer clock source (register 68h):
Bit(s)    Description    (Table P564)
 7-6    R_TIMER clock source selector
    00 SQW0
    01 SQW1
    10 SQW2
    11 SQW3
 5-4    IDLE_TIMER clock source selector (see bits 7-6)
 3-2    resume recovery time
    if register 40h bit 6 =1
        00 8 ms
        01 32 ms
        10 128 ms
        11 256 ms
    if register 40h bit 6 =0
        00 2 ms
        01 8 ms
        10 32 ms
        11 64 ms
 1    enable PPWR bit 1 suspend auto toggle (see also #P545)
 0    enable PPWR bit 0 suspend auto toggle (see also #P545)
Note:    bits 1 and 0 are not influenced by mask bits 5 and 4 of register 54h
SeeAlso: #P072,#P535

Bitfields for OPTi 82C463MV resume IRQ selects (register 6Ah):
Bit    Description    (Table P565)
 7    enable EPMI2 (resume on a rising edge)
 6    enable EPMI1 (resume on a rising edge)
 5    enable IRQ8 (resume on a falling edge)
 4    enable IRQ7 (resume on a rising edge)
 3    enable IRQ5 (resume on a rising edge)
 2    enable IRQ4 (resume on a rising edge)
 1    enable IRQ3 (resume on a rising edge)
 0    enable IRQ1 (resume on a rising edge)
SeeAlso: #P072

Bitfields for OPTi 82C463MV resume sources (register 6Bh):
Bit(s)    Description    (Table P566)
 7    refresh pulse width during sequencer operation
    =1 6 AT clocks
    =0 4 AT clocks
 6-3    reserved (0)
 2-0    resume sources (read-only)
    001 RI
    010 INTR (as selected in register 6Ah)
    100 SUSP/RSM pin
    else reserved
SeeAlso: #P072,#P565
----------P00220024--------------------------
PORT 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS
Note:    every access to PORT 0024h must be preceded by a write to PORT 0022h,
      even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P073)
0023  RW  DMA clock select (see #P046)
0024  RW  chip set data

(Table P073)
Values for OPTi "Viper" (82C557) system control registers:
 00h    Byte Merge/Prefetch and Sony Cache Module Control register (see #P786)
 00h    Compatible DRAM Configuration register 1 (see #P787) (refer to note)
 01h    DRAM Control register 1 (see #P788)
 02h    Cache Control register 1 (see #P789)
 03h    Cache Control register 2 (see #P790)
 04h    Shadow RAM Control register 1 (see #P791)
 05h    Shadow RAM Control register 2 (see #P792)
 06h    Shadow RAM Control register 3 (see #P793)
 07h    Tag Test register (see #P794)
 08h    CPU Cache Control register (see #P795)
 09h    System Memory Function register (see #P796)
 0Ah    DRAM Hole A Address Decode register 1 (see #P797)
 0Bh    DRAM Hole B Address Decode register 2 (see #P798)
 0Ch    Extended DMA register (see #P799)
 0Dh    Clock Control register (see #P800)
 0Eh    Cycle Control register 1 (see #P801)
 0Fh    Cycle Control register 2 (see #P802)
 10h    Miscellaneous Control register 1 (see #P803)
 11h    Miscellaneous Control register 2 (see #P804)
 12h    Refresh Control register (see #P805)
 13h    Memory Decode Control register 1 (see #P806)
 14h    Memory Decode Control register 2 (see #P807)
 15h    PCI Cycle Control register 1 (see #P808)
 16h    Dirty/Tag RAM Control register (see #P809)
 17h    PCI Cycle Control register 2 (see #P810)
 18h    Tristate Control register (see #P811)
 19h    Memory Decode Control register 3 (see #P812)
 1Ah-1Fh reserved
Note:    Byte Merge/Prefetch and Sony Cache Module Control register is accessed
      through register 00h when bit 7 of register 13h is set, otherwise
      Compatible DRAM Configuration register 1 is accessed as register 00h
    reserved registers 1Ah-1Fh must be written to 0
SeeAlso: #P058,#P806

Bitfields for OPTi "Viper" Byte Merge / Sony Cache Module Control register:
Bit(s)    Description    (Table P786)
 7    enable pipelining of single CPU cycles to memory
 6    enable video memory byte/word read prefetch. Enables the prefetching
      of bytes/words from PCI video memory to the CPU
 5    enable Sony SONIC-2WP support. If set, the ensure that the L2 cache
      has been disabled (register 02h bits 3-2)
 4    enable byte/word merge support
 3    enable byte/word merging with CPU pipelining (NA# generation) support
 2-1    time-out counter for byte/word merge. Determines the maximum time
      difference between two consecutive PCI bye/word writes to allow
      merging
    00  4 CPU CLKs
    01  8 CPU CLKs
    10 12 CPU CLKs
    11 16 CPU CLKs
 0    enable internal hold requests to be blocked while performing byte merge
SeeAlso: #P073

Bitfields for OPTi "Viper" Compatible DRAM Configuration register 1:
Bit(s)    Description    (Table P787)
 7    enable pipelining of single CPU cycles to memory
 6    second bank SIMM selection. SIMMs need to be single sided
    0 single sided SIMM not installed in bank 0
    1 single sided SIMM installed in bank 0
 5    first bank SIMM selection. SIMMs need to be single sided
    0 single sided SIMM not installed in bank 0
    1 single sided SIMM installed in bank 0
 4-0    banks 0 thru 3 DRAM configuration
    (val)    Bank0    Bank1    Bank2    Bank3
    00000    256K    256KB    -    -
    00001    512K    512K    -    -
    00010    1M    1M    -    -
    00011    2M    2M    -    -
    00100    4M    4M    -    -
    00101    8M    8M    -    -
    00110    256K    256K    256K    256K
    00111    256K    256K    512K    512K
    01000    512K    512K    512K    512K
    01001    256K    256K    1M    1M
    01010    512K    512K    1M    1M
    01011    1M    1M    1M    1M
    01100    256K    256K    2M    2M
    01101    512K    512K    2M    2M
    01110    1M    1M    2M    2M
    01111    2M    2M    2M    2M
    10000    256K    256K    4M    4M
    10001    512K    512K    4M    4M
    10010    1M    1M    4M    4M
    10011    2M    2M    4M    4M
    10100    4M    4M    4M    4M
    10101    256K    256K    8M    8M
    10110    512K    512K    8M    8M
    10111    1M    1M    8M    8M
    11000    2M    2M    8M    8M
    11001    4M    4M    8M    8M
    11010    8M    8M    8M    8M
Note:    these settings maintain backward compatibility with the "Python"
      (82C546/82C547) chipset, and they do not allow for much flexibility
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) DRAM Control register 1:
Bit(s)    Description    (Table P788)
 7    row address hold after RAS# active in CLKs
    0 2 CLKs
    1 1 CLK
 6    RAS# active/inactive on entering master mode
    0 normal page mode when starting a master cycle, RAS# will remain
    1 RAS# inactive when starting a master cycle
 5-4    RAS pulse width used during refresh
    00 7 CLKs
    01 6 CLKs
    10 5 CLKs
    11 4 CLKs
 3    CAS pulse width during reads
    0 3 CLKs
    1 2 CLKs
 2    CAS pulse width during writes
    0 3 CLKs
    1 2 CLKs
 1-0    RAS precharge time
    00 6 CLKs
    01 5 CLKs
    10 4 CLKs
    11 3 CLKs
SeeAlso: #P073,#P789

Bitfields for OPTi "Viper" (82C557) Cache Control register 1:
Bit(s)    Description    (Table P789)
 7-6    cache size selection; determines size of the L2 cache, along with
      register 0Fh bit 0. When set, it works as a *16 multiplier
    00  64K (1M when register 0Fh bit 0 set)
    01 128K (2M when register 0Fh bit 0 set)
    10 256K (reserved when register 0Fh bit 0 set)
    11 512K (reserved when register 0Fh bit 0 set)
 5-4    cache write policy; determines the write policy for the L2 cache
    00 L2 cache write-through
    01 Adaptive Write-back Mode 1
    10 Adaptive Write-back Mode 2
    11 L2 cache write-back
 3-2    cache mode select; determines the operating mode of the L2 cache
    00 disable
    01 Test Mode 1, External Tag Write (Tag data write-through reg. 07h)
    10 Test Mode 2, External Tag Read (Tag data read from register 07h)
    11 enable L2 cache
 1    enable DRAM posted write
 0    CAS precharge time
    0 2 CLKs
    1 1 CLK
SeeAlso: #P073,#P794,#P802,#P790

Bitfields for OPTi "Viper" (82C557) Cache Control register 2
Bit(s)    Description    (Table P790)
 7-6    L2 cache write burst mode timings
    00 X-4-4-4
    01 X-3-3-3
    10 X-2-2-2
    11 X-1-1-1
 5-4    L2 cache write lead-off cycle timings
    00 5-X-X-X
    01 4-X-X-X
    10 3-X-X-X
    11 2-X-X-X
 3-2    L2 cache read burst mode timings
    00 X-4-4-4
    01 X-3-3-3
    10 X-2-2-2
    11 X-1-1-1
 1-0    L2 cache read lead-off cycle timings
    00 5-X-X-X
    01 4-X-X-X
    10 3-X-X-X
    11 2-X-X-X
Note:    SRAM double bank implementation does not support lead-off timing
SeeAlso: #P073,#P789

Bitfields for OPTi "Viper" (82C557) Shadow RAM Control register 1:
Bit(s)    Description    (Table P791)
 7-6    CC000-CFFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 5-4    C8000-CBFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 3    enable synchronous SRAM pipelined read cycle 1-1-1-1
 2    E0000-EFFFF range selection
    0 area will always be non-cacheable
    1 are will be treated like the F0000h BIOS area
 1-0    C0000-C7FFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
Note:    bit 3 will act only when register 11h bit 3 and register 03h bits 3-2
      are all set
    when bit 2 is set, register 06h bits 3-0 should be set identically
SeeAlso: #P073,#P792

(Table P813)
Values for OPTi "Viper" (82C557) Shadow RAM Control setting:
 00    read/write PCI bus
 01    read from DRAM/write to PCI
 10    read from PCI/write to DRAM
 11    read from/write to DRAM
SeeAlso: #P791,#P792,#P793

Bitfields for OPTi "Viper" (82C557) Shadow RAM Control register 2:
Bit(s)    Description    (Table P792)
 7-6    DC000-DFFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 5-4    D8000-DBFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 3-2    D4000-D7FFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 1-0    D0000-D3FFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
SeeAlso: #P073,#P791,#P793

Bitfields for OPTi "Viper" (82C557) Shadow RAM Control register 3:
Bit(s)    Description    (Table P793)
 7    DRAM hole in system memory from 80000-9FFFF; gives the user the option
      to have some other device in this address range instead of system
      memory. When set, the SYSC will not start the system DRAM controller
      for accesses to this particular address range
    0 no memory hole
    1 enable memory hole
 6    wait state addition for PCI master snooping
    0 do not add a wait state
    1 add a wait state for the cycle access to finish and then do snooping
 5    enable C0000-C7FFF cacheability in L1 and L2 cache memory
 4    enable F0000-FFFFF cacheability in L1 and L2 cache memory
 3-2    F0000-FFFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
 1-0    E0000-EFFFF read/write control; determines the R/W control for these
      segments of the shadow RAM (see #P813)
Note:    L1 cacheability can be disabled thru register 08h bit 0
    If register 04h bit 2 is set, then F0000-FFFFF and E0000-EFFFF R/W
    control settings should have similar values
SeeAlso: #P073,#P792

Bitfields for OPTi "Viper" (82C557) Tag Test register:
Bit(s)    Description    (Table P794)
 7-0    Tag Test register; when in cache Test Mode, data is read from/written
      to this register
SeeAlso: #P073,#P789

Bitfields for OPTi "Viper" (82C557) CPU Cache Control register:
Bit(s)    Description    (Table P795)
 7    L2 cache single/double bank select
    0 two banks of L2 cache
    1 single bank of L2 cache (non-interleaved)
 6    enable snoop filtering for bus masters
 5    CPU HITM# pin sample timing
    0 delay one clock, therefore HITM# sampled on the third rising edge
      of LCLK after EADS# has been asserted
    1 do not delay, therefore HITM# sampled on the second rising edge
 4    enable parity checking
 3    Tag/Dirty RAM implementation
    0 Tag and Dirty are on separate chips
    1 Tag and Dirty are on the same chip
 2    enable CPU address pipelining
 1    enable L1 cache write-back and write-through control
    0 write-through only
    1 write-back enabled
 0    disable BIOS and Video BIOS areas cacheability in L1 cache
Note:    If asynchronous SRAM, then cache memory banks (when two are present)
      are interleaved, otherwise, they are not
    When register 04h bit 2 is set, bit 0 affects BIOS area E0000-EFFFF;
      when clear, bit 0 affects are F0000-FFFFF
SeeAlso: #P073,#P796

Bitfields for OPTi "Viper" (82C557) System Memory Function register:
Bit(s)    Description    (Table P796)
 7-6    DRAM Hole B size
    (address specified by register 0Bh, and register 0Ch bits 3-2)
    00 512K
    01   1M
    10   2M
    11   4M
 5-4    DRAM Hole B control mode
    00 disable
    01 write-through for L1 and L2 cache
    10 non-cacheable for L1 and L2 cache
    11 enable hole in DRAM
 3-2    DRAM Hole A size (settings same as bits 7-6)
    (address specified by register 0Ah, and register 0Ch bits 1-0)
 1-0    DRAM Hole A control mode (settings same as bits 5-4)
SeeAlso: #P073,#P798,#P799

Bitfields for OPTi "Viper" (82C557) DRAM Hole A Address Decode register 1:
Bit(s)    Description    (Table P797)
 7-0    DRAM Hole A address, bits 26-19
    (bits 1-0 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P073,#P799,#P798

Bitfields for OPTi "Viper" (82C557) DRAM Hole B Address Decode register 2:
Bit(s)    Description    (Table P798)
 7-0    DRAM Hole B address, bits 26-19
    (bits 3-2 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P073,#P799,#P797

Bitfields for OPTi "Viper" (82C557) Extended DMA register:
Bit(s)    Description    (Table P799)
 7    reserved (0)
 6    Fast BRDY# generation for DRAM write page hits
    0 BRDY# for DRAM writes generated on the fourth clock
    1 BRDY# for DRAM writes generated on the third clock
 5    HACALE one-half a clock cycle earlier
    0 HACALE normal timing
    1 HACALE one-half a clock cycle early enabled
 4    wider cache WE# pulse
    0 cache WE# pulse width is normal (~15ns)
    1 cache WE# pulse is wider (~17.5ns)
 3-2    DRAM Hole B starting address, bits 28-27 (see also #P797)
 1-0    DRAM Hole A starting address, bits 28-27 (see also #P798)
Note:    bits 26-19 of memory holes A and B are mapped from Indices 0Ah and 0Bh
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Clock Control register:
Bit(s)    Description    (Table P800)
 7    clock source for generation the syncronous SRAM timing
    0 CPU clock is the source for the timing and control signals
    1 ECLK is the source for the timing and control signals
 6    this bit is set if the skew between ECLK and CPU clock is too large
      (read-only bit, set by the 82C557 chip)
 5    enable auto skew detect; when this bit is set, bit 4 will be set
      automatically if the skew between CLK and ECLK is too large
 4    ECLK - CLK skew, activated when synchronou SRAMs are being used
    0 skew between CLK and ECLK is not too large
    1 skew is too large
 3    enable A0000-BFFFF as system memory
 2    wait state addition for PCI master doing address toggling as a 486
    0 linear burst mode style address toggling - no wait state addition
    1 i486 burst style address toggling - one wait state needs to be added
 1    PCI cycle claimed by the 82C557 during PCI pre-snoop cycle
    0 82C557 does not claim the PCI cycle after it asserts STOP#
    1 82C557 claims the PCI cycle after it asserts STOP#
 0    slow CPU clock; should be set if the CPU clock frequency has been
      reduced
    0 CPU clock frequency is normal
    1 CPU clock has been slowed down
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Cycle Control register 1:
Bit(s)    Description    (Table P801)
 7-6    PCI master read burst wait state control
    00 4 cycles
    01 3 cycles
    10 2 cycles
    11 reserved
 5-4    PCI master write burst wait state control (same settings as bits 7-6)
 3    master cycle parity enable; this bit becomes applicable when bit 4 of
      register 08h is set
    0 enable parity check during master cycles
    1 disable parity check during master cycles
 2    HACALE timing control
    0 HACALE high during HITM# before CPU ADS#
    1 HACALE low and CA4 always enabled during HITM cycle
 1    enable write protection for L1 BIOS
 0    PCI line comparator; this bit is only valid when bit 6 of register 08h
      is set
    0 use line comparator in PCI master
    1 generate inquire cycle for every new FRAME#
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Cycle Control register 2:
Bit(s)    Description    (Table P802)
 7    enable PCI pre-snooping feature
 6    AT master wait state control
    0 do not add any wait states for AT master cycles
    1 add wait wait states for AT master cycles
 5    wait state addition for synchronous SRAM even byte access
    0 do not add a wait state for a synchronous SRAM even byte access
    1 add one wait state for a synchronous SRAM even byte access
 4    PCI wait state addition for synchronous SRAM L2 cache implementation
    0 master does not wait for end of current cycle + CPU-PCI clock to
      become synchronous
    1 master waits for end of current cycle + wait for CPU-PCI clock to
      become synchronous
 3    reserved
 2    ADSC# generation for synchronous SRAM read cycle
    0 generate ADSC# immediately after CPU ADS# goes active
    1 generate ADSC# one clock after CPU ADS# goes active
 1    reserved
 0    L2 cache size selector; works along with bits 1-0 of register 02h
    0 below 1M
    1 1M and above
SeeAlso: #P073,#P789

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 1:
Bit(s)    Description    (Table P803)
 7    early decode of PCI/VL/AT cycle
    0 CPU to PCI/VL/AT slave cycle triggered after second T2
    1 CPU to PCI/VL/AT slave cycle triggered after first T2
 6    cache modified write cycle timing
    0 use the old address changing method, as in the 82C546/82C547
    1 two bank cache, CA4 delayed one-half a clock for write cycles
 5    pipelined read cycle timing; determines the lead-off cycle
    0 3-X-X-X read followed by a 3-X-X-X piped read cycle
    1 3-X-X-X read followed by a 2-X-X-X piped read cycle
 4    enable write hit pipelined
    0 do not enable 2-X-X-X pipelined write hit cycles
    1 enable 2-X-X-X pipelined write hit cycles
 3    write pulse timing control for cache write hit cycles
    0 do not change the write pulse timing during X-2-2-2 write hit cycles
    1 move the write pulse one-half a clock later in X-2-2-2 write hit
      cycles
 2    write pulse timing control for cache write hit cycles
    0 do not change the write pulse timing during 3-X-X-X write hit cycles
    1 move the write pulse one-half a clock later in 3-X-X-X write hit
      cycles
 1    external 74F126 select
    0 an external 74F126 is installed for CA3 and CA4
    1 an external 74F126 is not installed for CA3 and CA4
 0    LCLK select control; when this bit is set, the timing constraints
      between the LCLK and the CPUCLK inputs to the SYSC need to be met.
      This constraints are: LCLK <= 1/2 CPUCLK period before CPUCLK, and
      LCLK <= 0.5ns after CPUCLK
    0 LCLK is asynchronous to the CPUCLK
    1 LCLK is synchronous to the CPUCLK; LCLK = CPUCLK/2
Note:    bit 1 should always be set to 1
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 2:
Bit(s)    Description    (Table P804)
 7-6    reserved; must be set to 0
 5    cache inactive during Idle state control
    0 SRAM always active
    1 SRAM inactive during Idle state
 4    next address (NA#) mode control
    0 normal NA# timing used with asynchronous SRAMs
    1 new NA# timing for synchronous SRAMs; used only when CPU operating
      at 50MHz
 3    SRAM type
    0 asynchronous SRAM
    1 synchronous SRAM
 2    enable page miss posted write
 1    ISA/DMA IOCHRDY control
    0 old mode, no IOCHRDY during line hit
    1 drive IOCHRDY low until cycle is finished
 0    delay start
    0 old mode, do not delay internal master cycle after an inquire cycle
    1 delay internal master cycles by one LCLK after an inquire cycle
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Refresh Control register:
Bit(s)    Description    (Table P805)
 7    REFRESH#/32KHz source selection
    0 REFRESH# source is REFRESH# pulse from the 82C558 or the ISA master
    1 REFRESH# pulse source is a 32KHz clock
 6    reserved; must be written to 0
 5-4    suspend mode refresh
    00 from CLK state machine
    01 slef refresh based on 32KHz only
    10 normal refresh based on 32KHz only
    11 undefined
 3-2    slow refresh
    00 refresh on every REFRESH#/32KHz falling edge
    01 refresh on alternate REFRESH#/32KHz falling edge
    10 refresh on one in four REFRESH#/32KHz falling edge
    1 refresh on every REFRESH#/32KHz toggle
 1    enable bits 23-17 of LA from Refresh Page register (8Fh) during refresh
 0    enable output of bits 7-4 of DBC MP during master write
    0 disable the DBC from generation the MP[7:4] lines during PCI master
      writes; there must be a pull-up on MP0
    1 enable the DBC to generate the MP[7:4] lines during PIC master
      writes; there must be a pull-down on MP0
SeeAlso: #P073,#P806

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 1:
Bit(s)    Description    (Table P806)
 7    memory decode select
    0 Byte Merge/Prefetch and Sony Cache Module Control register is
      available in register 00h; compatible to 82C547 DRAM configurations
    1 Compatible DRAM Configuration register is available in register 00h;
      full decode option; this gives the user maximum flexibility in
      choosing different DRAM configurations
 6-4    full decode for logical bank 1 (RAS#1), if bit 7 set. This settings
      apply to 36-pin banks only (see #P814)
 3    enable SMRAM
 2-0    full decode for logical bank 0 (RAS#0), if bit 7 set. This settings
      apply to 36-pin banks only (see #P814)
SeeAlso: #P073,#P786,#P787

(Table P814)
Values for OPTi "Viper" (82C557) Memory Bank Decode Control registers:
 000      0K
 001    256K
 010    512K
 011      1M
 100      2M
 101      4M
 110      8M
 111     16M
SeeAlso: #P806,#P807,#P810

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 2:
Bit(s)    Description    (Table P807)
 7    reserved; must be written to 0
 6-4    full decode for logical bank 3 (RAS#3), if register 13h bit 7 is set
      (see #P814)
 3    SMRAM control
    0 disable SMRAM (enable SMRAM for both Code and Data if SMIACT# is
      active and register 13h bit 3 is set)
    1 enable SMRAM (enable SMRAM for Code only if SMIACT# is active and
      register 13h bit 3 is set)
 2-0    full decode for logical bank 2 (RAS#2), if register 13h bit 7 is set
      (see #P814)
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) PCI Cycle Control register 1:
Bit(s)    Description    (Table P808)
 7-6    CPU master to PCI memory slave, write IRDY# control
    00 3 LCLKs after end of address phase
    01 2 LCLKs after end of address phase
    10 1 LCLK after end of address phase
    11 0 LCLK after end of address phase
 5-4    CPU master to PCI slave write posting, bursting control
    00 PCI slave write, no posting, no bursting
    01 PCI slave write, posting enabled, no bursting
    10 PCI slave write, posting enabled, conservative bursting
    11 PCI slave write, posting enabled, aggressive bursting
 3-2    master retry timer
    00 retries unmasked after 10 PCICLKs
    01 retries unmasked after 18 PCICLKs
    10 retries unmasked after 34 PCICLKs
    11 retries unmasked after 66 PCICLKs
 1    reserved; must be written to 0
 0    PCI cycle, FRAME# timing control for pipelined cycles
    0 PCI cycle FRAME# assertion is done in the conservative mode style
    1 PCI cycle FRAME# assertion is done in the aggressive mode style
SeeAlso: #P073,#P810

Bitfields for OPTi "Viper" (82C557) Dirty/Tag RAM Control register:
Bit(s)    Description    (Table P809)
 7    Dirty pin selection; reflects the kind of SRAM chosen to implement the
      Dirty RAM; it also determines the functionality of the DIRTYI pin of
      the 82C557
    0 DIRTYI pin is input-only
    1 DIRTYI pin is bidirectional
 6    reserved; must be written to 0
 5    Tag RAM size
    0 = 8-bit Tag
    1 = 7-bit Tag
 4    write hit cycle lead-off time when combining Dirty/Tag RAM
    0 single write hit lead-off cycle = 5 cycles
    1 single write hit lead-off cycle = 4 cycles
 3    pre-snoop control
    0 pre-snoop for starting address 0 only
    1 pre-snoop for all addresses except those on the line boundary
 2    reserved; must be written to 0
 1    CPU to VL read access, DBC DLE# bits 1-0 timing
    0 LCLK high
    1 LCLK low
 0    HDOE# timing control
    0 HDOE# is negated normally
    1 HDOE# is negated one clock before the cycle finishes
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) PCI Cycle Control register 2:
Bit(s)    Description    (Table P810)
 7    NA# assertion control for PCI slave accesses when synchronous PCI clock
      is used
    0 no pipelining for accesses to PCI slave
    1 pipelining enabled for accesses to PCI slave for both synchronous and
      asynchronous PCI solutions; if set, overrides bit 6
 6    NA# assertion control for PCI slave accesses when asynchronous PCI
      clock is used
    0 no pipelining for accesses to PCI slave
    1 pipelining enabled for accesses to PCI slave for an asynchronous PCI
      implementation; this bit is overridden if bit 7 is set
 5    enable support for Intel standard BSRAM
    0 no support for Intel standard BSRAM
    1 support for Intel standard BSRAM; should be set only if using two
      banks of synchronous SRAM
 4    enable fast BRDY# generation for PCI cycles
 3    enable fast FRAME# generation for PCI cycles
 2    byte merging/piping control
    0 no pipelining when byte merging is on
    1 pipelining enabled along with byte merging
 1    pipelined synchronous SRAM support; this bit is applicable only if
      register 11h bit 3 is set
    0 standard synchronous SRAM installed
    1 pipelined synchronous SRAM installed
 0    Cyrix linear burst mode support
    0 normal Intel standard burst mode
    1 support for Cyrix linear burst mode
SeeAlso: #P073,#P808

Bitfields for OPTi "Viper" (82C557) Tristate Control register:
Bit(s)    Description    (Table P811)
 7-6    reserved; must be written to 0
 5    voltage selection for the CAS# lines 7-0
    0 CAS# lines 7-0 are driven out at 5.0V logic level
    1 CAS# lines 7-0 are driven out at 3.3V logic level
 4    programmable current drive for the MA[X], RAS[X]# and the DWE# lines
    0 driving capability on these lines is 4mA
    1 driving capability on these lines is 16mA
 3    enable tristate CPU interface during Suspend and during CPU power-off
 2    enable tristate PCI interface during Suspend and during PCI power-off
 1    enable tristate cache interface during Suspend and cache power-off
 0    enable the pull-up/pull-down resistors during Suspend and power-off
SeeAlso: #P073

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 3:
Bit(s)    Description    (Table P812)
 7    DIRTYWE# RAS5# selection; if six DRAM banks are chosen, then the line
      will become RAS#5, if this bit is set
    0 DIRTYWE# functions as DIRTYWE# (six banks of DRAM are not chosen)
    1 DIRTYWE# functions as RAS#5 (six banks of DRAM are chosen)
 6-4    full decode for logical bank 5 (RAS#5) if register 13h bit 7 and
      register 19h bit 7 are set (see #P814)
 3    MA11/RAS#4 selection; if five DRAM banks are chosen, then the MA11 line
      will become RAS#4, if this bit is set
    0 MA11 functions as MA11 (the fifth bank of DRAM is not chosen)
    1 MA11 functions as RAS#4 (five banks of DRAM have been chosen)
 2-0    full decode for logical bank 4 /RAS#4) if register 13h bit 7 and
      register 19h bit 3 are set (see #P814)
Note:    if bit 7 is set, then a combined Dirty/Tag SRAM solution must be
      implemented or else it will not have a Dirty RAM
    if bit 3 is set, then none of the DRAM banks will support the 8M*36
      or 16M*36 options
SeeAlso: #P073
----------P00220025--------------------------
PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)

0022  -W  CPU write mode register
0023  R-  configuration status register
        bit 7: 82360 configuration is open
0024  -W  82360 configuration index
0025  RW  82360 configuration data

Bitfields for Intel 82360SL CPU write mode register:
Bit(s)    Description    (Table P074)
 0    unlock configuration space
 1    enable selected unit
 3-2    unit
    00 memory configuration
    01 cache
    10 internal bus
    11 external bus
----------P0022002B--------------------------
PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx
Note:    initialisation in POST will disable these addresses, only a hard
      reset will enable them again.

0022w RW  82335 MCR memory configuration register (if LOCK=0) (see #P075)
0024w RW  82335 RC1 roll compare register (if LOCK=0) (see #P076)
0026w RW  82335 RC2 roll compare register (if LOCK=0) (see #P076)
0028w RW  82335 CC0 address range compare register (if LOCK=0) (see #P077)
002Aw RW  82335 CC1 address range compare register (if LOCK=0) (see #P077)

Bitfields for 82335 MCR memory configuration register:
Bit(s)    Description    (Table P075)
 15-12    reserved
 11    "VRO"    video read only (0=r/w, 1=r/o)
 10    "EN#"
    0=enable video RAM accesses (A0000h-8FFFFh)
    1=disable accesses
 9    "ENADP#"
    0=enable adapter ROM accesses (C0000h-8FFFFh)
    1=disable adapter ROM accesses, shadow enabled
 8    "ROMSIZE" 0=256KB ROM, 1=512KB ROM
 7-6    "INTERL" memory interleaving
    00 = 1 memory bank installed (no interleave)
    01 = 2 memory banks installed
    10 = 3 memory banks installed
    11 = 4 memory banks installed
 5    reserved
 4    "DSIZE"     0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
 3    "S640"     base memory size is 0=512KB, 1=640KB
 2-1    reserved
 0    "ROMEN#" ROM enable
    0 enable BIOS ROM accesses (E0000h-FFFFFh)
    1 disable BIOS ROM accesses, enable shadow
Note:    One of the remaining reserved bits is the LOCK bit, which will be set
      during power on, disabling access to the 82335s registers.

Bitfields for 82335 roll compare register:
Bit(s)    Description    (Table P076)
 15-9    selects address range to be remapped (C23-C17)
 8    reserved
 7-1    selects address bits to be included in re-mapping comparision (M23-M17)
 0    "EN" enables roll address mapping

Bitfields for 82335 address range compare register:
Bit(s)    Description    (Table P077)
 15-11    specifies top of address range (C23-C19)
 10-8    reserved
 7-3    selects address bits to be included in address range comparision
      (M23-M19)
 2-1    reserved
 0    "EN" enable address range comparision
----------P00240025--------------------------
PORT 0024-0025 - Intel 82091AA Advanced Integrated Peripheral
Range:    PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
      PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0024  ?W  configuration register index
0025  RW  configuration register data
----------P00240027--------------------------
PORT 0024-0026 - PicoPower Vesuvius - V3-LS
Note:    software must use 8-bit accesses to these ports; 16-bit accesses will
      be directed to the V1-LS chip in the chipset instead of the V3-LS
SeeAlso: PORT 0024h"V1-LS"

0024b  ?W  V3-LS register index (see #P446)
0026b  RW  V3-LS register data

(Table P446)
Values for PicoPower Vesuvius V3-LS register index:
 00h    Revision ID
 01h
 ...
 26h    PMI Trigger Source Register 2
details to follow (!!!natsemi\pt86c521-vc-b.pdf p.323)
SeeAlso: #P445
----------P00240027--------------------------
PORT 0024-0027 - PicoPower Vesuvius - V1-LS
Note:    software must use 16-bit accesses to these ports; 8-bit accesses will
      be directed to the V3-LS chip in the chipset instead of the V1-LS
SeeAlso: PORT 0024h"V3-LS"

0024w  ?W  V1-LS register index (see #P445)
0026w  RW  V1-LS register data

(Table P445)
Values for PicoPower Vesuvius V1-LS register index:
 01xxh    (reset sampling and miscellaneous)
 0100h
 ...
 011Fh    Docking Control
 02xxh    (DRAM registers)
 0200h
 ...
 0212h    Burst EDO control
 03xxh    (Power Management control)
 0300h
 ...
 0354h    Edge Detect Control
 04xxh    (Level-2 Cache)
 0400h    L2 Cache Configuration
 0401h    L2 Cache Timing
 0402h    L2 Cache Miscellaneous
details to follow (!!!natsemi\pt86c521-vc-b.pdf p.78, p.281)
SeeAlso: #P446
----------P00240028--------------------------
PORT 0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET

0024  Rw  data port
0028  ?W  index port to chipset registers (see #P078,#P079)

(Table P078)
Values for Headland HT321 register index:
 00h R    chip/revision,read-only
      bit7-4: reserved (=0)
      bit3-0: chip revision, 0=A, 1=B, 3=D
 01h RW system clocking (default=00h)
      bit7-4: reserved (=0)
      bit3-0: ISA speed set
 02h RW system parameters (default=00h) (see #P080)
 04h RW co-processor (default=00h)
      bit7-3: reserved (=0)
      bit2=1: soft-NPU reset blocked (386 only)
      bit1=1: weitek installed
      bit0=1: 387 installed
 06h RW DMA (default=00h) (see #P081)
 07h RW EPROM (default=00h) (see #P082)
 08h RW I/O and memory map holes (default=00h)
      bit7-4: reserved (=0)
      bit3    : 0/1 I/O map hole-A
      bit2    : reserved (=0)
      bit1    : 0/1 memory map hole-B
      bit0    : reserved (=0)
 10h RW hole-A low address (default=00h)
 11h RW hole-A high address (default=00h)
 19h RW mem hole-B start address, lower (default=00h)
 1Ah RW mem hole-B start address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B start
 1Ch RW mem hole-B end address, lower (default=00h)
 1Dh RW mem hole-B end address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B end
SeeAlso: #P079

(Table P079)
Values for Headland HT342 register index:
 20h R    identifier port read
      bit7-4: DRAM controller identifier (0010b)
      bit3-0: revision number (0=A)
 21h R    feature port read    (default=00h)
 24h RW DRAM options port #1 (default=00h)
      bit7    : 0/1 staggered refresh
      bit6    : refresh type
      bit5    : 0/1 DRAM paging
      bit4-2: CAS interleave
      bit1-0: banks
 25h    DRAM options port #2 (default=00h)
      bit7-6: DRAM bank 1 type
      bit5-4: DRAM bank 2 type
      bit3-2: DRAM bank 1?? type
      bit1-0: DRAM bank 0 type
 26h RW DRAM options port #3 (default=FFh) (see #P083)
 27h RW DRAM options port #4 (default=FFh) (see #P084)
 28h RW data transfer control port (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7    : initiate transfer
      bit6    : read/write transfer
      bit5-4: reserved
      bit3-0: transfer/destination
 29h RW RAM address register (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-5: reserved
      bit4-0: RAM address registers contents
 2Ah RW data transfer port   (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-6: reserved
      bit5    : EMS translation
      bit4    : reserved
      bit3    : 0/1 cacheing
      bit2    : 0/1 write
      bit1    : 0/1 read
      bit0    : 0/1 shadow
 2Bh RW other options          (default=00h) (see #P085)
 2Dh RW DRAM options port #5 (default=03h)
      bit7-5: reserved
      bit4    : 0/1 10µs RAS timeout
      bit3-2: BUS speed
      bit1-0: BUS recovery for DRAM cycles
           00b=0: 4-1-1-1    10b=0.5
           01b=1: 4-2-2-2    11b=1??
 82h    read transfer
 C2h    write transfer
SeeAlso: #P078

Bitfields for Headland HT321 register 02h (system parameters):
Bit(s)    Description    (Table P080)
 7-6    IO recovery time (rev. D+)
 5    parity override
 4-3    cycle-width
 2    0/1 PORT 0092h functionality
 1    IO decode
 0    0/1 posted backplane MEMWN cycles
SeeAlso: #P078

Bitfields for Headland HT321 register 06h (DMA control):
Bit(s)    Description    (Table P081)
 7    reserved (=0)
 6    1/0 IOCHRDY during master cycle (rev. C+)
 5    0/1 fast sample DMA
 4-3    DMA waitstate 00b=3 .. 11b=0
 2    0/1 DMA flow-through mode
 1    0/1 extended DMA page register
 0    DMA clock
SeeAlso: #P078

Bitfields for Headland HT321 register 07h (EPROM control):
Bit(s)    Description    (Table P082)
 7-6    reserved (=0)
 5    0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
 4    0/1 ROMEN for EPROM writes (rev. C+)
 3    0/1 middle BIOS region of 64KB space below 16MB
 2    ROM-size (0=64KB, 1=128KB)
 1    V-BIOS-add (0=separate, 1=same device)
 0    ROM-access time (0=250ns, 1=125ns)
SeeAlso: #P078

Bitfields for Headland HT342 register 26h (DRAM CAS control):
Bit(s)    Description    (Table P083)
 7    CAS hold on RAS (CAS before RAS refresh)
 6    CAS precharge
 5    CAS burst delay
 4    CAS delay (writes)
 3    CAS delay (reads)
 2    CAS active time (writes)
 1-0    CAS active time (reads)
SeeAlso: #P079,#P084

Bitfields for Headland HT342 register 27h (DRAM RAS control):
Bit(s)    Description    (Table P084)
 7    RAS delay
 6-5    RAS active (writes)
 4-2    RAS active (reads)
 1-0    RAS precharge
SeeAlso: #P079,#P083

Bitfields for Headland HT342 register 2Bh (other options):
Bit(s)    Description    (Table P085)
 7    reserved
 6    0/1 middle BIOS
 5    0/1 data pipeline
 4    0/1 data pipeline
 3    IO-decode
 2    reserved
 1    16bit DMA bridge
 0    0/1 write buffering
SeeAlso: #P079
----------P00260027--------------------------
PORT 0026-0027 - INTEL 82347 POWER MANAGEMENT PERIPHERAL
SeeAlso: PORT 0178h-0179h

0026  -W  index for data port (see #P086)
0027  RW  power management data

(Table P086)
Values for Intel 82437 Power Management Peripheral register index:
 C0h    suspend/wakeup status, system state
 C1h    power supply and activity status, general-purpose output/control
 C2h    control bits
 C3h    activity mask
 C4h    NMI mask
 C5h    I/O range for activity monitor
 C6h    power output control bits, ON state
 C7h    power output control bits, Doze state
 C8h    power output control bits, Sleep state
 C9h    power output control bits, Suspend state
 CAh    power control bits polarity control
 CBh    current output bits
 CCh    Doze timeout
 CDh    Sleep timeout
 CEh    Suspend timeout
 CFh    LCD display power timeout
 D0h    EL display power timeout
----------P00260027--------------------------
PORT 0026-0027 - Chips&Technologies CS4021 - "SuperState V" ALTERNATE CONFIG
Desc:    alternate copy of the configuration register access at PORT 0022h/0023h
      which may be used by system software in "SuperState V" to configure
      the chipset without disturbing accesses to PORT 0022h by user code
Notes:    SuperState V is an early version of system management mode
    these ports can only be accessed while the system is in SuperState V;
      similarly, some configuration registers are read-only via PORT 0022h
      and others can optionally be made read-only
SeeAlso: PORT 0022h"Chips&Technologies"
!!!chips\cs4021.pdf p.149

0026  -W  configuration register index
0027  RW  configuration register data
----------P0028002A--------------------------
PORT 0028-002A - 80486 "Deep Green" motherboard - ???

0028  ?W  index for data port
002A  RW  ??? data port

Note:    in order to access to the registers available through PORT 002A,
      an unlocking sequence must be written via PORT 0028:    write
      A0h, 05h, index to PORT 0028, then read/write PORT 002A, then
      write A5h to PORT 0028
----------P002E002F--------------------------
PORT 002E-002F - DELL ENHANCED PARALLEL PORT
SeeAlso: PORT 015Ch,PORT 026Eh,PORT 0398h

002E  -W  index for data port (see #P087)
002F  RW  EPP command data

(Table P087)
Values for Dell Enhanced Parallel Port register index:
 00h    bit 0: ???
 02h    bit 7: port in bidirectional mode
 04h    bits 0 and 2: ECP/EPP mode control
----------P002E002F--------------------------
PORT 002E-002F - Intel "Nonolet" Motherboard - POWER MANAGEMENT

002E  ?W  index for data port
002F  ?W  data port

code sequence posted in fido7.nice.sources by Konstantin Mohorea:
     out 2Eh,0Ch
     out 2Fh,75h
     out 2Eh,11h
     out 2Fh,00h
     out 2Eh,0Dh
     out 2Fh,A0h
----------P002E002F--------------------------
PORT 002E-002F - NS PC87306 SuperI/O - CONFIGURATION REGISTERS
InstallCheck: after a hardware reset, the first read of the index port returns
      88h, and a second consecutive read always returns 00h (while
      read-after-write always returns the written value)
Range:    PORT 002Eh, PORT 015Ch, PORT 026Eh, or PORT 0398h, depending on
      external strapping
Note:    to set a register, the data port must be written twice in a row; the
      value is latched on the second write

002E  RW  configuration register index
002F  RW  configuration register data
----------P0038003F--------------------------
PORT 0038-003F - PC radio by CoZet Info Systems
Notes:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
    All of these addresses show a readout of FF in initial state.
    Once started, all of the addresses show     FB, whatever might happen.
----------P0040005F--------------------------
PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)
Note:    XT & AT use ports 40h-43h; PS/2 uses ports 40h, 42h-44h, and 47h
SeeAlso: PORT 0044h,PORT 0048h

0040  RW  PIT  counter 0, counter divisor          (XT, AT, PS/2)
0041  RW  PIT  counter 1, RAM refresh counter    (XT, AT)
            don't set below 3 on PCs (default 12h)
0042  RW  PIT  counter 2, cassette & speaker    (XT, AT, PS/2)
    During normal operation mode (8253) 40h-42h set the counter values on
    write and get the current counter value on read. In 16bit modes two
    consequtive writes/reads must be issued, first with the low byte,
    followed by the high byte. In 8254 read back modes, all selected
    counters and status are latched and must be read out completely
    before normal operation is valid again.     Each counter switches back
    to normal operation after read out.  In 'get status and counter'
    mode the first byte read is the status, followed by one or two
    counter values. (see #P088)
0043  RW  PIT  mode port, control word register for counters 0-2 (see #P089)
    Once a control word has been written (43h), it must be followed
    immediately by performing the corresponding action to the counter
    registers (40h-42h), else the system may hang!!

Bitfields for 8254 PIT counter status byte:
Bit(s)    Description    (Table P088)
 7    PIN status of OUTx Pins (1=high, 0=low)
 6    counter start value loaded
    =0: yes, so counter latch is valid to be read
    =1: no, wait for counter latch to be set (may last a while)
5-0    counter mode, same as bit5-0 at 43h
SeeAlso: #P089

Bitfields for 8253/8254 PIT mode control word:
Bit(s)    Description    (Table P089)
 7-6    counter select
    00  counter 0 select
    01  counter 1 select      (not PS/2)
    10  counter 2 select
    11  (8253) reserved
        (8254) read back counter (see #P088)
---if counter select---
 5-4    counter access
    00  counter latch command
        BUG:    Intel Neptune/Mercury/Aries Chipset 8237IB (SIO) needs
              a short delay after issuing this command, else the
              MSB may be outdated concerning the LSB, resulting
              in large measuring errors.
            Workaround: Check for this condition by comparing
              results with last results and don't use erroneous
              results.
    01  read/write counter bits 0-7 only
    10  read/write counter bits 8-15 only
    11  read/write counter bits 0-7 first, then 8-15
 3-1    counter mode
    000 mode 0 select - zero detection interrupt
    001 mode 1 select - programmable one shot
    x10 mode 2 select - rate generator
    x11 mode 3 select - square wave generator
        counts down twice by two at a time; latch status and check
          value of OUT pin to determine which half-cycle is active
        divisor factor 3 not allowed!
    100 mode 4 select - software triggered strobe
    101 mode 5 select - hardware triggered strobe
 0    counting style
    0  binary counter 16 bits
    1  BCD counter (4 decades)
---if read back---
 5-4    what to read
    00 counter status, then value
    01 counter value
    10 counter status
    11 reserved
 3    select counter 2
 2    select counter 1
 1    select counter 0
 0    reserved (0)
Note:    after issuing a read back 'get status' command, any new read back
      command is ignored until the status is read from all selected
      counters.
----------P00440047--------------------------
PORT 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2
SeeAlso: PORT 0040h,PORT 0048h

0044  RW  PIT  counter 3 (PS/2)
        used as fail-safe timer. generates an NMI on time out.
        for user generated NMI see at 0462.
0047  -W  PIT  control word register counter 3 (PS/2, EISA)
    bit 7-6 = 00  counter 3 select
        = 01  reserved
        = 10  reserved
        = 11  reserved
    bit 5-4 = 00  counter latch command counter 3
        = 01  read/write counter bits 0-7 only
        = 1x  reserved
    bit 3-0 = 00
----------P0048004B--------------------------
PORT 0048-004B - EISA - PROGRAMMABLE INTERVAL TIMER 2
Note:    this second timer is also supported by many Intel chipsets
SeeAlso: PORT 0040h,PORT 0044h

0048  RW  EISA PIT2 counter 3 (Watchdog Timer)
0049  ??  EISA 8254 timer 2, not used (counter 4)
004A  RW  EISA PIT2 counter 5 (CPU speed control)
004B  -W  EISA PIT2 control word
--------K-P0060006F--------------------------
PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)
Note:    XT uses ports 60h-63h, AT uses ports 60h-64h

0060  RW  KB controller data port or keyboard input buffer (ISA, EISA)
        should only be read from after status port bit0 = 1
        should only be written to if status port bit1 = 0
0060  R-  KeyBoard or KB controller data output buffer (via PPI on XT)
        PC: input from port A of 8255, if bit7 in 61h set (see #P105)
        get scancodes, special codes (in PC: with bit7 in 61h cleared)
          (see #P099)

0061  R-  KB controller port B control register (ISA, EISA)
        system control port for compatibility with 8255 (see #P102)
0061  -W  KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
        system control port for compatibility with 8255 (see #P101)
0061  -W  PPI Programmable Peripheral Interface 8255 (XT only)
        system control port (see #P103)
0062  RW  PPI (XT only) data port C (see #P104)
0063  RW  PPI (XT only) command mode register (see #P106)

0064  R-  keyboard controller read status (see #P107,#P108,#P109)
0064  -W  keyboard controller input buffer (ISA, EISA) (see #P110)

0064  -W  (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
      stored in CMOS RAM that PPI should report for compatibility
0065  -W  (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
      stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
      compatibility

0065  R-  communications port (Olivetti M24)

Bitfields for AT keyboard controller input port:
Bit(s)    Description    (Table P090)
 7    keyboard enabled
 6    =0  CGA, else MDA
 5    =0  manufacturing jumper installed
 4    =0  system RAM 512K, else 640K
 3-0    reserved
SeeAlso: #P091,#P093

Bitfields for AT keyboard controller input port (Compaq):
Bit(s)    Description    (Table P091)
 7    security lock is unlocked
 6    =0  Compaq dual-scan display, 1=non-Compaq display
 5    system board dip switch 5 is OFF
 4    =0  auto speed selected, 1=high speed selected
 3    =0  slow (4MHz), 1 = fast (8MHz)
 2    no math coprocessor installed
 1-0    reserved
SeeAlso: #P092

Bitfields for AT keyboard controller output port:
Bit(s)    Description    (Table P092)
 7    keyboard data output
 6    keyboard clock output
 5    input buffer NOT full
 4    output buffer NOT empty
 3    reserved (see note)
 2    reserved (see note)
 1    gate A20
 0    system reset
Note:    bits 2 and 3 are the turbo speed switch or password lock on
      Award/AMI/Phoenix BIOSes.  These bits make use of nonstandard
      keyboard controller BIOS functionality to manipulate
        pin 23 (8041 port 22) as turbo switch for AWARD
        pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P090,#P093

Bitfields for HP Vectra keyboard controller output port:
Bit(s)    Description    (Table P093)
 7-5    reserved
 4    output buffer full (OBF) interrupt
 3    HP SVC interrupt
 2    HP-HIL controller AutoPoll
 1    A20 gate
 0    system reset
SeeAlso: #P092,#P094

Bitfields for HP Vectra command byte:
Bit(s)    Description    (Table P094)
 7    reserved (0)
 6    scancode conversion mode (1 = PC/XT, 0 = PC/AT)
 5    unused
 4    disable keyboard (unless bit 3 set)
 3    override keyboard disable
 2    System Flag (may be read from PORT 0060h)
 1    reserved
 0    OBF interrupt enable
SeeAlso: #P093

(Table P095)
Values for keyboard commands (data also goes to PORT 0060h):
Value    Count    Description
 EDh    double    set/reset mode indicators Caps Num Scrl
        bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
        all other bits must be zero.
 EEh    sngl    diagnostic echo. returns EEh.
 EFh    sngl    NOP (No OPeration). reserved for future use
 EF+26h    double    [Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
        keyboard must be disabled before this and has to
        be enabled after finished.
 F0h    double    get/set scan code set
        00h get current set
        01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
        02h scancode set 2 (ATs, PS/2, default)
        03h scancode set 3
 F2h    sngl    read keyboard ID (read two ID bytes)
        AT keyboards returns FA (ACK)
        MF2 returns AB 41 (translation) or
                AB 83 (pass through)
 F3h    double    set typematic rate/delay
        format of the second byte:
        bit7=0 : reserved
        bit6-5 : typemativ delay
             00b=250ms     10b= 750ms
             01b=500ms     11b=1000ms
        bit4-0 : typematic rate (see #P100)
 F4h    sngl    enable keyboard
 F5h    sngl    disable keyboard. set default parameters (no keyboard scanning)
 F6h    sngl    set default parameters
 F7h    sngl    [MCA] set all keys to typematic (scancode set 3)
 F8h    sngl    [MCA] set all keys to make/release
 F9h    sngl    [MCA] set all keys to make only
 FAh    sngl    [MCA] set all keys to typematic/make/release
 FBh    sngl    [MCA] set al keys to typematic
 FCh    double    [MCA] set specific key to make/release
 FDh    double    [MCA] set specific key to make only
 FEh    sngl    resend last scancode
 FFh    sngl    perform internal power-on reset function
Note:    each command is acknowledged by FAh (ACK), if not mentioned otherwise.
      See PORT 0060h-R for details.
SeeAlso: #P096

(Table P096)
Values for Mouse functions (for PS/2-like pointing devices):
Value    Count    Description
 E6h    sngl    set mouse scaling to 1:1
 E7h    sngl    set mouse scaling to 2:1
 E8h    double    set mouse resolution
        (00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
 E9h    sngl    get mouse information
        read two status bytes:
          byte 0: flags (see #P097)
          byte 1: resolution
 EAh    sngl    set mouse to stream mode (mouse sends data on any changes)
 EBh    sngl    get mouse data (from mouse to controller) (see #P098)
        on reading, each data packet consists of 8 bytes:
 ECh    sngl    reset mouse wrap mode (to normal mode)
 EEh    sngl    set wrap mode
 F0h    sngl    set remote mode (instead of stream mode), mouse sends data
          only on issueing command EBh.
 F2h    sngl    read mouse ID (read one, two?? ID bytes)
        00h=mouse
 F3h    double    set mouse sample rate in reports per second
        0Ah=10/s       50h= 80/s
        14h=20/s       64h=100/s
        28h=40/s       C8h=200/s
        3Ch=60/s
 F4h    sngl    enable mouse (in stream mode)
 F5h    sngl    disable mouse (in steam mode), set default parameters
 F6h    sngl    reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
          disabled
 FEh    sngl    resend last mouse data (8 bytes, see EBh)
 FFh    sngl    reset mouse
Notes:     must issue command D4h to PORT 0064h first to access mouse functions
     all commands except ECh and FFh are acknowledged by FAh (ACK) or
       FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P095

Bitfields for mouse status byte 0:
Bit(s)    Description    (Table P097)
 7    unused
 6    remote rather than stream mode
 5    mouse enabled
 4    scaling set to 2:1
 3    unused
 2    left button pressed
 1    unused
 0    right button pressed
SeeAlso: #P096,#P098

Format of mouse data packet:
Offset    Size    Description    (Table P098)
 00h    BYTE    status
        bit7    : y-data overrun
        bit6    : x-data overrun
        bit5    : y-data negative
        bit4    : x-data negative
        bit3-2=0: reserved
        bit1    : right button pressed
        bit0    : left button pressed
 01h    BYTE    reserved
 02h    BYTE    x-data
 03h    BYTE    reserved
 04h    BYTE    y-data
 05h    BYTE    reserved
 06h    BYTE    z-data (0)
 07h    BYTE    reserved
SeeAlso: #P096,#P097

(Table P099)
Values for keyboard special codes:
 00h    (MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
 00h    (mouse) ID
 AAh    BAT completion code (sent after errorfree Basic Assurance Test)
 ABh    first byte of general MF2 keyboard ID
 EEh    Echo command return
 FAh    Acknowledge (all general commands except Resend and Echo)
 FAh    (mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
 FCh    (MF2) BAT Failure Code (error in second half of the power on self test)
 FDh    (AT-keyboard) BAT Failure Code (error in the second half of the
      power-on self test)
 FEh    Resend: CPU to controller should resend last keyboard-command
 FEh    (mouse) CPU to controller should resend last mouse-command
 FFh    (MF2 in codeset1) keydetection/overrun error
Note:    keyboard stops scanning and waits for next command after returning
      code FCh or FDh
SeeAlso: PORT 0060h-R

(Table P100)
Values for keyboard typematic rate:
 00000b=30.0   10000b=7.5
 00001b=26.7   10001b=6.7
 00010b=24.0   10010b=6.0
 00011b=21.8   10011b=5.5
 00100b=20.0   10100b=5.0
 00101b=18.5   10101b=4.6
 00110b=17.1   10110b=4.3
 00111b=16.0   10111b=4.0
 01000b=15.0   11000b=3.7
 01001b=13.3   11001b=3.3
 01010b=12.0   11010b=3.0
 01011b=10.9   11011b=2.7
 01100b=10.0   11100b=2.5
 01101b= 9.2   11101b=2.3
 01110b= 8.5   11110b=2.1
 01111b= 8.0   11111b=2.0
SeeAlso: #P095

Bitfields for KB controller port B (system control port) [output]:
Bit(s)    Description    (Table P101)
 7    pulse to 1 for IRQ1 reset (PC,XT)
 6-4    reserved
 3    I/O channel parity check disable
 2    RAM parity check disable
 1    speaker data enable
 0    timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P102

Bitfields for KB ctrller port B control register (system control port) [input]:
Bit(s)    Description    (Table P102)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    mirrors timer 2 output condition
 4    toggles with each refresh request
 3    NMI I/O channel check status
 2    NMI parity check status
 1    speaker data status
 0    timer 2 clock gate to speaker status
SeeAlso: PORT 0061h-R,#P101

Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s)    Description    (Table P103)
 7    clear keyboard (only pulse, normally kept at 0)
 6    =0  hold keyboard clock low
 5    NMI I/O parity check disable
 4    NMI RAM parity check disable
 3    =0 read low nybble of switches S2
    =1 read high nybble of switches S2
 2    reserved, often used as turbo switch
    original PC: cassette motor off
 1    speaker data enable
 0    timer 2 gate to speaker enable
Note:    bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P0051,#P104,#P105,#P106

Bitfields for PPI (XT only) data port C:
Bit(s)    Description    (Table P104)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    timer 2 channel out
 4    reserved
    original PC: cassette data input
---
 3    system board RAM size type 1
 2    system board RAM size type 2
 1    coprocessor installed
 0    loop in POST
---
 3-0    DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P103,#P105,#P106

Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s)    Description    (Table P105)
 7-6    number of disk drives
    00  1 diskette drive
    01  2 diskette drives
    10  3 diskette drives
    11  4 diskette drives
 5-4    initial video
    00  reserved (video adapter has on-board BIOS)
    01  40*25 color (mono mode)
    10  80*25 color (mono mode)
    11  MDA 80*25
 3-2    memory size (using 256K chips)
    00  256K
    01  512K
    10  576K
    11  640K
 3-2    memory size (using 64K chips)
    00  64K
    01  128K
    10  192K
    11  256K
 3-2    memory size (original PC)
    00  16K
    01  32K
    10  48K
    11  64K
 1-0    reserved
 1    NPU (math coprocessor) present
 0    boot from floppy
SeeAlso: #P104,#P106,PORT 0060h-R

Bitfields for PPI (8255) command mode register:
Bit(s)    Description    (Table P106)
 7    activation function (0 = bit set/reset, 1 = mode set function)
 6,5    port A mode: 00 = mode0, 01 = mode1, 1x = mode2
 4    port A direction: 0 = output, 1 = input
 3    port C bits 7-4 direction: 0 = output, 1 = input
 2    port B mode: 0 = mode0, 1 = mode1
 1    port B direction: 0 = output, 1 = input
 0    port C bits 3-0 direction: 0 = output, 1 = input
Note:    Attention: Never write anything other than 99h to this port
      (better: never write anything to this port, only during BIOS
      init), as other values may connect multiple output drivers
      and will cause hardware damage in PC/XTs!  By setting command
      word to 99h, PPI will be set in input/output modes as it is
      necessary to support the commonly known IO-ports 60, 61, 62
      as desired.
SeeAlso: #P103,#P104,#P105

Bitfields for keyboard controller read status (ISA, EISA):
Bit(s)    Description    (Table P107)
 7    parity error on transmission from keyboard
 6    receive timeout
 5    transmit timeout
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (input 60/64 has data for 8042)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: PORT 0064h-R,#P108,#P109,#P110

Bitfields for keyboard controller read status (MCA):
Bit(s)    Description    (Table P108)
 7    parity error on transmission from keyboard
 6    general timeout
 5    mouse output buffer full
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: #P107,#P109,#P110

Bitfields for keyboard controller read status (Compaq):
Bit(s)    Description    (Table P109)
 7    parity error detected (11-bit format only). If an
      error is detected, a Resend command is sent to the
      keyboard once only, as an attempt to recover.
 6    receive timeout. transmission didn't finish in 2mS.
 5    transmission timeout error
    bit 5,6,7  cause
        1 0 0  No clock
        1 1 0  Clock OK, no response
        1 0 1  Clock OK, parity error
 4    =0 security lock engaged
 3    =1 data in OUTPUT register is command
    =0 data in OUTPUT register is data
 2    system flag status: 0=power up or reset     1=soft reset
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (PORT 0060h has data for system)
    bit is cleared after read access
SeeAlso: #P107,#P108,#P110

(Table P110)
Values for keyboard controller commands (data goes to PORT 0060h):
Value        Description
 20h    read    read byte zero of internal RAM, this is the last KB command
          sent to the 8041/8042
    Compaq    put current command byte on PORT 0060h (see #P111,#P112)
 21-3F    read    reads the byte specified in the lower 5 bits of the command
          in the 804x's internal RAM (see #P115)
 60-7F    double    writes the data byte to the address specified in the 5 lower
          bits of the command
 60h    Compaq    Load new command (60 to [64], command to [60]) (see #P112)
        (also general AT-class machines)
 A0h    AMI    get ASCIZ copyright message on PORT 0060h
 A1h    AMI    get controller version byte on PORT 0060h
 A1h    Compaq    unknown speedfunction ??
 A1h    C&T    CHIPS extensions (see #P466)
 A2h    Compaq    unknown speedfunction ??
 A2h    AMI    set keyboard controller pins 22 and 23 low
 A2h    C&T    turn on turbo LED
 A3h    Compaq    Enable system speed control
 A3h    AMI    set keyboard controller pins 22 and 23 high
 A3h    C&T    turn off turbo LED
 A4h    MCA    check if password installed
        returns PORT 0060h code F1h if no password, FAh if installed
 A4h    Compaq    Toggle speed
 A4h    AMI    set internal system speed flag to low
 A5h    MCA    load password
        write successive scan codes to PORT 0060h, terminate with 00h
 A5h    AMI    set internal system speed flag to high
 A5h    Compaq    Special read. the 8042 places the real values of port 2
          except for bits 4 and 5 wich are given a new definition in
          the output buffer. No output buffer full is generated.
            if bit 5 = 0, a 9-bit keyboard is in use
            if bit 5 = 1, an 11-bit keyboard is in use
            if bit 4 = 0, output-buff-full interrupt disabled
            if bit 4 = 1, output-buffer-full interrupt enabled
 A6h    MCA    check password
 A6h    AMI    get internal system speed flag on PORT 0060h
 A6h    Compaq    unknown speedfunction ??
 A7h    MCA    disable mouse port
 A7h    AMI    set internal flag indicating bad write cache
 A8h    MCA    enable mouse port
 A8h    AMI    set internal flag indicating good write cache
 A9h    MCA    test mouse port, return test result on PORT 0060h (see #P114)
 A9h    AMI    get internal flag indicating cache OK to PORT 0060h
 AAh    sngl    initiate self-test. will return 55h to data port if self-test
          successful, FCh if failed
 AAh    Compaq    initializes ports 1 and 2, disables the keyboard and clears
          the buffer pointers. It then places 55h in the output buffer.
 ABh    sngl    initiate interface test, return result value on PORT 0060h
          (see #P114)
 ACh    read    diagnostic dump. the contents of the 804x RAM, output port,
          input port, status word are sent to PORT 0060h in scan-code
          format; Chips&Technologies 8042's append "CHIPS Vxxx" where
          "xxx" is the controller version number
 ADh    sngl    disable keyboard (sets bit 4 of commmand byte)
 ADh    Vectra    HP Vectra diagnostic dump
 AEh    sngl    enable keyboard     (resets bit 4 of commmand byte)
 AFh    AWARD    Enhanced Command: read keyboard version
 AFh    AMI    set extended controller RAM
        write address to PORT 0060h, wait for controller ready, then
          write value to PORT 0060h
 B1h    AMI    set keyboard controller P11 line low
 B2h    AMI    set keyboard controller P12 line low
 B3h    AMI    set keyboard controller P13 line low
 B4h    AMI    set keyboard controller P22 line low
 B5h    AMI    set keyboard controller P23 line low
 B8h    AMI    set keyboard controller P10 line high
 B9h    AMI    set keyboard controller P11 line high
 BAh    AMI    set keyboard controller P12 line high
 BBh    AMI    set keyboard controller P13 line high
 BCh    AMI    set keyboard controller P22 line high
 BDh    AMI    set keyboard controller P23 line high
 C0h    read    read input port and place on PORT 0060h
        bit 7    keyboard NOT locked
        bit 6    =0 first video is CGA
            =1 first video is MDA
        bit 5    =0 factory testmode
            =1 normal
        bit 4    =0 256KB RAM, 1=512KB
        bit 5,3-0 are used in Intel chipset 386sx machines with
            AMI/Phoenix BIOSes for BIOS specific hardware settings
        bit 2    (MCA) no keyboard power
        bit 1    (MCA) current mouse serial data input state
        bit 0    (MCA) current keyboard serial input state
 C0h    Compaq    places status of input port in output buffer.  Use this
          command only when the output buffer is empty
 C1h    MCA    Enhanced Command: poll input port Low nibble, continuously
          place in PORT 0064h bits 7-4 until next command
 C2h    MCA    Enhanced Command: poll input port High nibble, continuously
          place in PORT 0064h bits 7-4 until next command
 C8h    AMI    unblock keyboard controller lines P22 and P23
 C9h    AMI    block keyboard controller lines P22 and P23
 CAh    AMI    read keyboard mode, return in 0060 bit 0
          (bit clear if ISA mode, set if PS/2 mode)
 CBh    AMI    set keyboard mode (write back mode byte returned by CAh,
          modifying only bit 0)
 CCh    AMI    ??? (used by AMI BIOS v1.00.12.AX1T APM code)
 D0h    read    read output port and place on PORT 0060h (see #P113)
 D0h    Compaq    places byte in output port in output buffer. Use this command
          only when the output buffer is empty
 D1h    double    write output port.  The next byte written to PORT 0060h will
          be written to the 804x output port; the original IBM AT and
          many compatibles use bit 1 of the output port to control
          the A20 gate.
        Important: bit 0 (system reset) should always be set here, as
              the system may hang constantly, use pulse output port
              (FEh) instead.
 D1h    Compaq    the system speed bits are not set by this command use
          commands A1-A6 (!) for speed functions.
 D2h    MCA    Enhanced Command: write keyboard output buffer
 D3h    MCA    Enhanced Command: write pointing device out.buf.
 D4h    MCA    write to mouse/pointing device instead of to keyboard; this
          controller command must precede every PORT 0060h command
          directed to the mouse, otherwise it will be sent to the
          keyboard
 D4h    AWARD    Enhanced Command: write to auxiliary device
 DDh    sngl    disable address line A20 (HP Vectra only???)
        default in Real Mode
 DFh    sngl    enable address line A20 (HP Vectra only???)
 E0h    read    read test inputs, and place in PORT 0060h
        bit0 = kbd clock, bit1 = kbd data
 Exxx    AWARD    Enhanced Command: active output port
 EDh    double    this is a two part command to control the state of the
          NumLock, CpasLock and ScrollLock LEDs
        The second byte contains the state to set LEDs.
            bit 7-3    reserved. should be set to 0.
            bit 2 = 0    Caps Lock LED off
            bit 1 = 0    Num Lock LED off
            bit 0 = 0    Scroll Lock LED off
 F0-FF    sngl    pulse output port low for 6 microseconds.
        bits 0-3 contain the mask for the bits to be pulsed.  A bit is
          pulsed if its mask bit is zero
        bit0=system reset. Don't set to zero. Pulse only!
Note:     keyboard controllers are widely different from each other.  You
       cannot generally exchange them between different machines.
     (Award) Derived from Award's Enhanced KB controller advertising sheet.
     (Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.

(Table P466)
Values for Chips&Technologies extension commands:
 00h    return ID - returns A6h for a C&T controller, part # N93N8042/A
 02h    write input port
    next data byte to PORT 0060h is written to the controller's input port
    Warning: the system must be designed to support output devices
          connected to the input port to avoid potential damage
 04h    select turbo switch input
    next byte selects input:
        bit 7: switch polarity
        (=0 input low = high speed, =1 input low = low speed)
        bits 6-0: one bit set selects corresponding bit in Port1 as turbo
 05h    select turbo LED output
    next byte selects output:
        bit 7: LED polarity    (=0 output low=LED on, =1 output low=LED off)
        bit 6: LED port (=0 Port1, =1 Port2)
        bits 5-0: one bit set selects corresponding bit in Port1/Port2 as
        LED output
Note:    these commands and any arguments are sent to PORT 0060h after writing
      command A1h to PORT 0064h
SeeAlso: #P110

Bitfields for Compaq keyboard command byte:
Bit(s)    Description    (Table P111)
 7    reserved
 6    =1 convert KB codes to 8086 scan codes
 5    =0 use 11-bit codes, 1=use 8086 codes
 4    =0 enable keyboard, 1=disable keyboard
 3    ignore security lock state
 2    this bit goes into bit2 status reg.
 1    reserved (0)
 0    generate interrupt (IRQ1) when output buffer full
SeeAlso: #P112

Bitfields for keyboard command byte (alternate description):
Bit(s)    Description    (Table P112)
 7    reserved (0)
 6    IBM PC compatibility mode
 5    IBM PC mode
    no parity, no stop bits, no translation
    (PS/2) force mouse clock low
 4    disable keyboard (clock)
 3    (AT) inhibit override -- ignore keyboard lock switch
    (PS/2) reserved
 2    system flag
 1    (AT) reserved (0)
    (PS/2) enable mouse output buffer full interrupt (IRQ12)
 0    enable output buffer full interrupt (IRQ1)
SeeAlso: #P111,#P113

Bitfields for keyboard controller output port:
Bit(s)    Description    (Table P113)
 7    keyboard data (output)
 6    keyboard clock (output)
 5    (AT) =0 input buffer empty
    (MCA) outptu buffer full with mouse byte (connected to IRQ12)
 4    output buffer full with keyboard byte (connected to IRQ1)
 3    (MCA) mouse data (output)
 2    (MCA) mouse clock (output)
    used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
      configuration of turbo switch
 1    gate address A20
 0    system reset
Note:    bit 0 (system reset) should always be set when writing the output
      port, as the system may hang constantly; use pulse output port
      (command FEh) instead.
SeeAlso: #P112

(Table P114)
Values for keyboard/mouse test result on PORT 0060h:
 00h    no error
 01h    keyboard clock line stuck low
 02h    keyboard clock line stuck high
 03h    keyboard data line is stuck low
 04h    keyboard data line stuck high
 05h    (Compaq only) diagnostic feature
SeeAlso: #P110

(Table P115)
Values for keyboard controller RAM location:
 00h    command byte (see #P111,#P112)
---MCA systems---
 13h    security on
    nonzero if password enabled
 14h    security off
    nonzero if password matched
 16h    password discard scancode 1
 17h    password discard scancode 2
Note:    make codes matching either discard scancode are ignored during password
      entry
----------P0065------------------------------
PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT
----------P0065------------------------------
PORT 0065 - ???

0065  RW  ???
        bit 2: A20 gate control (set = A20 enabled, clear = disabled)
----------P00660067--------------------------
PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES
----------P0066------------------------------
PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"
----------P0068------------------------------
PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL

Note:      on Micronics 386-25/386-33/486-25 motherboards, setting this port to
        00h enables full speed; setting it to C0h slows the system down by
        a factor corresponding to the value programmed into the EISA
        interval timer 2 at ports 004Ah and 004Bh
--------K-P0068006F--------------------------
PORT 0068-006F - HP Vectra Human Interface Link
SeeAlso: PORT 0060h"KEYBOARD"

0068  -W  (HP-Vectra) control buffer (HP commands) (see #P116)
0069  R-  (HP-Vectra) SVC (keyboard request SerViCe port)
006A  -W  (HP-Vectra) Acknowledge (clear processing, done)
006C-006F    HP-HIL    (Human Interface Link = async. serial inputs 0-7)

(Table P116)
Values for HP Vectra control buffer command code:
 00h-54h insert standard key make code into 8041 scancode buf
 55h-77h insert HP key make code into 8041 scancode buffer
 7Ah    pass through next data byte
 7Bh    set RAM Switch to 0
 7Ch    set RAM Switch to 1 (default)
 7Dh    set CRT Switch to 0
 7Eh    set CRT Switch to 1 (default)
 7Fh    reserved
 80h-D4h insert standard key break code into scancode buffer
 D5h-F7h insert HP key break code into scancode buffer
 F8h    enable AutoPoll
 F9h    disable AutoPoll
 FAh-FEh reserved
 FFh    keyboard overrun
----------P0069------------------------------
PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"
----------P006B006F--------------------------
PORT 006B-006F - SSGA CONTROL REGISTERS

006B  ??  RAM enable/remap
006C  ??  undocumented
006D  ??  undocumented
006E  ??  undocumented
006F  ??  undocumented
----------P0070007F--------------------------
PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)
Note:    the real-time clock may be either a discrete MC146814, MC146818, or
      an emulation thereof built into the motherboard chipset
SeeAlso: PORT 00A0h"XT"

0070  -W  CMOS RAM index register port (ISA, EISA)
         bit 7    = 1  NMI disabled from reaching CPU
            = 0  NMI enabled
         bit 6-0     CMOS RAM index
            (64 bytes in early systems, now usually 128 bytes)
    Note:    any write to PORT 0070h should be followed by an action to
          PORT 0071h or the RTC wil be left in an unknown state.
0071  RW  CMOS RAM data port (ISA, EISA) (see #P117)

(Table P117)
Values for Real-Time Clock register number (see also CMOS.LST):
 00h-0Dh clock registers
 0Eh    diagnostics status byte
 0Fh    shutdown status byte
 10h    diskette drive type for A: and B:
 11h    reserved / IBM fixed disk / setup options
 12h    fixed disk drive type for drive 0 and drive 1
 13h    reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
 14h    equipment byte
 15h    LSB of system base memory in Kb
 16h    MSB of system base memory in Kb
 17h    LSB of total extended memory in Kb
 18h    MSB of total extended memory in Kb
 19h    drive C extension byte
 1Ah    drive D extension byte
 1Bh-2Dh reserved
 20h-27h commonly used for first user-configurable drive type
 2Eh    CMOS MSB checksum over 10-2D
 2Fh    CMOS LSB checksum over 10-2D
 30h    LSB of extended memory found above 1Mb at POST
 31h    MSB of extended memory found above 1Mb at POST
 32h    date century in BCD
 33h    information flags
 34h-3Fh    reserved
 35h-3Ch commonly used for second user-configurable drive type
 3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
 42h-4Ch AMI 1990 Hyundai super-NB368S notebook
    ???
 54h-57h AMI 1990 Hyundai super-NB368S notebook
    ???
 5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
    ???
 60h-61h AMI 1990 Hyundai super-NB368S notebook
    ???
----------P0072------------------------------
PORT 0072 - Chips&Technologies 82C100 - NMI CONTROL

!!!chips\82c100.pdf p.41
----------P00720075--------------------------
PORT 0072-0075 - AMD-645 Peripheral Bus Controller - EXTENDED CMOS ACCESS
SeeAlso: PORT 0070h

0072  RW  CMOS memory address, region 2 (256 bytes)
0073  RW  CMOS memory data, region 2
0074  RW  CMOS memory address, region 3 (256 bytes)
0075  RW  CMOS memory data, region 3
Note:    on the AMD-645, ports 0072h and 0073h allow access to a full 256 bytes
      of RAM, including the standard 128 bytes available through ports
      0070h and 0071h
----------P0073------------------------------
PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0075h

0073  RW  ???
    bit 7: ???
    bit 6: disable ROM shadowing
    bit 5: ??? (related to IDE controller)
    bit 4: ???
    bit 3: ???
----------P00740076--------------------------
PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS
Note:    NVRAM may be 2K, 8K, or 16K
SeeAlso: PORT 0070h-007Fh,CMOS.LST

0074  -W  secondary CMOS RAM (IBM NVRAM) index, low byte
0075  -W  secondary CMOS RAM (IBM NVRAM) index, high (in bits 2-0)
0076  RW  secondary CMOS RAM (IBM NVRAM) data byte
----------P0075------------------------------
PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0073h,PORT 0078h"82378IB"

0075  R-  ???
      bits 3-2: external bus speed
           00  50 MHz
           01  66 MHz
           10  60 MHz
           11  40 MHz
----------P0078------------------------------
PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE

0078  ?W  NMI enable/disable
        bit 7 = 0  disable & clear hard reset from HP-HIL controller
              = 1  enable hard reset from HP-HIL controller chip
        bit 6-0       reserved
----------P0078------------------------------
PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER
Notes:    the BIOS uses this port for certain fine timings; presumably it is
      independent of processor speed (it appears to decrement at 1 MHz)
    the address at which this port appears may be set via the 82378's
      PCI configuration space word at offset 0080h (see #0860), or the
      timer may be disabled entirely
SeeAlso: PORT 0075h

0078w -W  set count-down timer
0078w R-  get current count (timer stops when it reaches 0000h)
----------P0078007F--------------------------
PORT 0078-007F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Note:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show FBh, whatever might happen.
----------P007C007D--------------------------
PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)
Notes:    cascaded to first controller.
    used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h,INT 68"Vectra",INT 6E"Vectra"

007C  RW  HP-Vectra  PIC 3  see at 0020     PIC 1
007D  RW  HP-Vectra  PIC 3  see at 0021     PIC 1
----------P0072------------------------------
PORT 007E - Chips&Technologies 82C100/110 - NMI STATUS
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"
!!!chips\82c100.pdf p.42
!!!chips\82c110.pdf p.39
----------P0072------------------------------
PORT 007F - Chips&Technologies 82C100/110 - POWER CONTROL AND RESET
SeeAlso: PORT 0072h"82C100",PORT 007Eh"82C100"
----------P0080------------------------------
PORT 0080 - MANUFACTURING DIAGNOSTICS PORT
Note:    sometimes used for a POST hex display

0080  -W  Manufacturing Diagnostics port
0080  R-  ???

(Table P118)
Values for AMI BIOS diagnostics codes:
 00h    system boot completed, control passed to INT 19 bootstrap loader
 01h    register test
 02h    video initialization; NMIs disabled
 03h    power-on delay complete
 04h    pre-keyboard-test initializations complete
 05h    soft-reset/power-on setting determined
 06h    ROM enabled
 07h    ROM BIOS checksum test passed
 08h    keyboard BAT command issued
 09h    keyboard controller BAT result verified
 0Ah    keyboard controller command code issued
 0Bh    keyboard controller command byte written
 0Ch    keyboard controller pins 23/24 blocked and unblocked
 0Dh    keyboard controller NOP processing in progress
 0Eh    CMOS RAM shutdown register read/write test passed
 0Fh    CMOS RAM checksum calculation complete
 10h    CMOS RAM initialization complete
 11h    CMOS RAM status register initialized
 12h    DMA controllers 1/2 and interrupt controllers 1/2 disabled
 13h    video display disabled, port B initialized
 14h    chipset initialization, auto memory detection
 15h    8254 channel 2 test half complete
 16h    8254 channel 2 test completed
 17h    8254 channel 1 test completed
 18h    8254 channel 0 test completed
 19h    memory refresh started
 1Ah    memory refresh line is toggling
 1Bh    memory refresh test completed
 20h    base 64K memory test started
 21h    address line test passed
 22h    parity toggle complete
 23h    base 64K sequential read/write test passed
 24h    pre-interrupt-vector-initialization configuration complete
 25h    interrupt vectors initialized
 26h    8042 input port read
 27h    global data initialization complete
 28h    post-interrupt-vector-initialization initialization complete
 29h    monochrome mode set
 2Ah    color mode set
 2Bh    parity toggle on option video ROM test complete
 2Ch    initialization before video ROM control complete
 2Dh    video ROM check complete
 2Eh    !!!
 A9h    returned from E0000h adapter ROM
 AAh    final initializations after adapter ROM initializations complete
SeeAlso: #P119,#P120,#P465

(Table P119)
Values for AWARD (non-PnP) diagnostic code:
 01h    Processor Test 1
 02h    Processor Test 2
 03h    initialize chips
 04h    test memory refresh toggle
 05h    blank video, initialize keyboard
 06h    reserved
 07h    test CMOS and CMOS batter status
 08h    setup low memory
 09h    early cache initialization
 0Ah    interrupt vector initialization
 0Bh    test CMOS RAM checksum
 0Ch    initialize keyboard
 0Dh    initialize video interface
 0Eh    test video memory
 0Fh    test DMA channel 0
 10h    test DMA channel 1
 11h    test DMA page registers
 12h    reserved
 13h    reserved
 14h    test timer channel 2
 15h    test master PIC mask bits
 16h    test slave PIC mask bits
 17h    test 8259 stuck interrupt bits
 18h    test 8259 interrupt functionality
 19h    test for stuck NMI
 1Ah    display CPU clock
 1Bh-1Eh reserved
 1Fh    set EISA mode
 20h    enable Slot 0 (system board)
 21h-2Fh enable Slots 1-15
 30h    get base and extended memory size
 31h    test base and extended memory
 32h    test EISA memory
 33h-3Bh reserved
 3Ch    set allow-setup flag
 3Dh    initialize / install mouse
 3Eh    initialize cache controller
 3Fh    reserved
 41h    initialize floppy controller and drives
 42h    initialize hard disk controller and drives
 43h    detect / initialize serial and parallel ports
 44h    reserved
 45h    initialize math coprocessor
 46h-4Dh reserved
 4Eh    Manufacturing Post loop / or / display any error messages
 4Fh    ask for password, if enabled
 50h    update CMOS RAM
 51h    pre-boot enable of parity, NMI, cache
 52h    initialize option ROMs
 53h    initialize BIOS time from RTC
 60h    setup boot-sector protection
 61h    set boot CPU speed
 62h    setup NumLock
 63h    attempt to boot via INT 19h
 B0h    spurious interrupt while in protected mode
 B1h    unclaimed NMI
 BEh    chipset default initialization
 BFh    chipset initialization
 C0h    turn off chipset cache
 C1h    check on-board memory size
 C5h    early shadow-RAM enable for faster boot
 C6h    detect external cache size
 E1h-EFh setup utility pages 1-15
 FFh    system booting operating system
SeeAlso: #P118,#P120,#P465

(Table P120)
Values for AWARD (Plug-and-Play) POST code:
 01h-02h reserved
 03h    initialize EISA register (if applicable)
 04h    reserved
 05h    keyboard controller test, initialize keyboard
 06h    reserved
 07h    test CMOS and CMOS batter status
 09h    program Cyrix CPU configuration; OEM-specific cache initialization
 0Ah    initialize interrupt vectors; early power management initialization
 0Bh    check CMOS RAM; assign I/O and memory to PCI devices
 0Ch    initialize BIOS data area
 0Dh    early chipset setup; measure CPU speed; video initialization
 0Eh    display Award logo, OEM-specific sign-on messages
 0Fh    test DMA channel 0
 10h    test DMA channel 1
 11h    test DMA page registers
 12h-13h reserved
 14h    test timer channel 2
 15h    test master PIC mask bits
 16h    test slave PIC mask bits
 17h    reserved
 19h    test 8259 functionality
 1Ah-1Dh reserved
 1Eh    EISA initialization (if applicable and EISA NVRAM checksum is good)
 1Fh-29h reserved
 30h    get base and extended memory size
 31h    test base and extended memory
 32h    program on-board serial/parallel ports, floppy controller
 33h-3Bh reserved
 3Ch    set allow-setup flag
 3Dh    initialize keyboard, install PS/2 mouse if attached
 3Eh    try to turn on L2 cache
 3Fh-40h reserved
 41h    initialize floppy controller, drives
 42h    initialize hard disk controller, drives
 43h    initialize serial/parallel ports (if PnP)
 44h    reserved
 45h    initialize math coprocessor
 46h-4Dh reserved
 4Eh    display any error messages
 4Fh    ask for password, if required
 50h    update CMOS RAM
 51h    reserved
 52h    initialize expansion ROMs, PCI, PnP, shadow RAM, power management
 53h    if not PnP, initialize serial/parallel ports; set BIOS time
 54h-5Fh reserved
 60h    set boot-sector protection
 61h    turn on L2 cache; set boot speed; final chipset/PM initialization
 62h    setup daylight savings time; set NumLock, typematic
 63h    update ESCD (PnP only) if changes; boot system via INT 19h
 B0h    spurious interrupt while in protected mode
 B1h    unclaimed NMI
 BEh    chipset default initialization
 BFh    chipset initialization
 C0h    turn off chipset cache, init DMA/PIC/timer/RTC with default values
 C1h    check on-board DRAM and cache size
 C3h    test first 256K DRAM, expand compressed BIOS image into DRAM
 C5h    early shadow-RAM enable for faster boot
 FFh    system is booting operating system
SeeAlso: #P118,#P119,#P465

(Table P465)
Values for Chips&Technologies 82C100/82C235 POST code:
 01h    flags register failed
 02h    a CPU register failed
 03h    incorrect ROM checksum
 04h    DMA controller failed
 05h    system timer failed
 06h    first 64K of RAM failed address test
 07h    first 64K of RAM failed RAM test
 08h    interrupt controller failed
 09h    "Hot Interrupt" occurred
 0Ah    reserved
 0Bh    CPU still in protected mode
 0Ch    DMA page register failed
 0Dh    no RAM refresh
 0Eh    no response from keyboard controller
 0Fh    unable to enter protected mode
 10h    GDT or IDT register failed
 11h    LDT register failed
 12h    task register failed
 13h    LSL instruction failed
 14h    LAR instruction failed
 15h    VERR or VERW instruction failed
 16h    keyboard controller A20 gate failed
 17h    exception failed, or shutduwon on unexpected exception
 18h    shutdown during memory test
 19h    checksum error in copyright string
 1Ah    BMS checksum error
---POST progress codes---
 50h    initialize hardware
 51h    initialize timer
 52h    initialize DMA controller
 53h    initialize 8259
 54h    initialize chipset
 55h    reserved
 56h    first entry into protected mode
 57h    memory-chip sizing
 58h    reserved
 59h    first exit from protected mode
 5Ah    system-board memory size determination
 5Bh    shadow RAM relocation
 5Ch    configure possible EMS
 5Dh    reserved
 5Eh    re-test lowest 64K of RAM
 5Fh    test shadow RAM
 60h    test CMOS RAM
 61h    test video
 63h    test protected mode interrupts
 64h    test A20
 65h    memory address line tests
 66h    test base memory
 67h    test extended memory
 68h    test timer interrupt
 69h    test real-time clock
 6Ah    test keyboard controller
 6Bh    test 80287
 6Ch    test RS232
 6Dh    test parallel port
 6Eh    reserved
 6Fh    test floppy disk controller
 70h    test fixed disk controller
 71h    test keylock
 72h    test mouse / pointing device
 73h-8Fh reserved
 90h    setup RAM
 91h    determine CPU speed
 92h    configuration check
 93h    initialize BIOS
 94h    POD bootstrap
 95h    reset ICs
 96h    setup cache controller
SeeAlso: #P118,#P119,#P120
----------P0080008F--------------------------
PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
008A  RW  DMA channel 7 address byte 2
008B  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register
----------P0080009F--------------------------
PORT 0080-009F - Intel386sx CHIPSET 82231
Note:    includes the DMA controller functionality on PORT 0080h to PORT 008Fh
----------P0084------------------------------
PORT 0084 - Compaq POST Diagnostic
--------X-P0084------------------------------
PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE
----------P00850086--------------------------
PORT 0085-0086 - Intel "Triton" chipset - ???
SeeAlso: PORT 00EBh"Triton"

0085  ?W  ???
0086  ?W  ???
----------P0090009F--------------------------
PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)

0090  ??  Central arbitration control port
0090  RW  POST diagnostic code (most PS/2 with ISA bus)
0091  R-  Card selection feedback
        bit 0 set when adapter addressed and responds, cleared on read
0092  RW  PS/2 system control port A  (port B is at PORT 0061h) (see #P121)
0094  -W  system board enable/setup register (see #P122)
0095  --  reserved
0096  -W  adapter enable / setup register (see #P123)
0097  --  reserved

Bitfields for PS/2 system control port A:
Bit(s)    Description    (Table P121)
 7-6    any bit set to 1 turns activity light on
 5    unused
 4    watchdog timout occurred
 3    =0 RTC/CMOS security lock (on password area) unlocked
    =1 CMOS locked (done by POST)
 2    unused
 1    A20 is active
 0    =0 system reset or write
    =1 pulse alternate reset pin (high-speed alternate CPU reset)
Notes:    once set, bit 3 may only be cleared by a power-on reset
    on at least the C&T 82C235, bit 0 remains set through a CPU reset to
      allow the BIOS to determine the reset method
SeeAlso: #P122,#P123,MSR 00001000h

Bitfields for PS/2 system board enable/setup register:
Bit(s)    Description    (Table P122)
 7    =1  enable functions
    =0  setup functions
 5    =1  enables VGA
    =0  setup VGA
 2    =1  enable integrated SCSI (PS/2 M77)
    =0  setup integrated SCSI
SeeAlso: #P121,#P123

Bitfields for PS/2 adapter enable/setup register:
Bit(s)    Description    (Table P123)
 7    activate Channel Reset on all slots
 6-4    unused (1)
 3    =1  setup adapter specified by bits 2-0
    =0  enable registers
 2-0    adapter slot select (000 = slot 1 ... 111 = slot 8)
SeeAlso: #P122
----------P00A000AF--------------------------
PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"

00A0  RW  PIC 2     same as 0020 for PIC 1
00A1  RW  PIC 2     same as 0021 for PIC 1 except for OCW1 (see #P124)

Bitfields for PIC2 output control word OCW1:
Bit(s)    Description    (Table P124)
 7    disable IRQ15 (reserved)
 6    disable IRQ14 (fixed disk interrupt)
 5    disable IRQ13 (coprocessor exception interrupt)
 4    disable IRQ12 (mouse interrupt)
 3    disable IRQ11 (reserved)
 2    disable IRQ10 (reserved)
 1    disable IRQ9  (redirect cascade)
 0    disable IRQ8  (real-time clock interrupt)
SeeAlso: #P014
----------P00A0------------------------------
PORT 00A0 - XT - NMI MASK REGISTER
SeeAlso: PORT 0070h,INT 02

00A0  RW  NMI mask register (XT only)
     bit 7 = 0 NMI signal disabled from reaching CPU
           = 1 NMI signal enabled
----------P00A000AF--------------------------
PORT 00A0-00AF - Chips&Technologies 82C100/110 - NMI CONTROL
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"

00A0  RW  NMI mask register (XT only)
     bit 7 = 0 NMI signal disabled from reaching CPU
           = 1 NMI signal enabled
00Ax  RW  mirrors of PORT 00A0h
----------P00A800A9--------------------------
PORT 00A8-00A9 - Via VT82C496G - CONFIGURATION REGISTERS

00A8  ?W  configuration register index
00A9  RW  configuration register data
----------P00A800A9--------------------------
PORT 00A8-00A9 - Via VT82C570M - CONFIGURATION REGISTERS

00A8  ?W  configuration register index
00A9  RW  configuration register data
----------P00A800A9--------------------------
PORT 00A8-00A9 - Via VT82C586A - GPIO

00A8  ?W  configuration register index
00A9  RW  configuration register data
----------P00B000BF--------------------------
PORT 00B0-00BF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P00B2------------------------------
PORT 00B2 - Intel chipsets - Advanced Power Management Control
Notes:    used to pass data between the operating system and the System
      Management Interrupt (SMI) handler
    writes to this port can cause an SMI; reads can cause STPCLK# to be
      asserted (putting the CPU in sleep mode)
    supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B3h,#0875

00B2  RW  control
----------P00B3------------------------------
PORT 00B3 - Intel chipsets - Advanced Power Management Status
Notes:    used to pass data between the operating system and the System
      Management Interrupt (SMI) handler
    supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B2h

00B3  RW  status
----------P00C0------------------------------
PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)
----------P00C000DF--------------------------
PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R-  DMA channel 4-7 status register (ISA, EISA) (see #P125)
00D0  -W  DMA channel 4-7 command register (ISA, EISA) (see #P126)
00D2  -W  DMA channel 4-7 write request register (ISA, EISA)
00D4  -W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P128)
00D6  -W  DMA channel 4-7 mode register (ISA, EISA) (see #P129)
00D8  -W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R-  DMA channel 4-7 read temporary register (ISA, EISA)
00DA  -W  DMA channel 4-7 master clear (ISA, EISA)
00DC  -W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE  -W  DMA channel 4-7 write mask register (ISA, EISA) (see #P130)
Notes:    the temporary register is used as holding register in memory-to-memory
      DMA transfers; it holds the last transferred byte
    channel 4 is used for cascading the first (8-bit) DMA controller
    base/current address registers can only address the memory in 16-bit
      words (i.e. they contain lines A1-A16 of the address bus with line
      A0 always equal to 0); base/current word count registers contain the
      number of 16-bit words
    command and request registers do not exist on PS/2 DMA controller

Bitfields for DMA channel 4-7 status register:
Bit(s)    Description    (Table P125)
 7 = 1    channel 7 request
 6 = 1    channel 6 request
 5 = 1    channel 5 request
 4 = 1    channel 4 request
 3 = 1    terminal count on channel 7
 2 = 1    terminal count on channel 6
 1 = 1    terminal count on channel 5
 0 = 1    terminal count on channel 4
SeeAlso: #P001,#P126

Bitfields for DMA channel 4-7 command register:
Bit(s)    Description    (Table P126)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1  extended write selection
    =0  late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing
 2    =1  enable controller
    =0  enable memory-to-memory transfer
 1-0    channel number (00 = 4 to 11 = 7)
SeeAlso: #P002,#P125,#P128

Bitfields for DMA channel 4-7 request register:
Bit(s)    Description    (Table P127)
 7-3    reserved (0)
 2    =0 clear request bit
    =1 set request bit
 1-0    channel number
    00 channel 4 select
    01 channel 5 select
    10 channel 6 select
    11 channel 7 select
SeeAlso: #P003,#P128

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)    Description    (Table P128)
 7-3    reserved
 2    =0  clear mask bit
    =1  set mask bit
 1-0    channel select
    00 channel 4 select
    01 channel 5 select
    10 channel 6 select
    11 channel 7 select
SeeAlso: #P004,#P126

Bitfields for DMA channel 4-7 mode register:
Bit(s)    Description    (Table P129)
 7-6    transfer mode
    00  demand mode
    01  single mode
    10  block mode
    11  cascade mode
 5    direction
    0  address increment select
    1  address decrement select
 4    autoinitialisation enabled
 3-2    operation
    00  verify operation
    01  write to memory
    10  read from memory
    11  reserved
 1-0    channel number
    00  channel 4 select
    01  channel 5 select
    10  channel 6 select
    11  channel 7 select
SeeAlso: #P005,#P128

Bitfields for DMA channel 4-7 write mask register:
Bit(s)    Description    (Table P130)
 7-4    reserved
 3    channel 7 mask bit
 2    channel 6 mask bit
 1    channel 5 mask bit
 0    channel 4 mask bit
Note:    each mask bit is automatically set when the corresponding channel
      reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P128,#P006
----------P00E000E1--------------------------
PORT 00E0-00E1 - CHIPSET FROM ACT

00E0  ?W  index for accesses to data port
00E1  R?  chip set data
----------P00E000E7--------------------------
PORT 00E0-00E7 - MICROCHANNEL

00E0  RW  split address register, memory encoding registers PS/2m80 only
    (see #P131)
00E1  RW  memory register (see #P132,#P133)
00E3  RW  error trace (bits 23-16 of address on last rising edge of ERS line)
00E4  RW  error trace (bits 15-8 of address on last rising edge of ERS line)
00E5  RW  error trace (see #P134)
00E7  RW  error trace (see #P135)

Bitfields for Microchannel Split Address Register:
Bit(s)    Description    (Table P131)
 7-6    unused
 5-4    2MB memory for connector 2 on Type2 motherboard
    bit 5: second MB disabled or not present
    bit 4: first MB disabled or not present
 3-0    address at which to place leftover from split in first MB, in MB
    (1-15, 0 is invalid when split is active)
SeeAlso: #P132,#P133

Bitfields for Microchanel Memory Register, Type1 motherboard:
Bit(s)    Description    (Table P132)
 7-6    1 MB memory for connector 2
    10 installed
    11 not installed
 5-4    1 MB memory for connector 1
    10 installed
    11 not installed
 3-1    split memory select
        ROM   convmem    over1M
    001    ON    640K    384K
    011    ON    512K    512K
    100    shadow    640K    0K
    101    ON    640K    0K
    110    shadow    512K    0K
    111    ON    512K    0K
 0    parity checking
    =0 enable
    =1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P131,#P133

Bitfields for Microchannel Memory Register, Type2 motherboard:
Bit(s)    Description    (Table P133)
 7-6    unused
 5-4    memory connector 1
    bit 5: second MB disabled or not present
    bit 4: first MB disabled or not present
 3-1    split memory select
        ROM   convmem    over1M
    000    shadow    640K    256K
    001    ON    640K    384K
    010    shadow    512K    384K
    011    ON    512K    512K
    100    shadow    640K    0K
    101    ON    640K    0K
    110    shadow    512K    0K
    111    ON    512K    0K
 0    parity checking
    =0 enable
    =1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P131,#P132

Bitfields for Microchannel Error Trace register E5h:
Bit(s)    Description    (Table P134)
 7-2    bits 7-2 of address on last rising edge of ERS line
 1    address space (0=I/O, 1=memory)
 0    =1 bus-master arbitration cycle
SeeAlso: #P135

Bitfields for Microchannel Error Trace register E7h:
Bit(s)    Description    (Table P135)
 7-1    unused
 0    bus cycle type
    =0 control (instruction fetch, halt, interrupt acknowledge)
    =1 data
SeeAlso: #P134
----------P00E000EF--------------------------
PORT 00E0-00EF - IBM PS/1 CLOCK
----------P00E1------------------------------
PORT 00E1 - STB PowerMEG - ???
Desc:    the STB PowerMEG is a memory expansion card capable of providing EMS

00E1  RW  ???
      bit 0: ???
--------X-P00E2------------------------------
PORT 00E2 - S3 Trio64V+ - I2C PORT
Range:    PORT 00E2h or PORT 00E8h; default depends on external pin, but can
      be reprogrammed via chip's CR6F
SeeAlso: PORT 00E8h,#M098
--------X-P00E8------------------------------
PORT 00E8 - S3 Trio64V+ - I2C PORT
Range:    PORT 00E2h or PORT 00E8h; default depends on external pin, but can
      be reprogrammed via chip's CR6F
SeeAlso: PORT 00E2h,#M098
----------P00EB------------------------------
PORT 00EB - Intel "Triton" chipset - ???
SeeAlso: PORT 0085h"Triton"

00EB  ?W  ???
----------P00EB------------------------------
PORT 00EB - DUMMY PORT FOR DELAY???
Note:    on a number of machines, the BIOS appears to write a copy of any
      data sent to numerous other ports to this port as well; it seems
      to be a dummy port used for short delays between writes to other
      ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00ED"DUMMY"

00EB  ?W  ???
----------P00EC00ED--------------------------
PORT 00EC-00ED - Compaq LTE Elite
----------P00ED------------------------------
PORT 00ED - DUMMY PORT FOR DELAY???
Note:    on a number of machines, the BIOS appears to write a copy of any
      data sent to numerous other ports to this port as well; it seems
      to be a dummy port used for short delays between writes to other
      ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00EB"DUMMY"

00EDw  ?W  ???
----------P00EF------------------------------
PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!
----------P00F000F5--------------------------
PORT 00F0-00F5 - PCjr Disk Controller

00F0  ??  disk controller
00F2  ??  disk controller control port
00F4  ??  disk controller status register
00F5  ??  disk controller data port
----------P00F000FF--------------------------
PORT 00F0-00FF - MATH COPROCESSOR (8087..80387)

00F0  -W  math coprocessor clear busy latch (write 00h)
00F1  -W  math coprocessor reset (write 00h)
00F8  RW  opcode transfer (CPU-coprocessor communication)
00FA  RW  opcode transfer
00FC  RW  opcode transfer
----------P00F9------------------------------
PORT 00F9 - Compaq LTE Elite
----------P00FB------------------------------
PORT 00FB - Compaq LTE Elite
----------P00F900FF--------------------------
PORT 00F9-00FF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P0100------------------------------
PORT 0100 - 3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0110h,PORT 0120h
----------P01000107--------------------------
PORT 0100-0107 - PS/2 POS (Programmable Option Select)
Note:    the default value for PORT 0102h is stored in CMOS 31h

0100  R      POS register 0    Low adapter ID byte
0101  R      POS register 1    High adapter ID byte
0102  RW  POS register 2    option select data byte 1 (see #P136)
0103  RW  POS register 3    option select data byte 2 (see #P496)
0104  RW  POS register 4    option select data byte 3
0105  RW  POS register 5    option select data byte 4
         bit 7    channel active (-CHCK)
         bit 6    channel status
0106  RW  POS register 6    Low subaddress extension
0107  RW  POS register 7    High subaddress extension

Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s)    Description    (Table P136)
 7      0  = unidirectional LPT port
      1  = bidirectional LPT port
 6-5    PS/2 Model 50 and higher
     00b = default LPT port at 3BCh
     01b = ""           378h
     10b = ""           278h
     11b = reserved
 4    enable parallel port
 3    serial port address
    =0 COM2 (02F8h, IRQ3)
    =1 COM1 (03F8h, IRQ4)
 2    enable serial port
 1    enable diskette controller
 0    (MCA) =0 override bits 1,2,4 and disable devices
 0    card enable (CDEN)
 0    =1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
      without monitor)
---ET4000---
 7-4    reserved???
 3    video RAM wait enable
 2    ET4000: ROM BIOS wait enable
 1    ET4000: I/O wait enable
Note:    access to this port is only possible when PORT 0094h bit 7 is low.
SeeAlso: #P496

Bitfields for Chips&Technologies 64200 "Wingine" setup register:
Bit(s)    Description    (Table P496)
 7    enable access to extended registers (see #P449)
Note:    on some C&T graphics chips, this register can be made read-only
      via XR70 (see #P449)
SeeAlso: #P136
----------P0100010F--------------------------
PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300
----------P0108010F--------------------------
PORT 0108-010F - IBM PS/2 - 8 digit LED info panel

010F  -W  leftmost character on display
010E  -W  second character
 ...
0108  -W  eighth character
----------P0110------------------------------
PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0120h"3COM"
----------P0120------------------------------
PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0110h"3COM"
----------P0130013F--------------------------
PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330
----------P01300133--------------------------
PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter.
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P01340137--------------------------
PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter.
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P0138013F--------------------------
PORT 0138-013F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P0140014F--------------------------
PORT 0140-014F - SCSI (alternate Small Computer System Interface) adapter
Note:    first adapter is at 0340-034F
----------P0140014F--------------------------
PORT 0140-014F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:    alternate address at 0150, 0160, 0170
Notes:    XL-220/221 are based on LOGIC Devices L53C80JC4 SCSI controller which
      is compatible with Symbios Logic (formaerly NCR) 53C80
    each SCSI data pin is inverted and compared with correcponding bit
      in the ID select register; if any matches are found while a bus free
      condition exists and SEL is active, SCSI controller will genarate an
      interrupt to indicate a selection or reselection
    pseudo-DMA register is provided by some on-card PLM, and decodes any
      address in the range 01x8-01xF; it should be accessed with 16-bit
      I/O instructions only causing 2 SCSI REQ/ACK hanshakes (8-bit I/O
      is treated as 16-bit, and second byte is lost); delayed assertion of
      the REQ signal or bus free condition on the SCSI bus causes the
      pseudo-DMA register to prolong ISA I/O cycle not asserting IOCHRDY
      signal (SCSI phase mismatch doesn't), and so may cause ISA bus to
      hang in not ready state!
    SCSI BIOS is an 8K ROM located at C8000-CBFFF if I/O port range
      0140-014F is selected, at CC000-CFFFF if I/O port range 0150-015F
      is selected, at D8000-DBFFF if I/O port range 0160-016F is selected,
      and at DC000-DFFFF if I/O port range 0170-017F is selected

0140  R-  current SCSI data bus register
0140  -W  output data register
0141  RW  initiator command register (see #P137)
0142  RW  mode register (see #P138)
0143  RW  target command register (see #P139)
0144  R-  current SCSI control register (see #P140)
0144  -W  ID select register
0145  R-  DMA status register (see #P141)
0145  -W  start DMA send register
      any write starts DMA send
0146  R-  input data register
      temporarily holds data byte received from the SCSI bus in DMA mode
0146  -W  start DMA target receive register
      any write starts target mode DMA receive
0147  R-  reset error/interrupt register
      any read resets the interrupt request latch and the error latches
0147  -W  start DMA initiator mode receive register
      any write starts initiator mode DMA receive
0148w RW  pseudo-DMA register

Bitfields for initiator command register:
Bit(s)    Description    (Table P137)
 7    assert RST
 6    (read) arbitration in progress
    (write) test mode
 5    (read) lost arbitration
 4    assert ACK
 3    assert BSY
 2    assert SEL
 1    assert ATN
 0    assert data bus
SeeAlso: #P138,#P139,#P140,#P141

Bitfields for mode register:
Bit(s)    Description    (Table P138)
 7    block mode
 6    target mode
 5    enable parity check
 4    enable parity interrupt
 3    enable end of DMA interrupt
 2    monitor BSY
 1    DMA mode
 0    arbitrate
SeeAlso: #P137

Bitfields for target command register:
Bit(s)    Description    (Table P139)
 7    (read) last byte sent
 6-4    reserved
 3    assert REQ
 2    assert MSG
 1    assert C/D
 0    assert I/O
SeeAlso: #P137

Bitfields for current SCSI control register:
Bit(s)    Description    (Table P140)
 7    RST
 6    BSY
 5    REQ
 4    MSG
 3    C/D
 2    I/O
 1    SEL
 0    parity
SeeAlso: #P137

Bitfields for DMA status register:
Bit(s)    Description    (Table P141)
 7    end of DMA
 6    DMA request
 5    parity error
 4    interrupt request
 3    phase match
 2    BSY error
 1    ATN
 0    ACK
SeeAlso: #P137
----------P0140014F--------------------------
PORT 0140-014F - Future Domain TMC-16x0 SCSI adapter
Range:    alternate address at 0150, 0160, 0170
Notes:    TMC-1650/1670 have a 25-pin external connector, whereas the 1660 and
      1680 have a SCSI-2 50-pin high-density external connector
    TMC-1670/1680 have floppy disk controller built in
    BIOS versions prior to 3.2 assigned SCSI ID 6 to SCSI adapter,
      versions 3.2 and greater use SCSI ID 7
    the drive ordering implemented in BIOS versions 3.4 and 3.5 is the
      opposite of the order (currently) used by the rest of the SCSI
      industry--for example, under DOS SCSI ID 0 will be D: and SCSI ID 1
      will be C:
    Future Domain TMC-16x0 SCSI adapter series are based upon Future Domain
      TMC-1800/18C50/18C30 SCSI controllers
    TMC-1800/18C50/18C30 are ISA SCSI controllers, TMC-36C70 is a PCI
      version of TMC-18C30
    TMC-1800/18C50 have 8K FIFO, TMC-18C30/36C70 have 2K FIFO
    Future Domain TMC-1650/1660/1670/1680/1610M/1610MER/1610MEX SCSI
      adapters are based on TMC-1800/18C50/18C30
    Quantum ISA-200S/250MG SCSI adapters are based on TMC-18C50 (?)
    Future Domain TMC-3260 and Adaptec AHA-2920 PCI SCSI adapters are
      based on TMC-36C70

0140  R-  read SCSI data register
0140  -W  write SCSI data register
0141  R-  SCSI status register (see #P142)
0141  -W  SCSI control register (see #P143)
0142  R-  TMC status register (see #P144)
0142  -W  interrupt control register (see #P145)
0143  R-  FIFO status register, TMC-18C50/18C30/36C70 chips only
0143  -W  SCSI mode control register (see #P146)
0144  R-  interrupt condition register, TMC-18C50/18C30/36C70 only (see #P147)
0144  -W  TMC control register (see #P148)
0145  R-  ID code LSB register
      27h for TMC-1800 chip
      E9h for TMC-18C50/18C30/36C70 chips
0145  -W  memory control register, TMC-18C50/18C30/36C70 only
0146  R-  ID code MSB register
      60h for TMC-18C50/18C30 chips
      61h for TMC-1800 chip
0147  R-  read loopback register
0147  -W  write loopback register
0148  RW  SCSI data no ACK register
0149  R-  interrupt status register (see #P149)
014A  R-  configuration register 1 (see #P150)
014B  R-  configuration register 2, TMC-18C50/18C30/36C70 only (see #P151)
014B  -W  I/O control register, TMC-18C30/36C70 only (see #P152)
014Cw R-  read FIFO data register
014Cw -W  write FIFO data register
014Ew R-  FIFO data count register
Notes:    any value written into the write loopback register can be read back
      from the read loopback register unchanged (this is used by the BIOS
      to test the controller)
    reading from read SCSI data register and writing to write SCSI data
      register causes REQ/ACK handshake to occur automatically, reading
      and writing the SCSI data no ACK register doesn't
    SCSI FIFO may be used only for DATA IN / DATA OUT phase transfers on
      TMC-1800; on TMC-18C50/18C30 it may also be used for COMMAND phase
      transfers

Bitfields for SCSI status register:
Bit(s)    Description    (Table P142)
 7    not BSY
 6    not MSG
 5    not I/O
 4    not C/D
 3    not REQ
 2    not SEL
 1    parity error???
 0    not ATN
SeeAlso: #P143,#P152

Bitfields for SCSI control register:
Bit(s)    Description    (Table P143)
 7    RST
 6    SEL
 5    BSY
 4    ATN
 3    I/O
 2    C/D
 1    MSG
 0    bus enable
SeeAlso: #P142,#P144,#P145

Bitfields for TMC status register:
Bit(s)    Description    (Table P144)
 7    bus enabled
 6    parity enabled
 5    FIFO enabled
 4    =1 data are expected to flow out from FIFO to SCSI bus
    =0 data are expected to flow from SCSI bus into FIFO
 3    SCSI reset
 2    ???
 1    arbitration complete
 0    interrupt request
SeeAlso: #P143

Bitfields for interrupt control register:
Bit(s)    Description    (Table P145)
 7    enable interrupt on REQ
 6    enable interrupt on SEL
 5    enable arbitration interrupt
 4    enable interrupt on ???
 0-3    FIFO threshold (how many 512 byte blocks in FIFO should be
      full/empty for interrupt to be generated)
SeeAlso: #P143

Bitfields for SCSI mode control register:
Bit(s)    Description    (Table P146)
 7    synchronous mode
 6    fast SCSI
 5-4    reserved?
 3-0    synchronous transfer period in 25 ns units
SeeAlso: #P143

Bitfields for interrupt condition register:
Bit(s)    Description    (Table P147)
 7    FIFO error interrupt
 6    forced interrupt???
 5    interrupt on RST
 4    arbitration interrupt
 3    interrupt on SEL
 2    interrupt on REQ
 1    interrupt on ???
 0    ???
SeeAlso: #P143

Bitfields for TMC control register:
Bit(s)    Description    (Table P148)
 7    enable FIFO
 6    =1 data are expected to flow out from FIFO to SCSI bus
    =0 data are expected to flow from SCSI bus into FIFO
 5    clear forced interrupt, TMC-18C50/18C30/36C70 only
 4    enable interrupt
 3    enable parity
 2    arbitrate
 1    force interrupt???
 0    clear SCSI reset flag???
SeeAlso: #P143
Note:    on the TMC-1800 the FIFO must be enabled and bit 6 must be set
      according to the expected data direction before a data phase will
      occur (the TMC-1800 probably doesn't generate interrupts on REQ in
      DATA IN / DATA OUT phases); on the TMC-18C50/18C30 it may be done
      when the interrupt on REQ occurs and the SCSI phase is
      DATA IN, DATA OUT or COMMAND

Bitfields for interrupt status register:
Bit(s)    Description    (Table P149)
 7    interrupt on REQ enabled
 6    interrupt on SEL enabled
 5    arbitration interrupt enabled
 4    interrupt on ??? enabled
 3    interrupt enabled
 2    ???
 1    always set???
 0    ???
SeeAlso: #P143

Bitfields for configuration register 1:
Bit(s)    Description    (Table P150)
 7-6    BIOS address range
    00 C8000h-C9FFFh
    01 CA000h-CBFFFh
    10 CE000h-CFFFFh
    11 DE000h-DFFFFh
 5-4    I/O address range
    00 140h-14Fh
    01 150h-15Fh
    10 160h-16Fh
    11 170h-17Fh
 3-1    interrupt select
    000 IRQ3
    001 IRQ5
    010 IRQ10
    011 IRQ11
    100 IRQ12
    101 IRQ14
    110 IRQ15
    111 no IRQ
 0    reserved???
Note:    the seven on-board configuration jumpers are read through this register
SeeAlso: #P143,#P151

Bitfields for configuration register 2:
Bit(s)    Description    (Table P151)
 7    32-bit mode enabled (TMC-18C30/36C70 only???)
 6-2    ???
 1    RAM disabled (TMC-18C30/36C70 only???)
 0    ???
Note:    256 byte on-chip RAM is mapped at offset 1F00h within the BIOS segment
SeeAlso: #P143,#P150

Bitfields for TMC control register:
Bit(s)    Description    (Table P152)
 7    enable 32-bit mode
 6-0    ???
SeeAlso: #P143
--------d-P0140014F--------------------------
PORT 0140-014F - Quantum ISA-200S/250MG SCSI adapter
Range:    alternate address at 0150, 0160, 0170
Note:    Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
      TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P01400157--------------------------
PORT 0140-0157 - RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
----------P0150015F--------------------------
PORT 0150-015F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:    alternate address at 0140, 0160, 0170
----------P0150015F--------------------------
PORT 0150-015F - Future Domain TMC-16x0 SCSI adapter
Range:    alternate address at 0140, 0160, 0170
--------d-P0150015F--------------------------
PORT 0150-015F - Quantum ISA-200S/250MG SCSI adapter
Range:    alternate address at 0140, 0160, 0170
Note:    Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
      TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P015C015D--------------------------
PORT 015C-015D - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 026Eh,PORT 0398h

015C  -W  index for data port
015D  RW  EPP command data
----------P015F------------------------------
PORT 015F - ARTEC Handyscanner A400Z.  alternate address at 35F.
----------P0160016F--------------------------
PORT 0160-016F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:    alternate address at 0140, 0150, 0170
----------P0160016F--------------------------
PORT 0160-016F - Future Domain TMC-16x0 SCSI adapter
Range:    alternate address at 0140, 0150, 0170
--------d-P0160016F--------------------------
PORT 0160-016F - Quantum ISA-200S/250MG SCSI adapter
Range:    alternate address at 0140, 0150, 0170
Note:    Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
      TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P0168016F--------------------------
PORT 0168-016F - 4th (Quaternary) EIDE Controller
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01700177--------------------------
PORT 0170-0177 - HDC 2    (2nd Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P0170017F--------------------------
PORT 0170-017F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:    alternate address at 0140, 0150, 0160
----------P0170017F--------------------------
PORT 0170-017F - Future Domain TMC-16x0 SCSI adapter
Range:    alternate address at 0140, 0150, 0160
--------d-P0170017F--------------------------
PORT 0170-017F - Quantum ISA-200S/250MG SCSI adapter
Range:    alternate address at 0140, 0150, 0160
Note:    Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
      TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P01780179--------------------------
PORT 0178-0179 - Power Management
SeeAlso: PORT 0026h,#P086

0178  -W  index selection for data port
0179  RW  power management data
----------P0178017F--------------------------
PORT 0178-017F - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P01CE01CF--------------------------
PORT 01CE-01CF - ATI Mach32 video chipset - ???

01CE  -W  index register
01CF  RW  data register
----------P01E801EF--------------------------
PORT 01E8-01EF - Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL

01ED  RW  select internal register. Data to/from 01EF
01EE  R-  ???
01EF  RW  register value
    05h  = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac)
         = 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac)
    10h memory size
       bits 2-0 = size
           (undefined,512K,640K,1024K,2560K,2048K,4096K,undef.)
    14h ???
       bit 2: 384K RAM of first 1024K relocated to top of memory
----------P01E801EF--------------------------
PORT 01E8-01EF - 3rd (Tertiary) EIDE Controller
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 0170h-0177h,PORT 01F0h-01F7h
----------P01F001F7--------------------------
PORT 01F0-01F7 - HDC 1    (1st Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 3510h-3513h

01F0  RW  data register
01F1  R-  error register (see #P153)
01F1  -W  WPC/4     (Write Precompensation Cylinder divided by 4)
01F2  RW  sector count
01F3  RW  sector number (CHS mode)
      logical block address, bits 0-7 (LBA mode)
01F4  RW  cylinder low (CHS mode)
      logical block address, bits 15-8 (LBA mode)
01F5  RW  cylinder high (CHS mode)
      logical block address, bits 23-16 (LBA mode)
01F6  RW  drive/head (see #P154)
01F7  R-  status register (see #P155)
01F7  -W  command register (see #P156)

Bitfields for Hard Disk Controller error register:
Bit(s)    Description    (Table P153)
---diagnostic mode errors---
 7    which drive failed (0 = master, 1 = slave)
 6-3    reserved
 2-0    error code
    001    no error detected
    010    formatter device error
    011    sector buffer error
    100    ECC circuitry error
    101    controlling microprocessor error
---operation mode---
 7    bad block detected
 6    uncorrectable ECC error
 5    reserved
 4    ID found
 3    reserved
 2    command aborted prematurely
 1    track 000 not found
 0    DAM not found (always 0 for CP-3022)
SeeAlso: #P154,#P155

Bitfields for hard disk controller drive/head specifier:
Bit(s)    Description    (Table P154)
 7    =1
 6    LBA mode enabled, rather than default CHS mode
 5    =1
 4    drive select (0 = drive 0, 1 = drive 1)
 3-0    head select bits (CHS mode)
    logical block address, bits 27-24 (LBA mode)
SeeAlso: #P153,#P155

Bitfields for hard disk controller status register:
Bit(s)    Description    (Table P155)
 7    controller is executing a command
 6    drive is ready
 5    write fault
 4    seek complete
 3    sector buffer requires servicing
 2    disk data read successfully corrected
 1    index - set to 1 each disk revolution
 0    previous command ended in an error
SeeAlso: #P153,#P156

(Table P156)
Values for hard disk controller command codes:
Command     Spec    Type    Proto    Description            class:
 00h        opt    nondata    NOP
 08h                device reset
 1xh        opt    nondata    recalibrate              1
 20h        req    PIOin    read sectors with retry          1
 21h        req    PIOin    read sectors without retry      1
 22h        req    PIOin    read long with retry          1
 23h        req    PIOin    read long without retry          1
 30h        req    PIOout    write sectors with retry      2
 31h        req    PIOout    write sectors without retry      2
 32h        req    PIOout    write long with retry          2
 33h        req    PIOout    write long without retry      2
 3Ch     IDE    opt    PIOout    write verify              3
 40h        req    nondata    read verify sectors with retry      1
 41h        req    nondata    read verify sectors without retry 1
 50h        req    vend    format track              2
 7xh        req    nondata    seek                  1
 8xh     IDE    vendor    vend    vendor unique 3
 90h        req    nondata    execute drive diagnostics      1
 91h        req    nondata    initialize drive parameters      1
 92h        opt    PIOout    download microcode
 94h E0h IDE    opt    nondata    standby immediate          1
 95h E1h IDE    opt    nondata    idle immediate              1
 96h E2h IDE    opt    nondata    standby                  1
 97h E3h IDE    opt    nondata    idle                  1
 98h E5h IDE    opt    nondata    check power mode          1
 99h E6h IDE    opt    nondata    set sleep mode              1
 9Ah     IDE    vendor    vend    vendor unique 1
 A0h     ATAPI            packet command
 A1h     ATAPI    opt    PIOin    ATAPI Identify            (see #P165)
 B0h     SMART    opt        Self Mon., Analysis, Rept. Tech. (see #P167)
 C0h-C3h IDE    vendor    vend    vendor unique 2
 C4h     IDE    opt    PIOin    read multiple              1
 C5h     IDE    opt    PIOout    write multiple              3
 C6h     IDE    opt    nondata    set multiple mode          1
 C7h     ATA-4            Read DMA O/Q
 C8h     IDE    opt    DMA    read DMA with retry          1
 C9h     IDE    opt    DMA    read DMA without retry          1
 CAh     IDE    opt    DMA    write DMA with retry          3
 CBh     IDE    opt    DMA    write DMA w/out retry          3
 CCh     ATA-4            Write DMA O/Q
 DAh                get media status
 DBh     ATA-2    opt    vend    acknowledge media chng        [Removable]
 DCh     ATA-2    opt    vend    Boot / Post-Boot        [Removable]
 DDh     ATA-2    opt    vend    Boot / Pre-Boot    (ATA-2)        [Removable]
 DEh     ATA-2    opt    vend    door lock            [Removable]
 DFh     ATA-2    opt    vend    door unlock            [Removable]
 E0h-E3h            (second half of commands 94h-96h)
 E4h     IDE    opt    PIOin    read buffer              1
 E5h-E6h            (second half of commands 98h-99h)
 E8h     IDE    opt    PIOout    write buffer              2
 E9h     IDE    opt    PIOout    write same              3
 EAh     ATA-3    opt        Secure Disable            [Security Mode]
 EAh     ATA-3    opt        Secure Lock            [Security Mode]
 EAh     ATA-3    opt        Secure State            [Security Mode]
 EAh     ATA-3    opt        Secure Enable WriteProt        [Security Mode]
 EBh     ATA-3    opt        Secure Enable            [Security Mode]
 EBh     ATA-3    opt        Secure Unlock            [Security Mode]
 ECh     IDE    req    PIOin    identify drive              1 (see #P157)
 EDh     ATA-2    opt    nondata    media eject            [Removable]
 EEh     ATA-3    opt        identify device DMA            (see #P157)
 EFh     IDE    opt    nondata    set features              1 (see #P175)
 F0h-F4h IDE        vend    EATA standard
 F1h                Security Set Password
 F2h                Security Unlock
 F3h                Security Erase Prepare
 F4h                Security Erase Unit
 F5h-FFh IDE    vendor    vend    vendor unique 4
 F5h                Security Freeze Lock
 F6h                Security Disable Password
SeeAlso: #P153,#P155

Format of IDE/ATA Identify Drive information:
Offset    Size    Description    (Table P157)
 00h    WORD    general configuration (see #P158)
 02h    WORD    number of logical cylinders
 04h    WORD    reserved
 06h    WORD    number of logical heads
 08h    WORD    vendor-specific (obsolete: unformatted bytes per track)
 0Ah    WORD    vendor-specific (obsolete: unformatted bytes per sector)
 0Ch    WORD    number of logical sectors
 0Eh    WORD    vendor-specific
 10h    WORD    vendor-specific
 12h    WORD    vendor-specific
 14h 10 WORDs    serial number
        no serial number if first word is 0000h
        else blank-padded ASCII serial number
 28h    WORD    vendor-specific
        [buffer type: 01h single-sector, 02h multisector,
          03h multisector with read cache]
 2Ah    WORD    controller buffer size in 512-byte sectors
        0000h = unspecified
 2Ch    WORD    number of vendor-specific (usually ECC) bytes on
          Read/Write Long; 0000h = unspecified
 2Eh  4    WORDs    firmware revision
        no revision number if first word is 0000h
        else blank-padded ASCII revision number
 36h 20    WORDs    model number
        no model number if first word is 0000h
        else blank-padded ASCII model string
 5Eh    WORD    read/write multiple support
        bits 7-0: maximum number of sectors per block supported
            00h if read/write multiple not supported
        bits 15-8: vendor-specified
 60h    WORD    able to do doubleword transfers if nonzero
 62h    WORD    capabilities (see #P159)
 64h    WORD    security mode
        bit 15: security-mode feature set supported
        bits 14-8: maximum number of passwords supported
 66h    WORD    PIO data transfer cycle timing
 68h    WORD    single-word DMA data transfer cycle timing
 6Ah    WORD    field validity
        bit 0: offsets 6Ch-75h valid
        bit 1: offsets 80h-8Dh valid
 6Ch    WORD    logical cylinders in current translation mode
 6Eh    WORD    logical heads in current translation mode
 70h    WORD    logical sectors per track in current translation mode
 72h    DWORD    current capacity in sectors (excluding device-specific uses)
 76h    WORD    multiple-sector support
        bits 7-0: count for read/write multiple command
        bit 8:    multiple-sector setting is valid
 78h    DWORD    total number of user-addressable sectors (LBA mode)
        00000000h if LBA mode not supported
 7Ch    WORD    single-word DMA transfer modes
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh    WORD    multiword DMA transfer
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high byte is bitmap of active mode (bit 8 = mode 0, etc.)
 80h    WORD    supported flow control PIO transfer modes
 82h    WORD    minimum multiword DMA transfer cycle time in ns
 84h    WORD    recommended multiword DMA cycle time in ns
 86h    WORD    minimum non-flow-control PIO transfer cycle time in ns
 88h    WORD    minimum PIO transfer cycle time with IORDY in ns
 8Ah  2 WORDs    reserved for future PIO modes (0)
 8Eh  2 WORDs    reserved (0)
 92h    WORD    command queueing/overlapped operation (see #P164)
 94h  6 WORDs    reserved (0)
 A0h    WORD    major revision number of specification to which device conforms
        01h = ATA-1, 02h = ATA-2, etc.    0000h/FFFFh = not reported
 A2h    WORD    minor revision number of specification to which device conforms
        0000h/FFFFh = not reported
 A4h    WORD    feature set support 1 (see #P160)
        (only valid if revision reported in A0h/A2h)
 A6h    WORD    feature set support 2 (see #P161)
        (only valid if revision reported in A0h/A2h)
 A8h    WORD    (ATA/ATAPI-4) feature set support extension (see #P162)
 AAh    WORD    feature set enabled 1 (see #P163)
        (only valid if revision reported in A0h/A2h)
 ACh    WORD    feature set enabled 2 (see #P161)
        (only valid if revision reported in A0h/A2h)
 AEh    WORD    (ATA/ATAPI-4) feature set enabled extension (see #P162)
 B0h 42 WORDs    reserved (0)
100h 32 WORDs    vendor-specific
100h    WORD    security status
140h 96 WORDs    reserved (0)
SeeAlso: #P165,#0199

Bitfields for IDE general configuration:
Bit(s)    Description    (Table P158)
 15    device class
    =0 ATA device
    =1 ATAPI device
 14    requires format speed tolerance gap
 13    supports track offset option
 12    supports data strobe offset
 11    disk rotational sped tolerance > 0.5%
 10-8    disk transfer rate
    001 <= 5Mbit/sec
    010 5-10 Mbit/sec
    100 > 10Mbit/sec
 7-6    drive type
    01 fixed media
    10 removable media
 5    synchronized drive motor option enabled
 4    head-switching time > 15 microseconds
 3    encoding
    =0 MFM
 2-1    sector type
    01 hard-sectored
    10 soft-sectored
 0    unused (0)
SeeAlso: #P157

Bitfields for IDE capabilities:
Bit(s)    Description    (Table P159)
 13    Standby Timer values used according to ATA standard
 11    IORDY supported
 10    device can disable use of IORDY
 9    LBA mode supported
 8    DMA supported
SeeAlso: #P157

Bitfields for ATA feature set support 1:
Bit(s)    Description    (Table P160)
 15    Identify Device DMA command is supported
 14    NOP (00h) command is supported
 13    Read Buffer command is supported
 12    Write Buffer command is supported
 11    Write Verify command is supported
 10    host protected area feature set is supported
 9    Device Reset (08h) command is supported
 8    Service interrupt is supported
 7    release interrupt is supported
 6    device supports look-ahead
 5    device supports write cache
 4    PACKET command feature set is supported
 3    power management is supported
 2    removable-media feature set is supported
 1    security feature set is supported
 0    SMART feature set is supported
Note:    values of 0000h and FFFFh indicate that this field is not supported
SeeAlso: #P157,#P161,#P162

Bitfields for ATA feature set support/enabled 2:
Bit(s)    Description    (Table P161)
 15    must be 0 if this field is supported
 14    must be 1 if this field is supported
 13-2    reserved
 1    Read DMA O/Q (C7h) and Write DMA O/Q (CCh) commands supported/enabled
 0    Download Microcode (92h) command is supported/enabled
SeeAlso: #P157,#P163,#P160,#P162

Bitfields for ATA feature set support extension:
Bit(s)    Description    (Table P162)
 15    must be 0 if this field is supported
 14    must be 1 if this field is supported
 13-0    reserved
SeeAlso: #P157,#P160,#P161

Bitfields for ATA feature set enabled 1:
Bit(s)    Description    (Table P163)
 15    Identify Device DMA command is supported
 14    NOP (00h) command is supported
 13    Read Buffer command is supported
 12    Write Buffer command is supported
 11    Write Verify command is supported
 10    host protected area feature set is supported
 9    Device Reset (08h) command is supported
 8    Service interrupt is enabled
 7    release interrupt is enabled
 6    look-ahead is enabled
 5    write cache is enabled
 4    PACKET command feature set is enabled
 3    power management is enabled
 2    removable-media feature set is enabled
 1    security feature set is enabled
 0    SMART feature set is enabled
SeeAlso: #P157,#P161

Bitfields for ATA/ATAPI-4 command queueing/overlapped operation support:
Bit(s)    Description    (Table P164)
 15    reserved
 14    device supports command queueing
 13    device supports overlapped operation
 12-5    reserved
 4-0    maximum depth of queued commands supported (0 if bit 14 clear)
SeeAlso: #P157

Format of ATAPI Identify Information:
Offset    Size    Description    (Table P165)
 00h    WORD    general configuration (see #P166)
 02h  9 WORDs    ???
 14h 10 WORDs    serial number
        no serial number if first word is 0000h
        else blank-padded ASCII serial number
 28h  3 WORDs    vendor-specific
 2Eh  4    WORDs    firmware revision
        no revision number if first word is 0000h
        else blank-padded ASCII revision number
 36h 20    WORDs    model number
        no model number if first word is 0000h
        else blank-padded ASCII model string
 5Eh    WORD    vendor-specific
 60h    WORD    reserved (0)
 62h    WORD    capabilities (see #P159)
 64h    WORD    security mode???
 66h    WORD    PIO data transfer cycle timing
 68h    WORD    single-word DMA data transfer cycle timing
 6Ah    WORD    field validity
        bit 0: offsets 6Ch-73h valid
        bit 1: offsets 80h-8Dh valid
 6Ch    WORD    ??? logical cylinders in current translation mode
 6Eh    WORD    ??? logical heads in current translation mode
 70h    WORD    ??? logical sectors per track in current translation mode
 72h  2    WORDs    ??? current capacity in sectors
 76h    WORD    ??? multiple-sector count for read/write multiple command
 78h  2    WORDs    ??? total number of user-addressable sectors (LBA mode)
 7Ch    WORD    single-word DMA transfer modes
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh    WORD    multiword DMA transfer
        low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
        high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 80h    WORD    supported flow control PIO transfer modes
 82h    WORD    minimum multiword DMA transfer cycle time
 84h    WORD    recommended multiword DMA cycle time
 86h    WORD    minimum non-flow-control PIO transfer cycle time
 88h    WORD    minimum PIO transfer cycle time with IORDY
 8Ah  2 WORDs    reserved for future PIO modes (0)
 8Eh    WORD    typical time for release when processing overlapped CMD in
          microseconds
 90h    WORD    ???
 92h    WORD    major ATAPI version number
 94h    WORD    minor ATAPI version number
 96h 54 WORDs    reserved (0)
100h 32 WORDs    vendor-specific
140h 96 WORDs    reserved (0)
SeeAlso: #P157

Bitfields for ATAPI General Configuration:
Bit(s)    Description    (Table P166)
 15-14    device type
    0x not ATAPI
    10 ATAPI
    11 reserved
 13    reserved
 12    device present (non-ATAPI)
 12-8    ATAPI device type (see #P669)
 7    device is removable
 6-5    CMD DMA Request type
    00 microprocessor DRQ
    01 interrupt DRQ
    10 accelerated DRQ
    11 reserved
 4-2    reserved
 1-0    CMD packet size (00 = 12 bytes, 01 = 16 bytes)
SeeAlso: #P165

(Table P669)
Values for ATAPI device type:
 00h    direct-access device (i.e. disk drive)
 01h    sequential-access device (i.e. tape drive)
 02h    printer
 03h    processor
 04h    write-once device
 05h    CD-ROM
 06h    scanner
 07h    optical memory
 08h    medium changer
 09h    communications device
 0Ah    reserved for ACS IT8
 0Bh    reserved for ACS IT8
 0Ch    array controller device (i.e. RAID)
 0Dh-1Eh reserved
 1Fh    unknown type or no device
SeeAlso: #P166

(Table P167)
Values for Self-Monitoring, Analysis, Reporting Technology (SMART) subcommand:
 D0h    Read Attribute Values (optional) (see #P169)
    results returned in 512-byte sector read from controller
 D1h    Read Attribute Thresholds (optional) (see #P168)
    results returned in 512-byte sector read from controller
 D2h    Disable Attribute Autosave (optional)
    sector-count register set to 0000h
 D2h    Enable Attribute Autosave
    sector-count register set to 00F1h
 D3h    Save Attribute Values (optional)
 D4h    execute off-line tests immediately (optional)
 D5h-D6h reserved
 D7h    vendor-specific
 D8h    Enable SMART Operations
 D9h    Disable SMART Operations
 DAh    Return SMART Status
    if any threshold(s) exceeded, CylinderLow set to F4h and CylinderHigh
      set to 2Ch
 DBh    Enable/Disable Automatic Off-Line Data Collection
    sector-count register set to 0000h to disable, 00F8h to enable
 DCh-DFh reserved
 E0h-EFh vendor-specific
Note:    to access SMART commands, the Cylinder Low register must be set to
      004Fh and the Cylinder High register must be set to 00C2h before
      invoking the SMART command with the SMART command number in the
      Features register
SeeAlso: #P156

Format of S.M.A.R.T. attribute thresholds sector:
Offset    Size    Description    (Table P168)
 00h    WORD    data structure revision number (0005h for SMART Revision 2.0)
 02h 12 BYTEs    attribute threshold data 1 (see #P171)
 ...
14Eh 12 BYTEs    attribute threshold data 30 (see #P171)
16Ah 18 BYTEs    reserved (0)
17Ch 131 BYTEs    vendor-specific
1FFh    BYTE    checksum (two's complement of eight-bit sum of first 511 bytes)
Note:    if the drive provides fewer than 30 attributes, all remaining attribute
      records are filled with NUL (00h) bytes
SeeAlso: #P167,#P169

Format of S.M.A.R.T. attribute values sector:
Offset    Size    Description    (Table P169)
 00h    WORD
 02h 12 BYTEs    attribute value data 1 (see #P172)
 ...
14Eh 12 BYTEs    attribute value data 30 (see #P172)
16Ah    BYTE    off-line data collection status (see #P173)
16Bh    BYTE    vendor-specific
16Ch    WORD    time to complete off-line data collection, in seconds
        0001h-FFFFh
16Eh    BYTE    vendor-sepcific
16Fh    BYTE    off-line data collection capability (see #P174)
170h    WORD    S.M.A.R.T. capabilities (see #P170)
172h 16 BYTEs    reserved (0)
182h 125 BYTEs    vendor-specific
1FFh    BYTE    checksum (two's complement of eight-bit sum of first 511 bytes)
Note:    if the drive provides fewer than 30 attributes, all remaining attribute
      records are filled with NUL (00h) bytes
SeeAlso: #P167,#P168

Bitfields for S.M.A.R.T capabilities:
Bit(s)    Description    (Table P170)
 0    attributes saved on going into power-saving mode
 1    Enable/Disable Attribute Autosave subcommands are supported
 2-15    reserved
SeeAlso: #P169

Format of S.M.A.R.T. attribute threshold:
Offset    Size    Description    (Table P171)
 00h    BYTE    attribute ID (01h-FFh)
 01h    BYTE    attribute threshold
        00h always passing
        01h minimum threshold value
        FDh maximum threshold value
        FEh invalid (do not use)
        FFh always failing (for testing)
 02h 10 BYTEs    reserved (0)
Note:    the attribute ID and actual threshold values are vendor-specific
SeeAlso: #P168,#P172

Format of S.M.A.R.T attribute value:
Offset    Size    Description    (Table P172)
 00h    BYTE    attribute ID (01h-FFh)
 01h    WORD    status flags
        bit 0: pre-failure/advisory
            =0 value < threshold indicates usage/age exceeding
                  design life
            =1 value < threshold indicates pre-failure condition
        bit 1: on-line data collection
        bits 2-5 vendor-specific
        bits 6-15 reserved
 03h    BYTE    attribute value (01h-FDh)
        initial value prior to data collection is 64h
 04h  8 BYTEs    vendor-specific
SeeAlso: #P169,#P171

(Table P173)
Values for S.M.A.R.T. off-line data collection status:
 00h    off-line collection never started
 01h    reserved
 02h    off-line data collection completed successfully
 03h    reserved
 04h    off-line data collection suspended by command from host
 05h    off-line data collection aborted by command from host
 06h    off-line data collection aborted due to fatal error
 07h-3Fh reserved
 40h-7Fh vendor-specific
 80h    off-line collection never started (auto-offline feature enabled)
 81h    reserved
 82h    off-line data collection completed successfully (auto-offline feature
      enabled)
 83h    reserved
 84h    off-line data collection suspended by command from host (auto-offline
      feature enabled)
 85h    off-line data collection aborted by command from host (auto-offline
      feature enabled)
 86h    off-line data collection aborted due to fatal error (auto-offline
      feature enabled)
 87h-BFh reserved
 C0h-FFh vendor-specific
SeeAlso: #P169,#P174

Bitfields for S.M.A.R.T. off-line data collection capabilities:
Bit(s)    Description    (Table P174)
 0    Execute Off-Line Immediate (D4h) subcommand is implemented
 1    Enable/Disable Automatic Off-Line subcommand is implemented
 2    abort/resume on interrupting command
    =0 off-line resumes automatically after an interrupting command
    =1 off-line collection is aborted by an interrupting command
 3-7    reserved
SeeAlso: #P167

(Table P175)
Values for Feature Code:
 01h    [opt] 8-bit instead of 16-bit data transfers
 02h    [opt] enable write cache
 03h          set transfer mode as specified by Sector Count register
 04h    [opt] enable all automatic defect reassignment
 22h    [opt] Write Same, user-specified area
 33h    [opt] disable retries
 44h          specify length of ECC bytes used by Read Long and Write Long
 54h    [opt] set cache segments (value in Sector Count register)
 55h          disable look-ahead
 66h          disable reverting to power-on defaults
 77h    [opt] disable ECC
 81h    [opt] 16-bit instead of 8-bit data transfers
 82h    [opt] disable write cache
 84h    [opt] disable all automatic defect reassignment
 88h    [opt] enable ECC
 99h    [opt] enable retries
 9Ah    [opt] set device maximum average current
 AAh          enable look-ahead
 ABh    [opt] set maximum prefecth (value in Sector Count register)
 BBh          use four bytes of ECC on Read Long and Write Long (for compat.)
 CCh          enable reverting to power-on defaults
 DDh    [opt] Write Same, entire disk
SeeAlso: #0198
----------P01F8------------------------------
PORT 01F8 - ???

01F8  RW  ???
        bit 0: A20 gate control (set = A20 enabled, clear = disabled)
----------P01F901FF--------------------------
PORT 01F9-01FF - PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
--------d-P0200------------------------------
PORT 0200 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0300h"Digidesign"
----------P0200020F--------------------------
PORT 0200-020F - Game port reserved I/O address space
0200-0207 - Game port, eight identical addresses on some boards

0201  R-  read joystick position and status (see #P176)
0201  -W  fire joystick's four one-shots
0201  RW  gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible,
        Covox 'voice master' & 'speech thing' compatible soundcard.
        (enabled if bit1=1 in PORT 038Fh. Because it is disabled on
        power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh)

Bitfields for joystick position and status:
Bit(s)    Description    (Table P176)
 7    status B joystick button 2 / D paddle button
 6    status B joystick button 1 / C paddle button
 5    status A joystick button 2 / B paddle button
 4    status A joystick button 1 / A paddle button
 3    B joystick Y coordinate       / D paddle coordinate
 2    B joystick X coordinate       / C paddle coordinate
 1    A joystick Y coordinate       / B paddle coordinate
 0    A joystick X coordinate       / A paddle coordinate
----------P020002FF--------------------------
PORT 0200-02FF - Sunshine uPW48, programmer for EPROM version CPU's 8748/8749
Range:    4 bit DIP switch installable in the range 20x-2Fx

0200-0203    adresses of the 8255 on the uPW48
0208-020B    adresses of ??? on the uPW48 (all showing zeros)
----------P02080209--------------------------
PORT 0208-0209 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8
----------P0208020A--------------------------
PORT 0208-020A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS
Range:    PORT 0208h or PORT 0218h, depending on configuration register 4Fh
      (see #P459)
SeeAlso: PORT 0022h"82C235"

0208  RW  EMS page register
0209  RW  EMS page register
020A  RW  EMS page register
----------P020C020F--------------------------
PORT 020C-020F - AIMS LAB PC Radio
Range:    configurable to PORT 020Ch or PORT 030Ch
Notes:    writing a value with bit 3 set to one of these ports turns on the
      radio; writing a value with bit 3 clear turns it off
    PORT 020Eh bits 1 indicates status of some kind
----------P02100217--------------------------
PORT 0210-0217 - Expansion unit (XT)

0210  -W  latch expansion bus data
0210  R-  verify expansion bus data
0211  -W  clear wait, test latch
0211  R-  High byte data address
0212  R-  Low byte data address
0213  -W  0=enable,  1=disable expansion unit
0214  -W  latch data  (receiver card port)
0214  R-  read data   (receiver card port)
0215  R-  High byte of address, then Low byte    (receiver card port)
----------P02100211--------------------------
PORT 0210-0211 - Game Blaster
Range:    PORT 02x0h-02x1h, x=1,2,...

0210  -W  register index
0211  ?W  register data
----------P02180219--------------------------
PORT 0218-0219 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P0208020A--------------------------
PORT 0218-021A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS
Range:    PORT 0208h or PORT 0218h, depending on configuration register 4Fh
      (see #P459)
SeeAlso: PORT 0022h"82C235"

0218  RW  EMS page register
0219  RW  EMS page register
021A  RW  EMS page register
----------P02200223--------------------------
PORT 0220-0223 - Sound Blaster / Adlib port (Stereo)
SeeAlso: PORT 0388h-0389h

0220  R-  Left speaker -- Status port
0220  -W  Left speaker -- Address port
0221  -W  Left speaker -- Data port
0222  R-  Right speaker -- Status port
0222  -W  Right speaker -- Address port
0223  -W  Right speaker -- Data port
----------P02200227--------------------------
PORT 0220-0227 - Soundblaster PRO and SSB 16 ASP
----------P02200228--------------------------
PORT 0220-0228 - C&T 82C570 CHIPSlink '3270' Protocol Controller
!!!chips\82c570.pdf p.7
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 2.0
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 4.0
Note:    the FM music is accessible on 0388/0389 for compatibility.

0220  R-  left FM status port
0220  -W  left FM music register address port (index)
0221  RW  left FM music data port
0222  R-  right FM status port
0222  -W  right FM music register address port (index)
0223  RW  right FM music data port
0224  -W  mixer register address port (index) (see #P667)
0225  RW  mixer data port
0226  -W  DSP reset
0228  R-  FM music status port
0228  -W  FM music register address port (index)
0229  -W  FM music data port
022A  R-  DSP read data (voice I/O and Midi)
022C  -W  DSP write data / write command
022C  R-  DSP write buffer status (bit 7)
022E  R-  DSP data available status (bit 7)

(Table P667)
Values for SB Mixer register index:
 Index    Description        PORT 0225h data
 00h    reset            00h = zero all mixer controls
 04h    voice select        high nybble = left, low nybble = right
 0Ah    microphone gain        bits 2-0 = gain
 22h    master gain        high nybble = left, low nybble = right
 26h    MIDI gain        high nybble = left, low nybble = right
 28h    CD gain            high nybble = left, low nybble = right
 2Eh    Line In            high nybble = left, low nybble = right
 30h    Master Left        bits 7-3 = volume
 31h    Master Right        bits 7-3 = volume
 32h    Voice Left        bits 7-3 = volume
 33h    Voice Right        bits 7-3 = volume
 34h    MIDI Left        bits 7-3 = volume
 35h    MIDI Right        bits 7-3 = volume
 36h    CD Left            bits 7-3 = volume
 37h    CD Right        bits 7-3 = volume
 38h    LineIn Left        bits 7-3 = volume
 39h    LineIn Right        bits 7-3 = volume
 3Ah    Microphone        bits 7-3 = gain
 3Bh    PC speaker        bits 7-3 = volume
 3Ch    Sound Output        highest set bit is enabled source (see #P668)
 3Dh    Sound Source (left)    highest set bit is enabled source (see #P668)
 3Eh    Sound Source (right)    highest set bit is enabled source (see #P668)
 40h    In gain            bits 7-6 = gain
                   (00 = x1, 01 = x2, 10 = x4, 11 = x8)
 41h    Out gain (left)        bits 7-6 = gain (as for In)
 42h    Out gain (right)    bits 7-6 = gain (as for In)
 43h    Automatic Gain Control    bit 0 = enable
 44h    Treble (left)        bits 7-3 = volume
 45h    Treble (right)        bits 7-3 = volume
 46h    Bass (left)        bits 7-3 = volume
 47h    Bass (right)        bits 7-3 = volume

Bitfields for SB Mixer sound source:
Bit(s)    Description    (Table P668)
 7    PC speaker???
 6    MIDI left
 5    MIDI right
 4    LineIn left
 3    LineIn right
 2    CD left
 1    CD right
 0    microphone
Note:    bits 7-5 are ignored for Sound Output register
SeeAlso: #P667
----------P022B------------------------------
PORT 022B - GI1904 Scanner Interface Adapter
Range:    PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
----------P022C------------------------------
PORT 022C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P022F------------------------------
PORT 022F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    An Adlib-compatible Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine"

022F  RW  Covox compatible speech I/O  (via internal A/D converter,
        each read access starts a new conversion cycle)
        register enabled if bit7=1 in PORT 038Fh
----------P02300233--------------------------
PORT 0230-0233 - Adaptec 154xB/154xC SCSI adapter.
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P02340237--------------------------
PORT 0234-0237 - Adaptec 154xB/154xC SCSI adapter.
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P0238023F--------------------------
PORT 0238-023F - COM port addresses on UniRAM card by German magazine c't
        selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
----------P0238023x--------------------------
PORT 0238-023B - Bus Mouse Port (secondary address)
Note:    secondary address for bus mice from MS and Logitech, and the ATI
      video adapter mouse
SeeAlso: PORT 023Ch"Mouse"
----------P023C023x--------------------------
PORT 023C-023F - Bus Mouse Port (primary address)
Note:    primary address for bus mice from MS and Logitech, the ATI video
      adapter mouse, and the Commodore PC30III bus mouse
SeeAlso: PORT 0238h"Mouse"
----------P0240024F--------------------------
PORT 0240-024F - Gravis Ultra Sound by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
SeeAlso: PORT 0340h-034Fh,PORT 0746h

0240  -W  Mix Control register (see #P177)
0241  R-  Read Data
0241  -W  Trigger Timer
0246  R-  IRQ Status Register (see #P178)
0248  RW  Timer Control Reg
      Same as ADLIB Board (see PORT 0200h)
0249  -W  Timer Data (see #P179)
024B  -W  IRQ Control Register (0240 bit 6 = 1) (see #P180)
024B  -W  DMA Control Register (0240 bit 6 = 0) (see #P181)
024F  RW  Register Controls (rev 3.4+)

Bitfields for Gravis Ultra Sound mix control register:
Bit(s)    Description    (Table P177)
 6       Control Register Select (see 024B)
 5       Enable MIDI Loopback
 4       Combine GF1 IRQ with MIDI IRQ
 3       Enable Latches
 2       Enable MIC IN
 1       Disable LINE OUT
 0       Disable LINE IN
SeeAlso: #P178

Bitfields for Gravis Ultra Sound IRQ status register:
Bit(s)    Description    (Table P178)
 7       DMA TC IRQ
 6       Volume Ramp IRQ
 5       WaveTable IRQ
 3       Timer 2 IRQ
 2       Timer 1 IRQ
 1       MIDI Receive IRQ
 0       MIDI Transmit IRQ
SeeAlso: #P177,#P180,#P181

Bitfields for Gravis Ultra Sound timer data:
Bit(s)    Description    (Table P179)
 7       Reset Timr IRQ
 6       Mask Timer 1
 5       Mask Timer 2
 1       Timer 2 Start
 0       Timer 1 Start
SeeAlso: #P178,#P180

Bitfields for Gravis Ultra Sound IRQ control register:
Bit(s)    Description    (Table P180)
 6    Combine Both IRQ
 5-3    MIDI IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
 2-0    GF1 IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
SeeAlso: #P178,#P181

Bitfields for Gravis Ultra Sound DMA Control Register:
Bit(s)    Description    (Table P181)
 6    Combine Both DMA
 5-3    DMA Select Register 2
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
 2-0    DMA Select Register 1
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
SeeAlso: #P178,#P180,#P221
----------P02400257--------------------------
PORT 0240-0257 - RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
----------P02580259--------------------------
PORT 0258-0259 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02580259--------------------------
PORT 0258-0259 - AT RAMBANK Memory Expansion Board - EXT MEMORY AND EMS-SUPPORT
Range:    base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h,
      or 02A8h
----------P0258025F--------------------------
PORT 0258-025F - Intel Above Board
----------P02600268--------------------------
PORT 0260-0268    -  LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02680269--------------------------
PORT 0268-0269 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P026B------------------------------
PORT 026B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
----------P026C------------------------------
PORT 026C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P026E026F--------------------------
PORT 026E-026F - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 0398h

026E  -W  index for data port
026F  RW  EPP command data
----------P03980399--------------------------
PORT 026E-026F - Intel 82091AA Advanced Integrated Peripheral
Range:    PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
      PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 0024h"82091AA",PORT 0398h"82091AA"

026E  ?W  configuration register index
026F  RW  configuration register data
----------P0278------------------------------
PORT 0278 - Covox 'Speech Thing' COMPATIBLES
SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine"

0278  -W  speech data output via printer data port
        (with mc-soundmachine, enabled if bit5=1 in 38F)
----------P0278027A--------------------------
PORT 0278-027A - PARALLEL PRINTER PORT (usually LPT1, sometimes LPT2)
Range:    usually PORT 03BCh, PORT 0278h, or PORT 0378h
SeeAlso: PORT 0278h"EPP",MEM 0040h:0008h,INT 17/AH=00h

0278  -W  data port
0279  R-  status port (see #P263 at PORT 03BCh)
027A  RW  control port (see #P264 at PORT 03BCh)
----------P0278027F--------------------------
PORT 0278-027F - Intel 82360SL/82091AA - EPP-mode PARALLEL PORT
Range:    PORT 0278h or PORT 0378h
SeeAlso: PORT 0278h"LPT1",PORT 0678h"ECP"

0278-027A    as for standard parallel port
027B  RW  address strobe
027C  RW  data strobe 0
027D  RW  data strobe 1
027E  RW  data strobe 2
027F  RW  data strobe 3
----------P0279------------------------------
PORT 0279 - Plug-and-Play - CONFIGURATION REGISTER
SeeAlso: PORT 0A79h

0279  -W  index into Plug-and-Play register set for Read Data Port and
      Write Data Port I/O (see #P182,#P183)

(Table P182)
Values for Plug-and-Play Card-Level Registers:
 00h    set Read Port address
    bits 9-2 of Read Data port address (bits 15-10 are always 0, bits 1-0
      are always 11); valid Read Port addresses are 0203h-03FFh
 01h    serial isolation
 02h    configuration control
 03h    Wake command
    (specifies which card is accessed through configuration registers)
 04h    resource data
 05h    status
 06h    Card Select Number (CSN)
 07h    logical device number
    (selects which logical device on card is accessed at locations 30h-FFh)
    (see #P183)
 08h-1Fh reserved
 20h-2Fh vendor-specific
Note:    there is one set of these registers per installed card
SeeAlso: #P183

(Table P183)
Values for Plug-and-Play Logical Device Registers:
 30h    activate
    bit 0: device is active on ISA bus
    bits 7-1: reserved (0)
 31h    I/O range check
    bit 0: I/O Read Pattern select (if bit 1 set, then I/O reads return
        55h if this bit is set, AAh if this bit is clear)
    bit 1: I/O Range Check Enable: if set, all reads from device I/O
          registers return 55h or AAh, depending on bit 0
    bits 7-2: reserved (0)
 32h-37h reserved
 38h-3Fh vendor-specific
 40h-44h 24-bit ISA memory descriptor 0
 45h-47h reserved
 48h-4Ch 24-bit ISA memory descriptor 1
 4Dh-4Fh reserved
 50h-54h 24-bit ISA memory descriptor 2
 55h-57h reserved
 58h-5Ch 24-bit ISA memory descriptor 3
 5Dh-5Fh reserved
 60h-6Fh I/O configuration registers 0-7
 70h-71h IRQ channel select 0
 72h-73h IRQ channel select 1
 74h-75h DMA configuration registers 0-1
 76h-7Eh 32-bit memory range configuration register 0
 7Fh     reserved
 80h-88h 32-bit memory range configuration register 1
 89h-8Fh reserved
 90h-98h 32-bit memory range configuration register 2
 99h-9Fh reserved
 A0h-A8h 32-bit memory range configuration register 3
 A9h-EFh reserved for logical device configuration
 F0h-FEh vendor-specific
 FFh    reserved
Note:    there is one set of these registers per logical device
SeeAlso: #P182
----------P0280------------------------------
PORT 0280 - LCD display on Wyse 2108 PC
----------P02800288--------------------------
PORT 0280-0288    - non-standard COM port addresses (V20-XT by German magazine c't)
        selectable from 0280, 0288, 0290, 0298, 6A0, 6A8
--------s-P02800283--------------------------
PORT 0280-0283 - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
----------P0288028F--------------------------
PORT 0288-028F    - non-standard COM port addresses (V20-XT by German magazine c't)
0280-0288    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
0290-0298
0298-029F
--------s-P02840287--------------------------
PORT 0284-0287 - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
--------s-P0288028F--------------------------
PORT 0288-028F - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
--------s-P028C028F--------------------------
PORT 028C-028F - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
----------P02A002A7--------------------------
PORT 02A0-02A7 - Sunshine EW-901BN, EW-904BN
        EPROM writer card (release 1986) for EPROMs up to 27512
02A0-02A3    adresses of the 8255 on the EW-90xBN
----------P02A202A3--------------------------
PORT 02A2-02A3 - MSM58321RS clock
----------P02A802A9--------------------------
PORT 02A8-02A9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02AB------------------------------
PORT 02AB - GI1904 Scanner Interface Adapter (default)
Range:    PORT 022Bh, PORT 026Bh, PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:    PORT 03ABh, PORT 03EBh
Note:    the GI1904 is used by many SPI 400/800dpi gray/halftone/color handy
      scanners by Marstek, Mustek, Conrad, Völkner and others
----------P02AC------------------------------
PORT 02AC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P02B002BF--------------------------
PORT 02B0-02BF - Trantor SCSI adapter
----------P02B002DF--------------------------
PORT 02B0-02DF - alternate EGA,    primary EGA at 03C0
----------P02B802B9--------------------------
PORT 02B8-02B9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02C002Cx--------------------------
PORT 02C0-02Cx - AST-clock
----------P02C002DF--------------------------
PORT 02C0-02DF - XT-Real Time Clock 2 (default jumpered address)
---------------------------------------------
PORT 02C0-02CF - EGA (2nd adapter)
SeeAlso: PORT 03C0h
--------V-P03C603C9--------------------------
PORT 02C6-02C9 - VGA/MCGA - DAC REGISTERS (alternate address)
Range:    PORT 03C6h or PORT 02C6h (alternate)
SeeAlso: PORT 03C6h
----------P02D002DA--------------------------
PORT 02D0-02DA - C&T 82C570 CHIPSlink '3270' Protocol Controller
!!!chips\82c570.pdf p.12
----------P02E002E8--------------------------
PORT 02E0-02E8 - LPT port address on the UniRAM card by German magazine c't
Range:    base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8.
----------P02E002EF--------------------------
PORT 02E0-02EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)
        (GAB 0 on XT)
02E1  ??  GPIB (adapter 0)
02E2
02E3
----------P02E002EF--------------------------
PORT 02E0-02EF - data aquisition     (AT)

02E2  ??  data aquisition (adapter 0)
02E3  ??  data aquisition (adapter 0)
----------P02E8------------------------------
PORT 02E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P02E802E9--------------------------
PORT 02E8-02E9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02E802EF--------------------------
PORT 02E8-02EF - serial port, same as 02F8, 03E8 and 03F8 (COM4)
----------P02E802EF--------------------------
PORT 02E8-02EF - 8514/A and compatible (e.g. ATI Graphics Ultra)

02E8  R-  display status
02E8  -W  horizontal total
02EA  RW  Lookup: DAC mask
02EB  -W  Lookup: DAC read index
02EC  -W  Lookup: DAC write index
02ED  RW  Lookup: DAC data
----------P02EA------------------------------
PORT 02EA - S3 86C928 video controller (ELSA Winner 1000)
----------P02EB------------------------------
PORT 02EB - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 032Bh, PORT 036Bh,
      PORT 03ABh, PORT 03EBh
----------P02EC------------------------------
PORT 02EC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P02F002F8--------------------------
PORT 02F0-02F8 - LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02F802FF--------------------------
PORT 02F8-02FF - serial port, same as 02E8, 03E8 and 03F8 (COM2)

02F8  -W  transmitter holding register
02F8  R-  receiver buffer register
02F8  RW  divisor latch, low byte    when DLAB=1
02F9  RW  divisor latch, high byte    when DLAB=1
02F9  RW  interrupt enable register when DLAB=0
02FA  R-  interrupt identification register
02FB  RW  line control register
02FC  RW  modem control register
02FD  R-  line status register
02FF  RW  scratch register
----------P0300------------------------------
PORT 0300 - Award POST Diagnostic
SeeAlso: PORT 0080h
--------d-P0300------------------------------
PORT 0300 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0200h"Digidesign"
--------s-P03000301--------------------------
PORT 0300-0301 - MPU-401 MIDI UART
Range:    alternate address at PORT 0330h, occasionally at PORT 0310h or
      PORT 0320h
----------P03000301--------------------------
PORT 0300-0301 - Soundblaster 16 ASP MPU-Midi EMULATION
----------P0300????--------------------------
PORT 0300-???? - HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142)
----------P03000303--------------------------
PORT 0300-0303 - Panasonic 52x CD-ROM SCSI Miniport
Range:    PORT 0300h-0303h,PORT 0320h-0323h,PORT 0340h-0343h,PORT 0360h-0363h,
      and PORT 0380h-0383h
----------P0300030F--------------------------
PORT 0300-030F - Philips CD-ROM player CM50
----------P0300030F--------------------------
PORT 0300-030F - CompaQ Tape drive adapter. alternate address at 0100
--------N-P0300031F--------------------------
PORT 0300-031F - 3com Ethernet adapters (default address)
--------N-P0300031F--------------------------
PORT 0300-031F - NE2000 compatible Ethernet adapters
Range:    may be placed at 0300h, 0320h, 0340h, or 0360h
SeeAlso: PORT 0300h"PCnet"
--------N-P0300031F--------------------------
PORT 0300-031F - AMD PCnet - NE2100-compatible Ethernet adapters
Range:    may be placed at 0300h, 0320h, 0340h, or 0360h, with the card's ROM
      appearing at segment C800h, CC00h, D000h, or D400h, respectively
Note:    for the PCnet-FAST chip, the I/O address may be read from the PCI
      configuration space at offset 10h (see #0798 at INT 1A/AX=B10Ah)
SeeAlso: PORT 0300h"NE2000",#0798

0300-030F  R-  address PROM (used to store Ethernet address, etc.)
0310w RW  Register Data Port (RDP) (see #P184,#P185)
0312w ?W  Register Access Port (RAP) (selects register index for RDP and IDP)
      (see #P202)
0314w ?W  Reset
0316w RW  ISA Bus Data Port (IDP)
0318w      reserved for vendor-specific use
031A-031F      reserved

(Table P184)
Values for AMD PCnet-ISA Register Data Port index:
 00h    "CSR0" status and control flags (see #P186)
 01h    "CSR1" low half of IADR (appears at PORT 0316h)
 02h    "CSR2" high half of IADR (appears at PORT 0317h)
 03h    "CSR3" interrupt masks (see #P187)
 04h    "CSR4" interrupt masks and status bits (see #P188)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh    "CSR15" mode (see #P192)
 4Ch    "CSR76" receive descriptor ring length
 4Eh    "CSR78" transmit descriptor ring length
 50h    "CSR80" FIFO threshold / DMA burst control (see #P196)
 52h    "CSR82" DMA bus timer
 58h    "CSR88" chip ID
 70h    "CSR112" number of missed packets
 72h    "CSR114" number of receive collisions
 7Ch    "CSR124" BMU test register
        bit 4: accept runt packets
SeeAlso: #P202,#P185

(Table P185)
Values for AMD PCnet-SCSI/PCnet-FAST Register Data Port index:
 00h    "CSR0" status and control flags (see #P186)
 01h    "CSR1" low half of IADR (appears at PORT 0316h)
 02h    "CSR2" high half of IADR (appears at PORT 0317h)
 03h    "CSR3" interrupt masks (see #P187)
 04h    "CSR4" interrupt masks and status bits (see #P188)
 05h    "CSR5" (PCnet-FAST) extended control and interrupt 1 (see #P189)
 06h    "CSR6" receive/transmit descriptor table lengths (see #P190)
 07h    "CSR7" (PCnet-FAST) extended control and interrupt 2 (see #P191)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh    "CSR15" mode (see #P192)
 10h    "CSR16"    alias of CSR1
 11h    "CSR17"    alias of CSR2
 12h    "CSR18" low half of current receive buffer address
 13h    "CSR19" high half of current receive buffer address
 14h    "CSR20" low half of current transmit buffer address
 15h    "CSR21" high half of current transmit buffer address
 16h    "CSR22" low half of next receive buffer address
 17h    "CSR23" high half of next receive buffer address
 18h    "CSR24" low half of receive-ring base address
 19h    "CSR25" high half of receive-ring base address
 1Ah    "CSR26" low half of next receive descriptor address
 1Bh    "CSR27" high half of next receive descriptor address
 1Ch    "CSR28" low half of current receive descriptor address
 1Dh    "CSR29" high half of current receive descriptor address
 1Eh    "CSR30" low half of transmit ring base address
 1Fh    "CSR31" high half of transmit ring base address
 20h    "CSR32" low half of next transmit descriptor address
 21h    "CSR33" high half of next transmit descriptor address
 22h    "CSR34" low half of current transmit descriptor address
 23h    "CSR35" high half of current transmit descriptor address
 24h    "CSR36" low half of next next receive descriptor address
 25h    "CSR37" high half of next next receive descriptor address
 26h    "CSR38" low half of next next transmit descriptor address
 27h    "CSR39" high half of next next transmit descriptor address
 28h    "CSR40" current receive byte count (see #P193)
 29h    "CSR41" current receive status
 2Ah    "CSR42" current transmit byte count (see #P194)
 2Bh    "CSR43" current transmit status
 2Ch    "CSR44" next receive byte count (bits 11-0; bits 15-12=0)
 2Dh    "CSR45" next receive status
 2Eh    "CSR46" transmit poll time counter
 2Fh    "CSR47" transmit polling interval
 30h    "CSR48" receive poll time counter
 31h    "CSR49" receive polling interval
 32h-39h reserved
 3Ah    "CSR58" software style (see #P195)
 3Bh    reserved
 3Ch    "CSR60" previous transmit descriptor address (low)
 3Dh    "CSR61" previous transmit descriptor address (high)
 3Eh    "CSR62" previous transmit byte count (bits 11-0; bits 15-12=0)
 3Fh    "CSR63" previous transmit status
 40h    "CSR64" next transmit buffer address (low)
 41h    "CSR65" next transmit buffer address (high)
 42h    "CSR66" next transmit byte count (bits 11-0; bits 15-12=0)
 43h    "CSR67" next transmit status
 44h-47h reserved
 48h    "CSR72" receive ring counter
 49h    reserved
 4Ah    "CSR74" transmit ring counter
 4Bh    reserved
 4Ch    "CSR76" receive descriptor ring length
 4Dh    reserved
 4Eh    "CSR78" transmit descriptor ring length
 4Fh    reserved
 50h    "CSR80" FIFO threshold / DMA burst control (see #P196)
 51h    reserved
 52h    "CSR82" (PCnet-SCSI) DMA bus timer
        (PCnet-FAST) transmit descriptor address (low)
 53h    reserved
 54h    "CSR84" DMA address register (low)
 55h    "CSR85" DMA address register (high)
 56h    "CSR86" buffer byte counter (bits 11-0; bits 15-12=0)
 57h    reserved
 58h    "CSR88" chip ID (low 16 bits) (see #P197)
 59h    "CSR89" chip ID (high 16 bits) (see #P197)
 5Ah    "CSR90" (PCnet-SCSI)
 5Bh    reserved
 5Ch    "CSR92" ring length conversion
 5Dh    reserved
 5Eh    "CSR94" (PCnet-SCSI)
 5Fh-63h reserved
 64h    "CSR100" bus timeout
 65h-6Fh reserved
 70h    "CSR112" number of missed packets
 71h    reserved
 72h    "CSR114" number of receive collisions
 73h-79h reserved
 7Ah    "CSR122" advanced feature control (see #P198)
 7Bh    reserved
 7Ch    "CSR124" BMU test register (see #P199)
 7Dh    "CSR125" (PCnet-FAST) MAC Enhanced Configuration Control (see #P200)
 7Eh-7Fh reserved
SeeAlso: #P184,#P224

Bitfields for AMD PCnet CSR0 status and control flags:
Bit(s)    Description    (Table P186)
 15    "ERR"    error; set if BABL, CERR, MISS, or MESS set
 14    "BABL"    network babbling control
 13    "CERR"    collision error
 12    "MISS"    missed frame
 11    "MERR"    memory error
 10    "RINT"    receive interrupt
 9    "TINT"    transmit interrupt
 8    "IDON"    initialization done
 7    "INTR"    interrupt flag
 6    "IENA"    interrupt enable
 5    "RXON"    recieve ON
 4    "TXON"    transmit ON
 3    "TDMD"    transmit demand
 2    "STOP"    stop -- disable all external activity
 1    "STRT"    start -- enable extrnal activity
 0    "INIT"    begin initialization procedure
SeeAlso: #P184,#P187

Bitfields for AMD PCnet CSR3 interrupt masks:
Bit(s)    Description    (Table P187)
 15    reserved
 14    "BABLM"    disable babble interrupt
 13    reserved
 12    "MISSM" disable missed-frame interrupt
 11    "MERM"    disable memory-error interrupt
 10    "RINTM"    disable receive interrupt
 9    "TINTM" disable transmit interrupt
 8    "IDONM" disable initialization-done interrupt
 7-5    reserved
 4    "DXMT2PD" disable Transmit Two Part Deferral
 3    "EMBA"    enable modified back-off algorithm
 2-0    reserved
Note:    other bits are reserved
SeeAlso: #P184,#P186,#P188

Bitfields for AMD PCnet CSR4 interrupt masks and status bits:
Bit(s)    Description    (Table P188)
 15    "ENTST"       enable Test Mode / CSR124 access
 14    "DMAPLUS"  disable CSR80 burst transaction counter
 13    "TIMER"       enable Bus Timer register
 12    "DPOLL"       disable transmit polling
 11    "APADXMT"  Auto-Pad Transmit
 10    "ASTRPRCV" enable automatic pad stripping
 9    "MFCO"       missed frame counter has overflowed
 8    "MFCOM"       disable interrupt on MFCO
 7    "UINTCMD"  (PCnet-FAST) user interrupt command
 6    "UINT"       (PCnet-FAST) user interrupt pending
            write 1 to clear
 5    "RCVCCO"   receive collision counter has overflowed
 4    "RCVCCOM"  disable interrupt on RCVCCO
 3    "TXSTRT"   Transmit Start
 2    "TXSTRTM"  disable interrupt on TXSTRT
 1    "JAB"       Jabber error
 0    "JABM"       disable interrupt on JAB
SeeAlso: #P184,#P187,#P185

Bitfields for AMD PCnet-FAST CSR5 extended control and interrupt 1:
Bit(s)    Description    (Table P189)
 31-16    reserved
 15    "TOKINTD"  disable Transmit OK interrupt
 14    "LTINTEN"  enable Last Transmit interrupt
 13-12    reserved
 11    "SINT"       System Interrupt (write 1 to clear)
 10    "SINTE"       enable System Interrupt
 9    "SLPINT"   Sleep Interrupt (write 1 to clear)
 8    "SLPINTE"  enable Sleep Interrupt
 7    "EXDINT"   Excessive Deferral Interrupt (write 1 to clear)
 6    "EXDINTE"  enable Excessive Deferral Interrupt
 5    "MPPLBA"   Magic Packet Physical Logical Broadcast Accept
 4    "MPINT"       Magic Packet Interrupt (write 1 to clear)
 3    "MPINTE"   enable Magic Packet Interrupt
 2    "MPEN"       enable Magic Packet mode
 1    "MPMODE"   Magic Packet mode active
 0    "SPND"       Suspend
SeeAlso: #P185,#P188,#P191

Bitfields for AMD PCnet CSR6 Descriptor Table Length register:
Bit(s)    Description    (Table P190)
 15-12    transmit encoded ring length
 11-8    receive encoded ring length
 7-0    reserved
SeeAlso: #P185,#P189

Bitfields for AMD PCnet CSR7 Extended Control and Interrupt 2:
Bit(s)    Description    (Table P191)
 15    "FASTSPNDE"  enable Fast Suspend
 14    "RXFRTG"     Receive Frame Tag
 13    "RDMD"         Receive Demand
 12    "RXDPOL"     disable receive polling
 11    "STINT"         Software Timer Interrupt (write 1 to clear)
 10    "STINTE"     enable Software Timer Interrupt
 9    "MREINT"     MII Management Read Error Interrupt (write 1 to clear)
 8    "MREINTE"    enable MII Management Read Error Interrupt
 7    "MAPINT"     MII Management Auto-Poll Interrupt (write 1 to clear)
 6    "MAPINTE"    enable MII Management Auto-Poll Interrupt
 5    "MCCINT"     MII Management Command Complete Interrupt (write 1 to clr)
 4    "MCCINTE"    enable MII Management Command Complete Interrupt
 3    "MCCIINT"    MII Management Command Complete Internal Interrupt
            (write 1 to clear)
 2    "MCCIINTE"   enable MII Manamagement Command Complete Internal Int.
 1    "MIIPDTINT"  MII PHY Detect Transition Interrupt (write 1 to clear)
 0    "MIIPDTINTE" enable MII PHY Detect Transition Interrupt
SeeAlso: #P185,#P189

Bitfields for AMD PCnet CSR15 mode flags:
Bit(s)    Description    (Table P192)
 15    "PROM"       promiscuous mode
 14    "DRCVBC"   disable Receive Broadcast
 13    "DRCVPA"   disable Receive Physical Address
 12    "DLNKTST"  disable Link Status
 11    "DAPC"       disable Automatic Polarity Correction
 10    "MENDECL"  MENDEC loopback mode
 9    "LRT/TSEL" Low Receive Threshold
 8-7    "PORTSEL"  Port Select
        00  AUI
        01  10Base-T
        10  GPSI
        11  reserved
 6    "INTL"       internal loopback
 5    "DRTY"       disable retry
 4    "FCOLL"       force collision
 3    "DXMTFCS"  disable Transmit CRC
 2    "LOOP"       enable Loopback
 1    "DTX"       disable transmitter
 0    "DRX"       disable receiver
SeeAlso: #P184,#P188,#P196

Bitfields for AMD PCnet CSR40 Current Receive Byte Count register:
Bit(s)    Description    (Table P193)
 15-12    reserved (0)
 11-0    current receive byte count (copy of BCNT field of current receive
      descriptor's RMD1)
SeeAlso: #P185,#P194

Bitfields for AMD PCnet CSR42 Current Transmit Byte Count register:
Bit(s)    Description    (Table P194)
 15-12    reserved (0)
 11-0    current transmit byte count (copy of BCNT field of current receive
      descriptor's TMD1)
SeeAlso: #P185,#P193

Bitfields for AMD PCnet CSR58 Software Style register:
Bit(s)    Description    (Table P195)
 15-11    reserved (undefined)
 10    "APERREN"    enabled advanced parity error handling
 9    "CSRPCNET"    PCnet-ISA compatibility (read-only)
 8    "SSIZE32"    32-bit software structures for data blocks
 7-0    "SWSTYLE"    software style
        00h LANCE/PCnet-ISA (16-bit software structures)
        01h reserved
        02h PCnet-PCI (32-bit software)
        03h PCnet-PCI (32-bit software)
SeeAlso: #P185

Bitfields for AMD PCnet CSR80 FIFO threshold and DMA burst control:
Bit(s)    Description    (Table P196)
 15-14    reserved
 13-12    receive FIFO high-water mark; request DMA when N byte available
    00 = 16 bytes
    01 = 32 bytes
    10 = 64 bytes
 11-10    transmit starting point; start transmission after N bytes written
    00 = 4 bytes
    01 = 16 bytes
    10 = 64 bytes
    11 = 112 bytes
 9-8    transmit FIFO low-water mark; start DMA when room for N bytes
    00 = 8 bytes
    01 = 16 bytes
    10 = 32 bytes
 7-0    DMA burst register
SeeAlso: #P184,#P192

Bitfields for AMD PCnet Chip ID register (read-only):
Bit(s)    Description    (Table P197)
 31-28    hardware version
 27-12    part number
    2623h = Am79C971
 11-1    manufacturer ID (0001h = AMD)
 0    reserved (1)
SeeAlso: #P185

Bitfields for AMD PCnet CSR122 Advanced Feature Control register:
Bit(s)    Description    (Table P198)
 15-1    reserved
 0    "RCVALGN"    DWORD-align received packets
SeeAlso: #P185,#P199

Bitfields for AMD PCnet CSR124 Test Register 1:
Bit(s)    Description    (Table P199)
 15-5    reserved
 4    (PCnet-SCSI) accept runt packets
 3    (PCnet-FAST) accept runt packets
 2-0    reserved
SeeAlso: #P185,#P198

Bitfields for AMD PCnet-FAST CSR125 MAC Enhanced Configuration Control reg:
Bit(s)    Description    (Table P200)
 15-8    inter-packet gap (reducing from default 96 can disrupt network)
 7-0    inter-frame spacing, part 1
SeeAlso: #P185

(Table P201)
Values for AMD PCnet-ISA ISA Bus Configuration Register index:
 00h    "MSRDA" width of DMA read signal
 01h    "MSWRA" width of DMA write signal
 02h    "MC"    ISA bus configuration (see #P204)
 05h    "LED1"    LED1 signal control (see #P205)
 06h    "LED2"    LED2 signal control (see #P205)
 07h    "LED3"    LED3 signal control (see #P205)
SeeAlso: #P184,#P224,#P202

(Table P202)
Values for AMD PCnet-SCSI Bus Configuration Register index:
 00h    "MSRDA" width of DMA read signal (reserved)
 01h    "MSWRA" width of DMA write signal (reserved)
 02h    "MC"    miscellaneous configuration (see #P204)
 03h    reserved
 04h    "LINKST" link status
 05h    "LED1"    LED1 signal control (see #P205) -- receive status
 06h    "LED2"    LED2 signal control (see #P205)
 07h    "LED3"    LED3 signal control (see #P205) -- transmit status
 08h-0Fh reserved
 10h    "IOBASEL"
 11h    "IOBASEU"
 12h    "BSBC"    burst size and bus control
 13h    "EECAS" EEPROM Control and Status
 14h    "SWS"    software style
 15h    "INTCON" reserved
SeeAlso: #P185,#P201,#P203

(Table P203)
Values for AMD PCnet-FAST Bus Configuration Register index:
 00h    "MSRDA"        width of DMA read signal (reserved)
 01h    "MSWRA"        width of DMA write signal (reserved)
 02h    "MC"        miscellaneous configuration (see #P204)
 03h    reserved    !!!p.154
 04h    "LED0"    LED0 status
 05h    "LED1"    LED1 signal control (see #P205) -- receive status
 06h    "LED2"    LED2 signal control (see #P205)
 07h    "LED3"    LED3 signal control (see #P205) -- transmit status
 08h    reserved
 09h    "FDC"        full-duplex control
 0Ah-0Fh reserved
 10h    "IOBASEL"    I/O base select (lo) -- reserved
 11h    "IOBASEU"    I/O base select (hi) -- reserved
 12h    "BSBC"        burst size and bus control
 13h    "EECAS"        EEPROM Control and Status
 14h    "SWS"        software style
 15h    "INTCON"    reserved
 16h    "PCILAT"    PCI-bus latency
 17h    "PCISID"    PCI subsystem ID
 18h    "PCISVID"    PCI subsystem vendor ID
 19h    "SRAMSIZ"    SRAM size
 1Ah    "SRAMB"        SRAM boundary
 1Bh    "SRAMIC"    SRAM interface control
 1Ch    "EBADDRL"    expansion bus address (low)
 1Dh    "EBADDRU"    expansion bus address (high)
 1Eh    "EBD"        expansion bus data port
 1Fh    "STVAL"        software timer value
 20h    "MIICAS"    MII control and status
 21h    "MIIADDR"    MII address
 22h    "MIIMDR"    MII management data
 23h    "PCIVID"    PCI vendor ID
SeeAlso: #P185,#P201,#P202

Bitfields for AMD PCnet ISA bus configuration:
Bit(s)    Description    (Table P204)
 3    EADISEL
 2    AWAKE
 1    ASEL
 0    XMAUSEL
SeeAlso: #P202,#P205

Bitfields for AMD PCnet LEDn signal control:
Bit(s)    Description    (Table P205)
 15    LEDOUT
 14-8    reserved
 7    PSE
 6-5    reserved
 4    XMTE
 3    RVPE
 2    RCVE
 1    JABE
 0    COLE
SeeAlso: #P202
----------P0300031F--------------------------
PORT 0300-031F - prototype cards
        Periscope hardware debugger
----------P030C030F--------------------------
PORT 030C-030F - AIMS LAB PC Radio
Range:    configurable to PORT 020Ch or PORT 030Ch
Notes:    writing a value with bit 3 set to one of these ports turns on the
      radio; writing a value with bit 3 clear turns it off
    PORT 020Eh bits 1 indicates status of some kind
--------s-P03100311--------------------------
PORT 0310-0311 - MPU-401 MIDI UART
Range:    alternate address at PORT 0300h or PORT 0330h, occasionally at
      PORT 0320h
----------P0310031F--------------------------
PORT 0310-031F - Philips CD-ROM player CM50
--------s-P03200321--------------------------
PORT 0320-0321 - MPU-401 MIDI UART
Range:    alternate address at PORT 0300h or PORT 0330h, occasionally at
      PORT 0310h
----------P03200323--------------------------
PORT 0320-0323 - XT HDC 1   (Hard Disk Controller)
SeeAlso: PORT 01F0h-01F7h

0320  RW  data register
0321  -W  reset controller
0321  R-  read controller hardware status (see #P206)
0322  R-  read DIPswitch setting on XT controller card
0322  -W  generate controller-select pulse
0323  -W  write pattern to DMA and INT mask register

Bitfields for XT hard disk controller hardware status:
Bit(s)    Description    (Table P206)
 7-6    always 0
 5    logical unit number
 4-2    always 0
 1    error occurred
 0    always 0
----------P03240327--------------------------
PORT 0324-0327 - XT HDC 2   (Hard Disk Controller)
----------P0328032B--------------------------
PORT 0328-032B - XT HDC 3   (Hard Disk Controller)
----------P032B------------------------------
PORT 032B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 036Bh,
      PORT 03ABh, PORT 03EBh
----------P032C------------------------------
PORT 032C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P032C032F--------------------------
PORT 032C-032F - XT HDC 4   (Hard Disk Controller)
----------P03300331--------------------------
PORT 0330-0331 - MPU-401 MIDI UART
Range:    alternate address at PORT 0300h, occasionally at PORT 0310h or
      PORT 0320h

0330  RW  data register
0331  R-  status register (see #P207)
0331  -W  command register (see #P208)
Note:    MPU-401 genarates an interrupt when MIDI code is ready; by reading
      MIDI code from the data register this interrupt is cleared

Bitfields for MPU-401 status register:
Bit(s)    Description    (Table P207)
 7    input ready
    =1 no data is available for reading
    =0 data is available for reading
 6    output ready
    =1 not ready to receive command/data byte
    =0 ready to receive command/data byte
 5-0    reserved
Note:    pending input seems to block the output
SeeAlso: #P208

(Table P208)
Values for MPU-401 commands (data go to/from PORT 0330h):
Command    Description         Results  Parameter
 01h    send MIDI stop           ACK          -
 02h    send MIDI start           ACK          -
 03h    send MIDI continue       ACK          -
 15h    stop all (recording,       ACK          -
      playback and MIDI)
 34h    return timing bytes       ACK          -
      in stop mode
 35h    enable mode messages       ACK          -
      to PC
 38h    enable system common       ACK          -
      messages to PC
 39h    enable real time       ACK          -
      messages to PC
 3Ch    use CLS sync           ACK          -
 3Dh    use SMPTE sync           ACK          -
 3Fh    enter UART mode           ACK          -
 80h    use MIDI sync           ACK          -
 81h    use FSK sync           ACK          -
 82h    use MIDI sync           ACK          -
 83h    enable metronome       ACK          -
 84h    disable metronome       ACK          -
 87h    enable pitch and       ACK          -
      controller
 8Ah    disable data in stopped       ACK          -
      mode
 8Bh    enable data in stop mode   ACK          -
 8Ch    disable measure end       ACK          -
      messages to host
 91h    enable ext MIDI control       ACK          -
 94h    disable clock to host       ACK          -
 95h    enable clock to host       ACK          -
 97h    enable system exclusive       ACK          -
      messages to PC
 ACh    get MIDI version     ACK,VER      -
 ADh    get revision         ACK,REV      -
 Cxh    set timebase to x*24       ACK          -
      ppqn (x>1)
 D0h    ???               ACK          -
 DFh    ???               ACK          -
 E0h    set tempo           ACK         BPS
 E4h    set clocks per click       ACK         CPC
 E6h    set beats per measure       ACK         BPM
 E7h    send all clocks to host       ACK        1 byte
                      (04h is sent)
 FFh    reset               ACK          -
Notes:    after receiving a command byte MPU-401 must reply with command
      acknowledge byte FEh in data register
    command parameters are sent, and response bytes are received through
      the data register
    no commands (except reset) can be issued in UART mode, and MPU-401
      must be reset to leave UART mode
    Key:
        ACK    command acknowledge byte (FEh)
        VER    MIDI version number
            bits 7-4: major version
            bits 0-3: minor version
        REV    revision number
        BPS    beats per second (8..250)
        CPC    clocks per click
        BPM    beats per measure
SeeAlso: #P208
----------P03300333--------------------------
PORT 0330-0333 - Adaptec 154xB/154xC SCSI adapter (default address)
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
Note:    BusLogic BT-545S and DTC 3290 seem to be "almost" compatible with
      the Adaptec AHA-154x

0330  R-  status register (see #P209)
0330  -W  control register (see #P210)
0331  R-  data in register
0331  -W  command / data out register (see #P212)
0332  R-  interrupt status register (see #P211)

Bitfields for AHA-154x status register:
Bit(s)    Description    (Table P209)
 7    self-test in progress (STST)
 6    diagnostic failure (DIAGF)
 5    mailbox initialization required (INIT)
 4    adapter idle (IDLE)
 3    command register full (CDF)
 2    data register full (DF)
 1    reserved
 0    invalid command (INVDCMD)
Note:    data in register should only be read if bit 2 is set
    command / data out register should only be written if bit 3 is zero
SeeAlso: #P210,#P211,#P212

Bitfields for AHA-154x control register:
Bit(s)    Description    (Table P210)
 7    hardware reset (HRST)
 6    software reset (SRST)
 5    interrupt reset (IRST)
 4    SCSI bus reset (SCRST)
 0-3    reserved
SeeAlso: #P209

Bitfields for AHA-154x interrupt status register:
Bit(s)    Description    (Table P211)
 7    any interrupt (ANYINTR)
 4-6    reserved
 3    SCSI reset detected (SCRD)
 2    host adapter command complete (HACC)
 1    mailbox out available (MBOA)
 0    mailbox in full (MBIF)
SeeAlso: #P209

(Table P212)
Values for AHA-154x host adapter commands:
Command    Description         Parameters              Results
 00h    no operation         -             -
 01h    mailbox initializa-  NMB,MBA0,MBA1,MBA2         -
      tion
 02h    start SCSI command     -             -
 03h    start BIOS command   BFN,TRG,CH,CLHH,HL,SN,SC,     -
                 BA0,BA1,BA2
 04h    adapter inquiry         -              BT,SOID,RC0,RC1
 05h    enable mailbox out     1 byte             -
      interrupt
 06h    set selection          4    bytes             -
      timeout
 07h    set bus on time        BON             -
 08h    set bus off time    BOFF             -
 09h    set AT bus transfer    ATBS             -
      speed
 0Ah    return installed     -              ID0,ID1,ID2,ID3,
      devices                      ID4,ID5,ID6,ID7
 0Bh    return configuration     -              DRQ,IRQ,SID
      data
 0Ch    enable target mode    2 bytes             -
 0Dh    return setup data    NSD              OPT,ATBS,
                              BON,BOFF,
                              NMB,MBA0,MBA1,MBA2,
                              S0,S1,S2,S3,S4,S5,S6,S7,
                              DS
 1Ah    write channel 2          3 bytes             -
      buffer
 1Bh    read channel 2          3    bytes             -
      buffer
 1Ch    write FIFO buffer     3    bytes             -
 1Dh    read FIFO buffer      3    bytes             -
 1Fh    echo command data     D             D
 20h    run adapter         -             -
      diagnostics
 21h    set adapter options   ESG,DS             -
 22h    program EEPROM          35 bytes             -
      (AHA-1542C)
 23h    return EEPROM data   ???,NED,EA              EEPROM data
      (AHA-1542C)                       bytes
 24h    set shadow RAM           1 byte             -
      parameters
      (AHA-1542C???)
 25h    BIOS mailbox          NMB,MBA0,MBA1,MBA2     -
      initialization
      (since AHA-1540B
      rev. 1.4???)
 26h    set BIOS bank 1         -             -
      (AHA-1542C???)
 27h    set BIOS bank 2         -             -
      (AHA-1542C???)
 28h    return extended BIOS     -               F,MBLC
      information (since
      AHA-1540B rev.
      1.4???)
 29h    enable mailbox          EMB,MBLC             -
      interface (since
      AHA-1540B rev.
      1.4???)
 82h    start BIOS SCSI         -             -
      command (since
      AHA-1540B rev.
      1.4???)
Note:    NMB       number of "in" and "out" mailboxes
    MBA0..MBA2 MSB..LSB of the physical address of the array of mailboxes
           (see #P213)
    BFN       BIOS function number
    TRG       bits 7-5: target ID
           bits 4-0: reserved
    CH       bits 7-4: reserved
           bits 3-0: bits 9-6 of cylinder number
    CLHH       bits 7-2: bits 5-0 of cylinder number
           bits 1-0: bits 5-4 of head number
    HL       bits 7-4: reserved
           bits 3-0: bits 3-0 of head number
    SN       sector number - 1
    SC       sector count
    BA0..BA2   MSB..LSB of the physical address of data buffer
    BT       board type
           20h BusLogic BT-545S
           31h Adaptec AHA-1540
           41h Adaptec AHA-1540A/1542A/1542B
           42h Adaptec AHA-1640
           43h Adaptec AHA-1542C
           44h Adaptec AHA-1542CF
           45h=Adaptec AHA-1542CF with BIOS v2.01
    SOID       special options ID
           30h ???
           41h standard model
    RC0/RC1       alphanumeric revision code
    BON       bus on time (time in microseconds adapter stays on the AT
             bus when transferring data: 2..15, default is 11)
    BOFF       bus off time (time in microseconds adapter stays off the AT
             bus when transferring data: 1..64, default is 4)
    ATBS       AT bus transfer speed
           00h,AAh 5.0    MB/s
           01h,99h 6.7    Mb/s
           02h       8.0    Mb/s
           03h,88h 10.0 Mb/s
           04h       5.7    Mb/s
           BBh       4.0    Mb/s???
           CCh       3.3    Mb/s???
           DDh       2.9    Mb/s???
           EEh       2.5    Mb/s???
           FFh       2.2    Mb/s???
    ID0..ID7   bit m in byte IDn is set if SCSI ID n LUN m is online
    DRQ       DRQ select
           bit 7:   DRQ7
           bit 6:   DRQ6
           bit 5:   DRQ5
           bit 4-1: reserved
           bit 0:   DRQ0
    IRQ       IRQ select
           bit 7: reserved
           bit 6: IRQ15
           bit 5: IRQ14
           bit 4: IRQ13
           bit 3: IRQ12
           bit 2: IRQ11
           bit 1: IRQ10
           bit 0: IRQ9
    SID       host adapter SCSI ID
    NSD       number of setup data bytes to return
    OPT       options
           bit 0: synchronous negotiation
           bit 1: SCSI parity
    S0..S7       synchronous transfer timings for target IDs 0..7
           each byte laid out as follows
           bit 7:    synchronous timing valid
           bits 6-4: synchronous transfer period
           bits 3-0: synchronous offset
    DS       disconnect status
           bit n is set if target ID n is unable to disconnect???
    D       any data byte (it must be echoed back)
    ESG       enable scatter/gather???
    NED       number of EEPROM data bytes to return
    EA       EEPROM address to read data from
    F       flags
           bit 3: extended BIOS enabled
    MBLC       mailbox lock code
           bit 0: BIOS uses 256 heads 63 sectors LBA to CHS
              translation???
    EMB       0 to enable mailbox interface???
Note:    all commands except 01h, 02h should only be issued if the host adapter
      is idle (bit 4 in PORT 0330h set)
    command 02h can be issued even if the command / data out register is
      full (bit 3 in PORT 0330h may be set)
    command 02h causes host adapter to scan both its SCSI and BIOS
      mailboxes; command 82h causes host adapter to scan its BIOS mailboxes
    all host adapter commands except 02h cause host adapter command
      complete interrupt (bit 2 in PORT 332h) after their completetion
    return setup data command (0Dh) returns the number of bytes requested
      with NSD parameter
    BusLogic BT-545S gets the adapter inquiry command (04h) wrong returning
      only one byte instead of four; DTC 3290 gets this command wrong too
SeeAlso: #P209,#P211

Format of AHA-154x mailbox array:
Offset    Size    Description    (Table P213)
 00h  N*4 BYTEs    array of N "out" mailboxes (see #P214)
 N*4  N*4 BYTEs    array of N "in" mailboxes (see #P214)
Notes:    the "out" mailboxes are scanned by the host adapter in a round-robin
      fashion, i.e. the host adapter first looks into an "out" mailbox
      which follows one least recently used (and wraps around if it was
      the last one in the array)
    array of "in" mailboxes is absent in the case of BIOS mailboxes
SeeAlso: #P209,#P215,#P216

Format of AHA-154x mailbox:
Offset    Size    Description    (Table P214)
 00h    BYTE    mailbox command/status code (see #P215,#P216)
 01h  3 BYTEs    address of the command control block (CCB) (see #P217)
        physical address in big-endian format
SeeAlso: #P209,#P213

(Table P215)
Values for mailbox out command codes:
 00h    CCB is free
 01h    start CCB
 02h    abort CCB
SeeAlso: #P209,#P213,#P216

(Table P216)
Values for mailbox in status codes:
 00h    command in progress
 01h    CCB completed
 02h    CCB aborted
 03h    CCB abort failed
 04h    CCB completed with error
SeeAlso: #P209,#P213,#P215

Format of AHA-154x command control block (CCB):
Offset    Size    Description    (Table P217)
 00h    BYTE    CCB operation code (see #P218)
 01h    BYTE    address and control
        bits 5-7: target/initiator ID
        bit 4:      outbound data
        bit 3:      inbound data
        bits 0-2: LUN
 02h    BYTE    SCSI command length
 03h    BYTE    request sense allocation length
        write 0 to disable auto-sense
 04h  3 BYTEs    data length
        in big-endian format
 07h  3 BYTEs    data pointer
        physical address in big-endian format
 0Ah  3 BYTEs    link pointer (link to the next CCB for linked commands)
        physical address in big-endian format
 0Dh    BYTE    command linking ID (for linked commands)
        mailbox status code (if this is a CCB in a BIOS mailbox,
        see #P216)
 0Eh    BYTE    host adapter status (see #P219)
 0Fh    BYTE    target device status
        SCSI status byte
 10h  2 BYTEs    reserved
 12h  N BYTEs    SCSI command descriptor block (CDB)
 12h+N M BYTEs    auto-sense data
SeeAlso: #P209

(Table P218)
Values for CCB type:
 00h    initiator CCB
 01h    target CCB
 02h    initiator CCB with scatter/gather (see #P220)
 03h    initiator CCB with residual length
 04h    initiator CCB with scatter/gather and residual length (see #P220)
 81h    bus device reset CCB
Note:    residual length is returned in the data length field of CCB
    initiator CCB with scatter/gather cannot have a zero data length
SeeAlso: #P209

(Table P219)
Values for host adapter status:
 00h    command complete
 0Ah    linked command complete (linked CCBs only)
 0Bh    linked command complete with flag (linked CCBs only)
 11h    selection time out
 12h    data overrun/underrun
 13h    unexpected bus free
 14h    target bus phase sequence failure
 15h    invalid mailbox out command
 16h    invalid CCB operation code
 17h    linked CCB does not have the same LUN
 18h    invalid target direction received from host (target mode only)
 19h    dupilcate CCB received in target mode
 1Ah    invalid CCB or segment list parameter
Note:    in the case of target bus sequence failure host adapter will generate
       a SCSI reset condition, notifying the host with a SCRD interrupt
SeeAlso: #P209

Format of AHA-154x scatter/gather segment:
Offset    Size    Description    (Table P220)
 00h  3 BYTEs    data length
        in big-endian format
 03h  3 BYTEs    data pointer
        physical address in big-endian format
SeeAlso: #P209
----------P0330033F--------------------------
PORT 0330-033F - CompaQ SCSI adapter. alternate address at 0130
--------d-P0330033F--------------------------
PORT 0330-033F - Philips CD-ROM player CM50
--------d-P03340337--------------------------
PORT 0334-0337 - Adaptec 154xB/154xC SCSI adapter.
Range:    four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
--------s-P0338------------------------------
PORT 0338 - AdLib soundblaster card
--------S-P0338033F--------------------------
PORT 0338-033F - COM port addresses on UniRAM card by German magazine c't
Range:    selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8
----------P0340034F--------------------------
PORT 0340-034F - Philips CD-ROM player CM50
----------P0340034F--------------------------
PORT 0340-034F - SCSI (1st Small Computer System Interface) adapter
Range:    alternate address at 0140-014F
--------s-P0340------------------------------
PORT 0340 - Crystal Semiconductor CDB4922 evaluation board
Desc:    the CDB4922 is an evaluation board for the CS4922 MPEG audio
      decoder (see I2C xxh"CS4922")
--------s-P0340034F--------------------------
PORT 0340-034F - Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
Note:    the AMD InterWave chip provides a superset of the UltraSound's
      functionality, including these ports
SeeAlso: PORT 0240h-024Fh,PORT 0746h

0340  -W  MIDI Control (see #P221)
0340  R-  MIDI Status (see #P222)
0341  -W  MIDI Transmit Data
0341  R-  MIDI Receive Data
0342  RW  GF1 Page Register / Voice Select
0343  RW  GF1/Global Register Select (see #P223)
0344  RW  GF1/Global Data Low Byte (16 bits)
0345  RW  GF1/Global Data High Byte (8 bits)
0346  -W  Mixer Data Port
0347  RW  GF1 DRAM
         Direct Read Write at Loction pointed with regs 43 and 44

Bitfields for Gravis Ultra Sound MIDI control register:
Bit(s)    Description    (Table P221)
 7       Receive IRQ (1 = enabled)
 5-6   Xmit IRQ
 0-1   Master Reset (1 = enabled)
SeeAlso: #P178,#P180,#P222

Bitfields for Gravis Ultra Sound MIDI status register:
Bit(s)    Description    (Table P222)
 7    Interrupt pending
 5    Overrun Error
 4    Framing Error
 1    Transmit Register Empty
 0    Receive Register Empty
SeeAlso: #P221,#P223

(Table P223)
Values for Gravis Ultra Sound GF1/Global Registers:
---Voice specific registers---
 00h  w        Voice Control (see #P225)
 01h  w        Frequency Control
         bit 15-10     Integer Portion
         bit 9-1     Fractional Portion
 02h  w        Start Address HIGH
         bit 12-0     Address Lines 19-7
 03h  w        Start Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of Start Address
 04h  w        End Address HIGH
         bit 12-0     Address Lines 19-7
 05h  w        End Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of End Address
 06h  w        Volume Ramp Rate
         bit 5-0     Amount added
         bit 7-6     Rate
 07h  w        Volume Ramp Start
         bit 7-4     Exponent
         bit 3-0     Mantissa
 08h  w        Volume Ramp End
         bit 7-4     Exponent
         bit 3-0     Mantissa
 09h  w        Current Volume
         bit 15-12     Exponent
         bit 11-4     Mantissa
 0Ah  w        Current Address HIGH
         bit 12-0     Address Lines 19-7
 0Bh  w        Current Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-0     Fractional Position
 0Ch  w        Pan Position
         bit 3-0     Pan Postion
 0Dh  w        Volume Control (see #P226)
 0Eh  w        Active Voices
         bit 5-0     #Voices -1  (allowed 13 - 31)
 0Fh  w        IRQ Source Register (see #P227)
---NOT voice specific---
 41h  r/w   DRAM DMA Control (see #P228)
 42h  w        DMA Start Address
         bits 15-0     DMA Address Lines 19-4
 43h  w        DRAM I/O Address LOW
 44h  w        DRAM I/O Address HIGH
         bits 0-3     Upper 4 Address Lines
 45h  r/w   Timer Control
         bit 3     Enable Timer 2
         bit 2     Enable Timer 1
 46h  w        Timer 1 Count (granularity of 80 micro sec)
 47h  w        Timer 2 Count (granulatity of 320 micro sec)
 48h  w        Sampling Frequency
         rate = 9878400 / (16 * (FREQ + 2))
 49h  r/w   Sampling Control (see #P229)
 4Bh  w        Joystick Trim DAC
 4Ch  r/w   RESET
         bit 2     GF1 Master IRQ Enable
         bit 1     DAC Enable
         bit 0     Master Reset
---Voice specific registers---
 80h  r        Voice Control (see 00h)
 81h  r        Frequency Control (see 01h)
 82h  r        Start Address HIGH (see 02h)
 83h  r        Start Address LOW (see 03h)
 84h  r        End Address HIGH (see 04h)
 85h  r        End Address LOW (see 05h)
 86h  r        Volume Ramp Rate (see 06h)
 87h  r        Volume Ramp Start (see 07h)
 88h  r        Volume Ramp End (see 08h)
 89h  r        Current Volume (see 09h)
 8Ah  r        Current Address HIGH (see 0Ah)
 8Bh  r        Current Address LOW (see 0Bh)
 8Ch  r        Pan Position (see 0Ch)
 8Dh  r        Volume Control (see 0Dh)
 8Eh  r        Active Voices (see 0Eh)
 8Fh  r        IRQ Status (see 0Fh)
SeeAlso: #P222,#P224

(Table P224)
Values for InterWave synthesizer registers:
---voice-specific registers---
 10h  w        synthesizer     upper address
 11h  w        synthesizer effects address high (16 bits)
 12h  w        synthesizer effects address low (16 bits)
 13h  w        synthesizer left offset (16 bits)
 14h  w        synthesizer effects output accumulator select
 15h  w        synthesizer mode select
 16h  w        synthesizer effects volume (16 bits)
 17h  w        synthesizer frequency LFO
 18h  w        synthesizer volume LFO
---NOT voice-specific---
 19h  w        synthesizer global mode
 1Ah  w        synthesizer LFO base address (16 bits)
---voice-specific registers---
 1Bh  w        synthesizer right offset (16 bits)
 1Ch  w        synthesizer left offset (16 bits)
 1Dh  w        synthesizer effect volume final (16 bits)
---NOT voice-specific---
 41h  r/w   local memory control: DMA control
 42h  r/w   local memory control: DMA start address bits 19-4 (16 bits)
 43h  w        local memory control: I/O address low (16 bits)
 44h  w        local memory control: I/O address high (16 bits)
 45h  r/w   AdLib/SoundBlaster control
 46h  r/w   AdLib timer 1
 47h  r/w   AdLib timer 2
 49h  r/w   ADC sample control
 4Bh  r/w   joystick trim
 4Ch  w        GUS reset
 50h  r/w   local memory control: DMA start address bits 23-20/3-0 (16 bits)
 51h  r/w   local memory control: 16-bit access
 52h  r/w   local memory control: configuration
 53h  r/w   local memory control: control
 54h  r/w   local memory control: record FIFO base address bits 23-8 (16-bit)
 55h  r/w   local memory control: playback FIFO base address bits 23-8 (16-bit)
 56h  r/w   local memory control: FIFO size (16-bit)
 57h  r/w   local memory control: DMA interleave control (16-bit)
 58h  r/w   local memory control: DMA interleaev base address bits 23-8
 59h  r/w   compatibility control
 5Ah  r/w   decode control
 5Bh  r/w   version number
 5Ch  r/w   MPU-401 emulation control A
 5Dh  r/w   MPU-401 emulation control B
 5Eh  w        MIDI receive FIFO access
 5Fh  -        reserved
 60h  r/w   emulation IRQ
---voice-specific registers---
 90h  r        synthesizer     upper address
 91h  r        synthesizer effects address high (16 bits)
 92h  r        synthesizer effects address low (16 bits)
 93h  r        synthesizer left offset (16 bits)
 94h  r        synthesizer effects output accumulator select
 95h  r        synthesizer mode select
 96h  r        synthesizer effects volume (16 bits)
 97h  r        synthesizer frequency LFO
 98h  r        synthesizer volume LFO
---NOT voice-specific---
 99h  r        synthesizer global mode
 9Ah  r        synthesizer LFO base address (16 bits)
---voice-specific registers---
 9Bh  r        synthesizer right offset (16 bits)
 9Ch  r        synthesizer left offset (16 bits)
 9Dh  r        synthesizer effect volume final (16 bits)
---NOT voice-specific---
 9Fh  r        synthesizer voices IRQ
Note:    these registers are *in*addition* to the Gravis UltraSound registers
SeeAlso: #P223

Bitfields for Gravis Ultra Sound voice control global register:
Bit(s)    Description    (Table P225)
 7     IRQ pending
 6     Direction
 5     Enable WAVE IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Size data (8/16 bits)
 1     Stop Voice
 0     Voice Stopped
SeeAlso: #P223,#P226

Bitfields for Gravis Ultra Sound volume control global register:
Bit(s)    Description    (Table P226)
 7     IRQ Pending
 6     Direction
 5     Enable Volume Ramp IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Rollover Condition
 1     Stop Ramp
 0     Ramp Stopped
SeeAlso: #P223,#P225

Bitfields for Gravis Ultra Sound IRQ source register:
Bit(s)    Description    (Table P227)
 7     WaveTable IRQ pending
 6     Volume Ramp IRQ pending
 4-0     Voice Number
SeeAlso: #P223,#P225,#P228

Bitfields for Gravis Ultra Sound DRAM DMA control register:
Bit(s)    Description    (Table P228)
 7     Invert MSB
 6     Data Size (8/16 bits)
 5     DMA Pending
 3-4     DMA Rate Divider
 2     DMA Channel Width (8/16 bits)
 1     DMA Direction (1 = read)
 0     DMA Enable
SeeAlso: #P223,#P227

Bitfields for Gravis Ultra Sound sampling control register:
Bit(s)    Description    (Table P229)
 7     Invert MSB
 6     DMA IRQ pending
 5     DMA IRQ enable
 2     DMA width (8/16 bits)
 1     Mode (mone/stereo)
 0     Start Sampling
SeeAlso: #P223
----------P03400357--------------------------
PORT 0340-0357 - RTC (1st Real Time Clock for XT)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
Range:    alternate at 0240-0257
SeeAlso:  PORT 0240h-0257h

0340  RW  0.001 seconds        0-99
0341  RW  0.1 and 0.01 seconds    0-99
0342  RW  seconds        0-59
0343  RW  minutes        0-59
0343  RW  hours            0-23
0345  RW  day of week        1-7
0346  RW  day of month        1-31
0347  RW  month            1-12
0348  RW  RAM (upper nybble only)
0349  RW  year            0-99
034A  RW  RAM last month storage
034B  RW  RAM year storage (-80)
034C  RW  RAM reserved
034D  RW  RAM not used
034E  RW  RAM not used
034F  RW  RAM not used
0350  R-  interrupt status register
0351  -W  interrupt control register
0352  -W  counter reset
0353  -W  RAM reset
0354  R-  status bit
0355  -W  GO command
0356  ??  standby interrupt
0357  ??  test mode
----------P03480357--------------------------
PORT 0348-0357 - DCA 3278
----------P034C034F--------------------------
PORT 034C-034F - Gravis UltraMax by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
----------P035A035B--------------------------
PORT 035A-035B - Adaptec AH1520 jumper settings

035A  R      I/O channel setup (see #P230)
035B  R      transfer mode setup (see #P231)

Bitfields for Adaptec AH1520 channel setup jumper settings:
Bit(s)    Description    (Table P230)
 7    SCSI parity disabled
 6-5    DMA channel (00 = channel 0, 01 = 5, 10 = 6, 11 = 7)
 4-3    IRQ number (00 = IRQ9, 01 = IRQ10, 10 = IRQ11, 11 = IRQ12)
 2-0    SCSI ID
SeeAlso: #P231

Bitfields for Adaptec AH1520 transfer mode setup jumper settings:
Bit(s)    Description    (Table P231)
 7    DMA transfer mode (clear for PIO)
 6    boot enabled
 5-4    boot type
    00 ???
    01 boot from floppy
    10 print configured options
    11 boot from hard disk
 3    enable sync negotiation
 2    enable target disconnection
 1-0    unused???
SeeAlso: #P230
----------P035F------------------------------
PORT 035F - ARTEC Handyscanner A400Z.  alternate address at 15F.
----------P03600367--------------------------
PORT 0360-0367 - PC network (XT only)
----------P0360036F--------------------------
PORT 0360-036F - PC network (AT)
----------P0360036F--------------------------
PORT 0360-036F - National Semiconductor DP8390(1)C/NS3249C network chipset
Note:    cards based on this IEEE 802.3 networking chipset can use any range
      of 16 consecutive addresses, and provide a total of four pages of
      sixteen registers (see #P232,#P233,#P234,#P299)

(Table P232)
Values for NS DP8390C/NS3249C network chipset Page 0 registers:
Number    Read Register                Write Register
 00h    Command reg. (see #P236)    CR    Command reg.        CR
 01h    current local DMA address 0    CLDA0    page start reg.        PSTART
 02h    current local DMA address 1    CLDA1    page stop reg.        PSTOP
 03h    boundary pointer        BNRY    boundary pointer    BNRY
 04h    transmit status reg.        TSR    Tx page start address    TPSR
 05h    number of collisions reg.    NCR    Tx byte count reg.0    TBCR0
 06h    FIFO                    Tx byte count reg.1    TBCR1
 07h    interrupt status reg.        ISR    interrupt status reg.    ISR
 08h    current remote DMA address 0    CRDA0    remote start addr.reg.0 RSAR0
 09h    current remote DMA address 1    CRDA1    remote start addr.reg.1 RSAR1
 0Ah    reserved                remote byte count reg.0 RBCR0
 0Bh    reserved                remote byte count reg.1 RBCR1
 0Ch    receive status reg.        RSR    Rx configuration reg.    RCR
 0Dh    tally counter 0 (frame errors)    CNTR0    Tx configuration reg.    TCR
 0Eh    tally counter 1 (CRC errors)    CNTR1    data configuration reg. DCR
 0Fh    tally counter 2 (missed pkt)    CNTR2    interrupt mask reg.    IMR
SeeAlso: #P233,#P234,#P235

(Table P233)
Values for NS DP8390C/NS3249C network chipset Page 1 registers:
Number    Read/Write
 00h    Command            CR (see #P236)
 01h    physical address reg.0    PAR0
 02h    physical address reg.1    PAR1
 03h    physical address reg.2    PAR2
 04h    physical address reg.3    PAR3
 05h    physical address reg.4    PAR4
 06h    physical address reg.5    PAR5
 07h    current page reg.    CURR
 08h    multicast address reg.0 MAR0
 09h    multicast address reg.1 MAR1
 0Ah    multicast address reg.2 MAR2
 0Bh    multicast address reg.3 MAR3
 0Ch    multicast address reg.4 MAR4
 0Dh    multicast address reg.5 MAR5
 0Eh    multicast address reg.6 MAR6
 0Fh    multicast address reg.7 MAR7
SeeAlso: #P232,#P234,#P235

(Table P234)
Values for NS DP8390C/NS3249C network chipset Page 2 registers:
Number    Read Register                Write Register
 00h    Command                CR    Command             CR
 01h    page start reg.            PSTART    current local DMA addr.0 CLDA0
 02h    page stop reg.            BPSTOP    current local DMA addr.1 CLDA1
 03h    remote next packet pointer        remote next packet pointer
 04h    Tx page start address        TPSR    reserved
 05h    local next packet pointer        local next packet pointer
 06h    address counter (upper)            address counter (upper)
 07h    address counter (lower)            address counter (lower)
 08h    reserved                reserved
 09h    reserved                reserved
 0Ah    reserved                reserved
 0Bh    reserved                reserved
 0Ch    Rx configuration reg.        RCR    reserved
 0Dh    Tx configuration reg.        TCR    reserved
 0Eh    data configuration reg.        DCR    reserved
 0Fh    interrupt mask reg.        IMR    reserved
Note:    this is a diagnostics page, and should never be modfied under normal
      operation.
SeeAlso: #P232,#P233,#P235

(Table P235)
Values for NS DP8390C/NS3249C network chipset Page 3 registers:
Number    Read Register                Write Register
 00h    Command CR (see #P236)            Command CR
Note:    Test Page - should never be modified!
SeeAlso: #P232,#P233,#P234

Bitfields for NS DP8390C/NS3249C network chipset command register (00h):
Bit(s)    Description    (Table P236)
 0    software reset command (1=offline, 0=online)
 1    do not activate NIC after reset command
 2    start transmision of a packet
 3-5    remote DMA command
    000 not allowed
    001 remote read
    010 remote write
    011 send packet
    1xx abort/complete rmote DMA
 6-7    page select
    00 register page 0
    01 register page 1
    10 register page 2
    11 register page 3
SeeAlso: #P235
----------P036B------------------------------
PORT 036B - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
      PORT 03ABh, PORT 03EBh
----------P036C------------------------------
PORT 036C - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
----------P03700377--------------------------
PORT 0370-0377 - FDC 2    (2nd Floppy Disk Controller)    first FDC at 03F0
Note:    floppy disk controller is usually an 8272, 8272A, NEC765 (or
      compatible), or an 82072 or 82077AA for perpendicular recording at
      2.88M
SeeAlso: PORT 03F0h-03F7h

0370  R-  diskette Extra High Density controller board jumpers (AT)
0370  R-  diskette controller status A (PS/2, PS/2 model 30)
0371  R-  diskette controller status B (PS/2, PS/2 model 30)
0372  -W  diskette controller DOR (Digital Output Register)
0374  R-  diskette controller main status register
0374  -W  diskette controller datarate select register
0375  RW  diskette controller command/data register
0376  RW  (2nd FIXED disk controller status/data register)
0377  RW  (2nd FIXED disk controller drive address register)
0377  R-  diskette controller DIR (Digital Input Register)
0377  -W  select register for diskette data transfer rate
----------P0378------------------------------
PORT 0378 - Covox 'Speech Thing' COMPATIBLE SPEECH OUTPUT
SeeAlso: PORT 022Fh"mc-soundmachine",PORT 0388h-038Fh"soundmachine"

0378  -W  speech output via printer port
      (with mc-soundmachine, enabled if bit4=1 in 38F)
----------P0378037A--------------------------
PORT 0378-037A - PARALLEL PRINTER PORT (usually LPT2, sometimes LPT3)
Range:    usually PORT 03BCh, PORT 0278h, or PORT 0378h
SeeAlso: MEM 0040h:000Ah,INT 17/AH=00h

0378  -W  data port
0379  R-  status port (see #P263 at PORT 03BCh)
037A  RW  control port (see #P264 at PORT 03BCh)

037B  ??  bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
----------P0378037F--------------------------
PORT 0378-037F - Intel 82360SL/82091AA - EPP-mode PARALLEL PORT
Range:    PORT 0278h or PORT 0378h
SeeAlso: PORT 0278h"LPT1",PORT 0778h"ECP"

0378-037A    as for standard parallel port
037B  RW  address strobe
037C  RW  data strobe 0
037D  RW  data strobe 1
037E  RW  data strobe 2
037F  RW  data strobe 3
----------P037C037F--------------------------
PORT 037C-037F - C&T F87000 Multi-Mode Peripheral Chip - OUTPUT PORTS

037C  -W  outputs driven to keyboard outputs COL7-COL0
037C  R-  inputs driven by keyboard pins ROW7-ROW0
037D  -W  outputs driven to keyboard outputs COL15-COL8
037E  -W  outputs driven to pins P2[7-1]; bit 0 enables UART clock when low
037F  -W  external output port
----------P0380038F--------------------------
PORT 0380-038F - 2nd BSC (Binary Synchronous Communication) adapter
SeeAlso:  PORT 03A0h"BSC"
----------P0380038C--------------------------
PORT 0380-038C - 2nd SDLC (Synchronous Data Link Control) adapter
Notes:    Initialization of the SDLC adapter is performed in a typical
      sequence like this: Setup 8255 port A-C configuration by writing
      98h to 383h, followed by initializing 8255 port C by writing 0Dh
      to 382h. Reset 8273 internal registers by pulsing 8255 port B4.
      After this the 8253 has to be programmed to the desired values
      (counter 0 in mode 3). Now the 8273 is ready to be configured for
      the operating mode that defines the communication environment in
      which it will be used.
    Note on 8273: Each 8273 protocol controllers internal register is
      programmed by individual set/reset commands (via 388h) in
      conjunction with a parameter (via 389h) that give an OR/AND mask
      to the internal register value.
      Although the 8273 is a full duplex device, there is only one
      command register. Thus, the command register must be used for
      only one command sequence at a time and the transmitter and
      receiver may never be simultaneously in a command phase.
      The system software starts the command phase by writing a command
      byte into the command register. If further information is required
      by the 8273 prior to execution of the command, the system software
      must write the list of parameters into the parameter register.
SeeAlso: PORT 03A0h"SDLC"

0380  R-   on adapter 8255(A5) port A: internal/external sensing (see #P237)
0381  -W   on adapter 8255(A5) port B: external modem interface (see #P238)
0382  RW   on adapter 8255(A5) port C: internal control (see #P239)
0383  ?W   on adapter 8255(A5) mode initialization
0384  RW   on adapter 8253 (programmable counter) counter 0:
        LSB / MSB square wave generator (input for timer 2, connected
          to 8255 bitC5)
0385  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
        (connected to 8255 bitA7, IRQ4 level)
0386  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
        (connected to 8255 bitA6, IRQ4 level)
0387  ?W   on adapter 8253 mode register (see #P240)
0388  R-   on adapter 8273 status register (see #P241)
0388  -W   on adapter 8273 command register (see #P242)
0389  R-   on adapter 8273 (immediate) result register (see #P249)
0389  -W   on adapter 8273 parameter register
        Commands issued via PORT 0388h may need additional parameters,
          which have to be passed through this port (see table).
038A  R-   on adapter 8273 transmit INT status (DMA/INT)
038A  -W   on adapter 8274 reset
038B  R-   on adapter 8273 receive INT status (DMA/INT)
038C  -W   on adapter 8273 data: direct program control (DPC)
      scratch-pad

Bitfields for SDLC 8255 port A:
Bit(s)    Description    (Table P237)
 7    =1 timer 1 output active
 6    =1 timer 2 output active
 5    =1 modem status changed
 4    receive clock active (if pulsing)
 3    =0 clear to send is on from interface
 2    transmit clock active (if pulsing)
 1    =0 data carrier detect is on from interface
 0    =0 ring indicator is on from interface
SeeAlso: #P238,#P239

Bitfields for SDLC 8255 port B:
Bit(s)    Description    (Table P238)
 7    enable IRQ 4 level interrupt
 6    =1 gate timer 1
 5    =1 gate timer 2
 4    =1 reset 8273
 3    =1 reset modem status changed logic
 2    =0 turn on test
 1    =0 turn on select standby at modem interface
 0    =0 turn on data signal rate select at modem interface
SeeAlso: #P237,#P239

Bitfields for SDLC 8255 port C:
Bit(s)    Description    (Table P239)
 7 R-    =? not used (detection: =1 SDLC, =0 may be SDLC or BSC??)
 6 R-    =0 test indicate active
 5 R-    timer 0 output (if pulsing)
 4 R-    receive data (if pulsing)
 3 -W    =0 gate interrupts 3 and 4
 2 -W    =1 electronic wrap
 1 -W    =1 gate external clock
 0 -W    =1 gate internal clock
SeeAlso: #P237,#P238

Bitfields for SDLC 8253 mode register:
Bit(s)    Description    (Table P240)
 7-6    SC1-SC0     00, 01, 10= select counter 0,1,2; 11=illegal
 5-4    RL1-RL0     00= couner latching operation
         01= read/load most significant byte (MSB)
         10= read/load least significant byte (LSB)
         11= read/load LSB first, then MSB
 3-1    M2-M0     000= mode 0
         001= mode 1
         x10= mode 2
         x11= mode 3
         100= mode 4
         101= mode 5
 0    BCD     0= binary counter 16bits
         1= BCD counter 4 decades

Bitfields for SDLC 8273 status register:
Bit(s)    Description    (Table P241)
 7    =1 command busy (CBSY)
 6    =1 command buffer full (CBF)
 5    =1 command parameter buffer full (CPBF)
 4    =1 command result buffer full (CRBF)
 3    =1 Rx interupt (RxINT)
 2    =1 Tx interupt (TxINT)
 1    =1 RxINT result available (RxIRA)
 0    =1 TxINT result available (TxIRA)
SeeAlso: #P242

(Table P242)
Values for SDCL 8273 command register:
 commands:           parameters:    results:   result port: int:
  A4: set one-bit delay        set mask     -           -    no
  64: reset one-bit delay   reset mask     -           -    no
  97: set data transfer        set mask     -           -    no
  57: reset data transfer   reset mask     -           -    no
  91: set operating mode    set mask     -           -    no
  51: reset operating mode  reset mask     -           -    no
  A0: set serial I/O mode   set mask     -           -    no
  60: reset serial I/O mode reset mask     -           -    no
  C0: general receive        B0,B1     RIC,R0,R1,A,C RXI/R   yes
  C1: selective receive        B0,B1,A1,A2     RIC,RD,R1,A,C RXI/R   yes
  C5: receive disable        -         -           -    no
  C8: transmit frame        L0, L1, A, C TIC           TXI/R   yes
  C9: transmit transparent  L0, L1     TIC           TXI/R   yes
  CC: abort transmit frame  -         TIC           TXI/R   yes
  CD: abort transmit        -         TIC           TXI/R   yes
  22: read 8273 port A        -         port value    result    no
  23: read 8273 port B        -         port value    result    no
  A3: set 8273 port A bit   set mask     -           -    no
  63: set 8273 port B bit   reset mask     -           -    no
Notes:    B0/B1 LSB/MSB of the receiver buffer length
    L0/L1 LSB/MSB of the Tx buffer length
    A1/A2 receive frame address match field one/two
    A     address fieldof received frame. In non-buffered mode, this
          result is not provided.
    C     control field of received frame. In non-buffered mode, this
          result is not provided.
    RXI/R TXI/R receive/transmit interrupt result register
    R0/R1 LBS/MSB of the length of the frame received
    RIC/TIC receiver/transmitter interrupt result code
SeeAlso: #P243,#P244,#P245,#P246,#P247,#P248

Bitfields for SDLC 8273 interal port A: Modem Control Input Port:
Bit(s)    Description    (Table P243)
 7-5    not used
 4    DSR change (PA4)
 3    CTS change (PA3)
 2    Data Set Ready (PA2)
 1    Carrier Detect (PA1)
 0    Clear to Send (PA0)
SeeAlso: #P242

Bitfields for SDLC 8273 interal port B: Modem Control Output Port:
Bit(s)    Description    (Table P244)
 7-6    not used
 5    Flag Detect (PB5)
 4-3    reserved
 2    Data Terminal Ready (PB2)
 1    reserved (PB1)
 0    Request to Send (PB0)
SeeAlso: #P242

Bitfields for SDLC 8273 internal: Operating Mode Register:
Bit(s)    Description    (Table P245)
 7-6    not used
 5    =1 HDLC abort enable
 4    =1 EOP interrupt enable
 3    =1 enable early Tx interrupt
 2    =1 Buffered Mode
 1    =1 Two Preframe Sync Characters
 0    =1 Flag Stream Mode
SeeAlso: #P242

Bitfields for SDLC 8273 internal: Serial I/O Register:
Bit(s)    Description    (Table P246)
 7-3    not used
 2    =1 Data Loopback
 1    =1 Clock Loopback
 0    =1 NRZI Mode
SeeAlso: #P242

Bitfields for SDLC 8273 internal: Data Transfer Mode Register:
Bit(s)    Description    (Table P247)
 7-1    not used
 0    =1 Interrupt Data Transfers
SeeAlso: #P242

Bitfields for SDLC 8273 internal: One-Bit Delay Mode Register:
Bit(s)    Description    (Table P248)
 7 =1    One-Bit Delay Enable
 6-0    not used
SeeAlso: #P242

(Table P249)
Values for SDLC 8273 result register:
 transmit result codes:         status after interrupt:
  0C: early transmit interrupt      transmitter active
  0D: frame transmit complete      idle or flags
  0E: DMA underrun          abort
  0F: clear to send error      abort
  10: abort complete          idle or flags
 receive result codes:
  X0: A1 match / general receive  active
  X1: A2 match              active
  03: CRC error              active
  04: abort detected          active
  05: idle detected          disabled
  06: EOP detected          disabled
  07: frame less than 32 bits      active
  08: DMA overrun          disabled
  09: memory buffer overflow      disabled
  0A: carrier detect failure      disabled
  0B: receiver interrupt overrun  disabled
 X bits received inlast byte:
   E: all eight bits of last byte (bit7-0)
   0: bit0 only
   8: bit1-0
   4: bit2-0
   C: bit3-0
   2: bit4-0
   A: bit5-0
   6: bit6-0
--------s-P03840387--------------------------
PORT 0384-0387 - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
----------P03880389--------------------------
PORT 0388-0389 - AdLib - MONO SOUND OUTPUT
Note:    also supported by SoundBlaster and compatibles
SeeAlso: PORT 0220h-0223h,PORT 0388h-038Fh"soundmachine"

0388  R-  both speakers -- Status
        bit7  : interrupt request (IRQ)
        bit6  : timer 1 overflow
        bit5  : timer 2 overflow
        bit4-0: reserved
0388  -W  both speakers -- Address port (see #P250)
    index in OPL2 (YMF3812), OPL3 (YMF262), OPL4 (YF278-F)
0389  -W  data port
Note:    the AdLib requires a delay of 3.3 microseconds between writing to
      PORT 0388h and writing to PORT 0389h, and a delay of 23 microseconds
      after a write to PORT 0389h before any other operation is allowed

(Table P250)
Values for AdLib address port index:
 01h    Enable waveform control
    bit 7-6: (OPL4, OPL3 in OPL2 mode only) lsi test
    bit 5: (OPL2 only) wave select enable (WS)
           (OPL4, OPL3) lsi test
    bit 4-0: lsi test
 02h    Timer #1 data (OPL2 and OPL3 in OPL2 mode only)
 03h    Timer #2 data (OPL2 and OPL3 in OPL2 mode only)
 04h    Timer control flags (OPL2 and OPL3 in OPL2 mode only)
    bit 7  : reset interrupt (RST)
    bit 6  : timer 1 mask (MASK1)
    bit 5  : timer 2 mask (MASK2)
    bit 4-2: reserved
    bit 1  : start timer 2 (ST2)
    bit 0  : start timer 1 (ST1)
 04h    (OPL3 in OPL3 mode only) connection select
    bit 7-6: reserved
    bit 5-0: connection selection
 05h    (OPL3) compatibility register
    bit 7-1: reserved
    bit 0: enable OPL3 mode (NEW), default disabled
 08h    Speech synthesis mode
    bit 7: (OPL2 only) speech synthesis or FM music mode (CSM)
    bit 6: select keyboard split point (SEL/NTS)
    bit 5-0: reserved
 20h-35h Amplitude Modulation / Vibrato
    bit 7: AM modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: sustain (EG)
    bit 4: keyboard scaling rate (KSR)
    bit 3-0: multi (MF)
 40h-55h Level key scaling / Total level
    bit 7-6: key scale level (KSL)
    bit 5-0: total level (TL)
 60h-75h Attack / Decay rate
    bit 7-4: attack rate
    bit 3-0: decay rate
 80h-95h Sustain / Release rate
    bit 7-4: sustain level
    bit 3-0: release rate
 A0h-A8h Octave / Frequency (LSB)
 A9h-AFh ???
 B0h-B8h Octave / Frequency Number
    bit 7-6: reserved
    bit 5  : key on, mute
    bit 4-2: block, octave
    bit 1-0: f-number (MSB)
 BDh    percussion, vibrato, AM    (OPL2, OPL3 in OPL2 mode only)
    bit 7: amplitude modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: ryhthm, percussion on/off (R)
    bit 4: bass drum on/off (BD)
    bit 3: snare drum on/off (SD)
    bit 2: tom-tom on/off (TOM)
    bit 1: top cymbal on/off (TC)
    bit 0: hi hat on/off (HH)
 C0h-C8h Feedback / Algorithm
    bit 7-4: OPL3: channel D-A
    bit 3-1: feedback
    bit 0: connection
 E0h-F5h Waveform Selection
    bit 7-3: reserved
    bit 2  : (OPL3) waveform bit2
    bit 1-0: waveform
SeeAlso: #P251

(Table P251)
Values for Sound Blaster registers inside groups:
Offset
 +00..+02: operators 1-3    modulator channel 1-3
 +03..+05: operators 4-6    carrier channel 1-3
 +08..+0A: operators 7-9    modulator channel 4-6
 +0B..+0D: operators 10-12  carrier channel 4-6
 +10..+12: operators 13-15  modulator channel 7-9
 +13..+15: operators 16-18  carrier channel 7-9
 +06, +07, +0E, +0F: reserved
SeeAlso: #P250
----------P03880389--------------------------
PORT 0388-0389 - Soundblaster PRO FM-Chip
----------P0388038B--------------------------
PORT 0388-038B - Soundblaster 16 ASP FM-Chip
--------s-P0388038B--------------------------
PORT 0388-038B - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
----------P0388038F--------------------------
PORT 0388-038F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    Adlib-compatible, Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 022Fh"soundmachine",PORT 0278h"Covox"

0388  -W  Covox 'speech thing' compatible speech output via printer port?
        enabled if bit 6 set in PORT 038Fh
0388  RW  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster")
0389  -W  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster")
038A  -W  I²C control for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA out (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL out (clock), enabled if bit2=1 in PORT 038Fh
038B  R-  I²C status for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA in (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL in (clock), enabled if bit2=1 in PORT 038Fh
038F  RW  configuration port (power on default=0, all features disabled)
    (see #P252)

Bitfields for mc-soundmachine configuration port:
Bit(s)    Description    (Table P252)
 7    Covox 'voice master' enabled at PORT 022Fh
 6     ""   'speech thing' enabled at PORT 03BCh
 5     ""             enabled at PORT 0278h
 4     ""             enabled at PORT 0378h
 3    not used (0388???)
 2    I²C bus enabled (see PORT 038Ah,PORT 038Bh)
 1    gameport enabled (see PORT 0201h)
 0    AdLib registers (see PORT 0388h,PORT 0389h) enabled
--------s-P038C038F--------------------------
PORT 038C-038F - Pro Audio Spectrum 16 (PAS16)
Range:    PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
      PORT 0388h (default), or PORT 038Ch
----------P03900397--------------------------
PORT 0390-0397 - Sunshine EW-901B, EW-904B
        EPROM writer card for EPROMs up to 27512
0390-0393  ??  adresses of the 8255 on the EW-90xB
----------P0390039F--------------------------
PORT 0390-039F - Cluster adapter (AT)

0390  ??  (adapter 0)    (XT)
0391  ??  (adapter 0)    (XT)
0392  ??  (adapter 0)    (XT)
0393  ??  (adapter 0)    (XT)
----------P03980399--------------------------
PORT 0398-0399 - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 026Eh

0398  -W  index for data port
0399  RW  EPP command data
----------P03980399--------------------------
PORT 0398-0399 - Intel 82091AA Advanced Integrated Peripheral
Range:    PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
      PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 0024h"82091AA",PORT 026Eh"82091AA"

0398  ?W  configuration register index
0399  RW  configuration register data
----------P03A003AC--------------------------
PORT 03A0-03AC - 1st SDLC (Binary Synchronous Data Link Control adapter)
SeeAlso: PORT 0380h"SDLC"
----------P03A003AF--------------------------
PORT 03A0-03AF - 1st BSC (Binary Synchronous Communication) adapter
Notes:    Initialization of the BSC adapter is performed in a typical
      sequence like this: Setup 8255 port A-C configuration by writing
      98h to 383h, followed by initializing 8255 port C by writing 0Dh
      to 382h. Reset 8251A internal registers by pulsing 8255 port B4.
      After this the 8253 has to be programmed to the desired values
      (counter 0 not used, counters 1 and 2 to mode 0). Now, the 8251A
      is ready to be loaded with a set of control words that define the
      communication environment.
    8251A: The control words are split into two formats, mode
      instruction and command instruction. The mode instruction must
      be inserted immediately after a reset operation (via 8255 port B4
      or setting command instruction bit6 to 'internal reset').
      The required synchronization characters are next loaded into the
      8251A (usually 32h for BSC). All control words written to the
      8251A after this will load the command instruction.
         reset -> mode instruction
              SYNC character 1
              SYNC character 2
              command instruction
              data ...
              command instruction
              data ...
              command instruction
              ...
SeeAlso: PORT 0380h"BSC"

03A0  R-   on adapter 8255(A5) port A: internal/external sensing (see #P253)
03A1  -W   on adapter 8255(A5) port B: external modem interface (see #P254)
03A2  RW   on adapter 8255(A5) port C: internal control (see #P255)
03A3  ?W   on adapter 8255(A5) mode initialization
03A4  RW   on adapter 8253 (programmable counter) counter 0:
        LSB / MSB square wave generator (unused in sync mode)
03A5  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
        (connected to 8255 bitA7, IRQ4 level)
03A6  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
        (connected to 8255 bitA6, IRQ4 level)
03A7  ?W   on adapter 8253 mode register (see #P256)
03A8  RW   on adapter 8251: data (see #P257)
03A9  R-   on adapter 8251: command/mode/USART status register (see #P258)

Bitfields for BSC 8255 port A:
Bit(s)    Description    (Table P253)
 7    =1 timer 1 output active
 6    =1 timer 2 output active
 5    =1 TxRDY active
 4    receive clock active (if pulsing)
 3    =0 clear to send is on from interface
 2    transmit clock active (if pulsing)
 1    =0 data carrier detect is on from interface
 0    =0 ring indicator is on from interface
SeeAlso: #P254

Bitfields for BSC 8255 port B:
Bit(s)    Description    (Table P254)
 7    =1 enable IRQ 4 level interrupt (timer 1 and 2)
 6    =1 gate timer 1
 5    =1 gate timer 2
 4    =1 reset 8251A
 3    =1 not used
 2    =0 turn on test
 1    =0 turn on select standby
 0    =0 turn on data signal rate select
SeeAlso: #P253,#P255

Bitfields for BSC 8255 port C:
Bit(s)    Description    (Table P255)
 7 R-    =0 BSC adapter (=1 may be used to detect SDLC??)
 6 R-    =0 test indicate active
 5 R-    timer 0 output (if pulsing)
 4 R-    receive data (if pulsing)
 3 -W    =0 enable timer 1 and 2 IRQ4 and receive IRQ 4
 2 -W    =1 electronic wrap
 1 -W    =1 gate external clock
 0 -W    =1 gate internal clock
SeeAlso: #P253,#P254

Bitfields for BSC 8253 mode register:
Bit(s)    Description    (Table P256)
 7-6    SC1-SC0     00, 01, 10= select counter 0,1,2; 11=illegal
 5-4    RL1-RL0     00= couner latching operation
         01= read/load most significant byte (MSB)
         10= read/load least significant byte (LSB)
         11= read/load LSB first, then MSB
 3-1    M2-M0     000= mode 0 (for counter 1 and 2)
         001= mode 1 (not used for BSC)
         x10= mode 2 (not used for BSC)
         x11= mode 3 (not used for BSC)
         100= mode 4 (not used for BSC)
         101= mode 5 (not used for BSC)
 0    BCD       0= binary counter 16bits
           1= BCD counter 4 decades

Bitfields for BSC 8251 data:
Bit(s)    Description    (Table P257)
---mode instruction (W)---
 7    =0 Double SYNC Character
 6    =1 SYNDET is an Input
 5    =1 Even Parity
 4    =1 Parity Enable
 3-2    Character Length 00=5bits, 01=6bits, 10=7bits, 11=8bits
 1-0    not used (always 0)
---SYNC character 1/2 (W)---
 string of two characters to be sync'ed at (in hunt mode).
---command instruction (W)---
 7    Enter Hunt Mode
 6    Internal Reset
 5    Request to Send
 4    Error Reset
 3    Send Break Character
 2    Receive Enable
 1    Data Terminal Ready
 0    Transmit Enable
---data (RW)---
    any data
SeeAlso: #P256,#P258

Bitfields for BSC 8251 command/mode/USART status:
Bit(s)    Description    (Table P258)
 7    Data Set Ready (indicated that DSR is at 0 level)
 6    SYNDET
 5    Framing Error (not used for synchronous communications)
 4    Overrun Error (OE flag on when Overrun Error occurs)
 3    Parity Error (PE flag on when a parity error occurs)
 2    TxEmpty
 1    RxRDY (causing IRQ 3 level)
 0    TxRDY (has not the same meaning as 8251A TxRDY output pin).
      THIS one is NOT conditioned by CTS and TxEnable (causing IRQ 4 level)
SeeAlso: #P257
----------P03AB------------------------------
PORT 03AB - GI1904 Scanner Interface Adapter
Range:    PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
      PORT 036Bh, PORT 03ABh, PORT 03EBh
----------P03AC------------------------------
PORT 03AC - GS-IF Scanner Interface adapter
Range:    PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
      PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:    many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
      others use this interface
--------V-P03B003BF--------------------------
PORT 03B0-03BF - MDA  (Monochrome Display Adapter based on 6845)

03B0  -W  same as 03B4
03B1  RW  same as 03B5
03B2  -W  same as 03B4
03B3  RW  same as 03B5
03B4  -W  MDA CRT index register     (MDA/mono EGA/mono VGA)
        selects which register (0-11h) is to be accessed through 03B5h
        Note: this port is read/write on some VGAs
        bit7-6: (VGA) reserved (0)
        bit5  : (VGA) reserved for testing (0)
        bit4-0: selects which register is to be accessed through 03B5h
03B5  RW  MDA CRT data register     (MDA/mono EGA/mono VGA) (see #P259,#P286)
        selected by PORT 03B4h. registers 0C-0F may be read
        Color adapters are at 3D4/3D5, but are mentioned here for
          better overview.
        There are differences in names and some bits functionality
          on EGA, VGA in their native modes, but clones in their
          emulation modes emulate the original 6845 at bit level. The
          default values are for MDA, HGC, CGA only, if not otherwise
          mentioned.
03B6  -W  same as 03B4h
03B7  RW  same as 03B5h
03B8  rW  MDA mode control register (see #P260)
03B9  ?W  reserved for color select register on color adapter
03B9  -W  MDA/HGC: set lightpen flipflop (value written is ignored)
        cannot be found on native mono EGA, mono VGA (without
          translation ROM)
03BA  R-  CRT status register (see #P261)
        (EGA/VGA) input status 1 register
03BA  -W  (mono EGA/mono VGA) feature control register
        (see PORT 03DAh-W for details; VGA, see PORT 03CAh-R)
03BB  -W  light pen strobe reset (on any value)

(Table P259)
Values for mono video adapter CRT data register index:
                  defaults:    MDA/HGC    HGC   CGA   CGA      CGA
                         text  graph text1 text2 graph
                           7  720x348  1     3      5,6
 00h    horizontal total              61h    35h   38h   71h      38h
          ET4000: in VGA mode scanlines-5
              in EGA mode scanlines-2
 01h    horizontal displayed              50h    2Dh   28h   50h      28h
          horizontal display end-1 (EGA,VGA)
 02h    horizontal sync position          52h    2Eh   2Dh 5Ah/5Ch 2Dh
 03h    sync pulse width              0Fh 07h/0Fh 0Ah   0Ah      0Ah
           bit7-4 vsync, bit3-0 hsync
          end horizontal blanking (EGA,VGA)
           VGA    : bit7=1      : enable read access to regs
                    10h, 11h (otherwise VGA clones
                    may show lightpen values)
           EGA,VGA: bit6-5=0-3: display enable skew control
            bit4-0      : end blanking
 04h    vertical total (vcycle-1)          19h    5Bh   1Fh   1Fh      7Fh
           bit7 only used on MCGA
          start horizontal retrace (EGA, VGA)
          Genoa SuperEGA only???:
           bit7  : start at odd memory address
           bit6-5: horizontal sync skew
           bit4-0: start retrace+ retrace width
 05h    vertical total adjust              06h    02h   06h   06h      06h
           bit7-5 only used on MCGA
          end horizontal retrace (EGA, VGA)
           bit7  : (EGA) start at odd memory address
               (VGA) bit5 of end horizontal retrace
           bit6-5: horizontal sync skew
           bit4-0: end horizontal retrace
 06h    vertical displayed              19h    57h   19h   19h      64h
           bit7 only used on MCGA
          (EGA) vertical total-1
          (VGA) vertical total-2
 07h    vertical sync pulse width-1          19h    57h   1Ch   1Ch 70h/66h
           bit7  only used on MCGA
          controller overflow (EGA,VGA)
           bit7: (VGA) bit9 of start vertical retrace (10h)
           bit6: (VGA) bit9 of vertical display end (12h)
           bit5: (VGA) bit9 of vertical total (06h)
             (EGA) bit5 of cursor-position (0Ah)
           bit4: bit8 of line compare (18h)
           bit3: bit8 of start vertical blanking (15h)
           bit2: bit8 of vertical retrace start (10h)
           bit1: bit8 of vertical display end (12h)
           bit0: bit8 of vertical total (06h)
 08h    interlace mode (not MCGA)          02h    02h   02h   02h      02h
           bit7-2: reserved
           bit1  : delay
           bit0=1: interlace on
          preset row scan (EGA, VGA)
           bit7  : reserved
           bit6-5: (VGA) byte panning (low-order bits of display start addr
          in odd/even and quad modes
           bit4-0: start row scan after retrace
 09h    maximum scan lines              0Dh    03h   07h   07h      01h
           bit7  : (VGA) double scan active
           bit6  : (VGA) bit9 of line compare (18h)
           bit5  : (VGA) bit9 of start vertical blanking (15h)
           bit4-0: maximum scan line 00..31 (height-1)
 0Ah    cursor start                  0Bh    00h   06h   06h 06h/00h
           bit7  : reserved
           bit6-5: original 6845: cursor on/off, blink interval
               (not on all adapters, as original MDA, CGA have
               extra circuitrity to avoid this!!)
           bit6-5: native EGA: not used
           bit6  : (VGA) not used
           bit5=0: (VGA) cursor on
           bit4-0: first cursor scanline
 0Bh    cursor end                  0Ch    00h   07h   07h 07h/00h
           bit7  : reserved
           bit6-5: EGA, VGA: cursor skew control
           bit4-0: end cursor row
 0Ch RW    start address high              00h    00h   00h   00h      00h
           bit7-6 not used by original 6845 (MDA,HGC,CGA)
 0Dh RW    start address low              00h    00h   00h   00h      00h
 0Eh RW    cursor location high              00h    00h   00h   00h      00h
           bit7-4 not used by original 6845 (MDA,HGC,CGA)
           bit5-4 reserved on MCGA
 0Fh RW cursor location low              00h    00h   00h   00h      00h
 10h R-    light pen high (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 10h R- MCGA at 3D5h only: mode control status register (see #P288)
 11h R- light pen low (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 14h -W HGC+,InColor: xMode register
 15h -W HGC+,InColor: underscore register
 16h -W HGC+,InColor: overstrike register
 17h -W    InColor: exception register
 18h -W    InColor: plane mask register
 19h -W    InColor: read/write control register
 1Ah -W    InColor: read/write color register
 1Bh -W    InColor: Latch Protect register
 1Ch RW    InColor: palette register
Notes:    registers 10h and 11h have varying uses on VGA (see #P286) and
      MCGA (see #P287)
    MDA, HGC, CGA: 6845 registers 00h-0Dh are write only, 0Eh, 0Fh
           are r/w, and 10h-11h are read only.
           The alternative initial defaults may be used
           sometimes on modern adapters.
    HGC+(RamFont): as with HGC, but 3 additional registers for font control
    emulations   : more registers may be r/w, but most often it's the
           same as with native 6845.
    MCGA (CGA+)  : Though this is a mixture of CGA and VGA, most
           registers are same as with CGA, but with some
           enhancements and incompatibilities to EGA, VGA.
    native EGA   : registers 00h-0Bh are write only, 0Ch-0Fh are
           r/w, 10h-11h are read/write, 12h-18h are write
           only. More regs may be r/w on enhanced clones.
    GenoaSuperEGA: adapter with chips SEQCRT GN006001 and GRAT
           GN006002, e.g. c't Super-EGA adapter. Is EGA
           clone with up to 800x600 and full 6845 emulation.
    native VGA   : all registers 00-18h are r/w, but 00h-07h are
           write-locked if bit7 in 11h is set.
    ET4000         : same as VGA, but with additional r/w registers
           32h-37h, protected by 'key' except 33h, 35h
           (see 3BFh for details). 35h is protected by
           bit7 in 11h. The 'key' must be issued at least
           after each power on or synchronous reset.
SeeAlso: #P286,#P287,#P260,#P261,#P287

Bitfields for mono video adapter mode control register:
Bit(s)    Description    (Table P260)
 7 not used by MDA, page number on HGC
 6    not used
 6  R-O    (mono ET4000 only) report status of bit 1 (enable 2nd page) of
      Hercules compatibility register (PORT 03BFh)
 5    enable blink (0 = intense background, 1 = blink)
 4    not used
 3    video enable
 2    not used
 1    (MDA) not used
    (HGC) graphics enable
    the 6845 has to be reprogrammed completely, if this bit is
      changed, otherwise the TTL-monitor may be damaged by wrong
      sync impulses!
 0    high resolution mode (always set on MDA)
---mono ET4000 only, W-O ---
 7-0    =A0h: second part of 'key', see Hercules compatibility register
      (PORT 03BFh) for details
Note:    this port might be completely or partially readable on very few MDA,
      HGC clones or emulations (e.g. Genoa SuperEGA), but not with the
      majority of original and clone chips.     It cannot be found on
      native mono EGA, mono VGA, but on most clones, where it is usually
      R/W.
SeeAlso: #P259,#P261

Bitfields for mono video adapter CRT status register:
Bit(s)    Description    (Table P261)
 7    HGC: vertical sync pulse in progress
 6-4    adapter identification
    (MSD says) if bit 7 changes within 8000h reads then
        =000 adapter is Hercules or compatible
        =001 adapter is Hercules+
        =101 adapter is Hercules InColor
        else: adapter is unknown
 6-4    =111 on MDA and some HGC clones
 5-4    (mono EGA, mono ET4000) diagnose video display feedback
    select from color plane enable
 3    (MDA,HGC) pixel stream (0=currently black, 1=currently white)
    (mono EGA, mono VGA) vertical retrace in progress
 2-1    (MDA) reserved
 2    (HGC, mono EGA) lightpen flipflop set
    (mono ET4000) reserved (0)
 1    (HGC) lightpen input stream (if set, current value to get from
      PORT 03B5h registers 10h-11h)
    (mono ET4000) reserved (0)
 0    horizontal drive enabled
SeeAlso: #P259,#P260

Bitfields for EGA,VGA mode control register:
Bit(s)    Description    (Table P262)
 7    0=CRTC reset and stop, 1=resume reset
 6    0=word-mode, 1=byte-mode (VGA: see 14h, bit6)
 5    0=14bit, 1=16bit address wrap
 4    (native VGA only) reserved (0)
 4    (EGA and most VGA clones) output control
    0: video driver active
    1: video driver not active
 3    linear address counter clock (0 = standard, 1 = clock/2)
    (VGA: see register 14h, bit 5)
 2    horizontal retrace clock (0 = standard, 1 = clock/2)
 1    row scan counter
    0: address bit 14 = scan bit 1
    1: address bit 14 not altered
 0    6845 compatibility mode
    0: address bit 13 = scan bit 0 (as with 6845)
    1: address bit 13 not altered
SeeAlso: #P259
--------P-P03BC03BF--------------------------
PORT 03BC-03BF - PARALLEL PRINTER PORT (MDA's LPT1)
Range:    PORT 0278h, PORT 0378h, or PORT 03BCh
SeeAlso: MEM 0040h:0008h

03BC  -W  data port
03BC  R-  bidirectional port: input from connector
      unidirectional port: last value written to port
03BD  R-  status port (see #P263)
03BE  RW  control port (see #P264)

Bitfields for parallel interface status port:
Bit(s)    Description    (Table P263)
 7    busy
 6    NOT acknowledge (approx. 5us low pulse)
 5    out of paper
 4    printer is selected
 3    *no* error
 2    IRQ has *not* occurred
    (PS/2) printer returned -ACK
 1-0    reserved
Note:    if bit 2 is clear (i.e. an interrupt has occurred), it is set again on
      reading the status register
SeeAlso: #P264

Bitfields for parallel interface control port:
Bit(s)    Description    (Table P264)
 7-6    reserved
 7    (see PORT 037Bh bit 7)
 5    (PS/2) enable bidirectional port
    (also requires enabling via PORT 0102h)
 4    enable IRQ (via -ACK)
 3    select printer (SLCT IN line)
 2    =0 initialize printer (-RESET line)
 1    automatic line feed
 0    strobe (must be set for minimum of 5 microseconds)
SeeAlso: #P263
--------V-P03BF------------------------------
PORT 03BF - Hercules configuration switch register
Note:    can also be found on EGA and VGA clones in Hercules emulation

03BF  -W  configuration switch register (see #P265)
03BF  -W  (ET4000) Hercules compatibility register (see #P266)
03BF  RW  (Genoa SuperEGA) miscellaneous register
    Note: only available in MDA, HGC, and CGA emulation; should be
      compatible with Hercules configuration register, but may contain
      additional features

Bitfields for Hercules configuration switch register:
Bit(s)    Description    (Table P265)
 7-2    reserved
 1    =0  disables upper 32K of graphics mode buffer
    =1  enables upper 32K of graphics mode buffer
 0    =0  prevents graphics mode
    =1  allows graphics mode
SeeAlso: #P266

Bitfields for ET4000 compatibility register:
Bit(s)    Description    (Table P266)
 1    =0 disables upper 32K of graphics mode buffer
    =1 enables upper 32K of graphics mode buffer
 0    reserved (not needed for HGC graphics)
 7-0    =03h: first part of 'key' for access to some extra
         ET4000 regs. To issue the 'key', the following
         code must be executed:
          MOV DX, 3BFh
          MOV AL, 3
          OUT DX, AL
          MOV DX, 3D8h  (3B8h in mono mode)
          MOV AL, 0A0h
          OUT DX, AL
SeeAlso: #P265
---------------------------------------------