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256 kB memory expansion for Commodore 64 Pekka Pessi <Pekka.Pessi@HUT.FI> Marko MΣkelΣ <Marko.Makela@Helsinki.FI> January--February, 1987 July 3rd, 1993 (*) Commodore 64 becomes remarkably more efficient by adding memory to it. Then the worst slow-down, incredibly slow disk drive, can be worked around by using a part of the memory as a RAM disk. In 1986, when the original article was written, there were no commercial memory extensions for sale in Finland. (Commodore's RAM Expansion Units came to our market in the year 1987.) Of course there were some in the USA, but they were quite useless, as they had only 64 kB of memory, and the price was high as well. When built by oneself, the following memory expansion should have costed 300--400 Finnish marks. One American dollar (USD) is equivalent to five or six Finnish marks (FIM). I constructed my expansion in 1993 March, and it costed 111 FIM. It could easily have been about 20 FIM cheaper. Many goals were set to the expansion. As many programs as possible should work also with it installed. This means that there could not be any radical changes to the memory map. The memory space of an expanded machine really remains same for a usual programmer. After reset, the computer doesn't differ from an unexpanded one practically at all. Even taking a look at the machine from outside doesn't reveal the expansion, as Pekka needed the expansion port for his IEEE-488 interface module, also designed by himself. The memory expansion is built in the machine on two add-on cards. As the mother board remains the same --- no traces are cut --- the expansion can be removed without a soldering iron. The design aimed to a hardware that supports programming. While making the RAM disk program, Pekka changed the hardware several times, until he was satisfied with it. --- * This document is based on Pekka Pessi's two articles published in the largest Nordic and Finnish home computer users' magazine, MikroBITTI, in its first two issues of the year 1987. Six years later, it was translated to English and edited by Marko MΣkelΣ, with help from Pekka Pessi. You can retrieve this document in PostScript format via anonymous FTP. The files are at FUNIC.FUnet.FI in the directory /pub/cbm/documents/256kB. Contents 1 Some basics 1.1 Expansion memory in 16 kB blocks 1.2 Memory chips 1.3 Dynamic headaches 1.4 Memory refresh 2 Building the expansion 2.1 Removing the old memory chips 2.2 Adding the new address line 2.3 Prepare to the final step 2.4 Testing 3 Using the expansion 3.1 The operation of the bank switcher 3.1.1 PIA's location in memory space 3.1.2 Block selection 3.1.3 Startup settings 3.2 Segmented memory 3.3 Critical addresses 3.4 Initializing the expansion 3.5 Programming in machine language 3.5.1 An exception: VIC memory 3.6 Programming in BASIC 4 Programming examples 4.1 Processing a huge array 4.2 Storing graphics 5 RAM disk and other programs 5.1 Memory test 5.2 Poor man's multitasking 5.3 Machine language monitor 5.4 RAM disk 5.4.1 Disk copiers 6 Other expansions 6.1 New operating system 7 Contacting the authors 1 Some basics 1.1 Expansion memory in 16 kB blocks The processor of Commodore 64, MOS 6510, is a 8-bit one, and its address bus is 16 bits wide. As other 8-bit processors, it can address only 64 kB of memory at a time. In the most 8-bit computers, the memory is limited to these 64 kB. How could one add memory above this limit? The solution is simple: the memory is divided into banks of not more than 64 kB, which are switched on and off. Some processors have been added a special circuit for this purpose, in which case the executing program can be in its own 64 kB block and the processed data in another block. For example, MOS 6509, a fellow processor of MOS 6510, works in this way, enabling access to one megabyte. After trial and error Pekka decided to divide the extended memory to sixteen blocks of sixteen kilobytes each. The processor can address four of them at a time. Every four 16 kB segment of the memory space can be mapped to any 16 kB block. Figure 1 shows the mapping right after startup. A similar memory mapping is in MSX II computers. However, the video chip VIC -- MOS 6567 (6566 for NTSC) -- retrieves its data from the memory outside the normal bus. The internal address registers of VIC are 14 bits wide, so it can address only 16 kB without external logic. The required two extra bits for accessing 64 kB are provided from the second CIA chip. The extra logic provides additional two address bits for accessing the whole 256 kB of memory. 6510's RAM RAM pool VIC's RAM +--$10000 --+ +-- $40000 --+ +--$10000 --+ | | /--->| Segment F |<---\ | | | Block 3 |-/ +-- $3C000 --+ \-| Block 0 | | | /--->| Segment E |<---\ | | +-- $C000 --+ | +-- $38000 --+ | +-- $C000 --+ | | |/-->| Segment D |<--\| | | | Block 2 |-/ | +-- $34000 --+ | \-| Block 1 | | | |/->| Segment C |<-\| | | +-- $8000 --+ || +-- $30000 --+ || +-- $8000 --+ | | || | Segment B | || | | | Block 1 |--/ | +-- $2C000 --+ | \--| Block 2 | | | | | Segment A | | | | +-- $4000 --+ | +-- $28000 --+ | +-- $4000 --+ | | | | Segment 9 | | | | | Block 0 |---/ +-- $24000 --+ \---| Block 3 | | | | Segment 8 | | | +-- $0000 --+ +-- $20000 --+ +-- $0000 --+ | Segment 7 | +-- $1C000 --+ | Segment 6 | +-- $18000 --+ | Segment 5 | +-- $14000 --+ | Segment 4 | +-- $10000 --+ | Segment 3 | +-- $0C000 --+ | Segment 2 | +-- $08000 --+ | Segment 1 | +-- $04000 --+ | Segment 0 | +-- $00000 --+ Figure 1. Memory mapping right after power-up 4164 41256 +--------+ +--------+ NC | 1 \/ 16| VSS MA8 | 1 \/ 16| VSS D | 2 15| -CAS D | 2 15| -CAS -W | 3 14| Q -W | 3 14| Q -RAS | 4 13| MA6 -RAS | 4 13| MA6 MA0 | 5 12| MA3 MA0 | 5 12| MA3 MA2 | 6 11| MA4 MA2 | 6 11| MA4 MA1 | 7 10| MA5 MA1 | 7 10| MA5 VDD | 8 9| MA7 VDD | 8 9| MA7 +--------+ +--------+ Figure 2. The Dynamic Random Access Memory Chips 4164 and 41256 1.2 Memory chips Commodore 64 uses 64 kb dynamic RAM chips of JEDEC standard. In 1982, when the Commodore 64 was introduced, they were most modern technology, they needed only one operating voltage supply instead of traditional three. The semiconductor memories have developed fast, however, and now a chip in a DIP of equal size can hold 256 kilobits. The pinout of these 256 kb chips differs minimally from the 64 kb ones. The smaller 64 kb chips, at least the ones used in Commodore 64, have one unused contact. The address line to handle three times bigger memory is tied to this pin. In the DRAMs the address lines are multiplexed: two address bits use successively the same pin. In the MikroBITTI article Pekka wrote that 256 kb chips are rather cheap, and the price would lower as the production rate increases. Nowadays the production must have almost stopped. When Pekka bought his chips between March and April of 1986, they costed about 50 FIM each. When the original article was published, they costed less than 20 FIM. After that the prices rised due to a memory shortage. But nowadays the chips don't cost practically anything, if you're lucky. Many users of IBM PC compatibles want to upgrade their system memory with 1 Mb chips or alike and would like to get rid of their old 256 kb chips. I bought my chips second-hand with total 35 FIM. The lowest price of unused chip I encountered was 13 FIM a piece and the highest was 30 FIM, almost 8 times the price I paid! The 256 kb chips don't consume significantly more power, so there is no need for a bigger power supply. However, devices that take their power directly from the computer can cause problems. You can find this out by experimenting. The speed of the chips doesn't prevent the replacement either. According to the Commodore 64 Programmer's Reference Guide, the computer can use chips with access time of 200 nanoseconds. Even the slowest 256 kb dynamic RAMs are not that slow. However, the bypass capacitors near the memory chips should be replaced with bigger ones. The 100 nF capacitors specified in the original Commodore schematic diagram would be big enough. All shipped units seem to be equipped with only 10 nF capacitors. (My machine works well, even though I haven't replaced any capacitors.) 1.3 Dynamic headaches The dynamic RAM chips are organized in rows and columns. In 64 kb chips, a row is 256 bits wide, and in 256 kb ones it is 512 bits wide. Also the memory address is divided into row and column addresses. When we access a bit in the dynamic RAM, the row address is asserted before the column address. Fortunately the VIC chip generates needed -RAS (Row Address select) and -CAS (Column Address Select) timing signals from the DOTCLOCK and PhiCOLOR signals. 1.4 Memory refresh A dynamic memory chip stores the data bits as charged tiny capacitors, which discharge among the time. The data must be refreshed periodically, every 2--4 milliseconds, by recharging the capacitors. If the whole contents of the memory was refreshed simultaneously, the power peak would cause enormous problems. Only a block of one or two rows can be refreshed at a time. The 64 kb chips have 128 blocks to be refreshed, which implies a 7-bit refresh counter (2^7 equals 128). In order to avoid disturbance, 256 kb chips must have more blocks. Thus they require a longer refresh counter (8 bits). As the amount of refresh cycles has increased, the capacitors' ability of keeping charge has been improved. The 64 kilobit DRAMs required 128 refresh cycles every 2 milliseconds, now the 256 kb chips need 256 cycles but every 4 ms. 2 Building the expansion Remember that the warranty expires if you start modifying the connections. If the warranty is still valid, consider and reconsider, before you expand the memory. You are doing the expansion at your own risk, we disclaim any warranties. You should have basic skills in electronics. A termostate soldering iron, desoldering pump or other desoldering tool, a screwdriver and a spoon are the only tools needed. The spoon is for removing the chips. A bottle top remover is not suitable for that. A tiny screwdriver is equally good. Just insert the screwdriver tip under one end of the chip and wound it a bit in upward angle so that the chip moves slightly. Then insert it to the other end of the chip and try to lift it a bit. You may have to repeat this procedure. There are two PC (printed circuit) boards. They are single-sided and relatively simple. The board A should suit all machines, also the new 64C. There is at least one new 64C board model which the boards do not suit directly. In addition to that, the new 64s may use so heavily integrated circuits that even modifying the add-on board layout slightly would not work. Board B1 is for rather new machines, whose serial number is between 250 000 and 2 000 000. The other board B2 is for old machines with an old motherboard and a serial number usually less than 100 000. Such machines have usually been purchased in the beginning of 1983 or before that. If neither board suits, the board B can be easily made from a Vero board, as it is so simple. I used a single board, although the `new' board would have suited well; the need for board B was eliminated by bending some feet of U13 and connecting wires from the other board directly to U12, U13 and U15. Even board A can be made from a Vero board, as we have done. But be careful, an uncoppered Vero board is not so solid. Every time you open the cover, some wires may get loose. I have had to re-solder many wires, almost every time I have opened the lid. Soldering with plenty of solder ought to cure this, but be careful to avoid short circuits. The installation begins of course by opening the machine and removing the keyboard and LED cables. It is useful to memorize, photograph or draw how the parts were initially connected. After removing the cables, open the screws that hold the motherboard with the case, and remove the board. 2.1 Removing the old memory chips First you have to remove the memory chips U9, U10, U11, U12, U21, U22, U23 and U24. They are of type 4164 (or 6665 or 6664 or 8064 or...). Open your machine and take a look at its mother board, as if you were typing. The board A is installed on the top of U2, a MOS 6526 CIA chip, the second chip at rear left. The memory chips are the rightmost eight of the ten leftmost small chips at the front of your computer. The board B is placed on U12, U13 and U15, which are at the right of the RAM block. If these memory chips are already on sockets, the most of the work is done for you. It helps a lot, if you remove the bypass capacitors before removing the chips. You should replace them with bigger ones, even with tantal capacitors. Removing the components is easiest with a desoldering pump. It becomes even easier, when you first solder the pins with fresh solder, so that the hartz from it makes the removal of old solder easier. Using much power is questionable, as the copper folio comes off the board in a surprisingly easy way. After you have removed the 4164s, you can solder the 16-pin sockets into their places. You can solder the capacitors back as well, if you removed them. 2.2 Adding the new address line You must connect the pin 1 of each memory chip socket. It is the extra address line (MA8) to the switcher. The best way is to solder a Wire-Wrap wire to each contact under the mother board, but any thin and pliable uni-strand wire should do. The wire does not affect in any way the computer's operation with 64 kb chips. After the pins have been connected together, they must be temporarily connected to +5 V, which is in the pin 8 of the memory chips. Comparing to TTL chips, the operating voltages are `reversed' in dynamic memories. Now the new 256 kb memory chips can be installed to the sockets (preferably right-side forward), and you can try switching the power on. 2.3 Prepare to the final step You do not have to connect anything except the power cable and the cable to the TV set or monitor. If the screen shows up normally, you may not (yet) have made any mistakes. If it does not show up at all, you have to find possible cut-outs and shorts. Multi-colored `@'s show up usually because of too small bypass capacitors. Another cause is that the pin 1 is not connected to +5 V. In this case the screen may come up normally, but a little disturbance in the operating voltage locks the computer locks up. Next you remove U13 (74LS257), U15 (74LS139) and U2 (M6526). Some of these chips may already be on sockets but you must remove the rest. After this step reinsert the chips and check if the machine boots up. On the Board A the chip U2 (M6526) and on Board B chips U12 and U15 can be installed into Wire-Wrap sockets. With them you can connect the chips to the motherboard handily and easily. The chip is then put in the socket, and it is on its normal place, although one and a half centimeters higher. However, inserting a Wire-Wrap socket in a normal socket destroys it so that you cannot insert a normal chip there any more. If you want to make your board removable, you would better use piggyback sockets everywhere. Piggyback sockets are a kind of IC sockets which have pins on both sides. You can insert other pins to the socket on the motherboard and solder another pins to the daughterboard. U13 is put on a normal socket, and a 16-pin piggyback socket is installed next to it so that the pins of the piggyback socket reach the socket that is on the motherboard. The boards can be connected together with a fixed cable, but the best way is using flat ribbon cable and connectors. (The worst way to use stiff uni-strand wires, as I did.) 2.4 Testing After you have installed the boards to your machine, it is time to test the connections. You can connect LED, keyboard and probably disk drive in addition to the power cable and the TV cable, but do not fasten the mounting screws yet. If the screen shows up and if the machine seems to operate, remove the jumper between MA8 and +5 V. Then you can input the following test program: 10 PB=57282 20 POKE PB,255:POKE PB+1,4:POKE PB,255 30 PRINT"PRESS A KEY AFTER THIS HAS DISAPPEARED": FOR I=0 TO 3000:NEXT 40 POKE PB,14:WAIT 198,15:GET A$:POKE PB,255 On the line 10 a variable PB is set up. It is the address of 6821's port B's peripheral register, data direction register, and the block selection register of segments 2 and 3 and VIC. The line 20 contains initialization of PIA: the lines PB0--PB7 are set outputs, the data direction register is switched to data register with `POKE PB+1,4', and the PB lines are set high. On the line 40 VIC is given block 0 ($00000--$0FFFF), and then the program waits for a keypress and restores the block F ($30000--$3FFFF). If this test program works as expected, the screen is filled with `@'s and other random characters. After this test you may want to run the `TEST' program among the distribution files. (See Section 5.1.) 3 Using the expansion 3.1 The operation of the bank switcher There are four new micro chips in the memory expansion. The most important of them is the PIA chip MC6821, which holds the values of block selections. PIA has two 8-bit ports set up in the addresses 57280 and 57282. The upper and lower four bits (nybbles) of each port determine, which 16 kB block is mapped to each 16 kB segment of C64's memory space. IC2 and IC3 participate in forming the memory block control signals. There is a chip equivalent to PIA even in the processor's own 6500 series, but it is not suitable for this connection, as it is not TTL compatible. The 6821 from Motorola 6800 series, which contains also processors reminding the 6502 and 6510, is bus compatible and suitable for this purpose. Commodore 64 asserts the 16 bit addresses to the original 64 kb chips in two parts. First it asserts the lower eight bits, then the higher eight. The 256 kb chips require two additional address bits, so the chips are given nine bits at a time. Due to this address multiplexing the block selection bits cannot be directly input to the memory chips, but they must be lead through the multiplexer circuitry of IC2, IC3 and U13. IC4 contributes to the operation during power-up. It ensures that C64 gets reasonable memory banks to its different segments. In the beginning the segments are filled with four upmost memory banks. 3.1.1 PIA's location in memory space PIA's data bus and E, -RESET and R/-W signals have been connected directly to the processor chip. (Pekka had made a prototype of board A that interfaces to the 6510 chip instead of the 6522.) Similarly are the RS0 and the RS1, which select a PIA register, connected to A0 and A1. The I/O block decoder (U15) tells us when the second I/O block is selected. This block resides in the area $DF00--$DFFF. The signal -I/O2 is connected to PIA's chip selection pin -CS, and it forms most of PIA's addressing. The address lines A6 and A7 limit PIA's area in I/O2 to $DFC0--$DFFF, because they are tied to CS pins. 3.1.2 Block selection As the memory space has been divided to four blocks of 16 kB, the A14 and A15 cannot be lead directly to the memory chips, but they participate in the block selection. These two address bits determine which of the four blocks is in use. For each block, the PIA ports tell which memory bank to map. Original A14 and A15 are connected to IC2 and IC3, which select the right output lines of PIA. For each 16 kB segment there are 4 output lines which form the block address for the segment. IC2 selects two lowest bits of the block address and feeds them to the address multiplexer chip U13 as B14 and B15. They are practically equivalent to the A14 and A15 signals. After the address bits A0--A7 have been asserted during the first addressing cycle, IC2 asserts B14 and B15 during the second (CAS) cycle. The 256 kb memory chips still need two extra address bits. The expansion must multiplex them with IC3, which is a `one-of-eight' multiplexer. Its eight inputs are tied to the two upmost bits of the four block addresses. A14 and A15 are connected to the IC3, but it needs yet another control signal to handle all eight input bits. This signal is -CAS, which controls multiplexing other address bits (MA0--MA7) as well. While the -CAS signal is low and the memory chips are fed the lowest bits (A0--A7) of the address, the IC3 selects the third bit of the block address determined by A14 and A15. This bit is called address bit A16, and it is asserted to the `extra' address line MA8 simultaneously with the lowmost bits. When -CAS is high, the upper address bits are fed, and IC3 selects the fourth bit of the block address determined by A14 and A15. It corresponds to the address bit A17 and is fed through the same MA8 during all the other upmost bits. The resistor on MA8 line protects IC3, because the inputs of dynamic memories are not fully TTL compatible. 3.1.3 Startup settings In order to enable the operation of the machine, each of the four segments must be mapped to a unique memory bank. The Commodore 64 tests the lowmost continuous area of writeable memory and would hang up, if the same bank was mapped to both $0000 and to $4000, for instance. Modifying the startup routines would cure this problem, but in that case the Kernal ROM chip should be changed. The bootup state can be achieved otherwise. -RESET signal sets all the PIA port lines to inputs. As input a line has an impedance of several megaohms. A TTL chip reads such a signal as a logical `1'. IC4 can force four bank selection pins (PA0, PA1, PA5 and PB0) low, so that the memory segments of C64 point to the four upmost memory banks in ascending order. The port A contains the bits 1101 1100 and the port B 1111 1110. As the IC4 has open collector outputs, it doesn't disturb the port's operation when outputting high state. That is why the initialization routines (see Section 3.4) write the value 52 to the address 57281, which forces the IC4 outputs high by lowering the CA2 line. 3.2 Segmented memory The memory space of Commodore 64 consists of four 16 kB segments: $0000--$3FFF, $4000--$7FFF, $8000--$BFFF and $C000--$FFFF. An expanded C64 uses the topmost four 16 kB banks after startup. It considers them as its whole world and does not know anything of the other memory banks. Figure 1 describes the situation. A total of twelve memory banks are left out of the 64's world. With expanded memory we can cheat the C64 by POKEing a suitable number to a known address to consider the lowmost block as the second segment, for example. Then all the operation that the C64 does at the second segment's area alter in fact the lowmost bank, although the Toad has no idea of it. This is the idea behind the whole expansion circuit. What is the benefit of it? The second segment (segment 1) is actually a good example of the function, because it resides in the middle of the RAM reserved for BASIC programs. If we make a little BASIC program that holds an array exactly in the third segment, we can switch another memory bank to that area while the program is running, and we have another 16 kilobytes to expand our table. In this manner all the free memory banks (12 * 16 kilobytes) can be taken in use, and the memory holds enormous arrays, which can be accessed simply by switching the memory bank. See Example 4.1 for an example of this technique. Another and more useful way to exploit the extra banks is to keep them as a RAM disk. A RAM disk means that you can copy even a whole disk to these banks and consider it as a new disk drive, from which you can load program and data at a very fast speed. For a RAM disk you need a smart program that redirects disk commands and executes them on the expanded memory. (See Section 5.4.) 3.3 Critical addresses The critical addresses of the device are 57280--57343 ($DFC0--$DFFF). There is the PIA chip to which you POKE the values to switch memory banks. The PIA does not have 64 registers, as one might think. There are sixteen copies of its 4 addresses in that memory area. For instance, the addresses 57280, 57284, 57288 and 57340 are equivalent to each other. 57280 is a memory place whose lowmost four bits (bits 0--3, low nybble) determine, which of the sixteen memory banks is accessed through the lowmost segment (segment 0) of Commodore 64. The upper four bits (bits 4--7, high nybble) specify, which of the banks show up at the second segment (segment 1). In a similar manner the low nybble of the address 57282 determines which bank resides at segment 2, and the high nybble tells the bank addressed via the upmost segment. These addresses have even another function. They can act as data direction registers as well, i.e. tell if the port lines are inputs or outputs. However, this application uses only some of the PIA's characteristics. For normal operation, all the port lines should be set to outputs. The function of these addresses depend on the bit 2 of the next address. For instance, the function of 57280 is defined with the address 57281. If you POKE there a value with its third bit set, the values written to 57280 will go to the data direction register. Inputs have the corresponding data direction register bits reset, and outputs have them set. See Tables 1--4 for a complete description of PIA registers. 3.4 Initializing the expansion Before using the expansion memory, you have to first initialize the PIA. Every time when a -RESET is issued, the PIA registers change to the default state. (See Section 3.1.3.) In the beginning of your program you will initialize the PIA registers so that the default memory banking remains: pia .equ $DFC0 LDA pia+1 ; Select Peripheral Registers ORA #4 STA pia+1 TAX LDA pia+3 ORA #4 STA pia+3 TAY LDA #$FE ; Set the default memory bank data STA pia LDA #$DC STA pia+2 TXA ; Select Data Direction Registers AND #$FD STA pia+1 TYA AND #$FD STA pia+3 LDA #$FF ; Set the ports to output STA pia STA pia+2 TXA AND #$C7 ORA #$30 ; Set CA1 and STA pia+1 ; select Peripheral Registers STY pia+3 You may want to use an array instead. That will save both space and processing time but lose generality. Someone may have CA1, CB1 and CB2 in use (see Section 6), and changing all the command register bits would cause side effects. However, here is a BASIC example of using an initialization table: 10 PIA=57280 20 FOR I=11 to 1 STEP -1:READ A:POKE PIA+I,A:NEXT 30 DATA 4,254,4,220,0,255,0,255,4,254,52 3.5 Programming in machine language Think it in hexadecimal numbers. There are sixteen memory blocks, numbered from 0 to F. The address $DFC0 holds two hexadecimal digits. The less significant digit, the one at right, selects the memory block for the segment 0 ($0000--$3FFF), whereas the other digit is for segment 1. The other important PIA address, $DFC2, selects the banks for segments 2 and 3 with is low and high nybble, respectively. For instance, if you want to switch bank E ($38000--$3BFFF) to segment 1, initialize the PIA and execute the following. Note that your program must run outside segment 1 ($4000--$7FFF). pia .equ $DFC0 LDA pia ; Segments 0 and 1 AND #$0F ; Preserve segment 0 ORA #$E0 ; Select bank E for segment 1 STA pia If you used our initialization routine before this, the memory areas $4000--$7FFF and $8000--$BFFF should now mirror each other. This is an easy way to peek under ROMs and I/O with a simple machine language monitor that does not play with the 6510's I/O registers to switch ROMs and I/O temporarily out. 3.5.1 An exception: VIC memory As the video chip's address bus is only fourteen bits wide, it can access only sixteen kilobytes directly. The two additional lines needed to address 64 kB are provided by the second CIA. Its lines PA1 and PA0 are the inverse of VIC's address lines VA15 and VA14. The VIC needs another two address lines to see full 256 kB of RAM. The PIA lines PB7 and PB6 (the uppest two bits of $DFC2) serve as VA17 and VA16. So, the VIC memory does not necessarily have to be accessible to 6510, but there is a restriction: As the bank selector for the upmost segment uses the same two lines, both the VIC bank and the bank for segment 3 cannot be chosen freely. For instance, if you want the VIC to `see' its RAM at $04000, the lines VA17--VA14 must be `0001'. You can select only banks 0--3 for segment 3 to fulfill this condition. Let's assume that you want bank 2 to be mapped there: cia2 .equ $DD00 pia .equ $DFC0 LDA cia2+1 ; First set the CIA2 lines ORA #$03 ; PA0 and PA1 to output. STA cia2+1 LDA cia2 ; Then set PA1 and reset PA0. AND #$FC ; Remember, the lines VA15 and VA14 ORA #$01 ; are the inverse of them. LDA pia+2 ; Segments 2 and 3 AND #$0F ; Preserve segment 2 ORA #$20 ; Select bank 2 for segment 3 STA pia+2 If you want the video bank selection to work as usually, you have four alternative memory bank configurations. The addresses $DFC2 and $DFC0 must contain one of the words $FEDC, $BA98, $7654 and $3210. You can use the expansion to debug or examine programs that occupy full 64 kilobytes of memory. When you issue a -RESET, the program's memory will remain totally unaltered, if it is outside the topmost four blocks. There is no need for a `freezer' cartridge. 3.6 Programming in BASIC With BASIC the use of the extra memory is a bit limited. In the upmost segment (segment 3) there is operating system ROM, under which you can place different memory banks, but reading them with BASIC is naturally impossible. However, in some cases writing data to this segment partially under Kernal ROM and I/O area may be a working solution. The lowmost kilobytes are free RAM, and it can be utilized by switching memory banks. But the benefit of the extra memory lowers, as you can use only the lowmost four kilobytes of each bank. You can read and write the area $C000--$DFFF of this segment using BASIC. Accessing the area $D000--$DFFF without machine language is tricky but possible. The highest segment but one, segment 2, is halfly under BASIC ROM, and only its lower half can be freely used. (You can always write under ROM.) When utilizing it, you have to take in consideration that those 8 kilobytes can be under a ROM module, if one is connected, or they could hold some of the variables and tables that are stored in the top of the BASIC memory. You have to construct your programs so that they do not collide with the segment's area. The lowmost segment, segment 0, contains Kernal's and BASIC interpreter's system variables. Normally you cannot change its contents, since the operating system would not find its status information. This can be worked around by copying those vital bytes to the new memory bank and switching the bank with a machine language routine. The only segment that can be wholly used with plain BASIC is the segment 1, the second one from the bottom ($4000--$7FFF). It resides in the middle of the space reserved for BASIC programs. If you construct your BASIC programs wisely, that is short enough, and ensure that the information used by BASIC are located exactly on this area, you can switch the banks in this segment freely and keep even all the twelwe extra banks as a huge data storage. Example 4.1 shows how you can create a table on this area and keep its data simultaneously in all the extra memory banks. 4 Programming examples 4.1 Processing a huge array 10 I=0:J=0:K=0:A=0 20 DD=56576:PIA=57280 30 FOR I=11 TO 0 STEP -1:READ A:POKE PIA,A:NEXT 31 DATA 4,254,4,220,0,255,0,255,4,254,52,220 40 K=16384-7:POKE 47,K AND 255:POKE 48,K/256: POKE 49,K AND 255:POKE 50,K/256 50 DIM A%(8191) 60 FOR I=0 TO 15:POKE PIA,I*16+12 70 PRINT I":";:FOR J=0 TO 9:PRINT A%(J),:NEXT:PRINT:NEXT 80 POKE PIA,220:END The program displays ten first integers of each memory bank. The table it reserves fills the whole segment 1, because each integer (notice the % sign) takes two bytes and 8192 of them are reserved. The contents of the table A% can be changed to another memory bank by simply POKEing PIA's corresponding register. On the line 40 the table is ensured to start at $4000 by changing the start and end addresses of tables in the addresses 47--50. Saving the name, size and dimensions of the table takes the seven bytes, which are subtracted from the start address. Reserving the table to an arbitrary address has its drawbacks. The size of the program and its variables may not exceed 14 kilobytes so that they could fit to the memory before the beginning of the table. All variables must definitely be declared before allocating the table. If you do not declare them by giving them a value, the interpreter finds really exotic values for them or transfers the table off its position. 4.2 Storing graphics 10 I=0:J=0:A=0:A$="" 20 DD=56576:PIA=57280:V=53248:COLOUR=50176 30 FOR I=11 TO 0 STEP -1:READ A:POKE PIA,A:NEXT 31 DATA 4,254,4,220,0,255,0,255,4,254,52,220 40 POKE V+24,16+8:POKE V+17,59 50 FOR I=0 TO 11:POKE PIA+2,I*16+14: POKE DD,PEEK(DD) AND 252 OR (NOT I AND 3) 60 FOR J=0 TO 999:POKE J+COLOUR,3:NEXT 70 GET A$:IF A$="" THEN 70 80 NEXT I 90 POKE PIA+2,254:POKE DD,PEEK(DD) OR 3: POKE V+24,23:POKE V+17,27 The extra memory can be used as a store of high resolution pictures as well. This program shows all twelve memory areas that could contain reasonable pictures. The pictures can be created with a BASIC extension that resides in RAM and saves its graphics under Kernal ROM. In those memory blocks that contain no pictures, you see random memory contents. High resolution graphics is enabled on the line 40. The beginning of the line 50 switches bank `I' to the segment 3 and switches the VIC chip to the same memory area. The second POKE statement selects the video bank. `(NOT I AND 3)' filters the extra bits off and inverts the essential ones so that they can be stored to the lowmost two bits of $DD00. The line 60 sets the picture's colour to black-cyan. The next line waits for a keystroke before showing another picture. After all blocks have been shown, the original state of the I/O chips is restored on the line 90. +------------------------------------------------------+ | Peripheral Register A | | (Peripheral Lines PA7--PA0) | +------------------------------------------------------+ | Bits Description | | 7--4 Block Selection, Segment 1 | | 3--0 Block Selection, Segment 0 | +------------------------------------------------------+ +------------------------------------------------------+ | Data Direction Register A | +------------------------------------------------------+ | Bits Description | | 7--0 Data Direction of Peripheral Lines PA7--PA0 | | When a bit is set, its corresponding | | Port A line is an output. Otherwise | | it is an input. | +------------------------------------------------------+ Table 1. The PIA address $DFC0 (57280) +-------------------------------------------------------------------+ | Control Register A | +-------------------------------------------------------------------+ |Bit(s) Description | | 7 IRQA1 Interrupt Flag | | Goes high on active transition of CA1; Automatically | | cleared by MPU read of Peripheral Register A. May also | | be cleared by hardware -RESET. | | | | 6 IRQA2 Interrupt Flag | | When CA2 is an input, IRQA2 goes high on active | | transition of CA2; Automatically cleared by MPU read of | | Peripheral Register A. May also be cleared by hardware | | -RESET. | | | | 5--3 CA2 Control | | 00x Input, triggered on falling edge | | 01x Input, triggered on rising edge | | When x is 1, -IRQA Interrupts by CA2 active transition | | are enabled. | | 10x Output, Read Strobe for Peripheral Register A | | CA2 goes low on first high-to-low E transition following | | a read of Peripheral Register A. When x is 0, it remains | | low until next active CA1 transition. When x is 1, CA2 | | remains low for one E cycle. | | 110 Reset CA2 | | 111 Set CA2 | | | | 2 Register in address $DFC0 | | 0 Data Direction Register | | 1 Peripheral Register | | | | 1 Determine Active CA1 Transition | | 0 IRQA1 set by high-to-low transition on CA1 | | 1 IRQA1 set by low-to-high transition on CA1 | | | | 0 CA1 Interrupt Request Enable/Disable | | 0 Disable -IRQA Interrupt by CA1 active transition. | | 1 Enable -IRQA Interrupt by CA1 active transition. | +-------------------------------------------------------------------+ Table 2. The PIA address $DFC1 (57281) +------------------------------------------------------+ | Peripheral Register B | | (Peripheral Lines PB7--PB0) | +------------------------------------------------------+ | Bits Description | | 7--4 Block Selection, Segment 3 | | 3--0 Block Selection, Segment 2 | +------------------------------------------------------+ +------------------------------------------------------+ | Data Direction Register B | +------------------------------------------------------+ | Bits Description | | 7--0 Data Direction of Peripheral Lines PB7--PB0 | | When a bit is set, its corresponding | | Port B line is an output. Otherwise | | it is an input. | +------------------------------------------------------+ Table 3. The PIA address $DFC2 (57282) +-------------------------------------------------------------------+ | Control Register B | +-------------------------------------------------------------------+ |Bit(s) Description | | 7 IRQB1 Interrupt Flag | | Goes high on active transition of CB1; Automatically | | cleared by MPU read of Peripheral Register B. May also | | be cleared by hardware -RESET. | | | | 6 IRQB2 Interrupt Flag | | When CB2 is an input, IRQB2 goes high on active | | transition of CB2; Automatically cleared by MPU read of | | Peripheral Register B. May also be cleared by hardware | | -RESET. | | | | 5--3 CB2 Control | | 00x Input, triggered on falling edge | | 01x Input, triggered on rising edge | | When x is 1, -IRQB Interrupts by CB2 active transition | | are enabled. | | 10x Output, Read Strobe for Peripheral Register B | | CB2 goes low on first high-to-low E transition following | | a read of Peripheral Register B. When x is 0, it remains | | low until next active CB1 transition. When x is 1, CB2 | | remains low for one E cycle. | | 110 Reset CB2 | | 111 Set CB2 | | | | 2 Register in address $DFC2 | | 0 Data Direction Register | | 1 Peripheral Register | | | | 1 Determine Active CB1 Transition | | 0 IRQB1 set by high-to-low transition on CB1 | | 1 IRQB1 set by low-to-high transition on CB1 | | | | 0 CB1 Interrupt Request Enable/Disable | | 0 Disable -IRQB Interrupt by CB1 active transition. | | 1 Enable -IRQB Interrupt by CB1 active transition. | +-------------------------------------------------------------------+ Table 4. The PIA address $DFC3 (57283) 5 RAM disk and other programs Because not even the manufacturer has taken a memory expansion into consideration, programs making use of extra memory are rare. However, it does not mean that you could not fully utilize the expansion. The most obvious utilization method is a RAM disk. When using VC-1541, it is not only luxury but almost vital condition. Pekka Pessi has made a couple of programs that utilize the 256 kB expansion. The software is distributed in two self-extracting archive files (SFXes). If you don't have got the files with this document, you can retrieve them via anonymous FTP from the server FUNIC.FUnet.FI. The directory /pub/cbm/documents/256kB contains files related to this expansion. The file ROS-V1.SFX (for RAM Operating System) holds the source code of the RAM disk program, and some miscellanous files. Order ``LOAD"ROS-V1.SFX", device'', and change a blank disk to the drive before RUNning. The second archive, UTIL256.SFX, has the following software: 5.1 Memory test The program TEST tests the block selection and the whole memory. If it jams before reporting ``Test passed'', something has gone wrong. Its source code is in the file TEST.A, which requires a library STRING.A. I translated the executable to English by patching the binary file. 5.2 Poor man's multitasking With the MULTI51200 program you can run four different programs. The program does no multitasking, it only keeps four environments in the memory, each in its own memory block. MULTI.A is the source code. After loading it with ``LOAD"MULTI51200", device,1'' and initializing the BASIC pointers with ``NEW'', you can switch the environments with ``SYS51200, f, b''. The parameter f is a flag determining if the current block will be copied to the destination block (0) or not (1). The b selects the destination block (0--3). The initial block is 3. 5.3 Machine language monitor If you don't like to switch the memory banks manually in your favourite machine language monitor, the MON256 utility is for you. The memory is again divided to four 64 kB blocks, numbered from 0 to 3. The commands are as follows: a nnnn cmd or Assembles instruction cmd to . nnnn cmd memory address nnnn. b bb ff Selects a block. The bb holds the block number, and ff is a flag. If it is 1, it directs all memory accessing to RAM. If it is 0, you can access the ROMs and I/O. c hhhh iiii jjjj Compares the memory area hhhh--iiii with the area beginning from jjjj. d [hhhh [iiii]] Disassembles memory. f hhhh iiii nn Fills the memory between hhhh and iiii with the byte pattern nn. g [hhhh] Executes program until a BRK is encountered. h hhhh iiii nn mm... or Hunts the memory area hhhh--iiii h hhhh iiii 'text for the byte sequence nn mm... or for `text'. j [hhhh] Calls a subroutine. l "filename"[,n] Loads a program. Default device number is 8. m [hhhh [iiii]] Hexadecimal dump of memory. > hhhh nn mm... Stores bytes in memory. r Dumps the registers (for `g' and `j'). ; Modifies the register values. s "filename",n,hhhh,jjjj Saves the memory area hhhh--jjjj to device n. t hhhh iiii jjjj Copies the memory area hhhh--iiii to jjjj. v "filename"[,n] Verifies a program. Default device number is 8. x Exits the monitor. @ [command] Sends `command' to device 8. If it begins with $, the disk directory will be read. If no command is given, the disk drive's status will be displayed. The source code for the monitor is split in the files MON.A, CONSOLE.A, COM.A, ROUTINES.A and TABELS.A. 5.4 RAM disk The most important utility is a RAM disk program, which occupies about 9 kilobytes of memory. It transfers Kernal and BASIC interpreter to RAM and patches the serial bus routines. The actual program is in the area $00800--$03FFF. It emulates all VC-1541 functions except relative files. For example, the commands U1, U2, B-A etc. work. UI+ and UI- make no difference. The program also detects some fast loaders and works with them installed. The loader is called RAM DISC, and the patched Kernal is in RAM.K. You need only patches to the low-level serial bus routines, so you may want to restore the original colors and keyboard definitions. To minimize incompatibility problems, you should replace the Kernal ROM with an EPROM holding the patched Kernal. The RAM disk routines are in RAM.C. 5.4.1 Disk copiers The program RAM DISC COPY copies a regular 1541 disk to RAM. It utilizes the slow U1 command, and it is included as an example only. The source code DUP.A exposes the RAM disk's storage format. A faster and more useful tool is FDUPLICATE. Using it, you can copy a regular disk to the RAM disk or vice versa. You can make multiple copies of a disk easily. This program's fast transfer routines are designed for PAL systems, and the utility cannot be used in NTSC machines without little modification. Its source code is in the two files S/SUCK and S/DSUCK. 6 Other expansions There are a couple of unused contacts in the PIA. In addition to that, two 7405 ports are not connected. The extra PIA lines include two inputs, CA1 and CB1, an input/output line CB2, and two Interrupt Request lines -IRQA and -IRQB. If you connect the -IRQA and -IRQB lines to the -IRQ and -NMI inputs of your system, you can have up to three new interrupt sources, useful for interfacing your custom hardware. And if you are running out of User Port pins, the three lines CA1, CB1 and CB2 can save you from designing an I/O cartridge. 6.1 New operating system I had purchased a PC board that allows you to choose between the Kernal ROM and a custom 8 kB EPROM (2764). I never added a fastloader or other useful routines to the Kernal, since I should have deleted some routines, i.e. the Datassette and RS-232 handling. But if you had more ROM, you could keep your new Kernal fully compatible with the old Kernal while adding new features to it. A 32 kB EPROM would easily hold the RAM disk routines, the disk copier and routines for adequately fast loading and saving. Still you would have plenty of space for controlling your own expansions, like a IEEE-488 interface or a SCSI bus. Figure 3 shows the pinouts for the original Kernal ROM (2364) and the replacement chip (27256). Connect the address lines A0--A12, the data bus (D0--D7) and the power supply lines (VCC and GND) together, and connect VPP to VCC. The signals -CS, -CE and -OE are for chip selection. Connect -CE and -OE together, and add 4.7 kilo-ohm resistors between both chips' VCC and chip selection lines. Then add a ON-ON switch between 2364's -CS, 27256's -CE and -OE, and the -KERNAL line that comes from the motherboard originally to 2364's -CS pin. Now you have only the lines A14 and A13 left. PIA's CB2 can control one of them, but what about the other? No problem, let's just give another function to CA2. The new operating system code can initialize the PIA so that the CA2 line will be initially low. And it will be set only when the operating system calls its internal routines. Tie 6821's CB2 and 7405's unused output pins (2 and 12 by default) to +5 V through 4.7 kilo-ohm resistors. This is because these pins are open-collector and cannot otherwise output high voltage. Then connect CB2 to 7405's pin 1 and 7405's pin 2 to 27256's A13. Lead CA2 through the other unused 7405 port to 27256's A14. Now those A14 and A13 lines are low upon start-up, and the computer will see the EPROM area $0000--$1FFF instead of Kernal ROM, if the switch is in right position. That part of the EPROM should initialize the PIA. Note that lowering the CA2 line immediately causes jump to another bank of the EPROM, i.e. to an address greater by $4000. If you are interested in programming a new 32 kB operating system, contact me. I may have done some preliminary work by then. 7 Contacting the authors If you have anything to ask or comment, feel free to contact us. Marko MΣkelΣ's addresses are: Internet: Marko.Makela@Helsinki.FI BitNet: MSMakela@FinUH Mail: Marko MΣkelΣ Sillitie 10 A FI-01480 Vantaa Finland 2364 27256 +--------------+ +--------------+ A7 | 1 \__/ 24 | VCC VPP | 1 \__/ 28 | VCC A6 | 2 23 | A8 A12 | 2 27 | A14 A5 | 3 22 | A9 A7 | 3 26 | A13 A4 | 4 21 | -CS2 A6 | 4 25 | A8 A3 | 5 20 | -CS1 A5 | 5 24 | A9 A2 | 6 19 | A10 A4 | 6 23 | A11 A1 | 7 18 | A11 A3 | 7 22 | -OE A0 | 8 17 | D7 A2 | 8 21 | A10 D0 | 9 16 | D6 A1 | 9 20 | -CE D1 | 10 15 | D5 A0 | 10 19 | D7 D2 | 11 14 | D4 D0 | 11 18 | D6 GND | 12 13 | D3 D1 | 12 17 | D5 +--------------+ D2 | 13 16 | D4 GND | 14 15 | D3 +--------------+ Figure 3. The Read-Only Memory Chips 2364 and 27256 IC4 ^ IC2 74LS153 ^ /--3-!-4----\ | +-----+ ^ | +-11-!-10--\| \-16-| Vcc | | 20 === C1 +--5-!-6--+---------6-| I0a | +------+------+ | 100 nF +--9-!-8-\|+--------5-| I1a | 2-| PA0 Vcc CNT |-40 V ^ | 74LS05 |||| /----4-| I2a | 3-| PA1 SP |-39 | 20 \-------\|||| |/---3-| I3a | 4-| PA2 -IRQ |-21 +-------+-------+ |+-----||--10-| I0b | 5-| PA3 RS0 |-38---\ 38-| -IRQA Vcc CA1 |-40 ||||| /||--11-| I1b | 6-| PA4 RS1 |-37-\ | 37-| -IRQB CA2 |-39-/|||+-|||--12-| I2b | 7-| PA5 RS2 |-36 | \---36-| RS0 PA0 |--2--/||| |||/-13-| I3b | 8-| PA6 RS3 |-35 \-----35-| RS1 PA1 |--3---/|| |||| | Ea |o-1-\ 9-| PA7 -RESET |-34-------34-| -RESET PA2 |-4-PA2>|| |||| | Eb |o15-+ 10-| PB0 D0 |-33-------33-| D0 PA3 |-5-PA3>|| |||| | GND |--8-+ 11-| PB1 D1 |-32-------32-| D1 PA4 |--6----||-/||| | | V 12-| PB2 D2 |-31-------31-| D2 PA5 |--7----/| ||| | | 13-| PB3 D3 |-30-------30-| D3 PA6 |--8-PA6>| ||| |S0 14|--<A14 14-| PB4 D4 |-29-------29-| D4 PA7 |--9-PA7>| ||| |S1 2|--<A15 15-| PB5 D5 |-28-------28-| D5 PB0 |-10-----/ ||| |Za 7|--B15> 16-| PB6 D6 |-27-------27-| D6 PB1 |-11--------/|| |Zb 9|o-B14> 17-| PB7 D7 |-26-------26-| D7 PB2 |-12-PB2> || +-----+ 24-| -FLAG Phi2 |-25-------25-| E PB3 |-13-PB3> || 18-| -PC -CS |-23 A7>-24-| CS PB4 |-14---------|/ | R/-W |-22-\IO2>-23-| -CS PB5 |-15---------/ | U2 Vss TOD |-19 | A6>-22-| CS PB6 |-16-PB6> +-------------+ \-----21-| R/-W PB7 |-17-PB7> 1 | M6526 | CB1 |-18 V | IC1 Vss CB2 |-19 ^ +---------------+ | 16 1 | MC6821 +-----------+ J1 V | Vcc | +--+ PA2>--4-| I0 Z |--5 | 1| CAS PA3>--3-| I1 Z |o-6-MA8> | 2| A15 PA6>--2-| I2 | | 3| MA8 PA7>--1-| I3 IC3 | | 4| A14 PB2>-15-| I4 | | 5| A7 PB3>-14-| I5 | | 6| B14 PB6>-13-| I6 S0 |-11-<CAS | 7| IO2 PB5>-12-| I7 S1 |-10-<A14 | 8| B15 /-7o| E S2 |--9-<A15 | 9| A6 | | GND | |10| GND V +-----------+ +--+ 8 | 74LS151 V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ^ ^ ^ | 16 | 8 | 16 +-----------+ +-----------+ +-----------+ | Vcc | | Vdd | | Vcc | 1o| IG 1Y0 |o-4 5-| MA0 Din |-2 <CAS--1-| SELECT 1Y |-4 2-| 1A 1Y1 |o-5 6-| MA1 Dout |-14 <A14-* B14>--2-| 1A 2Y |-7 3-| 1B 1Y2 |o-6 7-| MA2 -RAS |-4 <A6--3-| 1B 3Y |-9 15o| 2G 1Y3 |o-7 12-| MA3 -CAS |-12 5-| 2A 4Y |-12 14-| 2A 2Y0 |o12 11-| MA4 -WE |-3 6-| 2B G |o15 13-| 2B 2Y1 |o11 10-| MA5 | <A15-* B15>-11-| 3A | | 2Y2 |o10 13-| MA6 | <A7-10-| 3B | | U15 2Y3 |o-9-IO2> 9-| MA7 U12 | 14-| 4A | | GND | 1-| MA8 | 13-| 4B | +-----------+ | Vss | | GND | 8 | 74LS139 +-----------+ +-----------+ V 16 | 80256 8 | 74LS257 V V Figure 4. Schematics diagram of the expansion +----------------------------------------------+ | Electronic Components | +----------+-----------------------------------+ | Symbol | Description | +----------+-----------------------------------+ | IC1 | MC6821 | | IC2 | 74LS153 (or 74LS253) | | IC3 | 74LS151 (or 74LS251) | | IC4 | 74LS05 | | U9--U12, | 80256 or | | U21--U24 | compatible | | C1 | 100 nF polyester capacitor | | R1 | 33 ohm resistor | +----------+-----------------------------------+ +----------------------------------------------+ | Other Parts | +----------+-----------------------------------+ | Quantity | Quality | +----------+-----------------------------------+ | 2 pcs | 10-pin flat cable connector pair | | ca. 15 cm| 10-wire flat cable | | 1 pc | 16-pin piggyback socket | | 2 pcs | 16-pin WW-socket | | or | one 16-pin piggyback socket and | | | two normal 16-pin sockets | | 1 pc | 40-pin WW-socket | | or | one 40-pin piggyback socket and | | | a normal 40-pin socket | | 10 pcs | 16-pin socket | | 1 pc | 14-pin socket | | 8 pcs | 100 nF polyester capacitor (opt.) | | plenty of| connection wire | +----------+-----------------------------------+ Table 5. Parts list for the expansion