ftp.whtech.com/ftp.whtech.com.tar/ftp.whtech.com/Geneve/9640news/CAT14/DSKDSR.ARK

Text File | 2006-10-19 | 12KB | 444 lines

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How to Disk DSR by Mack McCormack

This is the second tutorial for the
advanced asembly language programmer.
The subject by request is disk DSR
routines at the disk ROM and direct
access to the controller chip level. In
reviewing the information I have on the
subject I find that the entire scope is
covered in five books for a total of
about 2,000 pages. Obviously, I must
limit my discussion. I'll break this
into several sub-series.  One final
point please, I enjoy sharing the
information I have learned with others
but have heard very little from the
advanced programmers. If you already
know all this information and would
like to see something else tell me or
if you would rather not bother at all
tell me and I'll concentrate on the
novices (that appears to be where the
real nterest is.)

     The dik DSR is developed on three
levels:


     Level 1 - Basic disk functions.
Sector Read/Write, head contro, drive
selections, track formatting an buffer
allocation


     Level 2 - The "file" concept. Each
file is assessible by its name and an
offset of a 256-byte block relative to
th beginning of the file.


     Level 3 - Extension to the user
level. Fixed or variable length records
or files.


     One other level which you won't
find documented is direct access to the
controller chip in the controller card.

     I intend to confine my discussion
to level 1 and chip level routines. Due
to length, this tutorial will discuss
sector I/O. Followed in subsequent
tutorials with formatting, direct file
access, and buffer allocation (ie. CALL
FILES).

     There are three different
controller chips contained in the three
different controller cards on the market
(TI, CorComp, MYARC). The chips are all
made by Western Digital. They are the WD
1771, WD 2793, and the WD 1770
respectively. Once again I will limit
this tutorial to the TI controller card
and its chip.  Everything in this
tutorial will pertain to all three cards
except direct access to the controller
chip and its associated commands. If you
own one of these other cards and need
additional information let me know but I
will not release proprietary information
on these two cards.

     First lets review the TI
controller card features and ROM. As you
know it can control up to 3 DS/SD
drives. There are 40 tracks per drive
and 9 sectors per track. Each sector is
256 bytes in length. Track 0 is closest
to the outside and track 39 nearest the
center of the disk. There is a built in
DSR ROM which contains 6 level one
routines which may be executed by
branching to them.  These will
accomplish almost all we need to do
except things like track I/O, Volume
Information Block update and others. To
get at these routines you must access
the Floppy Disk Controller (FDC) chip
directly. To accomplish this we need to
know how the FDC chip accesses the drive
and build from there. These are some of
the features of th WD 1771 chip.
Automatic track seek with verification,
in the read/write mode singl/multiple
sector read/write with automatic sector
seek.  Writes entire track for
formatting.  Programable track to track
step times.  Six registers:

     Data shift register - Assembles
serial data from the disk read and
transfers during write.

     Data Register - 8 bit holding
register during read/write operations.
During a seek command it contains the
desired track position.

     Track Register - 8 bit register
that contains the track number of the
current read/write head position.
Incremented by one as the head steps in
toward track 39 and decremented by one
towards track 00. Contents are compared
with the disk track number in the ID
field during read, write and verify.

     Sector Register - 8 bit register
for holding the desired sector
position. Contents compared with the
disk sector ID field during read and
write operations.

     Command Register - 8 bit register
for the command to be executed.

     Status Register - 8 bit register
to hold drive status.

     Much more on these registers as
the tutorials progress.


     There are eleven commands
available:

                     Bits
Type Command         7 6 5 4 3 2 1 0
_______________________________________

I    Restore         0 0 0 0 h V r1r0

I    Seek            0 0 0 1 h V r1r0

I    Step            0 0 1 u h V r1r0

I    Step In         0 1 0 u h V r1r0

I    Step Out        0 1 1 u h V r1r0

II   Read Command    1 0 0 m b E 0 0

II   Write Command   1 0 1 m b E a1a2

III  Read Address    1 1 0 0 0 E 0 0

III  Read Track      1 1 1 0 0 1 0 s

III  Write Track     1 1 1 1 0 1 0 0

IV   Force Interrupt 1 1 0 1 I3I2I1I4



Plug in the appropriate values by type
command:


Type I

h = Head load flag. 1-beginning. 2-not
    beginning.

V =Verify. 1-verify on last track.
    0-no verify.

r1r0 = Stepping motor rate. 0 0 - 6ms.
    1 0 - 10ms. 1 1 - 20ms.

u = Update flag. 1-update track
    register. 0-no update.

Note: Head step times are based on the
1 MHz clock contained in the controller
card.


Type II

m = multiple record. 0-single.
    1-multiple.

b = Block length flag. 1-IBM format
    (256 Byte). Other flags only if
    need to know.
a1a0 = Data Address Mark 00->FB(Data
    Mark)


Type III

s = Synchronize Flag. 0-Single density.

Type IV (interrupt condition flags)

I0 = 1, not ready to transisition.

I1 = 1, Ready to not ready transisition

I2 = 1, Index Pulse

I3 = 1, Immediate Interrupt

E = Enable head load and 10 msec delay

    1-delay. 0-head already loaded no
    delay.

This all seems confusing now but before
its all over you should have a better
understanding.

     Head loading means the read/write
heads are placed in contact with the
disk (the click you hear when the drive
activates) and data may be transfered.
The head stays loaded until a command
is received to unload or until timeout
occurs (2 disk revolutions).

     I suppose this is the best place
to cover the disk format. Have you ever
wondered what's in between the data
fields (256 bytes), well here it is.
Stick with this series and well write a
program to directly look at that data
with a track read command.


Number of Bytes  Whats There

     12          Index Gap. >FF

      6          Sync >00

* Sector begins here. Repeat 9 times *

      1          ID Single density >FE

      1          Track Address >00->27

      1          Side >00

      1          Sector Address >00->08

      1          Sector Len >01

      2          Cycle Redundancy Check
                 >F7

     11          Data Separator >FF

      6          Sync >00

      1          Data Address Mark >FB

    256          File Data

      2          CRC >F7

* Sector ends here *

     36          Data Separator >FF

    240          End of track fill >FF

From this you can see there are 3177
bytes per track but only 2304 are actual
data bytes.

So far we've covered the basic
background.  We will discuss what each
of these more as we proceed.

     There are three ways to perform a
sector I/O.  You may us the DSRLNK,
access the disk ROM without DSRLNK, or
access the controller chip directly.
Lets examine the first two methods.

     Sector I/O is commonly refered to
as subprogram 010. All arguments for
the I/O are passed thru the FAC block
in CPU RAM (>834A). Here's how it maps
out:

>834A-4B {Address of actual sector
         accessed when complete.}


>834C    Disk drive 1,2, or 3.


>834D    Read/Write 0=write. <>0=read


>834E-4F VDP Buffer Address (256 byte
         size).


>8350-51 Sector Number


Error codes returned at >8350 after
operation. 0=no error. 1=error.



****************************************
*                                      *
*       SECTOR I/O ROUTINE DEMO        *
*        USING  DSRLNK                 *
*          BY MACK MCCORMICK           *
*                                      *
****************************************
       DEF  SECTOR
       REF  VMBW,VMBR,DSRLNK

PABI   DATA >0110        SUBPROGRAM 010
CPUBUF BSS  256          CPU BUFFER


SECTOR LI   R0,>F80      ADDRESS OF PAB
       LI   R1,PABI      PAB
       LI   R2,2         TWO BYTES
       BLWP @VMBW        WRITE PAB TO VDP
       LI   R1,>0101
       MOV  R1,@>834C    /DISK DRIVE 1, <>0=READ
       LI   R1,>1000
       MOV  R1,@>834E    /VDP BUFFER START ADDRESS/ AT LEAST 256K
       CLR  R1
       MOV  R1,@>8350    /LOOK AT SECTOR 0
       LI   R1,>F80
       MOV  R1,@>8356    POINT TO THE PAB AT >8356
       BLWP @DSRLNK      ACCESS THE DISK
       DATA >A           USE DISK DSR SUBROUTINES
* NORMALLY YOU WOULD CHECK FOR ERRORS AT >8350 HERE
* YOU COULD ALSO CHECK >834A FOR ACTUAL SECTOR READ

*------------------------------*
*  PUT IT UP ON THE SCREEN     *
*-----------------------------*
       LI   R0,>1000     VDP BUFFER ADDRESS
       LI   R1,CPUBUF    CPU BUFFER ADDRESS
       LI   R2,256       MOVE 256 BYTES DOWN
       BLWP @VMBR
*THIS WOULD BE THE PLACE TO MANIPULATE DATA BEFORE WRITING IT BACK UP
       CLR  R0           SIT POSITION 0
       BLWP @VMBW        WRITE UP TO SCREEN IMAGE TABLE
*------------------------------*
*  WRITE BACK OUT TO DISK      *
*------------------------------*
       LI   R1,>0100     /DISK 1, WRITE/
       MOV  R1,@>834C
       BLWP @DSRLNK      WRITE IT BACK OUT
       DATA >A
       JMP  $            YOU WOULD EXIT THE PROGRAM HERE
       END
* YOU CAN SEE HOW EASY IT IS TO WRITE A SECTOR COPIER JUST FROM THIS SHORT CODE
* ADD A FEW WHISTLES AND BELLS AND YOU HAVE A FIRST CLASS PRODUCT



****************************************
*            2D EXAMPLE                *
*   SECTOR I/O ROUTINE DEMO USING      *
*        DIRECT ROM ACCESS             *
*   ACCOMPANIES SECTOR I/O TUTORIAL    *
*                                      *
****************************************
       DEF  SECTOR
       REF  VMBW,VMBR,GPLWS

SUBR   DATA >0110        SUBPROGRAM 010
CPUBUF BSS  256          CPU BUFFER
MYREG  BSS  >20          MY WORKSPACE


SECTOR LWPI GPLWS

       LI   R1,>0101
       MOV  R1,@>834C    /DISK DRIVE 1, <>0=READ
       LI   R1,>1000
       MOV  R1,@>834E    /VDP BUFFER START ADDRESS/ AT LEAST 256K
       CLR  R1
       MOV  R1,@>8350    /LOOK AT SECTOR 0
       LI   R12,>1100    SET CRU REGISTER TO BASE ADDRESS OF >1100 DSK DSR ROM
       SBO  0            PAGE INTHE DISK DSR ROM TO >4000

* Of course you could eliminate the next five instructions and manually scan the
* DSR ROM for the word which immediately proceeds >0110 and loaded R9 with that
* value which is >56DC in the case of the CorComp card and BL directly to it.
* I scanned the link table so this program could be used with other DSR
* subroutines and with all controller cards.
       LI   R9,>4000     BEGINNING OF DISK DSR ROM
NEXT   C    *R9+,@SUBR   SEARCH LINK TABLE FOR ENTRY POINT
       JNE  NEXT
       AI   R9,-4        SUBTRACT 4 FOR ENTRY POINT
       MOV  *R9,R9       GET THE ENTRY POINT ADDRESS
       BL   *R9          BRANCH TO THE ROUTINE

* NORMALLY YOU WOULD CHECK FOR ERRORS AT >8350 HERE
* YOU COULD ALSO CHECK >834A FOR ACTUAL SECTOR READ

*------------------------------*
*  PUT IT UP ON THE SCREEN     *
*------------------------------*
       NOP               NOP IS REQUIRED HERE BECAUSE THE DSR ROUTINE INCT's THE
*                        RT ADDRESS
       LI   R0,>1000     VDP BUFFER ADDRESS
       LI   R1,CPUBUF    CPU BUFFER ADDRESS
       LI   R2,256       MOVE 256 BYTES DOWN
       BLWP @VMBR
*THIS WOULD BE THE PLACE TO MANIPULATE DATA BEFORE WRITING IT BACK UP
       CLR  R0           SIT POSITION 0
       BLWP @VMBW        WRITE UP TO SCREEN IMAGE TABLE
*-----------------------------*
*  WRITE BACK OUT TO DISK      *
*------------------------------*
       LI   R1,>0100     /DISK 1, WRITE/
       MOV  R1,@>834C
       BL   *R9
       SBZ  0            PAGE OUT DISK DSR
       JMP  $            YOU WOULD EXIT THE PROGRAM HERE
       END


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