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Text File  |  1993-06-20  |  14KB  |  234 lines
  1. /*+-----------------------------------------------------------------------+
  2.  *| The following table defines the internal I/O registers contained      |
  3.  *| within the TMS34010 microprocessor.                                   |
  4.  *|                                                                       |
  5.  *| Author: Michael S. A. Robb         Version: 1.1        Date: 16/06/93 |
  6.  *+-----------------------------------------------------------------------+
  7.  */
  8.  
  9. #define IO_HESYNC      0xC0000000L     /* Horizontal End     Sync  */
  10. #define IO_HEBLNK      0xC0000010L     /* Horizontal End     Blank */
  11. #define IO_HSBLNK      0xC0000020L     /* Horizontal Start   Blank */
  12. #define IO_HTOTAL      0xC0000030L     /* Horizontal Total         */
  13. #define IO_VESYNC      0xC0000040L     /* Vertical   End     Sync  */
  14. #define IO_VEBLNK      0xC0000050L     /* Vertical   End     Blank */
  15. #define IO_VSBLNK      0xC0000060L     /* Vertical   Start   Blank */
  16. #define IO_VTOTAL      0xC0000070L     /* Video      Total         */
  17. #define IO_DPYCTL      0xC0000080L     /* Display    Control       */
  18. #define IO_DPYSTRT     0xC0000090L     /* Display    Start         */
  19. #define IO_DPYINT      0xC00000A0L     /* Display    Interrupt     */
  20. #define IO_CONTROL     0xC00000B0L     /* Control                  */
  21. #define IO_HSTDATA     0xC00000C0L     /* Host       Data          */
  22. #define IO_HSTADRL     0xC00000D0L     /* Host       Address Low   */
  23. #define IO_HSTADRH     0xC00000E0L     /* Host       Address High  */
  24. #define IO_HSTCTLL     0xC00000F0L     /* Host       Control Low   */
  25. #define IO_HSTCTLH     0xC0000100L     /* Host       Control High  */
  26. #define IO_INTENB      0xC0000110L     /* Interrupt  Enable        */
  27. #define IO_INTPEND     0xC0000120L     /* Interrupt  Pending       */
  28. #define IO_CONVSP      0xC0000130L     /* Conversion (Src. Pitch)  */
  29. #define IO_CONVDP      0xC0000140L     /* Conversion (Dst. Pitch)  */
  30. #define IO_PSIZE       0xC0000150L     /* Pixel      Size          */
  31. #define IO_PMASK       0xC0000160L     /* Plane      Mask          */
  32. #define IO_RESERVED1   0xC0000170L     /* Reserved                 */
  33. #define IO_RESERVED2   0xC0000180L     /* Reserved                 */
  34. #define IO_RESERVED3   0xC0000190L     /* Reserved                 */
  35. #define IO_RESERVED4   0xC00001A0L     /* Reserved                 */
  36. #define IO_DPYTAP      0xC00001B0L     /* Display    Tap Point     */
  37. #define IO_HCOUNT      0xC00001C0L     /* Horizontal Count         */
  38. #define IO_VCOUNT      0xC00001D0L     /* Vertical   Count         */
  39. #define IO_DPYADR      0xC00001E0L     /* Display    Address       */
  40. #define IO_REFCNT      0xC00001F0L     /* DRAM       Refresh Count */
  41.  
  42. /*+-----------------------------------------------------------------------+
  43.  *| The following table defines other external I/O registers accessible   |
  44.  *| via the TMS34010 microprocessor bus.                                  |
  45.  *+-----------------------------------------------------------------------+
  46.  */
  47.  
  48. #define RAMDAC_WRITE   0x06000000L     /* Write address for data.  */
  49. #define RAMDAC_DATA    0x06000010L     /* Data address.            */
  50. #define RAMDAC_COMMAND 0x06000020L     /* Command address.         */
  51. #define RAMDAC_READ    0x06000030L     /* Read address for data.   */
  52.  
  53. /*+-----------------------------------------------------------------------+
  54.  *| The following constants define the read and write addresses for the   |
  55.  *| CONFIGURATION 1 REGISTER.                                             |
  56.  *|                                                                       |
  57.  *|  15 14 13 12 11 10  9  8  7  6  5  4   3  2  1  0                     |
  58.  *| +-----------------------------------+---+--------+                    |
  59.  *| |  RESERVED                         |RS2|  VCLK  |                    |
  60.  *| +-----------------------------------+---+--------+                    |
  61.  *|                                                                       |
  62.  *| Bits 0-2  - Selects the clock frequency for the screen refresh.       |
  63.  *|             See CLOCK_ENUM.                                           |
  64.  *|                                                                       |
  65.  *| Bit    3  - Controls access to overlay and command access.            |
  66.  *|             See ACCESS_ENUM.                                          |
  67.  *|                                                                       |
  68.  *| Bits 4-15 - Not Used.                                                 |
  69.  *+-----------------------------------------------------------------------+
  70.  */
  71.  
  72. #define CONFIG1_WRITE  0x060000C0L     /* External timing write.   */
  73. #define CONFIG1_READ   0x060001C0L     /* Default configuration.   */
  74.  
  75. /*+-----------------------------------------------------------------------+
  76.  *| The following constants define the read and write addresses for the   |
  77.  *| CONFIGURATION 2 REGISTER.                                             |
  78.  *|                                                                       |
  79.  *|  15 14 13 12 11 10  9  8  7  6  5    4     3    2  1  0               |
  80.  *| +--------------------------------+----+-----+-----+----+              |
  81.  *| |  RESERVED                      |HINT|VSYNC|HSYNC|PSEL|              |
  82.  *| +--------------------------------+----+-----+-----+----+              |
  83.  *|                                                                       |
  84.  *| Bits 0-1  - 00 = VGA Control Video RAM                                |
  85.  *|             01 = 32 bits per pixel                                    |
  86.  *|             10 = 16 bits per pixel                                    |
  87.  *|             11 =  8 bits per pixel                                    |
  88.  *|                                                                       |
  89.  *| Bit    2  - Horizontal sync: 0 = Positive, 1 = Negative.              |
  90.  *|                                                                       |
  91.  *| Bit    3  - Vertical   sync: 0 = Positive, 1 = Negative.              |
  92.  *|                                                                       |
  93.  *| Bit    4  - Host interrupts: 0 = Disabled, 1 = Enabled.               |
  94.  *|                                                                       |
  95.  *| Bits 5-15 - Not used.                                                 |
  96.  *+-----------------------------------------------------------------------+
  97.  */
  98.  
  99. #define CONFIG2_WRITE  0x060000E0L     /* Display Pitch.           */
  100. #define CONFIG2_READ   0x060001E0L
  101.  
  102. /*+-----------------------------------------------------------------------+
  103.  *| The following table defines the TMS34010 registers which may be       |
  104.  *| accessed via the main CPU's data bus ie. the 80x86.                   |
  105.  *+-----------------------------------------------------------------------+
  106.  */
  107.  
  108. #define CPU_ADDRLO     0xC0007E00L     /* Host Address Low  Word   */
  109. #define CPU_ADDRHI     0xC0007F00L     /* Host Address High Word   */
  110. #define CPU_CONTROL    0xC0007D00L     /* Host Control             */
  111. #define CPU_SLOWDATA   0xC0007000L     /* Host Data Registers      */
  112. #define CPU_FASTDATA   0xA0000000L     /* Host Data Registers      */
  113.  
  114. #define HOST_AUTOINCR       0xD800     /* Automatic increments.    */
  115. #define HOST_NOINCR         0xC000     /* No increments.           */
  116.  
  117. /*+-----------------------------------------------------------------------+
  118.  *| The following constants define the various clock speeds that may be   |
  119.  *| used to drive the video monitor.                                      |
  120.  *|                                                                       |
  121.  *| Stored in the 'tms_clockbase' field of the TMS34010_MODE structure.   |
  122.  *+-----------------------------------------------------------------------+
  123.  */
  124.  
  125. #define CLOCK_14280MHZ      0x00       /* 14.280MHz ???  pixels ?? */
  126. #define CLOCK_20000MHZ      0x01       /* 20.000MHz 512  pixels 24 */
  127. #define CLOCK_VGA           0x02       /* Current VGA Clock        */
  128. #define CLOCK_36000MHZ      0x03       /* 36.000MHz 800  pixels  8 */
  129. #define CLOCK_44900MHZ      0x04       /* 44.900MHz 1024 pixels I8 */
  130. #define CLOCK_64000MHZ      0x05       /* 64.000MHz 1024 pixels U8 */
  131. #define CLOCK_25175MHZ      0x06       /* 25.175MHz 640  pixels 16 */
  132. #define CLOCK_50350MHZ      0x07       /* 50.350MHz 640  pixels  8 */
  133.  
  134. /*+-----------------------------------------------------------------------+
  135.  *| The following constants define the format of the current video mode.  |
  136.  *+-----------------------------------------------------------------------+
  137.  */
  138.  
  139. #define VSCAN_INTERLACED    0x00       /* Interlaced scan.         */
  140. #define VSCAN_UNINTERLACED  0x0C       /* Uninterlaced scan.       */
  141.  
  142. /*+-----------------------------------------------------------------------+
  143.  *| The following constants are used to select the size of pixels in the  |
  144.  *| current video mode.                                                   |
  145.  *+-----------------------------------------------------------------------+
  146.  */
  147.  
  148. #define PIXEL_SIZE8         0x03       /* Pixel depth -  8 bits.   */
  149. #define PIXEL_SIZE16        0x02       /* Pixel depth - 16 bits.   */
  150. #define PIXEL_SIZE32        0x01       /* Pixel depth - 32 bits.   */
  151.  
  152. /*+-----------------------------------------------------------------------+
  153.  *| The following constants are used to select the format of the overlay  |
  154.  *| option.                                                               |
  155.  *+-----------------------------------------------------------------------+
  156.  */
  157.  
  158. #define OVERLAY_4BITS       0x00       /* 4-bit overlay.           */
  159. #define OVERLAY_1BIT        0x02       /* 1-bit overlay.           */
  160. #define OVERLAY_NONE        0x03       /* No    overlay.           */
  161.  
  162. /*+-----------------------------------------------------------------------+
  163.  *| The following bit-masks are used with the Display Control register    |
  164.  *| DPYCTL.                                                               |
  165.  *+-----------------------------------------------------------------------+
  166.  */
  167.  
  168. #define HC_ENV              0x8000     /* Enable video.               */
  169. #define HC_NIL              0x4000     /* Noninterlaced video enable. */
  170. #define HC_DXV              0x2000     /* Disable external video.     */
  171. #define HC_SRE              0x1000     /* Screen refresh enable.      */
  172. #define HC_SRT              0x0800     /* Shift register enable.      */
  173. #define HC_ORG              0x0400     /* Screen origin select.       */
  174. #define HC_HSD              0x0001     /* Horizontal sync direction.  */
  175.  
  176. /*+-----------------------------------------------------------------------+
  177.  *| These values are used to select the display pitch for the VRAM shift  |
  178.  *| registers.                                                            |
  179.  *+-----------------------------------------------------------------------+
  180.  */
  181.  
  182. #define HC_DUDATE0          0x0000     /* Number of bytes per line.   */
  183. #define HC_DUDATE1          0x0004
  184. #define HC_DUDATE2          0x0008
  185. #define HC_DUDATE4          0x0010     /*  512 bytes per line.        */
  186. #define HC_DUDATE8          0x0020     /* 1024 bytes per line.        */
  187. #define HC_DUDATE16         0x0040     /* 2048 bytes per line.        */
  188. #define HC_DUDATE32         0x0080
  189. #define HC_DUDATE64         0x0100
  190. #define HC_DUDATE128        0x0200
  191.  
  192. /*+-----------------------------------------------------------------------+
  193.  *| These values are specific to the Hercules Graphics Station Card.      |
  194.  *+-----------------------------------------------------------------------+
  195.  */
  196.  
  197. #define MODE_UNINTERLACED    (HC_ENV|HC_DXV|HC_SRE|HC_NIL)
  198. #define MODE_INTERLACED      (HC_ENV|HC_DXV|HC_SRE)
  199. #define MODE_4KBYTE           HC_DUDATE32
  200. #define MODE_2KBYTE           HC_DUDATE16
  201. #define MODE_1KBYTE           HC_DUDATE8
  202. #define MODE_512BYTES         HC_DUDATE4
  203.  
  204. /*+-----------------------------------------------------------------------+
  205.  *| The following table shows the organisation of the CLUT control bits.  |
  206.  *|                                                                       |
  207.  *|                 Bits 3-2                                              |
  208.  *|                                                                       |
  209.  *|                        00            01          10         11        |
  210.  *|                  00    24/LU         24/NLU      NA         NA        |
  211.  *|  Bits 7-6        01    24/LU         24/NLU      8G/LU      8G/NLU    |
  212.  *|                  10    24/LU         24/NLU      NA         NA        |
  213.  *|                  11    NA            NA          NA         16/NLU    |
  214.  *|                                                                       |
  215.  *+-----------------------------------------------------------------------+
  216.  */
  217.  
  218. /*+-----------------------------------------------------------------------+
  219.  *| The following constants are for use with the BrookTree 473 palette    |
  220.  *| chip.                                                                 |
  221.  *+-----------------------------------------------------------------------+
  222.  */
  223.  
  224. #define MODE_24BIT_NOCLUT       0x34        /* 00xx01xx */
  225. #define MODE_24BIT_CLUT         0x10        /* 00xx00xx */
  226. #define MODE_16BIT              0xDC        /* 11xx11xx */
  227. #define MODE_8BIT_NOCLUT        0x5C        /* 01xx11xx */
  228. #define MODE_8BIT_CLUT          0x58        /* 01xx10xx */
  229.  
  230. #define DEFAULT_8BIT            (MODE_8BIT_CLUT    | OVERLAY_NONE)
  231. #define DEFAULT_16BIT           (MODE_16BIT        | OVERLAY_NONE)
  232. #define DEFAULT_24BIT           (MODE_24BIT_NOCLUT | OVERLAY_NONE)
  233.  
  234.